1/** @file 2 EFI PCI I/O Protocol provides the basic Memory, I/O, PCI configuration, 3 and DMA interfaces that a driver uses to access its PCI controller. 4 5 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR> 6 This program and the accompanying materials 7 are licensed and made available under the terms and conditions of the BSD License 8 which accompanies this distribution. The full text of the license may be found at 9 http://opensource.org/licenses/bsd-license.php 10 11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 14**/ 15 16#ifndef __PCI_IO_H__ 17#define __PCI_IO_H__ 18 19#define EFI_PCI_ROOT_IO_GUID \ 20 { 0x2F707EBB, 0x4A1A, 0x11d4, { 0x9A, 0x38, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }} 21 22/// 23/// Global ID for the PCI I/O Protocol 24/// 25#define EFI_PCI_IO_PROTOCOL_GUID \ 26 { 0x4cf5b200, 0x68b8, 0x4ca5, {0x9e, 0xec, 0xb2, 0x3e, 0x3f, 0x50, 0x2, 0x9a} } 27 28typedef struct _EFI_PCI_IO_PROTOCOL EFI_PCI_IO_PROTOCOL; 29 30/// 31/// ******************************************************* 32/// EFI_PCI_IO_PROTOCOL_WIDTH 33/// ******************************************************* 34/// 35typedef enum { 36 EfiPciIoWidthUint8 = 0, 37 EfiPciIoWidthUint16, 38 EfiPciIoWidthUint32, 39 EfiPciIoWidthUint64, 40 EfiPciIoWidthFifoUint8, 41 EfiPciIoWidthFifoUint16, 42 EfiPciIoWidthFifoUint32, 43 EfiPciIoWidthFifoUint64, 44 EfiPciIoWidthFillUint8, 45 EfiPciIoWidthFillUint16, 46 EfiPciIoWidthFillUint32, 47 EfiPciIoWidthFillUint64, 48 EfiPciIoWidthMaximum 49} EFI_PCI_IO_PROTOCOL_WIDTH; 50 51// 52// Complete PCI address generater 53// 54#define EFI_PCI_IO_PASS_THROUGH_BAR 0xff ///< Special BAR that passes a memory or I/O cycle through unchanged 55#define EFI_PCI_IO_ATTRIBUTE_MASK 0x077f ///< All the following I/O and Memory cycles 56#define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 ///< I/O cycles 0x0000-0x00FF (10 bit decode) 57#define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 ///< I/O cycles 0x0100-0x03FF or greater (10 bit decode) 58#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO 0x0004 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (10 bit decode) 59#define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 ///< MEM cycles 0xA0000-0xBFFFF (24 bit decode) 60#define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode) 61#define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 ///< I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode) 62#define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 ///< I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode) 63#define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 ///< Map a memory range so writes are combined 64#define EFI_PCI_IO_ATTRIBUTE_IO 0x0100 ///< Enable the I/O decode bit in the PCI Config Header 65#define EFI_PCI_IO_ATTRIBUTE_MEMORY 0x0200 ///< Enable the Memory decode bit in the PCI Config Header 66#define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER 0x0400 ///< Enable the DMA bit in the PCI Config Header 67#define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED 0x0800 ///< Map a memory range so all r/w accesses are cached 68#define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE 0x1000 ///< Disable a memory range 69#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 ///< Clear for an add-in PCI Device 70#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM 0x4000 ///< Clear for a physical PCI Option ROM accessed through ROM BAR 71#define EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000 ///< Clear for PCI controllers that can not genrate a DAC 72#define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 0x10000 ///< I/O cycles 0x0100-0x03FF or greater (16 bit decode) 73#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (16 bit decode) 74#define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 0x40000 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode) 75 76#define EFI_PCI_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER) 77#define EFI_VGA_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY | EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_IO) 78 79/// 80/// ******************************************************* 81/// EFI_PCI_IO_PROTOCOL_OPERATION 82/// ******************************************************* 83/// 84typedef enum { 85 /// 86 /// A read operation from system memory by a bus master. 87 /// 88 EfiPciIoOperationBusMasterRead, 89 /// 90 /// A write operation from system memory by a bus master. 91 /// 92 EfiPciIoOperationBusMasterWrite, 93 /// 94 /// Provides both read and write access to system memory by both the processor and a 95 /// bus master. The buffer is coherent from both the processor's and the bus master's point of view. 96 /// 97 EfiPciIoOperationBusMasterCommonBuffer, 98 EfiPciIoOperationMaximum 99} EFI_PCI_IO_PROTOCOL_OPERATION; 100 101/// 102/// ******************************************************* 103/// EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION 104/// ******************************************************* 105/// 106typedef enum { 107 /// 108 /// Retrieve the PCI controller's current attributes, and return them in Result. 109 /// 110 EfiPciIoAttributeOperationGet, 111 /// 112 /// Set the PCI controller's current attributes to Attributes. 113 /// 114 EfiPciIoAttributeOperationSet, 115 /// 116 /// Enable the attributes specified by the bits that are set in Attributes for this PCI controller. 117 /// 118 EfiPciIoAttributeOperationEnable, 119 /// 120 /// Disable the attributes specified by the bits that are set in Attributes for this PCI controller. 121 /// 122 EfiPciIoAttributeOperationDisable, 123 /// 124 /// Retrieve the PCI controller's supported attributes, and return them in Result. 125 /// 126 EfiPciIoAttributeOperationSupported, 127 EfiPciIoAttributeOperationMaximum 128} EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION; 129 130/** 131 Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is 132 satisfied or after a defined duration. 133 134 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 135 @param Width Signifies the width of the memory or I/O operations. 136 @param BarIndex The BAR index of the standard PCI Configuration header to use as the 137 base address for the memory operation to perform. 138 @param Offset The offset within the selected BAR to start the memory operation. 139 @param Mask Mask used for the polling criteria. 140 @param Value The comparison value used for the polling exit criteria. 141 @param Delay The number of 100 ns units to poll. 142 @param Result Pointer to the last value read from the memory location. 143 144 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria. 145 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller. 146 @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller. 147 @retval EFI_TIMEOUT Delay expired before a match occurred. 148 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. 149 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. 150 151**/ 152typedef 153EFI_STATUS 154(EFIAPI *EFI_PCI_IO_PROTOCOL_POLL_IO_MEM)( 155 IN EFI_PCI_IO_PROTOCOL *This, 156 IN EFI_PCI_IO_PROTOCOL_WIDTH Width, 157 IN UINT8 BarIndex, 158 IN UINT64 Offset, 159 IN UINT64 Mask, 160 IN UINT64 Value, 161 IN UINT64 Delay, 162 OUT UINT64 *Result 163 ); 164 165/** 166 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space. 167 168 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 169 @param Width Signifies the width of the memory or I/O operations. 170 @param BarIndex The BAR index of the standard PCI Configuration header to use as the 171 base address for the memory or I/O operation to perform. 172 @param Offset The offset within the selected BAR to start the memory or I/O operation. 173 @param Count The number of memory or I/O operations to perform. 174 @param Buffer For read operations, the destination buffer to store the results. For write 175 operations, the source buffer to write data from. 176 177 @retval EFI_SUCCESS The data was read from or written to the PCI controller. 178 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller. 179 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not 180 valid for the PCI BAR specified by BarIndex. 181 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. 182 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. 183 184**/ 185typedef 186EFI_STATUS 187(EFIAPI *EFI_PCI_IO_PROTOCOL_IO_MEM)( 188 IN EFI_PCI_IO_PROTOCOL *This, 189 IN EFI_PCI_IO_PROTOCOL_WIDTH Width, 190 IN UINT8 BarIndex, 191 IN UINT64 Offset, 192 IN UINTN Count, 193 IN OUT VOID *Buffer 194 ); 195 196typedef struct { 197 /// 198 /// Read PCI controller registers in the PCI memory or I/O space. 199 /// 200 EFI_PCI_IO_PROTOCOL_IO_MEM Read; 201 /// 202 /// Write PCI controller registers in the PCI memory or I/O space. 203 /// 204 EFI_PCI_IO_PROTOCOL_IO_MEM Write; 205} EFI_PCI_IO_PROTOCOL_ACCESS; 206 207/** 208 Enable a PCI driver to access PCI controller registers in PCI configuration space. 209 210 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 211 @param Width Signifies the width of the memory operations. 212 @param Offset The offset within the PCI configuration space for the PCI controller. 213 @param Count The number of PCI configuration operations to perform. 214 @param Buffer For read operations, the destination buffer to store the results. For write 215 operations, the source buffer to write data from. 216 217 218 @retval EFI_SUCCESS The data was read from or written to the PCI controller. 219 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not 220 valid for the PCI configuration header of the PCI controller. 221 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. 222 @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. 223 224**/ 225typedef 226EFI_STATUS 227(EFIAPI *EFI_PCI_IO_PROTOCOL_CONFIG)( 228 IN EFI_PCI_IO_PROTOCOL *This, 229 IN EFI_PCI_IO_PROTOCOL_WIDTH Width, 230 IN UINT32 Offset, 231 IN UINTN Count, 232 IN OUT VOID *Buffer 233 ); 234 235typedef struct { 236 /// 237 /// Read PCI controller registers in PCI configuration space. 238 /// 239 EFI_PCI_IO_PROTOCOL_CONFIG Read; 240 /// 241 /// Write PCI controller registers in PCI configuration space. 242 /// 243 EFI_PCI_IO_PROTOCOL_CONFIG Write; 244} EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS; 245 246/** 247 Enables a PCI driver to copy one region of PCI memory space to another region of PCI 248 memory space. 249 250 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 251 @param Width Signifies the width of the memory operations. 252 @param DestBarIndex The BAR index in the standard PCI Configuration header to use as the 253 base address for the memory operation to perform. 254 @param DestOffset The destination offset within the BAR specified by DestBarIndex to 255 start the memory writes for the copy operation. 256 @param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the 257 base address for the memory operation to perform. 258 @param SrcOffset The source offset within the BAR specified by SrcBarIndex to start 259 the memory reads for the copy operation. 260 @param Count The number of memory operations to perform. Bytes moved is Width 261 size * Count, starting at DestOffset and SrcOffset. 262 263 @retval EFI_SUCCESS The data was copied from one memory region to another memory region. 264 @retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller. 265 @retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller. 266 @retval EFI_UNSUPPORTED The address range specified by DestOffset, Width, and Count 267 is not valid for the PCI BAR specified by DestBarIndex. 268 @retval EFI_UNSUPPORTED The address range specified by SrcOffset, Width, and Count is 269 not valid for the PCI BAR specified by SrcBarIndex. 270 @retval EFI_INVALID_PARAMETER Width is invalid. 271 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. 272 273**/ 274typedef 275EFI_STATUS 276(EFIAPI *EFI_PCI_IO_PROTOCOL_COPY_MEM)( 277 IN EFI_PCI_IO_PROTOCOL *This, 278 IN EFI_PCI_IO_PROTOCOL_WIDTH Width, 279 IN UINT8 DestBarIndex, 280 IN UINT64 DestOffset, 281 IN UINT8 SrcBarIndex, 282 IN UINT64 SrcOffset, 283 IN UINTN Count 284 ); 285 286/** 287 Provides the PCI controller-specific addresses needed to access system memory. 288 289 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 290 @param Operation Indicates if the bus master is going to read or write to system memory. 291 @param HostAddress The system memory address to map to the PCI controller. 292 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes 293 that were mapped. 294 @param DeviceAddress The resulting map address for the bus master PCI controller to use to 295 access the hosts HostAddress. 296 @param Mapping A resulting value to pass to Unmap(). 297 298 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes. 299 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer. 300 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. 301 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. 302 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address. 303 304**/ 305typedef 306EFI_STATUS 307(EFIAPI *EFI_PCI_IO_PROTOCOL_MAP)( 308 IN EFI_PCI_IO_PROTOCOL *This, 309 IN EFI_PCI_IO_PROTOCOL_OPERATION Operation, 310 IN VOID *HostAddress, 311 IN OUT UINTN *NumberOfBytes, 312 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, 313 OUT VOID **Mapping 314 ); 315 316/** 317 Completes the Map() operation and releases any corresponding resources. 318 319 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 320 @param Mapping The mapping value returned from Map(). 321 322 @retval EFI_SUCCESS The range was unmapped. 323 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory. 324 325**/ 326typedef 327EFI_STATUS 328(EFIAPI *EFI_PCI_IO_PROTOCOL_UNMAP)( 329 IN EFI_PCI_IO_PROTOCOL *This, 330 IN VOID *Mapping 331 ); 332 333/** 334 Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer 335 mapping. 336 337 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 338 @param Type This parameter is not used and must be ignored. 339 @param MemoryType The type of memory to allocate, EfiBootServicesData or 340 EfiRuntimeServicesData. 341 @param Pages The number of pages to allocate. 342 @param HostAddress A pointer to store the base system memory address of the 343 allocated range. 344 @param Attributes The requested bit mask of attributes for the allocated range. 345 346 @retval EFI_SUCCESS The requested memory pages were allocated. 347 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are 348 MEMORY_WRITE_COMBINE and MEMORY_CACHED. 349 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. 350 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. 351 352**/ 353typedef 354EFI_STATUS 355(EFIAPI *EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER)( 356 IN EFI_PCI_IO_PROTOCOL *This, 357 IN EFI_ALLOCATE_TYPE Type, 358 IN EFI_MEMORY_TYPE MemoryType, 359 IN UINTN Pages, 360 OUT VOID **HostAddress, 361 IN UINT64 Attributes 362 ); 363 364/** 365 Frees memory that was allocated with AllocateBuffer(). 366 367 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 368 @param Pages The number of pages to free. 369 @param HostAddress The base system memory address of the allocated range. 370 371 @retval EFI_SUCCESS The requested memory pages were freed. 372 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages 373 was not allocated with AllocateBuffer(). 374 375**/ 376typedef 377EFI_STATUS 378(EFIAPI *EFI_PCI_IO_PROTOCOL_FREE_BUFFER)( 379 IN EFI_PCI_IO_PROTOCOL *This, 380 IN UINTN Pages, 381 IN VOID *HostAddress 382 ); 383 384/** 385 Flushes all PCI posted write transactions from a PCI host bridge to system memory. 386 387 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 388 389 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host 390 bridge to system memory. 391 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI 392 host bridge due to a hardware error. 393 394**/ 395typedef 396EFI_STATUS 397(EFIAPI *EFI_PCI_IO_PROTOCOL_FLUSH)( 398 IN EFI_PCI_IO_PROTOCOL *This 399 ); 400 401/** 402 Retrieves this PCI controller's current PCI bus number, device number, and function number. 403 404 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 405 @param SegmentNumber The PCI controller's current PCI segment number. 406 @param BusNumber The PCI controller's current PCI bus number. 407 @param DeviceNumber The PCI controller's current PCI device number. 408 @param FunctionNumber The PCI controller's current PCI function number. 409 410 @retval EFI_SUCCESS The PCI controller location was returned. 411 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. 412 413**/ 414typedef 415EFI_STATUS 416(EFIAPI *EFI_PCI_IO_PROTOCOL_GET_LOCATION)( 417 IN EFI_PCI_IO_PROTOCOL *This, 418 OUT UINTN *SegmentNumber, 419 OUT UINTN *BusNumber, 420 OUT UINTN *DeviceNumber, 421 OUT UINTN *FunctionNumber 422 ); 423 424/** 425 Performs an operation on the attributes that this PCI controller supports. The operations include 426 getting the set of supported attributes, retrieving the current attributes, setting the current 427 attributes, enabling attributes, and disabling attributes. 428 429 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 430 @param Operation The operation to perform on the attributes for this PCI controller. 431 @param Attributes The mask of attributes that are used for Set, Enable, and Disable 432 operations. 433 @param Result A pointer to the result mask of attributes that are returned for the Get 434 and Supported operations. 435 436 @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed. 437 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. 438 @retval EFI_UNSUPPORTED one or more of the bits set in 439 Attributes are not supported by this PCI controller or one of 440 its parent bridges when Operation is Set, Enable or Disable. 441 442**/ 443typedef 444EFI_STATUS 445(EFIAPI *EFI_PCI_IO_PROTOCOL_ATTRIBUTES)( 446 IN EFI_PCI_IO_PROTOCOL *This, 447 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation, 448 IN UINT64 Attributes, 449 OUT UINT64 *Result OPTIONAL 450 ); 451 452/** 453 Gets the attributes that this PCI controller supports setting on a BAR using 454 SetBarAttributes(), and retrieves the list of resource descriptors for a BAR. 455 456 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 457 @param BarIndex The BAR index of the standard PCI Configuration header to use as the 458 base address for resource range. The legal range for this field is 0..5. 459 @param Supports A pointer to the mask of attributes that this PCI controller supports 460 setting for this BAR with SetBarAttributes(). 461 @param Resources A pointer to the ACPI 2.0 resource descriptors that describe the current 462 configuration of this BAR of the PCI controller. 463 464 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI 465 controller supports are returned in Supports. If Resources 466 is not NULL, then the ACPI 2.0 resource descriptors that the PCI 467 controller is currently using are returned in Resources. 468 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL. 469 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller. 470 @retval EFI_OUT_OF_RESOURCES There are not enough resources available to allocate 471 Resources. 472 473**/ 474typedef 475EFI_STATUS 476(EFIAPI *EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES)( 477 IN EFI_PCI_IO_PROTOCOL *This, 478 IN UINT8 BarIndex, 479 OUT UINT64 *Supports, OPTIONAL 480 OUT VOID **Resources OPTIONAL 481 ); 482 483/** 484 Sets the attributes for a range of a BAR on a PCI controller. 485 486 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance. 487 @param Attributes The mask of attributes to set for the resource range specified by 488 BarIndex, Offset, and Length. 489 @param BarIndex The BAR index of the standard PCI Configuration header to use as the 490 base address for resource range. The legal range for this field is 0..5. 491 @param Offset A pointer to the BAR relative base address of the resource range to be 492 modified by the attributes specified by Attributes. 493 @param Length A pointer to the length of the resource range to be modified by the 494 attributes specified by Attributes. 495 496 @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource 497 range specified by BarIndex, Offset, and Length were 498 set on the PCI controller, and the actual resource range is returned 499 in Offset and Length. 500 @retval EFI_INVALID_PARAMETER Offset or Length is NULL. 501 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller. 502 @retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the 503 resource range specified by BarIndex, Offset, and 504 Length. 505 506**/ 507typedef 508EFI_STATUS 509(EFIAPI *EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES)( 510 IN EFI_PCI_IO_PROTOCOL *This, 511 IN UINT64 Attributes, 512 IN UINT8 BarIndex, 513 IN OUT UINT64 *Offset, 514 IN OUT UINT64 *Length 515 ); 516 517/// 518/// The EFI_PCI_IO_PROTOCOL provides the basic Memory, I/O, PCI configuration, 519/// and DMA interfaces used to abstract accesses to PCI controllers. 520/// There is one EFI_PCI_IO_PROTOCOL instance for each PCI controller on a PCI bus. 521/// A device driver that wishes to manage a PCI controller in a system will have to 522/// retrieve the EFI_PCI_IO_PROTOCOL instance that is associated with the PCI controller. 523/// 524struct _EFI_PCI_IO_PROTOCOL { 525 EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollMem; 526 EFI_PCI_IO_PROTOCOL_POLL_IO_MEM PollIo; 527 EFI_PCI_IO_PROTOCOL_ACCESS Mem; 528 EFI_PCI_IO_PROTOCOL_ACCESS Io; 529 EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS Pci; 530 EFI_PCI_IO_PROTOCOL_COPY_MEM CopyMem; 531 EFI_PCI_IO_PROTOCOL_MAP Map; 532 EFI_PCI_IO_PROTOCOL_UNMAP Unmap; 533 EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER AllocateBuffer; 534 EFI_PCI_IO_PROTOCOL_FREE_BUFFER FreeBuffer; 535 EFI_PCI_IO_PROTOCOL_FLUSH Flush; 536 EFI_PCI_IO_PROTOCOL_GET_LOCATION GetLocation; 537 EFI_PCI_IO_PROTOCOL_ATTRIBUTES Attributes; 538 EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES GetBarAttributes; 539 EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES SetBarAttributes; 540 541 /// 542 /// The size, in bytes, of the ROM image. 543 /// 544 UINT64 RomSize; 545 546 /// 547 /// A pointer to the in memory copy of the ROM image. The PCI Bus Driver is responsible 548 /// for allocating memory for the ROM image, and copying the contents of the ROM to memory. 549 /// The contents of this buffer are either from the PCI option ROM that can be accessed 550 /// through the ROM BAR of the PCI controller, or it is from a platform-specific location. 551 /// The Attributes() function can be used to determine from which of these two sources 552 /// the RomImage buffer was initialized. 553 /// 554 VOID *RomImage; 555}; 556 557extern EFI_GUID gEfiPciIoProtocolGuid; 558 559#endif 560