1//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This tablegen backend is responsible for emitting a description of the target
10// instruction set for the code generator.
11//
12//===----------------------------------------------------------------------===//
13
14#include "CodeGenDAGPatterns.h"
15#include "CodeGenInstruction.h"
16#include "CodeGenSchedule.h"
17#include "CodeGenTarget.h"
18#include "PredicateExpander.h"
19#include "SequenceToOffsetTable.h"
20#include "SubtargetFeatureInfo.h"
21#include "TableGenBackends.h"
22#include "Types.h"
23#include "llvm/ADT/ArrayRef.h"
24#include "llvm/ADT/STLExtras.h"
25#include "llvm/ADT/SmallVector.h"
26#include "llvm/ADT/StringExtras.h"
27#include "llvm/Support/Casting.h"
28#include "llvm/Support/raw_ostream.h"
29#include "llvm/TableGen/Error.h"
30#include "llvm/TableGen/Record.h"
31#include "llvm/TableGen/TableGenBackend.h"
32#include <cassert>
33#include <cstdint>
34#include <iterator>
35#include <map>
36#include <string>
37#include <utility>
38#include <vector>
39
40using namespace llvm;
41
42cl::OptionCategory InstrInfoEmitterCat("Options for -gen-instr-info");
43static cl::opt<bool> ExpandMIOperandInfo(
44    "instr-info-expand-mi-operand-info",
45    cl::desc("Expand operand's MIOperandInfo DAG into suboperands"),
46    cl::cat(InstrInfoEmitterCat), cl::init(true));
47
48namespace {
49
50class InstrInfoEmitter {
51  RecordKeeper &Records;
52  CodeGenDAGPatterns CDP;
53  const CodeGenSchedModels &SchedModels;
54
55public:
56  InstrInfoEmitter(RecordKeeper &R):
57    Records(R), CDP(R), SchedModels(CDP.getTargetInfo().getSchedModels()) {}
58
59  // run - Output the instruction set description.
60  void run(raw_ostream &OS);
61
62private:
63  void emitEnums(raw_ostream &OS);
64
65  typedef std::vector<std::string> OperandInfoTy;
66  typedef std::vector<OperandInfoTy> OperandInfoListTy;
67  typedef std::map<OperandInfoTy, unsigned> OperandInfoMapTy;
68
69  /// The keys of this map are maps which have OpName enum values as their keys
70  /// and instruction operand indices as their values.  The values of this map
71  /// are lists of instruction names.
72  typedef std::map<std::map<unsigned, unsigned>,
73                   std::vector<std::string>> OpNameMapTy;
74  typedef std::map<std::string, unsigned>::iterator StrUintMapIter;
75
76  /// Generate member functions in the target-specific GenInstrInfo class.
77  ///
78  /// This method is used to custom expand TIIPredicate definitions.
79  /// See file llvm/Target/TargetInstPredicates.td for a description of what is
80  /// a TIIPredicate and how to use it.
81  void emitTIIHelperMethods(raw_ostream &OS, StringRef TargetName,
82                            bool ExpandDefinition = true);
83
84  /// Expand TIIPredicate definitions to functions that accept a const MCInst
85  /// reference.
86  void emitMCIIHelperMethods(raw_ostream &OS, StringRef TargetName);
87
88  /// Write verifyInstructionPredicates methods.
89  void emitFeatureVerifier(raw_ostream &OS, const CodeGenTarget &Target);
90  void emitRecord(const CodeGenInstruction &Inst, unsigned Num,
91                  Record *InstrInfo,
92                  std::map<std::vector<Record *>, unsigned> &EL,
93                  const OperandInfoMapTy &OperandInfo, raw_ostream &OS);
94  void emitOperandTypeMappings(
95      raw_ostream &OS, const CodeGenTarget &Target,
96      ArrayRef<const CodeGenInstruction *> NumberedInstructions);
97  void initOperandMapData(
98            ArrayRef<const CodeGenInstruction *> NumberedInstructions,
99            StringRef Namespace,
100            std::map<std::string, unsigned> &Operands,
101            OpNameMapTy &OperandMap);
102  void emitOperandNameMappings(raw_ostream &OS, const CodeGenTarget &Target,
103            ArrayRef<const CodeGenInstruction*> NumberedInstructions);
104
105  void emitLogicalOperandSizeMappings(
106      raw_ostream &OS, StringRef Namespace,
107      ArrayRef<const CodeGenInstruction *> NumberedInstructions);
108  void emitLogicalOperandTypeMappings(
109      raw_ostream &OS, StringRef Namespace,
110      ArrayRef<const CodeGenInstruction *> NumberedInstructions);
111
112  // Operand information.
113  unsigned CollectOperandInfo(OperandInfoListTy &OperandInfoList,
114                              OperandInfoMapTy &OperandInfoMap);
115  void EmitOperandInfo(raw_ostream &OS, OperandInfoListTy &OperandInfoList);
116  OperandInfoTy GetOperandInfo(const CodeGenInstruction &Inst);
117};
118
119} // end anonymous namespace
120
121//===----------------------------------------------------------------------===//
122// Operand Info Emission.
123//===----------------------------------------------------------------------===//
124
125InstrInfoEmitter::OperandInfoTy
126InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
127  OperandInfoTy Result;
128
129  for (auto &Op : Inst.Operands) {
130    // Handle aggregate operands and normal operands the same way by expanding
131    // either case into a list of operands for this op.
132    std::vector<CGIOperandList::OperandInfo> OperandList;
133
134    // This might be a multiple operand thing.  Targets like X86 have
135    // registers in their multi-operand operands.  It may also be an anonymous
136    // operand, which has a single operand, but no declared class for the
137    // operand.
138    DagInit *MIOI = Op.MIOperandInfo;
139
140    if (!MIOI || MIOI->getNumArgs() == 0) {
141      // Single, anonymous, operand.
142      OperandList.push_back(Op);
143    } else {
144      for (unsigned j = 0, e = Op.MINumOperands; j != e; ++j) {
145        OperandList.push_back(Op);
146
147        auto *OpR = cast<DefInit>(MIOI->getArg(j))->getDef();
148        OperandList.back().Rec = OpR;
149      }
150    }
151
152    for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
153      Record *OpR = OperandList[j].Rec;
154      std::string Res;
155
156      if (OpR->isSubClassOf("RegisterOperand"))
157        OpR = OpR->getValueAsDef("RegClass");
158      if (OpR->isSubClassOf("RegisterClass"))
159        Res += getQualifiedName(OpR) + "RegClassID, ";
160      else if (OpR->isSubClassOf("PointerLikeRegClass"))
161        Res += utostr(OpR->getValueAsInt("RegClassKind")) + ", ";
162      else
163        // -1 means the operand does not have a fixed register class.
164        Res += "-1, ";
165
166      // Fill in applicable flags.
167      Res += "0";
168
169      // Ptr value whose register class is resolved via callback.
170      if (OpR->isSubClassOf("PointerLikeRegClass"))
171        Res += "|(1<<MCOI::LookupPtrRegClass)";
172
173      // Predicate operands.  Check to see if the original unexpanded operand
174      // was of type PredicateOp.
175      if (Op.Rec->isSubClassOf("PredicateOp"))
176        Res += "|(1<<MCOI::Predicate)";
177
178      // Optional def operands.  Check to see if the original unexpanded operand
179      // was of type OptionalDefOperand.
180      if (Op.Rec->isSubClassOf("OptionalDefOperand"))
181        Res += "|(1<<MCOI::OptionalDef)";
182
183      // Branch target operands.  Check to see if the original unexpanded
184      // operand was of type BranchTargetOperand.
185      if (Op.Rec->isSubClassOf("BranchTargetOperand"))
186        Res += "|(1<<MCOI::BranchTarget)";
187
188      // Fill in operand type.
189      Res += ", ";
190      assert(!Op.OperandType.empty() && "Invalid operand type.");
191      Res += Op.OperandType;
192
193      // Fill in constraint info.
194      Res += ", ";
195
196      const CGIOperandList::ConstraintInfo &Constraint =
197        Op.Constraints[j];
198      if (Constraint.isNone())
199        Res += "0";
200      else if (Constraint.isEarlyClobber())
201        Res += "MCOI_EARLY_CLOBBER";
202      else {
203        assert(Constraint.isTied());
204        Res += "MCOI_TIED_TO(" + utostr(Constraint.getTiedOperand()) + ")";
205      }
206
207      Result.push_back(Res);
208    }
209  }
210
211  return Result;
212}
213
214unsigned
215InstrInfoEmitter::CollectOperandInfo(OperandInfoListTy &OperandInfoList,
216                                     OperandInfoMapTy &OperandInfoMap) {
217  const CodeGenTarget &Target = CDP.getTargetInfo();
218  unsigned Offset = 0;
219  for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
220    OperandInfoTy OperandInfo = GetOperandInfo(*Inst);
221    if (OperandInfoMap.insert({OperandInfo, Offset}).second) {
222      OperandInfoList.push_back(OperandInfo);
223      Offset += OperandInfo.size();
224    }
225  }
226  return Offset;
227}
228
229void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS,
230                                       OperandInfoListTy &OperandInfoList) {
231  unsigned Offset = 0;
232  for (auto &OperandInfo : OperandInfoList) {
233    OS << "    /* " << Offset << " */";
234    for (auto &Info : OperandInfo)
235      OS << " { " << Info << " },";
236    OS << '\n';
237    Offset += OperandInfo.size();
238  }
239}
240
241/// Initialize data structures for generating operand name mappings.
242///
243/// \param Operands [out] A map used to generate the OpName enum with operand
244///        names as its keys and operand enum values as its values.
245/// \param OperandMap [out] A map for representing the operand name mappings for
246///        each instructions.  This is used to generate the OperandMap table as
247///        well as the getNamedOperandIdx() function.
248void InstrInfoEmitter::initOperandMapData(
249        ArrayRef<const CodeGenInstruction *> NumberedInstructions,
250        StringRef Namespace,
251        std::map<std::string, unsigned> &Operands,
252        OpNameMapTy &OperandMap) {
253  unsigned NumOperands = 0;
254  for (const CodeGenInstruction *Inst : NumberedInstructions) {
255    if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable"))
256      continue;
257    std::map<unsigned, unsigned> OpList;
258    for (const auto &Info : Inst->Operands) {
259      StrUintMapIter I = Operands.find(Info.Name);
260
261      if (I == Operands.end()) {
262        I = Operands.insert(Operands.begin(),
263                    std::pair<std::string, unsigned>(Info.Name, NumOperands++));
264      }
265      OpList[I->second] = Info.MIOperandNo;
266    }
267    OperandMap[OpList].push_back(Namespace.str() + "::" +
268                                 Inst->TheDef->getName().str());
269  }
270}
271
272/// Generate a table and function for looking up the indices of operands by
273/// name.
274///
275/// This code generates:
276/// - An enum in the llvm::TargetNamespace::OpName namespace, with one entry
277///   for each operand name.
278/// - A 2-dimensional table called OperandMap for mapping OpName enum values to
279///   operand indices.
280/// - A function called getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
281///   for looking up the operand index for an instruction, given a value from
282///   OpName enum
283void InstrInfoEmitter::emitOperandNameMappings(raw_ostream &OS,
284           const CodeGenTarget &Target,
285           ArrayRef<const CodeGenInstruction*> NumberedInstructions) {
286  StringRef Namespace = Target.getInstNamespace();
287  std::string OpNameNS = "OpName";
288  // Map of operand names to their enumeration value.  This will be used to
289  // generate the OpName enum.
290  std::map<std::string, unsigned> Operands;
291  OpNameMapTy OperandMap;
292
293  initOperandMapData(NumberedInstructions, Namespace, Operands, OperandMap);
294
295  OS << "#ifdef GET_INSTRINFO_OPERAND_ENUM\n";
296  OS << "#undef GET_INSTRINFO_OPERAND_ENUM\n";
297  OS << "namespace llvm {\n";
298  OS << "namespace " << Namespace << " {\n";
299  OS << "namespace " << OpNameNS << " {\n";
300  OS << "enum {\n";
301  for (const auto &Op : Operands)
302    OS << "  " << Op.first << " = " << Op.second << ",\n";
303
304  OS << "  OPERAND_LAST";
305  OS << "\n};\n";
306  OS << "} // end namespace OpName\n";
307  OS << "} // end namespace " << Namespace << "\n";
308  OS << "} // end namespace llvm\n";
309  OS << "#endif //GET_INSTRINFO_OPERAND_ENUM\n\n";
310
311  OS << "#ifdef GET_INSTRINFO_NAMED_OPS\n";
312  OS << "#undef GET_INSTRINFO_NAMED_OPS\n";
313  OS << "namespace llvm {\n";
314  OS << "namespace " << Namespace << " {\n";
315  OS << "LLVM_READONLY\n";
316  OS << "int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {\n";
317  if (!Operands.empty()) {
318    OS << "  static const int16_t OperandMap [][" << Operands.size()
319       << "] = {\n";
320    for (const auto &Entry : OperandMap) {
321      const std::map<unsigned, unsigned> &OpList = Entry.first;
322      OS << "{";
323
324      // Emit a row of the OperandMap table
325      for (unsigned i = 0, e = Operands.size(); i != e; ++i)
326        OS << (OpList.count(i) == 0 ? -1 : (int)OpList.find(i)->second) << ", ";
327
328      OS << "},\n";
329    }
330    OS << "};\n";
331
332    OS << "  switch(Opcode) {\n";
333    unsigned TableIndex = 0;
334    for (const auto &Entry : OperandMap) {
335      for (const std::string &Name : Entry.second)
336        OS << "  case " << Name << ":\n";
337
338      OS << "    return OperandMap[" << TableIndex++ << "][NamedIdx];\n";
339    }
340    OS << "  default: return -1;\n";
341    OS << "  }\n";
342  } else {
343    // There are no operands, so no need to emit anything
344    OS << "  return -1;\n";
345  }
346  OS << "}\n";
347  OS << "} // end namespace " << Namespace << "\n";
348  OS << "} // end namespace llvm\n";
349  OS << "#endif //GET_INSTRINFO_NAMED_OPS\n\n";
350}
351
352/// Generate an enum for all the operand types for this target, under the
353/// llvm::TargetNamespace::OpTypes namespace.
354/// Operand types are all definitions derived of the Operand Target.td class.
355void InstrInfoEmitter::emitOperandTypeMappings(
356    raw_ostream &OS, const CodeGenTarget &Target,
357    ArrayRef<const CodeGenInstruction *> NumberedInstructions) {
358
359  StringRef Namespace = Target.getInstNamespace();
360  std::vector<Record *> Operands = Records.getAllDerivedDefinitions("Operand");
361  std::vector<Record *> RegisterOperands =
362      Records.getAllDerivedDefinitions("RegisterOperand");
363  std::vector<Record *> RegisterClasses =
364      Records.getAllDerivedDefinitions("RegisterClass");
365
366  OS << "#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
367  OS << "#undef GET_INSTRINFO_OPERAND_TYPES_ENUM\n";
368  OS << "namespace llvm {\n";
369  OS << "namespace " << Namespace << " {\n";
370  OS << "namespace OpTypes {\n";
371  OS << "enum OperandType {\n";
372
373  unsigned EnumVal = 0;
374  for (const std::vector<Record *> *RecordsToAdd :
375       {&Operands, &RegisterOperands, &RegisterClasses}) {
376    for (const Record *Op : *RecordsToAdd) {
377      if (!Op->isAnonymous())
378        OS << "  " << Op->getName() << " = " << EnumVal << ",\n";
379      ++EnumVal;
380    }
381  }
382
383  OS << "  OPERAND_TYPE_LIST_END" << "\n};\n";
384  OS << "} // end namespace OpTypes\n";
385  OS << "} // end namespace " << Namespace << "\n";
386  OS << "} // end namespace llvm\n";
387  OS << "#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM\n\n";
388
389  OS << "#ifdef GET_INSTRINFO_OPERAND_TYPE\n";
390  OS << "#undef GET_INSTRINFO_OPERAND_TYPE\n";
391  OS << "namespace llvm {\n";
392  OS << "namespace " << Namespace << " {\n";
393  OS << "LLVM_READONLY\n";
394  OS << "static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {\n";
395  auto getInstrName = [&](int I) -> StringRef {
396    return NumberedInstructions[I]->TheDef->getName();
397  };
398  // TODO: Factor out duplicate operand lists to compress the tables.
399  if (!NumberedInstructions.empty()) {
400    std::vector<int> OperandOffsets;
401    std::vector<Record *> OperandRecords;
402    int CurrentOffset = 0;
403    for (const CodeGenInstruction *Inst : NumberedInstructions) {
404      OperandOffsets.push_back(CurrentOffset);
405      for (const auto &Op : Inst->Operands) {
406        const DagInit *MIOI = Op.MIOperandInfo;
407        if (!ExpandMIOperandInfo || !MIOI || MIOI->getNumArgs() == 0) {
408          // Single, anonymous, operand.
409          OperandRecords.push_back(Op.Rec);
410          ++CurrentOffset;
411        } else {
412          for (Init *Arg : MIOI->getArgs()) {
413            OperandRecords.push_back(cast<DefInit>(Arg)->getDef());
414            ++CurrentOffset;
415          }
416        }
417      }
418    }
419
420    // Emit the table of offsets (indexes) into the operand type table.
421    // Size the unsigned integer offset to save space.
422    assert(OperandRecords.size() <= UINT32_MAX &&
423           "Too many operands for offset table");
424    OS << "  static const " << getMinimalTypeForRange(OperandRecords.size());
425    OS << " Offsets[] = {\n";
426    for (int I = 0, E = OperandOffsets.size(); I != E; ++I) {
427      OS << "    /* " << getInstrName(I) << " */\n";
428      OS << "    " << OperandOffsets[I] << ",\n";
429    }
430    OS << "  };\n";
431
432    // Add an entry for the end so that we don't need to special case it below.
433    OperandOffsets.push_back(OperandRecords.size());
434
435    // Emit the actual operand types in a flat table.
436    // Size the signed integer operand type to save space.
437    assert(EnumVal <= INT16_MAX &&
438           "Too many operand types for operand types table");
439    OS << "\n  using namespace OpTypes;\n";
440    OS << "  static";
441    OS << ((EnumVal <= INT8_MAX) ? " const int8_t" : " const int16_t");
442    OS << " OpcodeOperandTypes[] = {\n    ";
443    for (int I = 0, E = OperandRecords.size(), CurOffset = 0; I != E; ++I) {
444      // We print each Opcode's operands in its own row.
445      if (I == OperandOffsets[CurOffset]) {
446        OS << "\n    /* " << getInstrName(CurOffset) << " */\n    ";
447        while (OperandOffsets[++CurOffset] == I)
448          OS << "/* " << getInstrName(CurOffset) << " */\n    ";
449      }
450      Record *OpR = OperandRecords[I];
451      if ((OpR->isSubClassOf("Operand") ||
452           OpR->isSubClassOf("RegisterOperand") ||
453           OpR->isSubClassOf("RegisterClass")) &&
454          !OpR->isAnonymous())
455        OS << OpR->getName();
456      else
457        OS << -1;
458      OS << ", ";
459    }
460    OS << "\n  };\n";
461
462    OS << "  return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];\n";
463  } else {
464    OS << "  llvm_unreachable(\"No instructions defined\");\n";
465  }
466  OS << "}\n";
467  OS << "} // end namespace " << Namespace << "\n";
468  OS << "} // end namespace llvm\n";
469  OS << "#endif // GET_INSTRINFO_OPERAND_TYPE\n\n";
470
471  OS << "#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE\n";
472  OS << "#undef GET_INSTRINFO_MEM_OPERAND_SIZE\n";
473  OS << "namespace llvm {\n";
474  OS << "namespace " << Namespace << " {\n";
475  OS << "LLVM_READONLY\n";
476  OS << "static int getMemOperandSize(int OpType) {\n";
477  OS << "  switch (OpType) {\n";
478  std::map<int, SmallVector<StringRef, 0>> SizeToOperandName;
479  for (const Record *Op : Operands) {
480    if (!Op->isSubClassOf("X86MemOperand"))
481      continue;
482    if (int Size = Op->getValueAsInt("Size"))
483      SizeToOperandName[Size].push_back(Op->getName());
484  }
485  OS << "  default: return 0;\n";
486  for (const auto &KV : SizeToOperandName) {
487    for (const StringRef &OperandName : KV.second)
488      OS << "  case OpTypes::" << OperandName << ":\n";
489    OS << "    return " << KV.first << ";\n\n";
490  }
491  OS << "  }\n}\n";
492  OS << "} // end namespace " << Namespace << "\n";
493  OS << "} // end namespace llvm\n";
494  OS << "#endif // GET_INSTRINFO_MEM_OPERAND_SIZE\n\n";
495}
496
497void InstrInfoEmitter::emitLogicalOperandSizeMappings(
498    raw_ostream &OS, StringRef Namespace,
499    ArrayRef<const CodeGenInstruction *> NumberedInstructions) {
500  std::map<std::vector<unsigned>, unsigned> LogicalOpSizeMap;
501
502  std::map<unsigned, std::vector<std::string>> InstMap;
503
504  size_t LogicalOpListSize = 0U;
505  std::vector<unsigned> LogicalOpList;
506  for (const auto *Inst : NumberedInstructions) {
507    if (!Inst->TheDef->getValueAsBit("UseLogicalOperandMappings"))
508      continue;
509
510    LogicalOpList.clear();
511    llvm::transform(Inst->Operands, std::back_inserter(LogicalOpList),
512                    [](const CGIOperandList::OperandInfo &Op) -> unsigned {
513                      auto *MIOI = Op.MIOperandInfo;
514                      if (!MIOI || MIOI->getNumArgs() == 0)
515                        return 1;
516                      return MIOI->getNumArgs();
517                    });
518    LogicalOpListSize = std::max(LogicalOpList.size(), LogicalOpListSize);
519
520    auto I =
521        LogicalOpSizeMap.insert({LogicalOpList, LogicalOpSizeMap.size()}).first;
522    InstMap[I->second].push_back(
523        (Namespace + "::" + Inst->TheDef->getName()).str());
524  }
525
526  OS << "#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP\n";
527  OS << "#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP\n";
528  OS << "namespace llvm {\n";
529  OS << "namespace " << Namespace << " {\n";
530  OS << "LLVM_READONLY static unsigned\n";
531  OS << "getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {\n";
532  if (!InstMap.empty()) {
533    std::vector<const std::vector<unsigned> *> LogicalOpSizeList(
534        LogicalOpSizeMap.size());
535    for (auto &P : LogicalOpSizeMap) {
536      LogicalOpSizeList[P.second] = &P.first;
537    }
538    OS << "  static const unsigned SizeMap[][" << LogicalOpListSize
539       << "] = {\n";
540    for (auto &R : LogicalOpSizeList) {
541      const auto &Row = *R;
542      OS << "   {";
543      int i;
544      for (i = 0; i < static_cast<int>(Row.size()); ++i) {
545        OS << Row[i] << ", ";
546      }
547      for (; i < static_cast<int>(LogicalOpListSize); ++i) {
548        OS << "0, ";
549      }
550      OS << "}, ";
551      OS << "\n";
552    }
553    OS << "  };\n";
554
555    OS << "  switch (Opcode) {\n";
556    OS << "  default: return LogicalOpIdx;\n";
557    for (auto &P : InstMap) {
558      auto OpMapIdx = P.first;
559      const auto &Insts = P.second;
560      for (const auto &Inst : Insts) {
561        OS << "  case " << Inst << ":\n";
562      }
563      OS << "    return SizeMap[" << OpMapIdx << "][LogicalOpIdx];\n";
564    }
565    OS << "  }\n";
566  } else {
567    OS << "  return LogicalOpIdx;\n";
568  }
569  OS << "}\n";
570
571  OS << "LLVM_READONLY static inline unsigned\n";
572  OS << "getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {\n";
573  OS << "  auto S = 0U;\n";
574  OS << "  for (auto i = 0U; i < LogicalOpIdx; ++i)\n";
575  OS << "    S += getLogicalOperandSize(Opcode, i);\n";
576  OS << "  return S;\n";
577  OS << "}\n";
578
579  OS << "} // end namespace " << Namespace << "\n";
580  OS << "} // end namespace llvm\n";
581  OS << "#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP\n\n";
582}
583
584void InstrInfoEmitter::emitLogicalOperandTypeMappings(
585    raw_ostream &OS, StringRef Namespace,
586    ArrayRef<const CodeGenInstruction *> NumberedInstructions) {
587  std::map<std::vector<std::string>, unsigned> LogicalOpTypeMap;
588
589  std::map<unsigned, std::vector<std::string>> InstMap;
590
591  size_t OpTypeListSize = 0U;
592  std::vector<std::string> LogicalOpTypeList;
593  for (const auto *Inst : NumberedInstructions) {
594    if (!Inst->TheDef->getValueAsBit("UseLogicalOperandMappings"))
595      continue;
596
597    LogicalOpTypeList.clear();
598    for (const auto &Op : Inst->Operands) {
599      auto *OpR = Op.Rec;
600      if ((OpR->isSubClassOf("Operand") ||
601           OpR->isSubClassOf("RegisterOperand") ||
602           OpR->isSubClassOf("RegisterClass")) &&
603          !OpR->isAnonymous()) {
604        LogicalOpTypeList.push_back(
605            (Namespace + "::OpTypes::" + Op.Rec->getName()).str());
606      } else {
607        LogicalOpTypeList.push_back("-1");
608      }
609    }
610    OpTypeListSize = std::max(LogicalOpTypeList.size(), OpTypeListSize);
611
612    auto I =
613        LogicalOpTypeMap.insert({LogicalOpTypeList, LogicalOpTypeMap.size()})
614            .first;
615    InstMap[I->second].push_back(
616        (Namespace + "::" + Inst->TheDef->getName()).str());
617  }
618
619  OS << "#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP\n";
620  OS << "#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP\n";
621  OS << "namespace llvm {\n";
622  OS << "namespace " << Namespace << " {\n";
623  OS << "LLVM_READONLY static int\n";
624  OS << "getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {\n";
625  if (!InstMap.empty()) {
626    std::vector<const std::vector<std::string> *> LogicalOpTypeList(
627        LogicalOpTypeMap.size());
628    for (auto &P : LogicalOpTypeMap) {
629      LogicalOpTypeList[P.second] = &P.first;
630    }
631    OS << "  static const int TypeMap[][" << OpTypeListSize << "] = {\n";
632    for (int r = 0, rs = LogicalOpTypeList.size(); r < rs; ++r) {
633      const auto &Row = *LogicalOpTypeList[r];
634      OS << "   {";
635      int i, s = Row.size();
636      for (i = 0; i < s; ++i) {
637        if (i > 0)
638          OS << ", ";
639        OS << Row[i];
640      }
641      for (; i < static_cast<int>(OpTypeListSize); ++i) {
642        if (i > 0)
643          OS << ", ";
644        OS << "-1";
645      }
646      OS << "}";
647      if (r != rs - 1)
648        OS << ",";
649      OS << "\n";
650    }
651    OS << "  };\n";
652
653    OS << "  switch (Opcode) {\n";
654    OS << "  default: return -1;\n";
655    for (auto &P : InstMap) {
656      auto OpMapIdx = P.first;
657      const auto &Insts = P.second;
658      for (const auto &Inst : Insts) {
659        OS << "  case " << Inst << ":\n";
660      }
661      OS << "    return TypeMap[" << OpMapIdx << "][LogicalOpIdx];\n";
662    }
663    OS << "  }\n";
664  } else {
665    OS << "  return -1;\n";
666  }
667  OS << "}\n";
668  OS << "} // end namespace " << Namespace << "\n";
669  OS << "} // end namespace llvm\n";
670  OS << "#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP\n\n";
671}
672
673void InstrInfoEmitter::emitMCIIHelperMethods(raw_ostream &OS,
674                                             StringRef TargetName) {
675  RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate");
676
677  OS << "#ifdef GET_INSTRINFO_MC_HELPER_DECLS\n";
678  OS << "#undef GET_INSTRINFO_MC_HELPER_DECLS\n\n";
679
680  OS << "namespace llvm {\n";
681  OS << "class MCInst;\n";
682  OS << "class FeatureBitset;\n\n";
683
684  OS << "namespace " << TargetName << "_MC {\n\n";
685
686  for (const Record *Rec : TIIPredicates) {
687    OS << "bool " << Rec->getValueAsString("FunctionName")
688        << "(const MCInst &MI);\n";
689  }
690
691  OS << "void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset "
692        "&Features);\n";
693
694  OS << "\n} // end namespace " << TargetName << "_MC\n";
695  OS << "} // end namespace llvm\n\n";
696
697  OS << "#endif // GET_INSTRINFO_MC_HELPER_DECLS\n\n";
698
699  OS << "#ifdef GET_INSTRINFO_MC_HELPERS\n";
700  OS << "#undef GET_INSTRINFO_MC_HELPERS\n\n";
701
702  OS << "namespace llvm {\n";
703  OS << "namespace " << TargetName << "_MC {\n\n";
704
705  PredicateExpander PE(TargetName);
706  PE.setExpandForMC(true);
707
708  for (const Record *Rec : TIIPredicates) {
709    OS << "bool " << Rec->getValueAsString("FunctionName");
710    OS << "(const MCInst &MI) {\n";
711
712    OS.indent(PE.getIndentLevel() * 2);
713    PE.expandStatement(OS, Rec->getValueAsDef("Body"));
714    OS << "\n}\n\n";
715  }
716
717  OS << "} // end namespace " << TargetName << "_MC\n";
718  OS << "} // end namespace llvm\n\n";
719
720  OS << "#endif // GET_GENISTRINFO_MC_HELPERS\n\n";
721}
722
723static std::string
724getNameForFeatureBitset(const std::vector<Record *> &FeatureBitset) {
725  std::string Name = "CEFBS";
726  for (const auto &Feature : FeatureBitset)
727    Name += ("_" + Feature->getName()).str();
728  return Name;
729}
730
731void InstrInfoEmitter::emitFeatureVerifier(raw_ostream &OS,
732                                           const CodeGenTarget &Target) {
733  const auto &All = SubtargetFeatureInfo::getAll(Records);
734  std::map<Record *, SubtargetFeatureInfo, LessRecordByID> SubtargetFeatures;
735  SubtargetFeatures.insert(All.begin(), All.end());
736
737  OS << "#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) "
738     << "||\\\n"
739     << "    defined(GET_AVAILABLE_OPCODE_CHECKER)\n"
740     << "#define GET_COMPUTE_FEATURES\n"
741     << "#endif\n";
742  OS << "#ifdef GET_COMPUTE_FEATURES\n"
743     << "#undef GET_COMPUTE_FEATURES\n"
744     << "namespace llvm {\n"
745     << "namespace " << Target.getName() << "_MC {\n\n";
746
747  // Emit the subtarget feature enumeration.
748  SubtargetFeatureInfo::emitSubtargetFeatureBitEnumeration(SubtargetFeatures,
749                                                           OS);
750  // Emit the available features compute function.
751  OS << "inline ";
752  SubtargetFeatureInfo::emitComputeAssemblerAvailableFeatures(
753      Target.getName(), "", "computeAvailableFeatures", SubtargetFeatures, OS);
754
755  std::vector<std::vector<Record *>> FeatureBitsets;
756  for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
757    FeatureBitsets.emplace_back();
758    for (Record *Predicate : Inst->TheDef->getValueAsListOfDefs("Predicates")) {
759      const auto &I = SubtargetFeatures.find(Predicate);
760      if (I != SubtargetFeatures.end())
761        FeatureBitsets.back().push_back(I->second.TheDef);
762    }
763  }
764
765  llvm::sort(FeatureBitsets, [&](const std::vector<Record *> &A,
766                                 const std::vector<Record *> &B) {
767    if (A.size() < B.size())
768      return true;
769    if (A.size() > B.size())
770      return false;
771    for (auto Pair : zip(A, B)) {
772      if (std::get<0>(Pair)->getName() < std::get<1>(Pair)->getName())
773        return true;
774      if (std::get<0>(Pair)->getName() > std::get<1>(Pair)->getName())
775        return false;
776    }
777    return false;
778  });
779  FeatureBitsets.erase(
780      std::unique(FeatureBitsets.begin(), FeatureBitsets.end()),
781      FeatureBitsets.end());
782  OS << "inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {\n"
783     << "  enum : " << getMinimalTypeForRange(FeatureBitsets.size()) << " {\n"
784     << "    CEFBS_None,\n";
785  for (const auto &FeatureBitset : FeatureBitsets) {
786    if (FeatureBitset.empty())
787      continue;
788    OS << "    " << getNameForFeatureBitset(FeatureBitset) << ",\n";
789  }
790  OS << "  };\n\n"
791     << "  static constexpr FeatureBitset FeatureBitsets[] = {\n"
792     << "    {}, // CEFBS_None\n";
793  for (const auto &FeatureBitset : FeatureBitsets) {
794    if (FeatureBitset.empty())
795      continue;
796    OS << "    {";
797    for (const auto &Feature : FeatureBitset) {
798      const auto &I = SubtargetFeatures.find(Feature);
799      assert(I != SubtargetFeatures.end() && "Didn't import predicate?");
800      OS << I->second.getEnumBitName() << ", ";
801    }
802    OS << "},\n";
803  }
804  OS << "  };\n"
805     << "  static constexpr " << getMinimalTypeForRange(FeatureBitsets.size())
806     << " RequiredFeaturesRefs[] = {\n";
807  unsigned InstIdx = 0;
808  for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
809    OS << "    CEFBS";
810    unsigned NumPredicates = 0;
811    for (Record *Predicate : Inst->TheDef->getValueAsListOfDefs("Predicates")) {
812      const auto &I = SubtargetFeatures.find(Predicate);
813      if (I != SubtargetFeatures.end()) {
814        OS << '_' << I->second.TheDef->getName();
815        NumPredicates++;
816      }
817    }
818    if (!NumPredicates)
819      OS << "_None";
820    OS << ", // " << Inst->TheDef->getName() << " = " << InstIdx << "\n";
821    InstIdx++;
822  }
823  OS << "  };\n\n"
824     << "  assert(Opcode < " << InstIdx << ");\n"
825     << "  return FeatureBitsets[RequiredFeaturesRefs[Opcode]];\n"
826     << "}\n\n";
827
828  OS << "} // end namespace " << Target.getName() << "_MC\n"
829     << "} // end namespace llvm\n"
830     << "#endif // GET_COMPUTE_FEATURES\n\n";
831
832  OS << "#ifdef GET_AVAILABLE_OPCODE_CHECKER\n"
833     << "#undef GET_AVAILABLE_OPCODE_CHECKER\n"
834     << "namespace llvm {\n"
835     << "namespace " << Target.getName() << "_MC {\n";
836  OS << "bool isOpcodeAvailable("
837     << "unsigned Opcode, const FeatureBitset &Features) {\n"
838     << "  FeatureBitset AvailableFeatures = "
839     << "computeAvailableFeatures(Features);\n"
840     << "  FeatureBitset RequiredFeatures = "
841     << "computeRequiredFeatures(Opcode);\n"
842     << "  FeatureBitset MissingFeatures =\n"
843     << "      (AvailableFeatures & RequiredFeatures) ^\n"
844     << "      RequiredFeatures;\n"
845     << "  return !MissingFeatures.any();\n"
846     << "}\n";
847  OS << "} // end namespace " << Target.getName() << "_MC\n"
848     << "} // end namespace llvm\n"
849     << "#endif // GET_AVAILABLE_OPCODE_CHECKER\n\n";
850
851  OS << "#ifdef ENABLE_INSTR_PREDICATE_VERIFIER\n"
852     << "#undef ENABLE_INSTR_PREDICATE_VERIFIER\n"
853     << "#include <sstream>\n\n";
854
855  OS << "namespace llvm {\n";
856  OS << "namespace " << Target.getName() << "_MC {\n\n";
857
858  // Emit the name table for error messages.
859  OS << "#ifndef NDEBUG\n";
860  SubtargetFeatureInfo::emitNameTable(SubtargetFeatures, OS);
861  OS << "#endif // NDEBUG\n\n";
862
863  // Emit the predicate verifier.
864  OS << "void verifyInstructionPredicates(\n"
865     << "    unsigned Opcode, const FeatureBitset &Features) {\n"
866     << "#ifndef NDEBUG\n";
867  OS << "  FeatureBitset AvailableFeatures = "
868        "computeAvailableFeatures(Features);\n";
869  OS << "  FeatureBitset RequiredFeatures = "
870     << "computeRequiredFeatures(Opcode);\n";
871  OS << "  FeatureBitset MissingFeatures =\n"
872     << "      (AvailableFeatures & RequiredFeatures) ^\n"
873     << "      RequiredFeatures;\n"
874     << "  if (MissingFeatures.any()) {\n"
875     << "    std::ostringstream Msg;\n"
876     << "    Msg << \"Attempting to emit \" << &" << Target.getName()
877     << "InstrNameData[" << Target.getName() << "InstrNameIndices[Opcode]]\n"
878     << "        << \" instruction but the \";\n"
879     << "    for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)\n"
880     << "      if (MissingFeatures.test(i))\n"
881     << "        Msg << SubtargetFeatureNames[i] << \" \";\n"
882     << "    Msg << \"predicate(s) are not met\";\n"
883     << "    report_fatal_error(Msg.str().c_str());\n"
884     << "  }\n"
885     << "#endif // NDEBUG\n";
886  OS << "}\n";
887  OS << "} // end namespace " << Target.getName() << "_MC\n";
888  OS << "} // end namespace llvm\n";
889  OS << "#endif // ENABLE_INSTR_PREDICATE_VERIFIER\n\n";
890}
891
892void InstrInfoEmitter::emitTIIHelperMethods(raw_ostream &OS,
893                                            StringRef TargetName,
894                                            bool ExpandDefinition) {
895  RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate");
896  if (TIIPredicates.empty())
897    return;
898
899  PredicateExpander PE(TargetName);
900  PE.setExpandForMC(false);
901
902  for (const Record *Rec : TIIPredicates) {
903    OS << (ExpandDefinition ? "" : "static ") << "bool ";
904    if (ExpandDefinition)
905      OS << TargetName << "InstrInfo::";
906    OS << Rec->getValueAsString("FunctionName");
907    OS << "(const MachineInstr &MI)";
908    if (!ExpandDefinition) {
909      OS << ";\n";
910      continue;
911    }
912
913    OS << " {\n";
914    OS.indent(PE.getIndentLevel() * 2);
915    PE.expandStatement(OS, Rec->getValueAsDef("Body"));
916    OS << "\n}\n\n";
917  }
918}
919
920//===----------------------------------------------------------------------===//
921// Main Output.
922//===----------------------------------------------------------------------===//
923
924// run - Emit the main instruction description records for the target...
925void InstrInfoEmitter::run(raw_ostream &OS) {
926  emitSourceFileHeader("Target Instruction Enum Values and Descriptors", OS);
927  emitEnums(OS);
928
929  CodeGenTarget &Target = CDP.getTargetInfo();
930  const std::string &TargetName = std::string(Target.getName());
931  Record *InstrInfo = Target.getInstructionSet();
932
933  // Collect all of the operand info records.
934  Records.startTimer("Collect operand info");
935  OperandInfoListTy OperandInfoList;
936  OperandInfoMapTy OperandInfoMap;
937  unsigned OperandInfoSize =
938      CollectOperandInfo(OperandInfoList, OperandInfoMap);
939
940  // Collect all of the instruction's implicit uses and defs.
941  Records.startTimer("Collect uses/defs");
942  std::map<std::vector<Record*>, unsigned> EmittedLists;
943  std::vector<std::vector<Record *>> ImplicitLists;
944  unsigned ImplicitListSize = 0;
945  for (const CodeGenInstruction *II : Target.getInstructionsByEnumValue()) {
946    std::vector<Record *> ImplicitOps = II->ImplicitUses;
947    llvm::append_range(ImplicitOps, II->ImplicitDefs);
948    if (EmittedLists.insert({ImplicitOps, ImplicitListSize}).second) {
949      ImplicitLists.push_back(ImplicitOps);
950      ImplicitListSize += ImplicitOps.size();
951    }
952  }
953
954  ArrayRef<const CodeGenInstruction *> NumberedInstructions =
955      Target.getInstructionsByEnumValue();
956  OS << "#if defined(GET_INSTRINFO_MC_DESC) || "
957        "defined(GET_INSTRINFO_CTOR_DTOR)\n";
958  OS << "namespace llvm {\n\n";
959
960  OS << "struct " << TargetName << "InstrTable {\n";
961  OS << "  MCInstrDesc Insts[" << NumberedInstructions.size() << "];\n";
962  OS << "  static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "
963        "\"Unwanted padding between Insts and OperandInfo\");\n";
964  OS << "  MCOperandInfo OperandInfo[" << OperandInfoSize << "];\n";
965  OS << "  static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "
966        "\"Unwanted padding between OperandInfo and ImplicitOps\");\n";
967  OS << "  MCPhysReg ImplicitOps[" << std::max(ImplicitListSize, 1U) << "];\n";
968  OS << "};\n\n";
969
970  OS << "} // end namespace llvm\n";
971  OS << "#endif // defined(GET_INSTRINFO_MC_DESC) || "
972        "defined(GET_INSTRINFO_CTOR_DTOR)\n\n";
973
974  OS << "#ifdef GET_INSTRINFO_MC_DESC\n";
975  OS << "#undef GET_INSTRINFO_MC_DESC\n";
976  OS << "namespace llvm {\n\n";
977
978  // Emit all of the MCInstrDesc records in reverse ENUM ordering.
979  Records.startTimer("Emit InstrDesc records");
980  OS << "static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);\n";
981  OS << "static constexpr unsigned " << TargetName << "ImpOpBase = sizeof "
982     << TargetName << "InstrTable::OperandInfo / (sizeof(MCPhysReg));\n\n";
983
984  OS << "extern const " << TargetName << "InstrTable " << TargetName
985     << "Descs = {\n  {\n";
986  SequenceToOffsetTable<std::string> InstrNames;
987  unsigned Num = NumberedInstructions.size();
988  for (const CodeGenInstruction *Inst : reverse(NumberedInstructions)) {
989    // Keep a list of the instruction names.
990    InstrNames.add(std::string(Inst->TheDef->getName()));
991    // Emit the record into the table.
992    emitRecord(*Inst, --Num, InstrInfo, EmittedLists, OperandInfoMap, OS);
993  }
994
995  OS << "  }, {\n";
996
997  // Emit all of the operand info records.
998  Records.startTimer("Emit operand info");
999  EmitOperandInfo(OS, OperandInfoList);
1000
1001  OS << "  }, {\n";
1002
1003  // Emit all of the instruction's implicit uses and defs.
1004  Records.startTimer("Emit uses/defs");
1005  for (auto &List : ImplicitLists) {
1006    OS << "    /* " << EmittedLists[List] << " */";
1007    for (auto &Reg : List)
1008      OS << ' ' << getQualifiedName(Reg) << ',';
1009    OS << '\n';
1010  }
1011
1012  OS << "  }\n};\n\n";
1013
1014  // Emit the array of instruction names.
1015  Records.startTimer("Emit instruction names");
1016  InstrNames.layout();
1017  InstrNames.emitStringLiteralDef(OS, Twine("extern const char ") + TargetName +
1018                                          "InstrNameData[]");
1019
1020  OS << "extern const unsigned " << TargetName <<"InstrNameIndices[] = {";
1021  Num = 0;
1022  for (const CodeGenInstruction *Inst : NumberedInstructions) {
1023    // Newline every eight entries.
1024    if (Num % 8 == 0)
1025      OS << "\n    ";
1026    OS << InstrNames.get(std::string(Inst->TheDef->getName())) << "U, ";
1027    ++Num;
1028  }
1029  OS << "\n};\n\n";
1030
1031  bool HasDeprecationFeatures =
1032      llvm::any_of(NumberedInstructions, [](const CodeGenInstruction *Inst) {
1033        return !Inst->HasComplexDeprecationPredicate &&
1034               !Inst->DeprecatedReason.empty();
1035      });
1036  if (HasDeprecationFeatures) {
1037    OS << "extern const uint8_t " << TargetName
1038       << "InstrDeprecationFeatures[] = {";
1039    Num = 0;
1040    for (const CodeGenInstruction *Inst : NumberedInstructions) {
1041      if (Num % 8 == 0)
1042        OS << "\n    ";
1043      if (!Inst->HasComplexDeprecationPredicate &&
1044          !Inst->DeprecatedReason.empty())
1045        OS << Target.getInstNamespace() << "::" << Inst->DeprecatedReason
1046           << ", ";
1047      else
1048        OS << "uint8_t(-1), ";
1049      ++Num;
1050    }
1051    OS << "\n};\n\n";
1052  }
1053
1054  bool HasComplexDeprecationInfos =
1055      llvm::any_of(NumberedInstructions, [](const CodeGenInstruction *Inst) {
1056        return Inst->HasComplexDeprecationPredicate;
1057      });
1058  if (HasComplexDeprecationInfos) {
1059    OS << "extern const MCInstrInfo::ComplexDeprecationPredicate " << TargetName
1060       << "InstrComplexDeprecationInfos[] = {";
1061    Num = 0;
1062    for (const CodeGenInstruction *Inst : NumberedInstructions) {
1063      if (Num % 8 == 0)
1064        OS << "\n    ";
1065      if (Inst->HasComplexDeprecationPredicate)
1066        // Emit a function pointer to the complex predicate method.
1067        OS << "&get" << Inst->DeprecatedReason << "DeprecationInfo, ";
1068      else
1069        OS << "nullptr, ";
1070      ++Num;
1071    }
1072    OS << "\n};\n\n";
1073  }
1074
1075  // MCInstrInfo initialization routine.
1076  Records.startTimer("Emit initialization routine");
1077  OS << "static inline void Init" << TargetName
1078     << "MCInstrInfo(MCInstrInfo *II) {\n";
1079  OS << "  II->InitMCInstrInfo(" << TargetName << "Descs.Insts, " << TargetName
1080     << "InstrNameIndices, " << TargetName << "InstrNameData, ";
1081  if (HasDeprecationFeatures)
1082    OS << TargetName << "InstrDeprecationFeatures, ";
1083  else
1084    OS << "nullptr, ";
1085  if (HasComplexDeprecationInfos)
1086    OS << TargetName << "InstrComplexDeprecationInfos, ";
1087  else
1088    OS << "nullptr, ";
1089  OS << NumberedInstructions.size() << ");\n}\n\n";
1090
1091  OS << "} // end namespace llvm\n";
1092
1093  OS << "#endif // GET_INSTRINFO_MC_DESC\n\n";
1094
1095  // Create a TargetInstrInfo subclass to hide the MC layer initialization.
1096  OS << "#ifdef GET_INSTRINFO_HEADER\n";
1097  OS << "#undef GET_INSTRINFO_HEADER\n";
1098
1099  std::string ClassName = TargetName + "GenInstrInfo";
1100  OS << "namespace llvm {\n";
1101  OS << "struct " << ClassName << " : public TargetInstrInfo {\n"
1102     << "  explicit " << ClassName
1103     << "(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, "
1104        "unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);\n"
1105     << "  ~" << ClassName << "() override = default;\n";
1106
1107
1108  OS << "\n};\n} // end namespace llvm\n";
1109
1110  OS << "#endif // GET_INSTRINFO_HEADER\n\n";
1111
1112  OS << "#ifdef GET_INSTRINFO_HELPER_DECLS\n";
1113  OS << "#undef GET_INSTRINFO_HELPER_DECLS\n\n";
1114  emitTIIHelperMethods(OS, TargetName, /* ExpandDefinition = */ false);
1115  OS << "\n";
1116  OS << "#endif // GET_INSTRINFO_HELPER_DECLS\n\n";
1117
1118  OS << "#ifdef GET_INSTRINFO_HELPERS\n";
1119  OS << "#undef GET_INSTRINFO_HELPERS\n\n";
1120  emitTIIHelperMethods(OS, TargetName, /* ExpandDefinition = */ true);
1121  OS << "#endif // GET_INSTRINFO_HELPERS\n\n";
1122
1123  OS << "#ifdef GET_INSTRINFO_CTOR_DTOR\n";
1124  OS << "#undef GET_INSTRINFO_CTOR_DTOR\n";
1125
1126  OS << "namespace llvm {\n";
1127  OS << "extern const " << TargetName << "InstrTable " << TargetName
1128     << "Descs;\n";
1129  OS << "extern const unsigned " << TargetName << "InstrNameIndices[];\n";
1130  OS << "extern const char " << TargetName << "InstrNameData[];\n";
1131  if (HasDeprecationFeatures)
1132    OS << "extern const uint8_t " << TargetName
1133       << "InstrDeprecationFeatures[];\n";
1134  if (HasComplexDeprecationInfos)
1135    OS << "extern const MCInstrInfo::ComplexDeprecationPredicate " << TargetName
1136       << "InstrComplexDeprecationInfos[];\n";
1137  OS << ClassName << "::" << ClassName
1138     << "(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned "
1139        "CatchRetOpcode, unsigned ReturnOpcode)\n"
1140     << "  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, "
1141        "ReturnOpcode) {\n"
1142     << "  InitMCInstrInfo(" << TargetName << "Descs.Insts, " << TargetName
1143     << "InstrNameIndices, " << TargetName << "InstrNameData, ";
1144  if (HasDeprecationFeatures)
1145    OS << TargetName << "InstrDeprecationFeatures, ";
1146  else
1147    OS << "nullptr, ";
1148  if (HasComplexDeprecationInfos)
1149    OS << TargetName << "InstrComplexDeprecationInfos, ";
1150  else
1151    OS << "nullptr, ";
1152  OS << NumberedInstructions.size() << ");\n}\n";
1153  OS << "} // end namespace llvm\n";
1154
1155  OS << "#endif // GET_INSTRINFO_CTOR_DTOR\n\n";
1156
1157  Records.startTimer("Emit operand name mappings");
1158  emitOperandNameMappings(OS, Target, NumberedInstructions);
1159
1160  Records.startTimer("Emit operand type mappings");
1161  emitOperandTypeMappings(OS, Target, NumberedInstructions);
1162
1163  Records.startTimer("Emit logical operand size mappings");
1164  emitLogicalOperandSizeMappings(OS, TargetName, NumberedInstructions);
1165
1166  Records.startTimer("Emit logical operand type mappings");
1167  emitLogicalOperandTypeMappings(OS, TargetName, NumberedInstructions);
1168
1169  Records.startTimer("Emit helper methods");
1170  emitMCIIHelperMethods(OS, TargetName);
1171
1172  Records.startTimer("Emit verifier methods");
1173  emitFeatureVerifier(OS, Target);
1174}
1175
1176void InstrInfoEmitter::emitRecord(
1177    const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo,
1178    std::map<std::vector<Record *>, unsigned> &EmittedLists,
1179    const OperandInfoMapTy &OperandInfoMap, raw_ostream &OS) {
1180  int MinOperands = 0;
1181  if (!Inst.Operands.empty())
1182    // Each logical operand can be multiple MI operands.
1183    MinOperands = Inst.Operands.back().MIOperandNo +
1184                  Inst.Operands.back().MINumOperands;
1185
1186  OS << "    { ";
1187  OS << Num << ",\t" << MinOperands << ",\t" << Inst.Operands.NumDefs << ",\t"
1188     << Inst.TheDef->getValueAsInt("Size") << ",\t"
1189     << SchedModels.getSchedClassIdx(Inst) << ",\t";
1190
1191  CodeGenTarget &Target = CDP.getTargetInfo();
1192
1193  // Emit the implicit use/def list...
1194  OS << Inst.ImplicitUses.size() << ",\t" << Inst.ImplicitDefs.size() << ",\t";
1195  std::vector<Record *> ImplicitOps = Inst.ImplicitUses;
1196  llvm::append_range(ImplicitOps, Inst.ImplicitDefs);
1197  OS << Target.getName() << "ImpOpBase + " << EmittedLists[ImplicitOps]
1198     << ",\t";
1199
1200  // Emit the operand info offset.
1201  OperandInfoTy OperandInfo = GetOperandInfo(Inst);
1202  OS << OperandInfoMap.find(OperandInfo)->second << ",\t0";
1203
1204  // Emit all of the target independent flags...
1205  if (Inst.isPreISelOpcode)    OS << "|(1ULL<<MCID::PreISelOpcode)";
1206  if (Inst.isPseudo)           OS << "|(1ULL<<MCID::Pseudo)";
1207  if (Inst.isMeta)             OS << "|(1ULL<<MCID::Meta)";
1208  if (Inst.isReturn)           OS << "|(1ULL<<MCID::Return)";
1209  if (Inst.isEHScopeReturn)    OS << "|(1ULL<<MCID::EHScopeReturn)";
1210  if (Inst.isBranch)           OS << "|(1ULL<<MCID::Branch)";
1211  if (Inst.isIndirectBranch)   OS << "|(1ULL<<MCID::IndirectBranch)";
1212  if (Inst.isCompare)          OS << "|(1ULL<<MCID::Compare)";
1213  if (Inst.isMoveImm)          OS << "|(1ULL<<MCID::MoveImm)";
1214  if (Inst.isMoveReg)          OS << "|(1ULL<<MCID::MoveReg)";
1215  if (Inst.isBitcast)          OS << "|(1ULL<<MCID::Bitcast)";
1216  if (Inst.isAdd)              OS << "|(1ULL<<MCID::Add)";
1217  if (Inst.isTrap)             OS << "|(1ULL<<MCID::Trap)";
1218  if (Inst.isSelect)           OS << "|(1ULL<<MCID::Select)";
1219  if (Inst.isBarrier)          OS << "|(1ULL<<MCID::Barrier)";
1220  if (Inst.hasDelaySlot)       OS << "|(1ULL<<MCID::DelaySlot)";
1221  if (Inst.isCall)             OS << "|(1ULL<<MCID::Call)";
1222  if (Inst.canFoldAsLoad)      OS << "|(1ULL<<MCID::FoldableAsLoad)";
1223  if (Inst.mayLoad)            OS << "|(1ULL<<MCID::MayLoad)";
1224  if (Inst.mayStore)           OS << "|(1ULL<<MCID::MayStore)";
1225  if (Inst.mayRaiseFPException) OS << "|(1ULL<<MCID::MayRaiseFPException)";
1226  if (Inst.isPredicable)       OS << "|(1ULL<<MCID::Predicable)";
1227  if (Inst.isConvertibleToThreeAddress) OS << "|(1ULL<<MCID::ConvertibleTo3Addr)";
1228  if (Inst.isCommutable)       OS << "|(1ULL<<MCID::Commutable)";
1229  if (Inst.isTerminator)       OS << "|(1ULL<<MCID::Terminator)";
1230  if (Inst.isReMaterializable) OS << "|(1ULL<<MCID::Rematerializable)";
1231  if (Inst.isNotDuplicable)    OS << "|(1ULL<<MCID::NotDuplicable)";
1232  if (Inst.Operands.hasOptionalDef) OS << "|(1ULL<<MCID::HasOptionalDef)";
1233  if (Inst.usesCustomInserter) OS << "|(1ULL<<MCID::UsesCustomInserter)";
1234  if (Inst.hasPostISelHook)    OS << "|(1ULL<<MCID::HasPostISelHook)";
1235  if (Inst.Operands.isVariadic)OS << "|(1ULL<<MCID::Variadic)";
1236  if (Inst.hasSideEffects)     OS << "|(1ULL<<MCID::UnmodeledSideEffects)";
1237  if (Inst.isAsCheapAsAMove)   OS << "|(1ULL<<MCID::CheapAsAMove)";
1238  if (!Target.getAllowRegisterRenaming() || Inst.hasExtraSrcRegAllocReq)
1239    OS << "|(1ULL<<MCID::ExtraSrcRegAllocReq)";
1240  if (!Target.getAllowRegisterRenaming() || Inst.hasExtraDefRegAllocReq)
1241    OS << "|(1ULL<<MCID::ExtraDefRegAllocReq)";
1242  if (Inst.isRegSequence) OS << "|(1ULL<<MCID::RegSequence)";
1243  if (Inst.isExtractSubreg) OS << "|(1ULL<<MCID::ExtractSubreg)";
1244  if (Inst.isInsertSubreg) OS << "|(1ULL<<MCID::InsertSubreg)";
1245  if (Inst.isConvergent) OS << "|(1ULL<<MCID::Convergent)";
1246  if (Inst.variadicOpsAreDefs) OS << "|(1ULL<<MCID::VariadicOpsAreDefs)";
1247  if (Inst.isAuthenticated) OS << "|(1ULL<<MCID::Authenticated)";
1248
1249  // Emit all of the target-specific flags...
1250  BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
1251  if (!TSF)
1252    PrintFatalError(Inst.TheDef->getLoc(), "no TSFlags?");
1253  uint64_t Value = 0;
1254  for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) {
1255    if (const auto *Bit = dyn_cast<BitInit>(TSF->getBit(i)))
1256      Value |= uint64_t(Bit->getValue()) << i;
1257    else
1258      PrintFatalError(Inst.TheDef->getLoc(),
1259                      "Invalid TSFlags bit in " + Inst.TheDef->getName());
1260  }
1261  OS << ", 0x";
1262  OS.write_hex(Value);
1263  OS << "ULL";
1264
1265  OS << " },  // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
1266}
1267
1268// emitEnums - Print out enum values for all of the instructions.
1269void InstrInfoEmitter::emitEnums(raw_ostream &OS) {
1270  OS << "#ifdef GET_INSTRINFO_ENUM\n";
1271  OS << "#undef GET_INSTRINFO_ENUM\n";
1272
1273  OS << "namespace llvm {\n\n";
1274
1275  const CodeGenTarget &Target = CDP.getTargetInfo();
1276
1277  // We must emit the PHI opcode first...
1278  StringRef Namespace = Target.getInstNamespace();
1279
1280  if (Namespace.empty())
1281    PrintFatalError("No instructions defined!");
1282
1283  OS << "namespace " << Namespace << " {\n";
1284  OS << "  enum {\n";
1285  unsigned Num = 0;
1286  for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue())
1287    OS << "    " << Inst->TheDef->getName() << "\t= " << Num++ << ",\n";
1288  OS << "    INSTRUCTION_LIST_END = " << Num << "\n";
1289  OS << "  };\n\n";
1290  OS << "} // end namespace " << Namespace << "\n";
1291  OS << "} // end namespace llvm\n";
1292  OS << "#endif // GET_INSTRINFO_ENUM\n\n";
1293
1294  OS << "#ifdef GET_INSTRINFO_SCHED_ENUM\n";
1295  OS << "#undef GET_INSTRINFO_SCHED_ENUM\n";
1296  OS << "namespace llvm {\n\n";
1297  OS << "namespace " << Namespace << " {\n";
1298  OS << "namespace Sched {\n";
1299  OS << "  enum {\n";
1300  Num = 0;
1301  for (const auto &Class : SchedModels.explicit_classes())
1302    OS << "    " << Class.Name << "\t= " << Num++ << ",\n";
1303  OS << "    SCHED_LIST_END = " << Num << "\n";
1304  OS << "  };\n";
1305  OS << "} // end namespace Sched\n";
1306  OS << "} // end namespace " << Namespace << "\n";
1307  OS << "} // end namespace llvm\n";
1308
1309  OS << "#endif // GET_INSTRINFO_SCHED_ENUM\n\n";
1310}
1311
1312static void EmitInstrInfo(RecordKeeper &RK, raw_ostream &OS) {
1313  RK.startTimer("Analyze DAG patterns");
1314  InstrInfoEmitter(RK).run(OS);
1315  RK.startTimer("Emit map table");
1316  EmitMapTable(RK, OS);
1317}
1318
1319static TableGen::Emitter::Opt X("gen-instr-info", EmitInstrInfo,
1320                                "Generate instruction descriptions");
1321