1//===- MipsSEISelLowering.h - MipsSE DAG Lowering Interface -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Subclass of MipsTargetLowering specialized for mips32/64.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
14#define LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
15
16#include "MipsISelLowering.h"
17#include "llvm/CodeGen/MachineValueType.h"
18#include "llvm/CodeGen/SelectionDAGNodes.h"
19
20namespace llvm {
21
22class MachineBasicBlock;
23class MachineInstr;
24class MipsSubtarget;
25class MipsTargetMachine;
26class SelectionDAG;
27class TargetRegisterClass;
28
29  class MipsSETargetLowering : public MipsTargetLowering  {
30  public:
31    explicit MipsSETargetLowering(const MipsTargetMachine &TM,
32                                  const MipsSubtarget &STI);
33
34    /// Enable MSA support for the given integer type and Register
35    /// class.
36    void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
37
38    /// Enable MSA support for the given floating-point type and
39    /// Register class.
40    void addMSAFloatType(MVT::SimpleValueType Ty,
41                         const TargetRegisterClass *RC);
42
43    bool allowsMisalignedMemoryAccesses(
44        EVT VT, unsigned AS = 0, Align Alignment = Align(1),
45        MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
46        unsigned *Fast = nullptr) const override;
47
48    SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
49
50    SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
51
52    MachineBasicBlock *
53    EmitInstrWithCustomInserter(MachineInstr &MI,
54                                MachineBasicBlock *MBB) const override;
55
56    bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override {
57      return false;
58    }
59
60    const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
61
62  private:
63    bool isEligibleForTailCallOptimization(
64        const CCState &CCInfo, unsigned NextStackOffset,
65        const MipsFunctionInfo &FI) const override;
66
67    void
68    getOpndList(SmallVectorImpl<SDValue> &Ops,
69                std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
70                bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
71                bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
72                SDValue Chain) const override;
73
74    SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
75    SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
76    SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
77
78    SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
79                        SelectionDAG &DAG) const;
80
81    SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
82    SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
83    SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
84    SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
85    SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
86    /// Lower VECTOR_SHUFFLE into one of a number of instructions
87    /// depending on the indices in the shuffle.
88    SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
89    SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
90
91    MachineBasicBlock *emitBPOSGE32(MachineInstr &MI,
92                                    MachineBasicBlock *BB) const;
93    MachineBasicBlock *emitMSACBranchPseudo(MachineInstr &MI,
94                                            MachineBasicBlock *BB,
95                                            unsigned BranchOp) const;
96    /// Emit the COPY_FW pseudo instruction
97    MachineBasicBlock *emitCOPY_FW(MachineInstr &MI,
98                                   MachineBasicBlock *BB) const;
99    /// Emit the COPY_FD pseudo instruction
100    MachineBasicBlock *emitCOPY_FD(MachineInstr &MI,
101                                   MachineBasicBlock *BB) const;
102    /// Emit the INSERT_FW pseudo instruction
103    MachineBasicBlock *emitINSERT_FW(MachineInstr &MI,
104                                     MachineBasicBlock *BB) const;
105    /// Emit the INSERT_FD pseudo instruction
106    MachineBasicBlock *emitINSERT_FD(MachineInstr &MI,
107                                     MachineBasicBlock *BB) const;
108    /// Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction
109    MachineBasicBlock *emitINSERT_DF_VIDX(MachineInstr &MI,
110                                          MachineBasicBlock *BB,
111                                          unsigned EltSizeInBytes,
112                                          bool IsFP) const;
113    /// Emit the FILL_FW pseudo instruction
114    MachineBasicBlock *emitFILL_FW(MachineInstr &MI,
115                                   MachineBasicBlock *BB) const;
116    /// Emit the FILL_FD pseudo instruction
117    MachineBasicBlock *emitFILL_FD(MachineInstr &MI,
118                                   MachineBasicBlock *BB) const;
119    /// Emit the FEXP2_W_1 pseudo instructions.
120    MachineBasicBlock *emitFEXP2_W_1(MachineInstr &MI,
121                                     MachineBasicBlock *BB) const;
122    /// Emit the FEXP2_D_1 pseudo instructions.
123    MachineBasicBlock *emitFEXP2_D_1(MachineInstr &MI,
124                                     MachineBasicBlock *BB) const;
125    /// Emit the FILL_FW pseudo instruction
126    MachineBasicBlock *emitLD_F16_PSEUDO(MachineInstr &MI,
127                                   MachineBasicBlock *BB) const;
128    /// Emit the FILL_FD pseudo instruction
129    MachineBasicBlock *emitST_F16_PSEUDO(MachineInstr &MI,
130                                   MachineBasicBlock *BB) const;
131    /// Emit the FEXP2_W_1 pseudo instructions.
132    MachineBasicBlock *emitFPEXTEND_PSEUDO(MachineInstr &MI,
133                                           MachineBasicBlock *BB,
134                                           bool IsFGR64) const;
135    /// Emit the FEXP2_D_1 pseudo instructions.
136    MachineBasicBlock *emitFPROUND_PSEUDO(MachineInstr &MI,
137                                          MachineBasicBlock *BBi,
138                                          bool IsFGR64) const;
139  };
140
141} // end namespace llvm
142
143#endif // LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
144