1//===-- ARM.h - Top-level interface for ARM representation ------*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file contains the entry points for global functions defined in the LLVM 10// ARM back-end. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_LIB_TARGET_ARM_ARM_H 15#define LLVM_LIB_TARGET_ARM_ARM_H 16 17#include "llvm/IR/LegacyPassManager.h" 18#include "llvm/Support/CodeGen.h" 19#include <functional> 20 21namespace llvm { 22 23class ARMAsmPrinter; 24class ARMBaseTargetMachine; 25class ARMRegisterBankInfo; 26class ARMSubtarget; 27class Function; 28class FunctionPass; 29class InstructionSelector; 30class MCInst; 31class MachineInstr; 32class PassRegistry; 33 34Pass *createMVETailPredicationPass(); 35FunctionPass *createARMLowOverheadLoopsPass(); 36FunctionPass *createARMBlockPlacementPass(); 37Pass *createARMParallelDSPPass(); 38FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM, 39 CodeGenOptLevel OptLevel); 40FunctionPass *createA15SDOptimizerPass(); 41FunctionPass *createARMLoadStoreOptimizationPass(bool PreAlloc = false); 42FunctionPass *createARMExpandPseudoPass(); 43FunctionPass *createARMBranchTargetsPass(); 44FunctionPass *createARMConstantIslandPass(); 45FunctionPass *createMLxExpansionPass(); 46FunctionPass *createThumb2ITBlockPass(); 47FunctionPass *createMVEVPTBlockPass(); 48FunctionPass *createMVETPAndVPTOptimisationsPass(); 49FunctionPass *createARMOptimizeBarriersPass(); 50FunctionPass *createThumb2SizeReductionPass( 51 std::function<bool(const Function &)> Ftor = nullptr); 52InstructionSelector * 53createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI, 54 const ARMRegisterBankInfo &RBI); 55Pass *createMVEGatherScatterLoweringPass(); 56FunctionPass *createARMSLSHardeningPass(); 57FunctionPass *createARMIndirectThunks(); 58Pass *createMVELaneInterleavingPass(); 59FunctionPass *createARMFixCortexA57AES1742098Pass(); 60 61void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, 62 ARMAsmPrinter &AP); 63 64void initializeARMBlockPlacementPass(PassRegistry &); 65void initializeARMBranchTargetsPass(PassRegistry &); 66void initializeARMConstantIslandsPass(PassRegistry &); 67void initializeARMDAGToDAGISelPass(PassRegistry &); 68void initializeARMExpandPseudoPass(PassRegistry &); 69void initializeARMFixCortexA57AES1742098Pass(PassRegistry &); 70void initializeARMLoadStoreOptPass(PassRegistry &); 71void initializeARMLowOverheadLoopsPass(PassRegistry &); 72void initializeARMParallelDSPPass(PassRegistry &); 73void initializeARMPreAllocLoadStoreOptPass(PassRegistry &); 74void initializeARMSLSHardeningPass(PassRegistry &); 75void initializeMVEGatherScatterLoweringPass(PassRegistry &); 76void initializeMVELaneInterleavingPass(PassRegistry &); 77void initializeMVETPAndVPTOptimisationsPass(PassRegistry &); 78void initializeMVETailPredicationPass(PassRegistry &); 79void initializeMVEVPTBlockPass(PassRegistry &); 80void initializeThumb2ITBlockPass(PassRegistry &); 81void initializeThumb2SizeReducePass(PassRegistry &); 82 83} // end namespace llvm 84 85#endif // LLVM_LIB_TARGET_ARM_ARM_H 86