1//===-- SIModeRegisterDefaults.h --------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_AMDGPU_SIMODEREGISTERDEFAULTS_H
10#define LLVM_LIB_TARGET_AMDGPU_SIMODEREGISTERDEFAULTS_H
11
12#include "Utils/AMDGPUBaseInfo.h"
13#include "llvm/ADT/FloatingPointMode.h"
14
15namespace llvm {
16
17class GCNSubtarget;
18
19// Track defaults for fields in the MODE register.
20struct SIModeRegisterDefaults {
21  /// Floating point opcodes that support exception flag gathering quiet and
22  /// propagate signaling NaN inputs per IEEE 754-2008. Min_dx10 and max_dx10
23  /// become IEEE 754- 2008 compliant due to signaling NaN propagation and
24  /// quieting.
25  bool IEEE : 1;
26
27  /// Used by the vector ALU to force DX10-style treatment of NaNs: when set,
28  /// clamp NaN to zero; otherwise, pass NaN through.
29  bool DX10Clamp : 1;
30
31  /// If this is set, neither input or output denormals are flushed for most f32
32  /// instructions.
33  DenormalMode FP32Denormals;
34
35  /// If this is set, neither input or output denormals are flushed for both f64
36  /// and f16/v2f16 instructions.
37  DenormalMode FP64FP16Denormals;
38
39  SIModeRegisterDefaults() :
40    IEEE(true),
41    DX10Clamp(true),
42    FP32Denormals(DenormalMode::getIEEE()),
43    FP64FP16Denormals(DenormalMode::getIEEE()) {}
44
45  SIModeRegisterDefaults(const Function &F, const GCNSubtarget &ST);
46
47  static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC) {
48    SIModeRegisterDefaults Mode;
49    Mode.IEEE = !AMDGPU::isShader(CC);
50    return Mode;
51  }
52
53  bool operator==(const SIModeRegisterDefaults Other) const {
54    return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp &&
55           FP32Denormals == Other.FP32Denormals &&
56           FP64FP16Denormals == Other.FP64FP16Denormals;
57  }
58
59  /// Get the encoding value for the FP_DENORM bits of the mode register for the
60  /// FP32 denormal mode.
61  uint32_t fpDenormModeSPValue() const {
62    if (FP32Denormals == DenormalMode::getPreserveSign())
63      return FP_DENORM_FLUSH_IN_FLUSH_OUT;
64    if (FP32Denormals.Output == DenormalMode::PreserveSign)
65      return FP_DENORM_FLUSH_OUT;
66    if (FP32Denormals.Input == DenormalMode::PreserveSign)
67      return FP_DENORM_FLUSH_IN;
68    return FP_DENORM_FLUSH_NONE;
69  }
70
71  /// Get the encoding value for the FP_DENORM bits of the mode register for the
72  /// FP64/FP16 denormal mode.
73  uint32_t fpDenormModeDPValue() const {
74    if (FP64FP16Denormals == DenormalMode::getPreserveSign())
75      return FP_DENORM_FLUSH_IN_FLUSH_OUT;
76    if (FP64FP16Denormals.Output == DenormalMode::PreserveSign)
77      return FP_DENORM_FLUSH_OUT;
78    if (FP64FP16Denormals.Input == DenormalMode::PreserveSign)
79      return FP_DENORM_FLUSH_IN;
80    return FP_DENORM_FLUSH_NONE;
81  }
82
83  // FIXME: Inlining should be OK for dx10-clamp, since the caller's mode should
84  // be able to override.
85  bool isInlineCompatible(SIModeRegisterDefaults CalleeMode) const {
86    return DX10Clamp == CalleeMode.DX10Clamp && IEEE == CalleeMode.IEEE;
87  }
88};
89
90namespace AMDGPU {
91
92/// Return values used for llvm.get.rounding
93///
94/// When both the F32 and F64/F16 modes are the same, returns the standard
95/// values. If they differ, returns an extended mode starting at 8.
96enum AMDGPUFltRounds : int8_t {
97  // Inherit everything from RoundingMode
98  TowardZero = static_cast<int8_t>(RoundingMode::TowardZero),
99  NearestTiesToEven = static_cast<int8_t>(RoundingMode::NearestTiesToEven),
100  TowardPositive = static_cast<int8_t>(RoundingMode::TowardPositive),
101  TowardNegative = static_cast<int8_t>(RoundingMode::TowardNegative),
102  NearestTiesToAwayUnsupported =
103      static_cast<int8_t>(RoundingMode::NearestTiesToAway),
104
105  Dynamic = static_cast<int8_t>(RoundingMode::Dynamic),
106
107  // Permute the mismatched rounding mode cases.  If the modes are the same, use
108  // the standard values, otherwise, these values are sorted such that higher
109  // hardware encoded values have higher enum values.
110  NearestTiesToEvenF32_NearestTiesToEvenF64 = NearestTiesToEven,
111  NearestTiesToEvenF32_TowardPositiveF64 = 8,
112  NearestTiesToEvenF32_TowardNegativeF64 = 9,
113  NearestTiesToEvenF32_TowardZeroF64 = 10,
114
115  TowardPositiveF32_NearestTiesToEvenF64 = 11,
116  TowardPositiveF32_TowardPositiveF64 = TowardPositive,
117  TowardPositiveF32_TowardNegativeF64 = 12,
118  TowardPositiveF32_TowardZeroF64 = 13,
119
120  TowardNegativeF32_NearestTiesToEvenF64 = 14,
121  TowardNegativeF32_TowardPositiveF64 = 15,
122  TowardNegativeF32_TowardNegativeF64 = TowardNegative,
123  TowardNegativeF32_TowardZeroF64 = 16,
124
125  TowardZeroF32_NearestTiesToEvenF64 = 17,
126  TowardZeroF32_TowardPositiveF64 = 18,
127  TowardZeroF32_TowardNegativeF64 = 19,
128  TowardZeroF32_TowardZeroF64 = TowardZero,
129
130  Invalid = static_cast<int8_t>(RoundingMode::Invalid)
131};
132
133/// Offset of nonstandard values for llvm.get.rounding results from the largest
134/// supported mode.
135static constexpr uint32_t ExtendedFltRoundOffset = 4;
136
137/// Offset in mode register of f32 rounding mode.
138static constexpr uint32_t F32FltRoundOffset = 0;
139
140/// Offset in mode register of f64/f16 rounding mode.
141static constexpr uint32_t F64FltRoundOffset = 2;
142
143// Bit indexed table to convert from hardware rounding mode values to FLT_ROUNDS
144// values.
145extern const uint64_t FltRoundConversionTable;
146
147} // end namespace AMDGPU
148
149} // end namespace llvm
150
151#endif // LLVM_LIB_TARGET_AMDGPU_SIMODEREGISTERDEFAULTS_H
152