1//===--- BuiltinsPPC.def - PowerPC Builtin function database ----*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the PowerPC-specific builtin function database. Users of 10// this file must define the BUILTIN macro or the CUSTOM_BUILTIN macro to 11// make use of this information. The latter is used for builtins requiring 12// custom code generation and checking. 13// 14//===----------------------------------------------------------------------===// 15 16// FIXME: this needs to be the full list supported by GCC. Right now, I'm just 17// adding stuff on demand. 18 19// The format of this database matches clang/Basic/Builtins.def except for the 20// MMA builtins that are using their own format documented below. 21 22#ifndef BUILTIN 23#define BUILTIN(ID, TYPE, ATTRS) 24#endif 25 26#if defined(BUILTIN) && !defined(TARGET_BUILTIN) 27#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS) 28#endif 29 30#ifndef CUSTOM_BUILTIN 31#define CUSTOM_BUILTIN(ID, INTR, TYPES, ACCUMULATE, FEATURE) \ 32 TARGET_BUILTIN(__builtin_##ID, "i.", "t", FEATURE) 33#endif 34 35#define UNALIASED_CUSTOM_BUILTIN(ID, TYPES, ACCUMULATE, FEATURE) \ 36 CUSTOM_BUILTIN(ID, ID, TYPES, ACCUMULATE, FEATURE) 37 38// GCC predefined macros to rename builtins, undef them to keep original names. 39#if defined(__GNUC__) && !defined(__clang__) 40#undef __builtin_vsx_xvnmaddadp 41#undef __builtin_vsx_xvnmaddasp 42#undef __builtin_vsx_xvmsubasp 43#undef __builtin_vsx_xvmsubadp 44#undef __builtin_vsx_xvmaddadp 45#undef __builtin_vsx_xvnmsubasp 46#undef __builtin_vsx_xvnmsubadp 47#undef __builtin_vsx_xvmaddasp 48#endif 49 50// XL Compatibility built-ins 51BUILTIN(__builtin_ppc_popcntb, "ULiULi", "") 52BUILTIN(__builtin_ppc_poppar4, "iUi", "") 53BUILTIN(__builtin_ppc_poppar8, "iULLi", "") 54BUILTIN(__builtin_ppc_eieio, "v", "") 55BUILTIN(__builtin_ppc_iospace_eieio, "v", "") 56BUILTIN(__builtin_ppc_isync, "v", "") 57BUILTIN(__builtin_ppc_lwsync, "v", "") 58BUILTIN(__builtin_ppc_iospace_lwsync, "v", "") 59BUILTIN(__builtin_ppc_sync, "v", "") 60BUILTIN(__builtin_ppc_iospace_sync, "v", "") 61BUILTIN(__builtin_ppc_dcbfl, "vvC*", "") 62BUILTIN(__builtin_ppc_dcbflp, "vvC*", "") 63BUILTIN(__builtin_ppc_dcbst, "vvC*", "") 64BUILTIN(__builtin_ppc_dcbt, "vv*", "") 65BUILTIN(__builtin_ppc_dcbtst, "vv*", "") 66BUILTIN(__builtin_ppc_dcbz, "vv*", "") 67TARGET_BUILTIN(__builtin_ppc_icbt, "vv*", "", "isa-v207-instructions") 68BUILTIN(__builtin_ppc_fric, "dd", "") 69BUILTIN(__builtin_ppc_frim, "dd", "") 70BUILTIN(__builtin_ppc_frims, "ff", "") 71BUILTIN(__builtin_ppc_frin, "dd", "") 72BUILTIN(__builtin_ppc_frins, "ff", "") 73BUILTIN(__builtin_ppc_frip, "dd", "") 74BUILTIN(__builtin_ppc_frips, "ff", "") 75BUILTIN(__builtin_ppc_friz, "dd", "") 76BUILTIN(__builtin_ppc_frizs, "ff", "") 77BUILTIN(__builtin_ppc_fsel, "dddd", "") 78BUILTIN(__builtin_ppc_fsels, "ffff", "") 79BUILTIN(__builtin_ppc_frsqrte, "dd", "") 80BUILTIN(__builtin_ppc_frsqrtes, "ff", "") 81BUILTIN(__builtin_ppc_fsqrt, "dd", "") 82BUILTIN(__builtin_ppc_fsqrts, "ff", "") 83BUILTIN(__builtin_ppc_compare_and_swap, "iiD*i*i", "") 84BUILTIN(__builtin_ppc_compare_and_swaplp, "iLiD*Li*Li", "") 85BUILTIN(__builtin_ppc_fetch_and_add, "iiD*i", "") 86BUILTIN(__builtin_ppc_fetch_and_addlp, "LiLiD*Li", "") 87BUILTIN(__builtin_ppc_fetch_and_and, "UiUiD*Ui", "") 88BUILTIN(__builtin_ppc_fetch_and_andlp, "ULiULiD*ULi", "") 89BUILTIN(__builtin_ppc_fetch_and_or, "UiUiD*Ui", "") 90BUILTIN(__builtin_ppc_fetch_and_orlp, "ULiULiD*ULi", "") 91BUILTIN(__builtin_ppc_fetch_and_swap, "UiUiD*Ui", "") 92BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi", "") 93BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "") 94BUILTIN(__builtin_ppc_lwarx, "iiD*", "") 95TARGET_BUILTIN(__builtin_ppc_lharx, "ssD*", "", "isa-v207-instructions") 96TARGET_BUILTIN(__builtin_ppc_lbarx, "ccD*", "", "isa-v207-instructions") 97BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "") 98BUILTIN(__builtin_ppc_stwcx, "iiD*i", "") 99TARGET_BUILTIN(__builtin_ppc_sthcx, "isD*s", "", "isa-v207-instructions") 100TARGET_BUILTIN(__builtin_ppc_stbcx, "icD*i", "", "isa-v207-instructions") 101BUILTIN(__builtin_ppc_tdw, "vLLiLLiIUi", "") 102BUILTIN(__builtin_ppc_tw, "viiIUi", "") 103BUILTIN(__builtin_ppc_trap, "vi", "") 104BUILTIN(__builtin_ppc_trapd, "vLi", "") 105BUILTIN(__builtin_ppc_fcfid, "dd", "") 106BUILTIN(__builtin_ppc_fcfud, "dd", "") 107BUILTIN(__builtin_ppc_fctid, "dd", "") 108BUILTIN(__builtin_ppc_fctidz, "dd", "") 109BUILTIN(__builtin_ppc_fctiw, "dd", "") 110BUILTIN(__builtin_ppc_fctiwz, "dd", "") 111BUILTIN(__builtin_ppc_fctudz, "dd", "") 112BUILTIN(__builtin_ppc_fctuwz, "dd", "") 113 114// fence builtin prevents all instructions moved across it 115BUILTIN(__builtin_ppc_fence, "v", "") 116 117BUILTIN(__builtin_ppc_swdiv_nochk, "ddd", "") 118BUILTIN(__builtin_ppc_swdivs_nochk, "fff", "") 119BUILTIN(__builtin_ppc_alignx, "vIivC*", "nc") 120BUILTIN(__builtin_ppc_rdlam, "UWiUWiUWiUWIi", "nc") 121TARGET_BUILTIN(__builtin_ppc_compare_exp_uo, "idd", "", "isa-v30-instructions,vsx") 122TARGET_BUILTIN(__builtin_ppc_compare_exp_lt, "idd", "", "isa-v30-instructions,vsx") 123TARGET_BUILTIN(__builtin_ppc_compare_exp_gt, "idd", "", "isa-v30-instructions,vsx") 124TARGET_BUILTIN(__builtin_ppc_compare_exp_eq, "idd", "", "isa-v30-instructions,vsx") 125TARGET_BUILTIN(__builtin_ppc_test_data_class, "idIi", "t", "isa-v30-instructions,vsx") 126BUILTIN(__builtin_ppc_swdiv, "ddd", "") 127BUILTIN(__builtin_ppc_swdivs, "fff", "") 128// Compare 129TARGET_BUILTIN(__builtin_ppc_cmpeqb, "LLiLLiLLi", "", "isa-v30-instructions") 130TARGET_BUILTIN(__builtin_ppc_cmprb, "iCIiii", "", "isa-v30-instructions") 131TARGET_BUILTIN(__builtin_ppc_setb, "LLiLLiLLi", "", "isa-v30-instructions") 132BUILTIN(__builtin_ppc_cmpb, "LLiLLiLLi", "") 133// Multiply 134BUILTIN(__builtin_ppc_mulhd, "LLiLiLi", "") 135BUILTIN(__builtin_ppc_mulhdu, "ULLiULiULi", "") 136BUILTIN(__builtin_ppc_mulhw, "iii", "") 137BUILTIN(__builtin_ppc_mulhwu, "UiUiUi", "") 138TARGET_BUILTIN(__builtin_ppc_maddhd, "LLiLLiLLiLLi", "", "isa-v30-instructions") 139TARGET_BUILTIN(__builtin_ppc_maddhdu, "ULLiULLiULLiULLi", "", 140 "isa-v30-instructions") 141TARGET_BUILTIN(__builtin_ppc_maddld, "LLiLLiLLiLLi", "", "isa-v30-instructions") 142// Rotate 143BUILTIN(__builtin_ppc_rlwnm, "UiUiUiIUi", "") 144BUILTIN(__builtin_ppc_rlwimi, "UiUiUiIUiIUi", "") 145BUILTIN(__builtin_ppc_rldimi, "ULLiULLiULLiIUiIULLi", "") 146// load 147BUILTIN(__builtin_ppc_load2r, "UsUs*", "") 148BUILTIN(__builtin_ppc_load4r, "UiUi*", "") 149TARGET_BUILTIN(__builtin_ppc_load8r, "ULLiULLi*", "", "isa-v206-instructions") 150// store 151BUILTIN(__builtin_ppc_store2r, "vUiUs*", "") 152BUILTIN(__builtin_ppc_store4r, "vUiUi*", "") 153TARGET_BUILTIN(__builtin_ppc_store8r, "vULLiULLi*", "", "isa-v206-instructions") 154TARGET_BUILTIN(__builtin_ppc_extract_exp, "Uid", "", "power9-vector") 155TARGET_BUILTIN(__builtin_ppc_extract_sig, "ULLid", "", "power9-vector") 156BUILTIN(__builtin_ppc_mtfsb0, "vUIi", "") 157BUILTIN(__builtin_ppc_mtfsb1, "vUIi", "") 158BUILTIN(__builtin_ppc_mffs, "d", "") 159TARGET_BUILTIN(__builtin_ppc_mffsl, "d", "", "isa-v30-instructions") 160BUILTIN(__builtin_ppc_mtfsf, "vUIiUi", "") 161BUILTIN(__builtin_ppc_mtfsfi, "vUIiUIi", "") 162BUILTIN(__builtin_ppc_set_fpscr_rn, "di", "") 163TARGET_BUILTIN(__builtin_ppc_insert_exp, "ddULLi", "", "power9-vector") 164BUILTIN(__builtin_ppc_fmsub, "dddd", "") 165BUILTIN(__builtin_ppc_fmsubs, "ffff", "") 166BUILTIN(__builtin_ppc_fnmadd, "dddd", "") 167BUILTIN(__builtin_ppc_fnmadds, "ffff", "") 168BUILTIN(__builtin_ppc_fnmsub, "dddd", "") 169BUILTIN(__builtin_ppc_fnmsubs, "ffff", "") 170BUILTIN(__builtin_ppc_fre, "dd", "") 171BUILTIN(__builtin_ppc_fres, "ff", "") 172BUILTIN(__builtin_ppc_dcbtstt, "vv*", "") 173BUILTIN(__builtin_ppc_dcbtt, "vv*", "") 174BUILTIN(__builtin_ppc_mftbu, "Ui", "") 175BUILTIN(__builtin_ppc_mfmsr, "Ui", "") 176BUILTIN(__builtin_ppc_mfspr, "ULiIi", "") 177BUILTIN(__builtin_ppc_mtmsr, "vUi", "") 178BUILTIN(__builtin_ppc_mtspr, "vIiULi", "") 179BUILTIN(__builtin_ppc_stfiw, "viC*d", "") 180TARGET_BUILTIN(__builtin_ppc_addex, "LLiLLiLLiCIi", "", "isa-v30-instructions") 181// select 182BUILTIN(__builtin_ppc_maxfe, "LdLdLdLd.", "t") 183BUILTIN(__builtin_ppc_maxfl, "dddd.", "t") 184BUILTIN(__builtin_ppc_maxfs, "ffff.", "t") 185BUILTIN(__builtin_ppc_minfe, "LdLdLdLd.", "t") 186BUILTIN(__builtin_ppc_minfl, "dddd.", "t") 187BUILTIN(__builtin_ppc_minfs, "ffff.", "t") 188// Floating Negative Absolute Value 189BUILTIN(__builtin_ppc_fnabs, "dd", "") 190BUILTIN(__builtin_ppc_fnabss, "ff", "") 191 192BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n") 193 194// This is just a placeholder, the types and attributes are wrong. 195TARGET_BUILTIN(__builtin_altivec_vaddcuw, "V4UiV4UiV4Ui", "", "altivec") 196 197TARGET_BUILTIN(__builtin_altivec_vaddsbs, "V16ScV16ScV16Sc", "", "altivec") 198TARGET_BUILTIN(__builtin_altivec_vaddubs, "V16UcV16UcV16Uc", "", "altivec") 199TARGET_BUILTIN(__builtin_altivec_vaddshs, "V8SsV8SsV8Ss", "", "altivec") 200TARGET_BUILTIN(__builtin_altivec_vadduhs, "V8UsV8UsV8Us", "", "altivec") 201TARGET_BUILTIN(__builtin_altivec_vaddsws, "V4SiV4SiV4Si", "", "altivec") 202TARGET_BUILTIN(__builtin_altivec_vadduws, "V4UiV4UiV4Ui", "", "altivec") 203TARGET_BUILTIN(__builtin_altivec_vaddeuqm, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi", "", 204 "power8-vector") 205TARGET_BUILTIN(__builtin_altivec_vaddcuq, "V1ULLLiV1ULLLiV1ULLLi", "", 206 "power8-vector") 207TARGET_BUILTIN(__builtin_altivec_vaddecuq, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi", "", 208 "power8-vector") 209TARGET_BUILTIN(__builtin_altivec_vadduqm, "V1ULLLiV16UcV16Uc", "", 210 "power8-vector") 211TARGET_BUILTIN(__builtin_altivec_vaddeuqm_c, "V16UcV16UcV16UcV16Uc", "", 212 "power8-vector") 213TARGET_BUILTIN(__builtin_altivec_vaddcuq_c, "V16UcV16UcV16Uc", "", 214 "power8-vector") 215TARGET_BUILTIN(__builtin_altivec_vaddecuq_c, "V16UcV16UcV16UcV16Uc", "", 216 "power8-vector") 217 218TARGET_BUILTIN(__builtin_altivec_vsubsbs, "V16ScV16ScV16Sc", "", "altivec") 219TARGET_BUILTIN(__builtin_altivec_vsububs, "V16UcV16UcV16Uc", "", "altivec") 220TARGET_BUILTIN(__builtin_altivec_vsubshs, "V8SsV8SsV8Ss", "", "altivec") 221TARGET_BUILTIN(__builtin_altivec_vsubuhs, "V8UsV8UsV8Us", "", "altivec") 222TARGET_BUILTIN(__builtin_altivec_vsubsws, "V4SiV4SiV4Si", "", "altivec") 223TARGET_BUILTIN(__builtin_altivec_vsubuws, "V4UiV4UiV4Ui", "", "altivec") 224TARGET_BUILTIN(__builtin_altivec_vsubeuqm, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi", "", 225 "power8-vector") 226TARGET_BUILTIN(__builtin_altivec_vsubcuq, "V1ULLLiV1ULLLiV1ULLLi", "", 227 "power8-vector") 228TARGET_BUILTIN(__builtin_altivec_vsubecuq, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi", "", 229 "power8-vector") 230TARGET_BUILTIN(__builtin_altivec_vsubuqm, "V1ULLLiV16UcV16Uc", "", 231 "power8-vector") 232TARGET_BUILTIN(__builtin_altivec_vsubeuqm_c, "V16UcV16UcV16UcV16Uc", "", 233 "power8-vector") 234TARGET_BUILTIN(__builtin_altivec_vsubcuq_c, "V16UcV16UcV16Uc", "", 235 "power8-vector") 236TARGET_BUILTIN(__builtin_altivec_vsubecuq_c, "V16UcV16UcV16UcV16Uc", "", 237 "power8-vector") 238 239TARGET_BUILTIN(__builtin_altivec_vavgsb, "V16ScV16ScV16Sc", "", "altivec") 240TARGET_BUILTIN(__builtin_altivec_vavgub, "V16UcV16UcV16Uc", "", "altivec") 241TARGET_BUILTIN(__builtin_altivec_vavgsh, "V8SsV8SsV8Ss", "", "altivec") 242TARGET_BUILTIN(__builtin_altivec_vavguh, "V8UsV8UsV8Us", "", "altivec") 243TARGET_BUILTIN(__builtin_altivec_vavgsw, "V4SiV4SiV4Si", "", "altivec") 244TARGET_BUILTIN(__builtin_altivec_vavguw, "V4UiV4UiV4Ui", "", "altivec") 245 246TARGET_BUILTIN(__builtin_altivec_vrfip, "V4fV4f", "", "altivec") 247 248TARGET_BUILTIN(__builtin_altivec_vcfsx, "V4fV4SiIi", "", "altivec") 249TARGET_BUILTIN(__builtin_altivec_vcfux, "V4fV4UiIi", "", "altivec") 250TARGET_BUILTIN(__builtin_altivec_vctsxs, "V4SiV4fIi", "", "altivec") 251TARGET_BUILTIN(__builtin_altivec_vctuxs, "V4UiV4fIi", "", "altivec") 252 253TARGET_BUILTIN(__builtin_altivec_dss, "vUIi", "", "altivec") 254TARGET_BUILTIN(__builtin_altivec_dssall, "v", "", "altivec") 255TARGET_BUILTIN(__builtin_altivec_dst, "vvC*iUIi", "", "altivec") 256TARGET_BUILTIN(__builtin_altivec_dstt, "vvC*iUIi", "", "altivec") 257TARGET_BUILTIN(__builtin_altivec_dstst, "vvC*iUIi", "", "altivec") 258TARGET_BUILTIN(__builtin_altivec_dststt, "vvC*iUIi", "", "altivec") 259 260TARGET_BUILTIN(__builtin_altivec_vexptefp, "V4fV4f", "", "altivec") 261 262TARGET_BUILTIN(__builtin_altivec_vrfim, "V4fV4f", "", "altivec") 263 264TARGET_BUILTIN(__builtin_altivec_lvx, "V4iLivC*", "", "altivec") 265TARGET_BUILTIN(__builtin_altivec_lvxl, "V4iLivC*", "", "altivec") 266TARGET_BUILTIN(__builtin_altivec_lvebx, "V16cLivC*", "", "altivec") 267TARGET_BUILTIN(__builtin_altivec_lvehx, "V8sLivC*", "", "altivec") 268TARGET_BUILTIN(__builtin_altivec_lvewx, "V4iLivC*", "", "altivec") 269 270TARGET_BUILTIN(__builtin_altivec_vlogefp, "V4fV4f", "", "altivec") 271 272TARGET_BUILTIN(__builtin_altivec_lvsl, "V16cUcvC*", "", "altivec") 273TARGET_BUILTIN(__builtin_altivec_lvsr, "V16cUcvC*", "", "altivec") 274 275TARGET_BUILTIN(__builtin_altivec_vmaddfp, "V4fV4fV4fV4f", "", "altivec") 276TARGET_BUILTIN(__builtin_altivec_vmhaddshs, "V8sV8sV8sV8s", "", "altivec") 277TARGET_BUILTIN(__builtin_altivec_vmhraddshs, "V8sV8sV8sV8s", "", "altivec") 278 279TARGET_BUILTIN(__builtin_altivec_vmsumubm, "V4UiV16UcV16UcV4Ui", "", "altivec") 280TARGET_BUILTIN(__builtin_altivec_vmsummbm, "V4SiV16ScV16UcV4Si", "", "altivec") 281TARGET_BUILTIN(__builtin_altivec_vmsumuhm, "V4UiV8UsV8UsV4Ui", "", "altivec") 282TARGET_BUILTIN(__builtin_altivec_vmsumshm, "V4SiV8SsV8SsV4Si", "", "altivec") 283TARGET_BUILTIN(__builtin_altivec_vmsumuhs, "V4UiV8UsV8UsV4Ui", "", "altivec") 284TARGET_BUILTIN(__builtin_altivec_vmsumshs, "V4SiV8SsV8SsV4Si", "", "altivec") 285 286TARGET_BUILTIN(__builtin_altivec_vmuleub, "V8UsV16UcV16Uc", "", "altivec") 287TARGET_BUILTIN(__builtin_altivec_vmulesb, "V8SsV16ScV16Sc", "", "altivec") 288TARGET_BUILTIN(__builtin_altivec_vmuleuh, "V4UiV8UsV8Us", "", "altivec") 289TARGET_BUILTIN(__builtin_altivec_vmulesh, "V4SiV8SsV8Ss", "", "altivec") 290TARGET_BUILTIN(__builtin_altivec_vmuleuw, "V2ULLiV4UiV4Ui", "", "power8-vector") 291TARGET_BUILTIN(__builtin_altivec_vmulesw, "V2SLLiV4SiV4Si", "", "power8-vector") 292TARGET_BUILTIN(__builtin_altivec_vmuloub, "V8UsV16UcV16Uc", "", "altivec") 293TARGET_BUILTIN(__builtin_altivec_vmulosb, "V8SsV16ScV16Sc", "", "altivec") 294TARGET_BUILTIN(__builtin_altivec_vmulouh, "V4UiV8UsV8Us", "", "altivec") 295TARGET_BUILTIN(__builtin_altivec_vmulosh, "V4SiV8SsV8Ss", "", "altivec") 296TARGET_BUILTIN(__builtin_altivec_vmulouw, "V2ULLiV4UiV4Ui", "", "power8-vector") 297TARGET_BUILTIN(__builtin_altivec_vmulosw, "V2SLLiV4SiV4Si", "", "power8-vector") 298TARGET_BUILTIN(__builtin_altivec_vmuleud, "V1ULLLiV2ULLiV2ULLi", "", 299 "power10-vector") 300TARGET_BUILTIN(__builtin_altivec_vmulesd, "V1SLLLiV2SLLiV2SLLi", "", 301 "power10-vector") 302TARGET_BUILTIN(__builtin_altivec_vmuloud, "V1ULLLiV2ULLiV2ULLi", "", 303 "power10-vector") 304TARGET_BUILTIN(__builtin_altivec_vmulosd, "V1SLLLiV2SLLiV2SLLi", "", 305 "power10-vector") 306TARGET_BUILTIN(__builtin_altivec_vmsumcud, "V1ULLLiV2ULLiV2ULLiV1ULLLi", "", 307 "power10-vector") 308 309TARGET_BUILTIN(__builtin_altivec_vnmsubfp, "V4fV4fV4fV4f", "", "altivec") 310 311TARGET_BUILTIN(__builtin_altivec_vpkpx, "V8sV4UiV4Ui", "", "altivec") 312TARGET_BUILTIN(__builtin_altivec_vpkuhus, "V16UcV8UsV8Us", "", "altivec") 313TARGET_BUILTIN(__builtin_altivec_vpkshss, "V16ScV8SsV8Ss", "", "altivec") 314TARGET_BUILTIN(__builtin_altivec_vpkuwus, "V8UsV4UiV4Ui", "", "altivec") 315TARGET_BUILTIN(__builtin_altivec_vpkswss, "V8SsV4SiV4Si", "", "altivec") 316TARGET_BUILTIN(__builtin_altivec_vpkshus, "V16UcV8SsV8Ss", "", "altivec") 317TARGET_BUILTIN(__builtin_altivec_vpkswus, "V8UsV4SiV4Si", "", "altivec") 318TARGET_BUILTIN(__builtin_altivec_vpksdss, "V4SiV2SLLiV2SLLi", "", 319 "power8-vector") 320TARGET_BUILTIN(__builtin_altivec_vpksdus, "V4UiV2SLLiV2SLLi", "", 321 "power8-vector") 322TARGET_BUILTIN(__builtin_altivec_vpkudus, "V4UiV2ULLiV2ULLi", "", 323 "power8-vector") 324TARGET_BUILTIN(__builtin_altivec_vpkudum, "V4UiV2ULLiV2ULLi", "", 325 "power8-vector") 326 327TARGET_BUILTIN(__builtin_altivec_vperm_4si, "V4iV4iV4iV16Uc", "", "altivec") 328 329TARGET_BUILTIN(__builtin_altivec_stvx, "vV4iLiv*", "", "altivec") 330TARGET_BUILTIN(__builtin_altivec_stvxl, "vV4iLiv*", "", "altivec") 331TARGET_BUILTIN(__builtin_altivec_stvebx, "vV16cLiv*", "", "altivec") 332TARGET_BUILTIN(__builtin_altivec_stvehx, "vV8sLiv*", "", "altivec") 333TARGET_BUILTIN(__builtin_altivec_stvewx, "vV4iLiv*", "", "altivec") 334 335TARGET_BUILTIN(__builtin_altivec_vcmpbfp, "V4iV4fV4f", "", "altivec") 336 337TARGET_BUILTIN(__builtin_altivec_vcmpgefp, "V4iV4fV4f", "", "altivec") 338 339TARGET_BUILTIN(__builtin_altivec_vcmpequb, "V16cV16cV16c", "", "altivec") 340TARGET_BUILTIN(__builtin_altivec_vcmpequh, "V8sV8sV8s", "", "altivec") 341TARGET_BUILTIN(__builtin_altivec_vcmpequw, "V4iV4iV4i", "", "altivec") 342TARGET_BUILTIN(__builtin_altivec_vcmpequd, "V2LLiV2LLiV2LLi", "", 343 "power8-vector") 344TARGET_BUILTIN(__builtin_altivec_vcmpeqfp, "V4iV4fV4f", "", "altivec") 345 346TARGET_BUILTIN(__builtin_altivec_vcmpneb, "V16cV16cV16c", "", "power9-vector") 347TARGET_BUILTIN(__builtin_altivec_vcmpneh, "V8sV8sV8s", "", "power9-vector") 348TARGET_BUILTIN(__builtin_altivec_vcmpnew, "V4iV4iV4i", "", "power9-vector") 349 350TARGET_BUILTIN(__builtin_altivec_vcmpnezb, "V16cV16cV16c", "", "power9-vector") 351TARGET_BUILTIN(__builtin_altivec_vcmpnezh, "V8sV8sV8s", "", "power9-vector") 352TARGET_BUILTIN(__builtin_altivec_vcmpnezw, "V4iV4iV4i", "", "power9-vector") 353 354TARGET_BUILTIN(__builtin_altivec_vcmpgtsb, "V16cV16ScV16Sc", "", "altivec") 355TARGET_BUILTIN(__builtin_altivec_vcmpgtub, "V16cV16UcV16Uc", "", "altivec") 356TARGET_BUILTIN(__builtin_altivec_vcmpgtsh, "V8sV8SsV8Ss", "", "altivec") 357TARGET_BUILTIN(__builtin_altivec_vcmpgtuh, "V8sV8UsV8Us", "", "altivec") 358TARGET_BUILTIN(__builtin_altivec_vcmpgtsw, "V4iV4SiV4Si", "", "altivec") 359TARGET_BUILTIN(__builtin_altivec_vcmpgtuw, "V4iV4UiV4Ui", "", "altivec") 360TARGET_BUILTIN(__builtin_altivec_vcmpgtsd, "V2LLiV2LLiV2LLi", "", 361 "power8-vector") 362TARGET_BUILTIN(__builtin_altivec_vcmpgtud, "V2LLiV2ULLiV2ULLi", "", 363 "power8-vector") 364TARGET_BUILTIN(__builtin_altivec_vcmpgtfp, "V4iV4fV4f", "", "altivec") 365 366// P10 Vector compare builtins. 367TARGET_BUILTIN(__builtin_altivec_vcmpequq, "V1LLLiV1ULLLiV1ULLLi", "", 368 "power10-vector") 369TARGET_BUILTIN(__builtin_altivec_vcmpgtsq, "V1LLLiV1SLLLiV1SLLLi", "", 370 "power10-vector") 371TARGET_BUILTIN(__builtin_altivec_vcmpgtuq, "V1LLLiV1ULLLiV1ULLLi", "", 372 "power10-vector") 373TARGET_BUILTIN(__builtin_altivec_vcmpequq_p, "iiV1ULLLiV1LLLi", "", "altivec") 374TARGET_BUILTIN(__builtin_altivec_vcmpgtsq_p, "iiV1SLLLiV1SLLLi", "", 375 "power10-vector") 376TARGET_BUILTIN(__builtin_altivec_vcmpgtuq_p, "iiV1ULLLiV1ULLLi", "", 377 "power10-vector") 378 379TARGET_BUILTIN(__builtin_altivec_vmaxsb, "V16ScV16ScV16Sc", "", "altivec") 380TARGET_BUILTIN(__builtin_altivec_vmaxub, "V16UcV16UcV16Uc", "", "altivec") 381TARGET_BUILTIN(__builtin_altivec_vmaxsh, "V8SsV8SsV8Ss", "", "altivec") 382TARGET_BUILTIN(__builtin_altivec_vmaxuh, "V8UsV8UsV8Us", "", "altivec") 383TARGET_BUILTIN(__builtin_altivec_vmaxsw, "V4SiV4SiV4Si", "", "altivec") 384TARGET_BUILTIN(__builtin_altivec_vmaxuw, "V4UiV4UiV4Ui", "", "altivec") 385TARGET_BUILTIN(__builtin_altivec_vmaxsd, "V2LLiV2LLiV2LLi", "", "power8-vector") 386TARGET_BUILTIN(__builtin_altivec_vmaxud, "V2ULLiV2ULLiV2ULLi", "", 387 "power8-vector") 388TARGET_BUILTIN(__builtin_altivec_vmaxfp, "V4fV4fV4f", "", "altivec") 389 390TARGET_BUILTIN(__builtin_altivec_mfvscr, "V8Us", "", "altivec") 391 392TARGET_BUILTIN(__builtin_altivec_vminsb, "V16ScV16ScV16Sc", "", "altivec") 393TARGET_BUILTIN(__builtin_altivec_vminub, "V16UcV16UcV16Uc", "", "altivec") 394TARGET_BUILTIN(__builtin_altivec_vminsh, "V8SsV8SsV8Ss", "", "altivec") 395TARGET_BUILTIN(__builtin_altivec_vminuh, "V8UsV8UsV8Us", "", "altivec") 396TARGET_BUILTIN(__builtin_altivec_vminsw, "V4SiV4SiV4Si", "", "altivec") 397TARGET_BUILTIN(__builtin_altivec_vminuw, "V4UiV4UiV4Ui", "", "altivec") 398TARGET_BUILTIN(__builtin_altivec_vminsd, "V2LLiV2LLiV2LLi", "", "power8-vector") 399TARGET_BUILTIN(__builtin_altivec_vminud, "V2ULLiV2ULLiV2ULLi", "", 400 "power8-vector") 401TARGET_BUILTIN(__builtin_altivec_vminfp, "V4fV4fV4f", "", "altivec") 402 403TARGET_BUILTIN(__builtin_altivec_mtvscr, "vV4i", "", "altivec") 404 405TARGET_BUILTIN(__builtin_altivec_vrefp, "V4fV4f", "", "altivec") 406 407TARGET_BUILTIN(__builtin_altivec_vrlb, "V16cV16cV16Uc", "", "altivec") 408TARGET_BUILTIN(__builtin_altivec_vrlh, "V8sV8sV8Us", "", "altivec") 409TARGET_BUILTIN(__builtin_altivec_vrlw, "V4iV4iV4Ui", "", "altivec") 410TARGET_BUILTIN(__builtin_altivec_vrld, "V2LLiV2LLiV2ULLi", "", "power8-vector") 411 412TARGET_BUILTIN(__builtin_altivec_vsel_4si, "V4iV4iV4iV4Ui", "", "altivec") 413 414TARGET_BUILTIN(__builtin_altivec_vsl, "V4iV4iV4i", "", "altivec") 415TARGET_BUILTIN(__builtin_altivec_vslo, "V4iV4iV4i", "", "altivec") 416 417TARGET_BUILTIN(__builtin_altivec_vsrab, "V16cV16cV16Uc", "", "altivec") 418TARGET_BUILTIN(__builtin_altivec_vsrah, "V8sV8sV8Us", "", "altivec") 419TARGET_BUILTIN(__builtin_altivec_vsraw, "V4iV4iV4Ui", "", "altivec") 420 421TARGET_BUILTIN(__builtin_altivec_vsr, "V4iV4iV4i", "", "altivec") 422TARGET_BUILTIN(__builtin_altivec_vsro, "V4iV4iV4i", "", "altivec") 423 424TARGET_BUILTIN(__builtin_altivec_vrfin, "V4fV4f", "", "altivec") 425 426TARGET_BUILTIN(__builtin_altivec_vrsqrtefp, "V4fV4f", "", "altivec") 427 428TARGET_BUILTIN(__builtin_altivec_vsubcuw, "V4UiV4UiV4Ui", "", "altivec") 429 430TARGET_BUILTIN(__builtin_altivec_vsum4sbs, "V4SiV16ScV4Si", "", "altivec") 431TARGET_BUILTIN(__builtin_altivec_vsum4ubs, "V4UiV16UcV4Ui", "", "altivec") 432TARGET_BUILTIN(__builtin_altivec_vsum4shs, "V4SiV8SsV4Si", "", "altivec") 433 434TARGET_BUILTIN(__builtin_altivec_vsum2sws, "V4SiV4SiV4Si", "", "altivec") 435 436TARGET_BUILTIN(__builtin_altivec_vsumsws, "V4SiV4SiV4Si", "", "altivec") 437 438TARGET_BUILTIN(__builtin_altivec_vrfiz, "V4fV4f", "", "altivec") 439 440TARGET_BUILTIN(__builtin_altivec_vupkhsb, "V8sV16c", "", "altivec") 441TARGET_BUILTIN(__builtin_altivec_vupkhpx, "V4UiV8s", "", "altivec") 442TARGET_BUILTIN(__builtin_altivec_vupkhsh, "V4iV8s", "", "altivec") 443TARGET_BUILTIN(__builtin_altivec_vupkhsw, "V2LLiV4i", "", "power8-vector") 444 445TARGET_BUILTIN(__builtin_altivec_vupklsb, "V8sV16c", "", "altivec") 446TARGET_BUILTIN(__builtin_altivec_vupklpx, "V4UiV8s", "", "altivec") 447TARGET_BUILTIN(__builtin_altivec_vupklsh, "V4iV8s", "", "altivec") 448TARGET_BUILTIN(__builtin_altivec_vupklsw, "V2LLiV4i", "", "power8-vector") 449 450TARGET_BUILTIN(__builtin_altivec_vcmpbfp_p, "iiV4fV4f", "", "altivec") 451 452TARGET_BUILTIN(__builtin_altivec_vcmpgefp_p, "iiV4fV4f", "", "altivec") 453 454TARGET_BUILTIN(__builtin_altivec_vcmpequb_p, "iiV16cV16c", "", "altivec") 455TARGET_BUILTIN(__builtin_altivec_vcmpequh_p, "iiV8sV8s", "", "altivec") 456TARGET_BUILTIN(__builtin_altivec_vcmpequw_p, "iiV4iV4i", "", "altivec") 457TARGET_BUILTIN(__builtin_altivec_vcmpequd_p, "iiV2LLiV2LLi", "", "vsx") 458TARGET_BUILTIN(__builtin_altivec_vcmpeqfp_p, "iiV4fV4f", "", "altivec") 459 460TARGET_BUILTIN(__builtin_altivec_vcmpneb_p, "iiV16cV16c", "", "power9-vector") 461TARGET_BUILTIN(__builtin_altivec_vcmpneh_p, "iiV8sV8s", "", "power9-vector") 462TARGET_BUILTIN(__builtin_altivec_vcmpnew_p, "iiV4iV4i", "", "power9-vector") 463TARGET_BUILTIN(__builtin_altivec_vcmpned_p, "iiV2LLiV2LLi", "", "vsx") 464 465TARGET_BUILTIN(__builtin_altivec_vcmpgtsb_p, "iiV16ScV16Sc", "", "altivec") 466TARGET_BUILTIN(__builtin_altivec_vcmpgtub_p, "iiV16UcV16Uc", "", "altivec") 467TARGET_BUILTIN(__builtin_altivec_vcmpgtsh_p, "iiV8SsV8Ss", "", "altivec") 468TARGET_BUILTIN(__builtin_altivec_vcmpgtuh_p, "iiV8UsV8Us", "", "altivec") 469TARGET_BUILTIN(__builtin_altivec_vcmpgtsw_p, "iiV4SiV4Si", "", "altivec") 470TARGET_BUILTIN(__builtin_altivec_vcmpgtuw_p, "iiV4UiV4Ui", "", "altivec") 471TARGET_BUILTIN(__builtin_altivec_vcmpgtsd_p, "iiV2LLiV2LLi", "", "vsx") 472TARGET_BUILTIN(__builtin_altivec_vcmpgtud_p, "iiV2ULLiV2ULLi", "", "vsx") 473TARGET_BUILTIN(__builtin_altivec_vcmpgtfp_p, "iiV4fV4f", "", "altivec") 474 475TARGET_BUILTIN(__builtin_altivec_vgbbd, "V16UcV16Uc", "", "power8-vector") 476TARGET_BUILTIN(__builtin_altivec_vbpermq, "V2ULLiV16UcV16Uc", "", 477 "power8-vector") 478TARGET_BUILTIN(__builtin_altivec_vbpermd, "V2ULLiV2ULLiV16Uc", "", 479 "power9-vector") 480 481// P8 Crypto built-ins. 482TARGET_BUILTIN(__builtin_altivec_crypto_vsbox, "V16UcV16Uc", "", 483 "power8-vector") 484TARGET_BUILTIN(__builtin_altivec_crypto_vpermxor, "V16UcV16UcV16UcV16Uc", "", 485 "power8-vector") 486TARGET_BUILTIN(__builtin_altivec_crypto_vpermxor_be, "V16UcV16UcV16UcV16Uc", "", 487 "power8-vector") 488TARGET_BUILTIN(__builtin_altivec_crypto_vshasigmaw, "V4UiV4UiIiIi", "", 489 "power8-vector") 490TARGET_BUILTIN(__builtin_altivec_crypto_vshasigmad, "V2ULLiV2ULLiIiIi", "", 491 "power8-vector") 492TARGET_BUILTIN(__builtin_altivec_crypto_vcipher, "V16UcV16UcV16Uc", "", 493 "power8-vector") 494TARGET_BUILTIN(__builtin_altivec_crypto_vcipherlast, "V16UcV16UcV16Uc", "", 495 "power8-vector") 496TARGET_BUILTIN(__builtin_altivec_crypto_vncipher, "V16UcV16UcV16Uc", "", 497 "power8-vector") 498TARGET_BUILTIN(__builtin_altivec_crypto_vncipherlast, "V16UcV16UcV16Uc", "", 499 "power8-vector") 500TARGET_BUILTIN(__builtin_altivec_crypto_vpmsumb, "V16UcV16UcV16Uc", "", 501 "power8-vector") 502TARGET_BUILTIN(__builtin_altivec_crypto_vpmsumh, "V8UsV8UsV8Us", "", 503 "power8-vector") 504TARGET_BUILTIN(__builtin_altivec_crypto_vpmsumw, "V4UiV4UiV4Ui", "", 505 "power8-vector") 506TARGET_BUILTIN(__builtin_altivec_crypto_vpmsumd, "V2ULLiV2ULLiV2ULLi", "", 507 "power8-vector") 508 509TARGET_BUILTIN(__builtin_altivec_vclzb, "V16UcV16Uc", "", "power8-vector") 510TARGET_BUILTIN(__builtin_altivec_vclzh, "V8UsV8Us", "", "power8-vector") 511TARGET_BUILTIN(__builtin_altivec_vclzw, "V4UiV4Ui", "", "power8-vector") 512TARGET_BUILTIN(__builtin_altivec_vclzd, "V2ULLiV2ULLi", "", "power8-vector") 513TARGET_BUILTIN(__builtin_altivec_vctzb, "V16UcV16Uc", "", "power9-vector") 514TARGET_BUILTIN(__builtin_altivec_vctzh, "V8UsV8Us", "", "power9-vector") 515TARGET_BUILTIN(__builtin_altivec_vctzw, "V4UiV4Ui", "", "power9-vector") 516TARGET_BUILTIN(__builtin_altivec_vctzd, "V2ULLiV2ULLi", "", "power9-vector") 517 518// P8 BCD builtins. 519TARGET_BUILTIN(__builtin_ppc_bcdadd, "V16UcV16UcV16UcIi", "", 520 "isa-v207-instructions") 521TARGET_BUILTIN(__builtin_ppc_bcdsub, "V16UcV16UcV16UcIi", "", 522 "isa-v207-instructions") 523TARGET_BUILTIN(__builtin_ppc_bcdadd_p, "iiV16UcV16Uc", "", 524 "isa-v207-instructions") 525TARGET_BUILTIN(__builtin_ppc_bcdsub_p, "iiV16UcV16Uc", "", 526 "isa-v207-instructions") 527 528TARGET_BUILTIN(__builtin_altivec_vclzlsbb, "SiV16Uc", "", "power9-vector") 529TARGET_BUILTIN(__builtin_altivec_vctzlsbb, "SiV16Uc", "", "power9-vector") 530TARGET_BUILTIN(__builtin_altivec_vprtybw, "V4UiV4Ui", "", "power9-vector") 531TARGET_BUILTIN(__builtin_altivec_vprtybd, "V2ULLiV2ULLi", "", "power9-vector") 532TARGET_BUILTIN(__builtin_altivec_vprtybq, "V1ULLLiV1ULLLi", "", "power9-vector") 533 534// Vector population count built-ins 535TARGET_BUILTIN(__builtin_altivec_vpopcntb, "V16UcV16Uc", "", "power8-vector") 536TARGET_BUILTIN(__builtin_altivec_vpopcnth, "V8UsV8Us", "", "power8-vector") 537TARGET_BUILTIN(__builtin_altivec_vpopcntw, "V4UiV4Ui", "", "power8-vector") 538TARGET_BUILTIN(__builtin_altivec_vpopcntd, "V2ULLiV2ULLi", "", "power8-vector") 539 540// Absolute difference built-ins 541TARGET_BUILTIN(__builtin_altivec_vabsdub, "V16UcV16UcV16Uc", "", 542 "power9-vector") 543TARGET_BUILTIN(__builtin_altivec_vabsduh, "V8UsV8UsV8Us", "", "power9-vector") 544TARGET_BUILTIN(__builtin_altivec_vabsduw, "V4UiV4UiV4Ui", "", "power9-vector") 545 546// P9 Shift built-ins. 547TARGET_BUILTIN(__builtin_altivec_vslv, "V16UcV16UcV16Uc", "", "power9-vector") 548TARGET_BUILTIN(__builtin_altivec_vsrv, "V16UcV16UcV16Uc", "", "power9-vector") 549 550// P9 Vector rotate built-ins 551TARGET_BUILTIN(__builtin_altivec_vrlwmi, "V4UiV4UiV4UiV4Ui", "", 552 "power9-vector") 553TARGET_BUILTIN(__builtin_altivec_vrldmi, "V2ULLiV2ULLiV2ULLiV2ULLi", "", 554 "power9-vector") 555TARGET_BUILTIN(__builtin_altivec_vrlwnm, "V4UiV4UiV4Ui", "", "power9-vector") 556TARGET_BUILTIN(__builtin_altivec_vrldnm, "V2ULLiV2ULLiV2ULLi", "", 557 "power9-vector") 558 559// P9 Vector extend sign builtins. 560TARGET_BUILTIN(__builtin_altivec_vextsb2w, "V4SiV16Sc", "", "power9-vector") 561TARGET_BUILTIN(__builtin_altivec_vextsb2d, "V2SLLiV16Sc", "", "power9-vector") 562TARGET_BUILTIN(__builtin_altivec_vextsh2w, "V4SiV8Ss", "", "power9-vector") 563TARGET_BUILTIN(__builtin_altivec_vextsh2d, "V2SLLiV8Ss", "", "power9-vector") 564TARGET_BUILTIN(__builtin_altivec_vextsw2d, "V2SLLiV4Si", "", "power9-vector") 565 566// P10 Vector extend sign builtins. 567TARGET_BUILTIN(__builtin_altivec_vextsd2q, "V1SLLLiV2SLLi", "", 568 "power10-vector") 569 570// P10 Vector Extract with Mask built-ins. 571TARGET_BUILTIN(__builtin_altivec_vextractbm, "UiV16Uc", "", "power10-vector") 572TARGET_BUILTIN(__builtin_altivec_vextracthm, "UiV8Us", "", "power10-vector") 573TARGET_BUILTIN(__builtin_altivec_vextractwm, "UiV4Ui", "", "power10-vector") 574TARGET_BUILTIN(__builtin_altivec_vextractdm, "UiV2ULLi", "", "power10-vector") 575TARGET_BUILTIN(__builtin_altivec_vextractqm, "UiV1ULLLi", "", "power10-vector") 576 577// P10 Vector Divide Extended built-ins. 578TARGET_BUILTIN(__builtin_altivec_vdivesw, "V4SiV4SiV4Si", "", "power10-vector") 579TARGET_BUILTIN(__builtin_altivec_vdiveuw, "V4UiV4UiV4Ui", "", "power10-vector") 580TARGET_BUILTIN(__builtin_altivec_vdivesd, "V2LLiV2LLiV2LLi", "", 581 "power10-vector") 582TARGET_BUILTIN(__builtin_altivec_vdiveud, "V2ULLiV2ULLiV2ULLi", "", 583 "power10-vector") 584TARGET_BUILTIN(__builtin_altivec_vdivesq, "V1SLLLiV1SLLLiV1SLLLi", "", 585 "power10-vector") 586TARGET_BUILTIN(__builtin_altivec_vdiveuq, "V1ULLLiV1ULLLiV1ULLLi", "", 587 "power10-vector") 588 589// P10 Vector Multiply High built-ins. 590TARGET_BUILTIN(__builtin_altivec_vmulhsw, "V4SiV4SiV4Si", "", "power10-vector") 591TARGET_BUILTIN(__builtin_altivec_vmulhuw, "V4UiV4UiV4Ui", "", "power10-vector") 592TARGET_BUILTIN(__builtin_altivec_vmulhsd, "V2LLiV2LLiV2LLi", "", 593 "power10-vector") 594TARGET_BUILTIN(__builtin_altivec_vmulhud, "V2ULLiV2ULLiV2ULLi", "", 595 "power10-vector") 596 597// P10 Vector Expand with Mask built-ins. 598TARGET_BUILTIN(__builtin_altivec_vexpandbm, "V16UcV16Uc", "", "power10-vector") 599TARGET_BUILTIN(__builtin_altivec_vexpandhm, "V8UsV8Us", "", "power10-vector") 600TARGET_BUILTIN(__builtin_altivec_vexpandwm, "V4UiV4Ui", "", "power10-vector") 601TARGET_BUILTIN(__builtin_altivec_vexpanddm, "V2ULLiV2ULLi", "", 602 "power10-vector") 603TARGET_BUILTIN(__builtin_altivec_vexpandqm, "V1ULLLiV1ULLLi", "", 604 "power10-vector") 605 606// P10 Vector Count with Mask built-ins. 607TARGET_BUILTIN(__builtin_altivec_vcntmbb, "ULLiV16UcUi", "", "power10-vector") 608TARGET_BUILTIN(__builtin_altivec_vcntmbh, "ULLiV8UsUi", "", "power10-vector") 609TARGET_BUILTIN(__builtin_altivec_vcntmbw, "ULLiV4UiUi", "", "power10-vector") 610TARGET_BUILTIN(__builtin_altivec_vcntmbd, "ULLiV2ULLiUi", "", "power10-vector") 611 612// P10 Move to VSR with Mask built-ins. 613TARGET_BUILTIN(__builtin_altivec_mtvsrbm, "V16UcULLi", "", "power10-vector") 614TARGET_BUILTIN(__builtin_altivec_mtvsrhm, "V8UsULLi", "", "power10-vector") 615TARGET_BUILTIN(__builtin_altivec_mtvsrwm, "V4UiULLi", "", "power10-vector") 616TARGET_BUILTIN(__builtin_altivec_mtvsrdm, "V2ULLiULLi", "", "power10-vector") 617TARGET_BUILTIN(__builtin_altivec_mtvsrqm, "V1ULLLiULLi", "", "power10-vector") 618 619// P10 Vector Parallel Bits built-ins. 620TARGET_BUILTIN(__builtin_altivec_vpdepd, "V2ULLiV2ULLiV2ULLi", "", 621 "power10-vector") 622TARGET_BUILTIN(__builtin_altivec_vpextd, "V2ULLiV2ULLiV2ULLi", "", 623 "power10-vector") 624 625// P10 Vector String Isolate Built-ins. 626TARGET_BUILTIN(__builtin_altivec_vstribr, "V16UcV16Uc", "", "power10-vector") 627TARGET_BUILTIN(__builtin_altivec_vstribl, "V16UcV16Uc", "", "power10-vector") 628TARGET_BUILTIN(__builtin_altivec_vstrihr, "V8sV8s", "", "power10-vector") 629TARGET_BUILTIN(__builtin_altivec_vstrihl, "V8sV8s", "", "power10-vector") 630TARGET_BUILTIN(__builtin_altivec_vstribr_p, "iiV16Uc", "", "power10-vector") 631TARGET_BUILTIN(__builtin_altivec_vstribl_p, "iiV16Uc", "", "power10-vector") 632TARGET_BUILTIN(__builtin_altivec_vstrihr_p, "iiV8s", "", "power10-vector") 633TARGET_BUILTIN(__builtin_altivec_vstrihl_p, "iiV8s", "", "power10-vector") 634 635// P10 Vector Centrifuge built-in. 636TARGET_BUILTIN(__builtin_altivec_vcfuged, "V2ULLiV2ULLiV2ULLi", "", 637 "power10-vector") 638 639// P10 Vector Gather Every N-th Bit built-in. 640TARGET_BUILTIN(__builtin_altivec_vgnb, "ULLiV1ULLLiIi", "", "power10-vector") 641 642// P10 Vector Clear Bytes built-ins. 643TARGET_BUILTIN(__builtin_altivec_vclrlb, "V16UcV16UcUi", "", "power10-vector") 644TARGET_BUILTIN(__builtin_altivec_vclrrb, "V16UcV16UcUi", "", "power10-vector") 645 646// P10 Vector Count Leading / Trailing Zeroes under bit Mask built-ins. 647TARGET_BUILTIN(__builtin_altivec_vclzdm, "V2ULLiV2ULLiV2ULLi", "", 648 "power10-vector") 649TARGET_BUILTIN(__builtin_altivec_vctzdm, "V2ULLiV2ULLiV2ULLi", "", 650 "power10-vector") 651 652// P10 Vector Shift built-ins. 653TARGET_BUILTIN(__builtin_altivec_vsldbi, "V16UcV16UcV16UcIi", "", 654 "power10-vector") 655TARGET_BUILTIN(__builtin_altivec_vsrdbi, "V16UcV16UcV16UcIi", "", 656 "power10-vector") 657 658// P10 Vector Insert built-ins. 659TARGET_BUILTIN(__builtin_altivec_vinsblx, "V16UcV16UcUiUi", "", 660 "power10-vector") 661TARGET_BUILTIN(__builtin_altivec_vinsbrx, "V16UcV16UcUiUi", "", 662 "power10-vector") 663TARGET_BUILTIN(__builtin_altivec_vinshlx, "V8UsV8UsUiUi", "", "power10-vector") 664TARGET_BUILTIN(__builtin_altivec_vinshrx, "V8UsV8UsUiUi", "", "power10-vector") 665TARGET_BUILTIN(__builtin_altivec_vinswlx, "V4UiV4UiUiUi", "", "power10-vector") 666TARGET_BUILTIN(__builtin_altivec_vinswrx, "V4UiV4UiUiUi", "", "power10-vector") 667TARGET_BUILTIN(__builtin_altivec_vinsdlx, "V2ULLiV2ULLiULLiULLi", "", 668 "power10-vector") 669TARGET_BUILTIN(__builtin_altivec_vinsdrx, "V2ULLiV2ULLiULLiULLi", "", 670 "power10-vector") 671TARGET_BUILTIN(__builtin_altivec_vinsbvlx, "V16UcV16UcUiV16Uc", "", 672 "power10-vector") 673TARGET_BUILTIN(__builtin_altivec_vinsbvrx, "V16UcV16UcUiV16Uc", "", 674 "power10-vector") 675TARGET_BUILTIN(__builtin_altivec_vinshvlx, "V8UsV8UsUiV8Us", "", 676 "power10-vector") 677TARGET_BUILTIN(__builtin_altivec_vinshvrx, "V8UsV8UsUiV8Us", "", 678 "power10-vector") 679TARGET_BUILTIN(__builtin_altivec_vinswvlx, "V4UiV4UiUiV4Ui", "", 680 "power10-vector") 681TARGET_BUILTIN(__builtin_altivec_vinswvrx, "V4UiV4UiUiV4Ui", "", 682 "power10-vector") 683TARGET_BUILTIN(__builtin_altivec_vinsw, "V16UcV16UcUiIi", "", "power10-vector") 684TARGET_BUILTIN(__builtin_altivec_vinsd, "V16UcV16UcULLiIi", "", 685 "power10-vector") 686TARGET_BUILTIN(__builtin_altivec_vinsw_elt, "V16UcV16UcUiiC", "", 687 "power10-vector") 688TARGET_BUILTIN(__builtin_altivec_vinsd_elt, "V16UcV16UcULLiiC", "", 689 "power10-vector") 690 691// P10 Vector Extract built-ins. 692TARGET_BUILTIN(__builtin_altivec_vextdubvlx, "V2ULLiV16UcV16UcUi", "", 693 "power10-vector") 694TARGET_BUILTIN(__builtin_altivec_vextdubvrx, "V2ULLiV16UcV16UcUi", "", 695 "power10-vector") 696TARGET_BUILTIN(__builtin_altivec_vextduhvlx, "V2ULLiV8UsV8UsUi", "", 697 "power10-vector") 698TARGET_BUILTIN(__builtin_altivec_vextduhvrx, "V2ULLiV8UsV8UsUi", "", 699 "power10-vector") 700TARGET_BUILTIN(__builtin_altivec_vextduwvlx, "V2ULLiV4UiV4UiUi", "", 701 "power10-vector") 702TARGET_BUILTIN(__builtin_altivec_vextduwvrx, "V2ULLiV4UiV4UiUi", "", 703 "power10-vector") 704TARGET_BUILTIN(__builtin_altivec_vextddvlx, "V2ULLiV2ULLiV2ULLiUi", "", 705 "power10-vector") 706TARGET_BUILTIN(__builtin_altivec_vextddvrx, "V2ULLiV2ULLiV2ULLiUi", "", 707 "power10-vector") 708 709// P10 Vector rotate built-ins. 710TARGET_BUILTIN(__builtin_altivec_vrlqmi, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi", "", 711 "power10-vector") 712TARGET_BUILTIN(__builtin_altivec_vrlqnm, "V1ULLLiV1ULLLiV1ULLLi", "", 713 "power10-vector") 714 715// VSX built-ins. 716 717TARGET_BUILTIN(__builtin_vsx_lxvd2x, "V2dLivC*", "", "vsx") 718TARGET_BUILTIN(__builtin_vsx_lxvw4x, "V4iLivC*", "", "vsx") 719TARGET_BUILTIN(__builtin_vsx_lxvd2x_be, "V2dSLLivC*", "", "vsx") 720TARGET_BUILTIN(__builtin_vsx_lxvw4x_be, "V4iSLLivC*", "", "vsx") 721 722TARGET_BUILTIN(__builtin_vsx_stxvd2x, "vV2dLiv*", "", "vsx") 723TARGET_BUILTIN(__builtin_vsx_stxvw4x, "vV4iLiv*", "", "vsx") 724TARGET_BUILTIN(__builtin_vsx_stxvd2x_be, "vV2dSLLivC*", "", "vsx") 725TARGET_BUILTIN(__builtin_vsx_stxvw4x_be, "vV4iSLLivC*", "", "vsx") 726 727TARGET_BUILTIN(__builtin_vsx_lxvl, "V4ivC*ULLi", "", "power9-vector") 728TARGET_BUILTIN(__builtin_vsx_lxvll, "V4ivC*ULLi", "", "power9-vector") 729TARGET_BUILTIN(__builtin_vsx_stxvl, "vV4iv*ULLi", "", "power9-vector") 730TARGET_BUILTIN(__builtin_vsx_stxvll, "vV4iv*ULLi", "", "power9-vector") 731TARGET_BUILTIN(__builtin_vsx_ldrmb, "V16UcCc*Ii", "", "isa-v207-instructions") 732TARGET_BUILTIN(__builtin_vsx_strmb, "vCc*IiV16Uc", "", "isa-v207-instructions") 733 734TARGET_BUILTIN(__builtin_vsx_xvmaxdp, "V2dV2dV2d", "", "vsx") 735TARGET_BUILTIN(__builtin_vsx_xvmaxsp, "V4fV4fV4f", "", "vsx") 736TARGET_BUILTIN(__builtin_vsx_xsmaxdp, "ddd", "", "vsx") 737 738TARGET_BUILTIN(__builtin_vsx_xvmindp, "V2dV2dV2d", "", "vsx") 739TARGET_BUILTIN(__builtin_vsx_xvminsp, "V4fV4fV4f", "", "vsx") 740TARGET_BUILTIN(__builtin_vsx_xsmindp, "ddd", "", "vsx") 741 742TARGET_BUILTIN(__builtin_vsx_xvdivdp, "V2dV2dV2d", "", "vsx") 743TARGET_BUILTIN(__builtin_vsx_xvdivsp, "V4fV4fV4f", "", "vsx") 744 745TARGET_BUILTIN(__builtin_vsx_xvrdpip, "V2dV2d", "", "vsx") 746TARGET_BUILTIN(__builtin_vsx_xvrspip, "V4fV4f", "", "vsx") 747 748TARGET_BUILTIN(__builtin_vsx_xvcmpeqdp, "V2ULLiV2dV2d", "", "vsx") 749TARGET_BUILTIN(__builtin_vsx_xvcmpeqsp, "V4UiV4fV4f", "", "vsx") 750 751TARGET_BUILTIN(__builtin_vsx_xvcmpeqdp_p, "iiV2dV2d", "", "vsx") 752TARGET_BUILTIN(__builtin_vsx_xvcmpeqsp_p, "iiV4fV4f", "", "vsx") 753 754TARGET_BUILTIN(__builtin_vsx_xvcmpgedp, "V2ULLiV2dV2d", "", "vsx") 755TARGET_BUILTIN(__builtin_vsx_xvcmpgesp, "V4UiV4fV4f", "", "vsx") 756 757TARGET_BUILTIN(__builtin_vsx_xvcmpgedp_p, "iiV2dV2d", "", "vsx") 758TARGET_BUILTIN(__builtin_vsx_xvcmpgesp_p, "iiV4fV4f", "", "vsx") 759 760TARGET_BUILTIN(__builtin_vsx_xvcmpgtdp, "V2ULLiV2dV2d", "", "vsx") 761TARGET_BUILTIN(__builtin_vsx_xvcmpgtsp, "V4UiV4fV4f", "", "vsx") 762 763TARGET_BUILTIN(__builtin_vsx_xvcmpgtdp_p, "iiV2dV2d", "", "vsx") 764TARGET_BUILTIN(__builtin_vsx_xvcmpgtsp_p, "iiV4fV4f", "", "vsx") 765 766TARGET_BUILTIN(__builtin_vsx_xvrdpim, "V2dV2d", "", "vsx") 767TARGET_BUILTIN(__builtin_vsx_xvrspim, "V4fV4f", "", "vsx") 768 769TARGET_BUILTIN(__builtin_vsx_xvrdpi, "V2dV2d", "", "vsx") 770TARGET_BUILTIN(__builtin_vsx_xvrspi, "V4fV4f", "", "vsx") 771 772TARGET_BUILTIN(__builtin_vsx_xvrdpic, "V2dV2d", "", "vsx") 773TARGET_BUILTIN(__builtin_vsx_xvrspic, "V4fV4f", "", "vsx") 774 775TARGET_BUILTIN(__builtin_vsx_xvrdpiz, "V2dV2d", "", "vsx") 776TARGET_BUILTIN(__builtin_vsx_xvrspiz, "V4fV4f", "", "vsx") 777 778TARGET_BUILTIN(__builtin_vsx_xvmaddadp, "V2dV2dV2dV2d", "", "vsx") 779TARGET_BUILTIN(__builtin_vsx_xvmaddasp, "V4fV4fV4fV4f", "", "vsx") 780 781TARGET_BUILTIN(__builtin_vsx_xvmsubadp, "V2dV2dV2dV2d", "", "vsx") 782TARGET_BUILTIN(__builtin_vsx_xvmsubasp, "V4fV4fV4fV4f", "", "vsx") 783 784TARGET_BUILTIN(__builtin_vsx_xvmuldp, "V2dV2dV2d", "", "vsx") 785TARGET_BUILTIN(__builtin_vsx_xvmulsp, "V4fV4fV4f", "", "vsx") 786 787TARGET_BUILTIN(__builtin_vsx_xvnmaddadp, "V2dV2dV2dV2d", "", "vsx") 788TARGET_BUILTIN(__builtin_vsx_xvnmaddasp, "V4fV4fV4fV4f", "", "vsx") 789 790TARGET_BUILTIN(__builtin_vsx_xvnmsubadp, "V2dV2dV2dV2d", "", "vsx") 791TARGET_BUILTIN(__builtin_vsx_xvnmsubasp, "V4fV4fV4fV4f", "", "vsx") 792 793TARGET_BUILTIN(__builtin_vsx_xvredp, "V2dV2d", "", "vsx") 794TARGET_BUILTIN(__builtin_vsx_xvresp, "V4fV4f", "", "vsx") 795 796TARGET_BUILTIN(__builtin_vsx_xvrsqrtedp, "V2dV2d", "", "vsx") 797TARGET_BUILTIN(__builtin_vsx_xvrsqrtesp, "V4fV4f", "", "vsx") 798 799TARGET_BUILTIN(__builtin_vsx_xvsqrtdp, "V2dV2d", "", "vsx") 800TARGET_BUILTIN(__builtin_vsx_xvsqrtsp, "V4fV4f", "", "vsx") 801 802TARGET_BUILTIN(__builtin_vsx_xxleqv, "V4UiV4UiV4Ui", "", "power8-vector") 803 804TARGET_BUILTIN(__builtin_vsx_xvcpsgndp, "V2dV2dV2d", "", "vsx") 805TARGET_BUILTIN(__builtin_vsx_xvcpsgnsp, "V4fV4fV4f", "", "vsx") 806 807TARGET_BUILTIN(__builtin_vsx_xvabssp, "V4fV4f", "", "vsx") 808TARGET_BUILTIN(__builtin_vsx_xvabsdp, "V2dV2d", "", "vsx") 809 810TARGET_BUILTIN(__builtin_vsx_xxgenpcvbm, "V16UcV16Uci", "", "power10-vector") 811TARGET_BUILTIN(__builtin_vsx_xxgenpcvhm, "V8UsV8Usi", "", "power10-vector") 812TARGET_BUILTIN(__builtin_vsx_xxgenpcvwm, "V4UiV4Uii", "", "power10-vector") 813TARGET_BUILTIN(__builtin_vsx_xxgenpcvdm, "V2ULLiV2ULLii", "", "power10-vector") 814 815// vector Insert/Extract exponent/significand builtins 816TARGET_BUILTIN(__builtin_vsx_xviexpdp, "V2dV2ULLiV2ULLi", "", "power9-vector") 817TARGET_BUILTIN(__builtin_vsx_xviexpsp, "V4fV4UiV4Ui", "", "power9-vector") 818TARGET_BUILTIN(__builtin_vsx_xvxexpdp, "V2ULLiV2d", "", "power9-vector") 819TARGET_BUILTIN(__builtin_vsx_xvxexpsp, "V4UiV4f", "", "power9-vector") 820TARGET_BUILTIN(__builtin_vsx_xvxsigdp, "V2ULLiV2d", "", "power9-vector") 821TARGET_BUILTIN(__builtin_vsx_xvxsigsp, "V4UiV4f", "", "power9-vector") 822 823// Conversion builtins 824TARGET_BUILTIN(__builtin_vsx_xvcvdpsxws, "V4SiV2d", "", "vsx") 825TARGET_BUILTIN(__builtin_vsx_xvcvdpuxws, "V4UiV2d", "", "vsx") 826TARGET_BUILTIN(__builtin_vsx_xvcvspsxds, "V2SLLiV4f", "", "vsx") 827TARGET_BUILTIN(__builtin_vsx_xvcvspuxds, "V2ULLiV4f", "", "vsx") 828TARGET_BUILTIN(__builtin_vsx_xvcvsxwdp, "V2dV4Si", "", "vsx") 829TARGET_BUILTIN(__builtin_vsx_xvcvuxwdp, "V2dV4Ui", "", "vsx") 830TARGET_BUILTIN(__builtin_vsx_xvcvspdp, "V2dV4f", "", "vsx") 831TARGET_BUILTIN(__builtin_vsx_xvcvsxdsp, "V4fV2SLLi", "", "vsx") 832TARGET_BUILTIN(__builtin_vsx_xvcvuxdsp, "V4fV2ULLi", "", "vsx") 833TARGET_BUILTIN(__builtin_vsx_xvcvdpsp, "V4fV2d", "", "vsx") 834 835TARGET_BUILTIN(__builtin_vsx_xvcvsphp, "V4fV4f", "", "power9-vector") 836TARGET_BUILTIN(__builtin_vsx_xvcvhpsp, "V4fV8Us", "", "power9-vector") 837 838TARGET_BUILTIN(__builtin_vsx_xvcvspbf16, "V16UcV16Uc", "", "power10-vector") 839TARGET_BUILTIN(__builtin_vsx_xvcvbf16spn, "V16UcV16Uc", "", "power10-vector") 840 841// Vector Test Data Class builtins 842TARGET_BUILTIN(__builtin_vsx_xvtstdcdp, "V2ULLiV2dIi", "", "power9-vector") 843TARGET_BUILTIN(__builtin_vsx_xvtstdcsp, "V4UiV4fIi", "", "power9-vector") 844 845TARGET_BUILTIN(__builtin_vsx_insertword, "V16UcV4UiV16UcIi", "", "vsx") 846TARGET_BUILTIN(__builtin_vsx_extractuword, "V2ULLiV16UcIi", "", "vsx") 847 848TARGET_BUILTIN(__builtin_vsx_xxpermdi, "v.", "t", "vsx") 849TARGET_BUILTIN(__builtin_vsx_xxsldwi, "v.", "t", "vsx") 850 851TARGET_BUILTIN(__builtin_vsx_xxeval, "V2ULLiV2ULLiV2ULLiV2ULLiIi", "", 852 "power10-vector") 853 854TARGET_BUILTIN(__builtin_vsx_xvtlsbb, "iV16UcUi", "", "power10-vector") 855 856TARGET_BUILTIN(__builtin_vsx_xvtdivdp, "iV2dV2d", "", "vsx") 857TARGET_BUILTIN(__builtin_vsx_xvtdivsp, "iV4fV4f", "", "vsx") 858TARGET_BUILTIN(__builtin_vsx_xvtsqrtdp, "iV2d", "", "vsx") 859TARGET_BUILTIN(__builtin_vsx_xvtsqrtsp, "iV4f", "", "vsx") 860 861// P10 Vector Permute Extended built-in. 862TARGET_BUILTIN(__builtin_vsx_xxpermx, "V16UcV16UcV16UcV16UcIi", "", 863 "power10-vector") 864 865// P10 Vector Blend built-ins. 866TARGET_BUILTIN(__builtin_vsx_xxblendvb, "V16UcV16UcV16UcV16Uc", "", 867 "power10-vector") 868TARGET_BUILTIN(__builtin_vsx_xxblendvh, "V8UsV8UsV8UsV8Us", "", 869 "power10-vector") 870TARGET_BUILTIN(__builtin_vsx_xxblendvw, "V4UiV4UiV4UiV4Ui", "", 871 "power10-vector") 872TARGET_BUILTIN(__builtin_vsx_xxblendvd, "V2ULLiV2ULLiV2ULLiV2ULLi", "", 873 "power10-vector") 874 875// Float 128 built-ins 876TARGET_BUILTIN(__builtin_sqrtf128_round_to_odd, "LLdLLd", "", "float128") 877TARGET_BUILTIN(__builtin_addf128_round_to_odd, "LLdLLdLLd", "", "float128") 878TARGET_BUILTIN(__builtin_subf128_round_to_odd, "LLdLLdLLd", "", "float128") 879TARGET_BUILTIN(__builtin_mulf128_round_to_odd, "LLdLLdLLd", "", "float128") 880TARGET_BUILTIN(__builtin_divf128_round_to_odd, "LLdLLdLLd", "", "float128") 881TARGET_BUILTIN(__builtin_fmaf128_round_to_odd, "LLdLLdLLdLLd", "", "float128") 882TARGET_BUILTIN(__builtin_truncf128_round_to_odd, "dLLd", "", "float128") 883TARGET_BUILTIN(__builtin_vsx_scalar_extract_expq, "ULLiLLd", "", "float128") 884TARGET_BUILTIN(__builtin_vsx_scalar_insert_exp_qp, "LLdLLdULLi", "", "float128") 885 886// Fastmath by default builtins 887BUILTIN(__builtin_ppc_rsqrtf, "V4fV4f", "") 888BUILTIN(__builtin_ppc_rsqrtd, "V2dV2d", "") 889BUILTIN(__builtin_ppc_recipdivf, "V4fV4fV4f", "") 890BUILTIN(__builtin_ppc_recipdivd, "V2dV2dV2d", "") 891 892// HTM builtins 893TARGET_BUILTIN(__builtin_tbegin, "UiUIi", "", "htm") 894TARGET_BUILTIN(__builtin_tend, "UiUIi", "", "htm") 895 896TARGET_BUILTIN(__builtin_tabort, "UiUi", "", "htm") 897TARGET_BUILTIN(__builtin_tabortdc, "UiUiUiUi", "", "htm") 898TARGET_BUILTIN(__builtin_tabortdci, "UiUiUii", "", "htm") 899TARGET_BUILTIN(__builtin_tabortwc, "UiUiUiUi", "", "htm") 900TARGET_BUILTIN(__builtin_tabortwci, "UiUiUii", "", "htm") 901 902TARGET_BUILTIN(__builtin_tcheck, "Ui", "", "htm") 903TARGET_BUILTIN(__builtin_treclaim, "UiUi", "", "htm") 904TARGET_BUILTIN(__builtin_trechkpt, "Ui", "", "htm") 905TARGET_BUILTIN(__builtin_tsr, "UiUi", "", "htm") 906 907TARGET_BUILTIN(__builtin_tendall, "Ui", "", "htm") 908TARGET_BUILTIN(__builtin_tresume, "Ui", "", "htm") 909TARGET_BUILTIN(__builtin_tsuspend, "Ui", "", "htm") 910 911TARGET_BUILTIN(__builtin_get_texasr, "LUi", "c", "htm") 912TARGET_BUILTIN(__builtin_get_texasru, "LUi", "c", "htm") 913TARGET_BUILTIN(__builtin_get_tfhar, "LUi", "c", "htm") 914TARGET_BUILTIN(__builtin_get_tfiar, "LUi", "c", "htm") 915 916TARGET_BUILTIN(__builtin_set_texasr, "vLUi", "c", "htm") 917TARGET_BUILTIN(__builtin_set_texasru, "vLUi", "c", "htm") 918TARGET_BUILTIN(__builtin_set_tfhar, "vLUi", "c", "htm") 919TARGET_BUILTIN(__builtin_set_tfiar, "vLUi", "c", "htm") 920 921TARGET_BUILTIN(__builtin_ttest, "LUi", "", "htm") 922 923// Scalar built-ins 924TARGET_BUILTIN(__builtin_divwe, "SiSiSi", "", "extdiv") 925TARGET_BUILTIN(__builtin_divweu, "UiUiUi", "", "extdiv") 926TARGET_BUILTIN(__builtin_divde, "SLLiSLLiSLLi", "", "extdiv") 927TARGET_BUILTIN(__builtin_divdeu, "ULLiULLiULLi", "", "extdiv") 928TARGET_BUILTIN(__builtin_bpermd, "SLLiSLLiSLLi", "", "bpermd") 929TARGET_BUILTIN(__builtin_pdepd, "ULLiULLiULLi", "", "isa-v31-instructions") 930TARGET_BUILTIN(__builtin_pextd, "ULLiULLiULLi", "", "isa-v31-instructions") 931TARGET_BUILTIN(__builtin_cfuged, "ULLiULLiULLi", "", "isa-v31-instructions") 932TARGET_BUILTIN(__builtin_cntlzdm, "ULLiULLiULLi", "", "isa-v31-instructions") 933TARGET_BUILTIN(__builtin_cnttzdm, "ULLiULLiULLi", "", "isa-v31-instructions") 934 935// Double-double (un)pack 936BUILTIN(__builtin_unpack_longdouble, "dLdIi", "") 937BUILTIN(__builtin_pack_longdouble, "Lddd", "") 938 939// Generate random number 940TARGET_BUILTIN(__builtin_darn, "LLi", "", "isa-v30-instructions") 941TARGET_BUILTIN(__builtin_darn_raw, "LLi", "", "isa-v30-instructions") 942TARGET_BUILTIN(__builtin_darn_32, "i", "", "isa-v30-instructions") 943 944// Vector int128 (un)pack 945TARGET_BUILTIN(__builtin_unpack_vector_int128, "ULLiV1LLLii", "", "vsx") 946TARGET_BUILTIN(__builtin_pack_vector_int128, "V1LLLiULLiULLi", "", "vsx") 947 948// Set the floating point rounding mode 949BUILTIN(__builtin_setrnd, "di", "") 950 951// Get content from current FPSCR 952BUILTIN(__builtin_readflm, "d", "") 953 954// Set content of FPSCR, and return its content before update 955BUILTIN(__builtin_setflm, "dd", "") 956 957// Cache built-ins 958BUILTIN(__builtin_dcbf, "vvC*", "") 959 960// Built-ins requiring custom code generation. 961// Because these built-ins rely on target-dependent types and to avoid pervasive 962// change, they are type checked manually in Sema using custom type descriptors. 963// The first argument of the CUSTOM_BUILTIN macro is the name of the built-in 964// with its prefix, the second argument is the name of the intrinsic this 965// built-in generates, the third argument specifies the type of the function 966// (result value, then each argument) as follows: 967// i -> Unsigned integer followed by the greatest possible value for that 968// argument or 0 if no constraint on the value. 969// (e.g. i15 for a 4-bits value) 970// V -> Vector type used with MMA built-ins (vector unsigned char) 971// W -> PPC Vector type followed by the size of the vector type. 972// (e.g. W512 for __vector_quad) 973// any other descriptor -> Fall back to generic type descriptor decoding. 974// The 'C' suffix can be used as a suffix to specify the const type. 975// The '*' suffix can be used as a suffix to specify a pointer to a type. 976// The fourth argument is set to true if the built-in accumulates its result into 977// its given accumulator. 978 979// Provided builtins with _mma_ prefix for compatibility. 980CUSTOM_BUILTIN(mma_lxvp, vsx_lxvp, "W256SLiW256C*", false, 981 "paired-vector-memops") 982CUSTOM_BUILTIN(mma_stxvp, vsx_stxvp, "vW256SLiW256*", false, 983 "paired-vector-memops") 984CUSTOM_BUILTIN(mma_assemble_pair, vsx_assemble_pair, "vW256*VV", false, 985 "paired-vector-memops") 986CUSTOM_BUILTIN(mma_disassemble_pair, vsx_disassemble_pair, "vv*W256*", false, 987 "paired-vector-memops") 988CUSTOM_BUILTIN(vsx_build_pair, vsx_assemble_pair, "vW256*VV", false, 989 "paired-vector-memops") 990CUSTOM_BUILTIN(mma_build_acc, mma_assemble_acc, "vW512*VVVV", false, "mma") 991 992// UNALIASED_CUSTOM_BUILTIN macro is used for built-ins that have 993// the same name as that of the intrinsic they generate, i.e. the 994// ID and INTR are the same. 995// This avoids repeating the ID and INTR in the macro expression. 996 997UNALIASED_CUSTOM_BUILTIN(vsx_lxvp, "W256SLiW256C*", false, 998 "paired-vector-memops") 999UNALIASED_CUSTOM_BUILTIN(vsx_stxvp, "vW256SLiW256*", false, 1000 "paired-vector-memops") 1001UNALIASED_CUSTOM_BUILTIN(vsx_assemble_pair, "vW256*VV", false, 1002 "paired-vector-memops") 1003UNALIASED_CUSTOM_BUILTIN(vsx_disassemble_pair, "vv*W256*", false, 1004 "paired-vector-memops") 1005 1006// TODO: Require only mma after backend supports these without paired memops 1007UNALIASED_CUSTOM_BUILTIN(mma_assemble_acc, "vW512*VVVV", false, 1008 "mma,paired-vector-memops") 1009UNALIASED_CUSTOM_BUILTIN(mma_disassemble_acc, "vv*W512*", false, 1010 "mma,paired-vector-memops") 1011UNALIASED_CUSTOM_BUILTIN(mma_xxmtacc, "vW512*", true, 1012 "mma,paired-vector-memops") 1013UNALIASED_CUSTOM_BUILTIN(mma_xxmfacc, "vW512*", true, 1014 "mma,paired-vector-memops") 1015UNALIASED_CUSTOM_BUILTIN(mma_xxsetaccz, "vW512*", false, 1016 "mma,paired-vector-memops") 1017UNALIASED_CUSTOM_BUILTIN(mma_xvi4ger8, "vW512*VV", false, 1018 "mma,paired-vector-memops") 1019UNALIASED_CUSTOM_BUILTIN(mma_xvi8ger4, "vW512*VV", false, 1020 "mma,paired-vector-memops") 1021UNALIASED_CUSTOM_BUILTIN(mma_xvi16ger2, "vW512*VV", false, 1022 "mma,paired-vector-memops") 1023UNALIASED_CUSTOM_BUILTIN(mma_xvi16ger2s, "vW512*VV", false, 1024 "mma,paired-vector-memops") 1025UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2, "vW512*VV", false, 1026 "mma,paired-vector-memops") 1027UNALIASED_CUSTOM_BUILTIN(mma_xvf32ger, "vW512*VV", false, 1028 "mma,paired-vector-memops") 1029UNALIASED_CUSTOM_BUILTIN(mma_xvf64ger, "vW512*W256V", false, 1030 "mma,paired-vector-memops") 1031UNALIASED_CUSTOM_BUILTIN(mma_pmxvi4ger8, "vW512*VVi15i15i255", false, 1032 "mma,paired-vector-memops") 1033UNALIASED_CUSTOM_BUILTIN(mma_pmxvi8ger4, "vW512*VVi15i15i15", false, 1034 "mma,paired-vector-memops") 1035UNALIASED_CUSTOM_BUILTIN(mma_pmxvi16ger2, "vW512*VVi15i15i3", false, 1036 "mma,paired-vector-memops") 1037UNALIASED_CUSTOM_BUILTIN(mma_pmxvi16ger2s, "vW512*VVi15i15i3", false, 1038 "mma,paired-vector-memops") 1039UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2, "vW512*VVi15i15i3", false, 1040 "mma,paired-vector-memops") 1041UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32ger, "vW512*VVi15i15", false, 1042 "mma,paired-vector-memops") 1043UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64ger, "vW512*W256Vi15i3", false, 1044 "mma,paired-vector-memops") 1045UNALIASED_CUSTOM_BUILTIN(mma_xvi4ger8pp, "vW512*VV", true, 1046 "mma,paired-vector-memops") 1047UNALIASED_CUSTOM_BUILTIN(mma_xvi8ger4pp, "vW512*VV", true, 1048 "mma,paired-vector-memops") 1049UNALIASED_CUSTOM_BUILTIN(mma_xvi8ger4spp, "vW512*VV", true, 1050 "mma,paired-vector-memops") 1051UNALIASED_CUSTOM_BUILTIN(mma_xvi16ger2pp, "vW512*VV", true, 1052 "mma,paired-vector-memops") 1053UNALIASED_CUSTOM_BUILTIN(mma_xvi16ger2spp, "vW512*VV", true, 1054 "mma,paired-vector-memops") 1055UNALIASED_CUSTOM_BUILTIN(mma_pmxvi4ger8pp, "vW512*VVi15i15i255", true, 1056 "mma,paired-vector-memops") 1057UNALIASED_CUSTOM_BUILTIN(mma_pmxvi8ger4pp, "vW512*VVi15i15i15", true, 1058 "mma,paired-vector-memops") 1059UNALIASED_CUSTOM_BUILTIN(mma_pmxvi8ger4spp, "vW512*VVi15i15i15", true, 1060 "mma,paired-vector-memops") 1061UNALIASED_CUSTOM_BUILTIN(mma_pmxvi16ger2pp, "vW512*VVi15i15i3", true, 1062 "mma,paired-vector-memops") 1063UNALIASED_CUSTOM_BUILTIN(mma_pmxvi16ger2spp, "vW512*VVi15i15i3", true, 1064 "mma,paired-vector-memops") 1065UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2pp, "vW512*VV", true, 1066 "mma,paired-vector-memops") 1067UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2pn, "vW512*VV", true, 1068 "mma,paired-vector-memops") 1069UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2np, "vW512*VV", true, 1070 "mma,paired-vector-memops") 1071UNALIASED_CUSTOM_BUILTIN(mma_xvf16ger2nn, "vW512*VV", true, 1072 "mma,paired-vector-memops") 1073UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2pp, "vW512*VVi15i15i3", true, 1074 "mma,paired-vector-memops") 1075UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2pn, "vW512*VVi15i15i3", true, 1076 "mma,paired-vector-memops") 1077UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2np, "vW512*VVi15i15i3", true, 1078 "mma,paired-vector-memops") 1079UNALIASED_CUSTOM_BUILTIN(mma_pmxvf16ger2nn, "vW512*VVi15i15i3", true, 1080 "mma,paired-vector-memops") 1081UNALIASED_CUSTOM_BUILTIN(mma_xvf32gerpp, "vW512*VV", true, 1082 "mma,paired-vector-memops") 1083UNALIASED_CUSTOM_BUILTIN(mma_xvf32gerpn, "vW512*VV", true, 1084 "mma,paired-vector-memops") 1085UNALIASED_CUSTOM_BUILTIN(mma_xvf32gernp, "vW512*VV", true, 1086 "mma,paired-vector-memops") 1087UNALIASED_CUSTOM_BUILTIN(mma_xvf32gernn, "vW512*VV", true, 1088 "mma,paired-vector-memops") 1089UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32gerpp, "vW512*VVi15i15", true, 1090 "mma,paired-vector-memops") 1091UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32gerpn, "vW512*VVi15i15", true, 1092 "mma,paired-vector-memops") 1093UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32gernp, "vW512*VVi15i15", true, 1094 "mma,paired-vector-memops") 1095UNALIASED_CUSTOM_BUILTIN(mma_pmxvf32gernn, "vW512*VVi15i15", true, 1096 "mma,paired-vector-memops") 1097UNALIASED_CUSTOM_BUILTIN(mma_xvf64gerpp, "vW512*W256V", true, 1098 "mma,paired-vector-memops") 1099UNALIASED_CUSTOM_BUILTIN(mma_xvf64gerpn, "vW512*W256V", true, 1100 "mma,paired-vector-memops") 1101UNALIASED_CUSTOM_BUILTIN(mma_xvf64gernp, "vW512*W256V", true, 1102 "mma,paired-vector-memops") 1103UNALIASED_CUSTOM_BUILTIN(mma_xvf64gernn, "vW512*W256V", true, 1104 "mma,paired-vector-memops") 1105UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64gerpp, "vW512*W256Vi15i3", true, 1106 "mma,paired-vector-memops") 1107UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64gerpn, "vW512*W256Vi15i3", true, 1108 "mma,paired-vector-memops") 1109UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64gernp, "vW512*W256Vi15i3", true, 1110 "mma,paired-vector-memops") 1111UNALIASED_CUSTOM_BUILTIN(mma_pmxvf64gernn, "vW512*W256Vi15i3", true, 1112 "mma,paired-vector-memops") 1113UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2, "vW512*VV", false, 1114 "mma,paired-vector-memops") 1115UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2, "vW512*VVi15i15i3", false, 1116 "mma,paired-vector-memops") 1117UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2pp, "vW512*VV", true, 1118 "mma,paired-vector-memops") 1119UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2pn, "vW512*VV", true, 1120 "mma,paired-vector-memops") 1121UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2np, "vW512*VV", true, 1122 "mma,paired-vector-memops") 1123UNALIASED_CUSTOM_BUILTIN(mma_xvbf16ger2nn, "vW512*VV", true, 1124 "mma,paired-vector-memops") 1125UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2pp, "vW512*VVi15i15i3", true, 1126 "mma,paired-vector-memops") 1127UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2pn, "vW512*VVi15i15i3", true, 1128 "mma,paired-vector-memops") 1129UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2np, "vW512*VVi15i15i3", true, 1130 "mma,paired-vector-memops") 1131UNALIASED_CUSTOM_BUILTIN(mma_pmxvbf16ger2nn, "vW512*VVi15i15i3", true, 1132 "mma,paired-vector-memops") 1133 1134// FIXME: Obviously incomplete. 1135 1136#undef BUILTIN 1137#undef CUSTOM_BUILTIN 1138#undef UNALIASED_CUSTOM_BUILTIN 1139