1/*
2 * Single-precision vector atanh(x) function.
3 *
4 * Copyright (c) 2022-2023, Arm Limited.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
6 */
7
8#include "v_math.h"
9#include "pl_sig.h"
10#include "pl_test.h"
11#include "v_log1pf_inline.h"
12
13const static struct data
14{
15  struct v_log1pf_data log1pf_consts;
16  uint32x4_t one;
17#if WANT_SIMD_EXCEPT
18  uint32x4_t tiny_bound;
19#endif
20} data = {
21  .log1pf_consts = V_LOG1PF_CONSTANTS_TABLE,
22  .one = V4 (0x3f800000),
23#if WANT_SIMD_EXCEPT
24  /* 0x1p-12, below which atanhf(x) rounds to x.  */
25  .tiny_bound = V4 (0x39800000),
26#endif
27};
28
29#define AbsMask v_u32 (0x7fffffff)
30#define Half v_u32 (0x3f000000)
31
32static float32x4_t NOINLINE VPCS_ATTR
33special_case (float32x4_t x, float32x4_t y, uint32x4_t special)
34{
35  return v_call_f32 (atanhf, x, y, special);
36}
37
38/* Approximation for vector single-precision atanh(x) using modified log1p.
39   The maximum error is 3.08 ULP:
40   __v_atanhf(0x1.ff215p-5) got 0x1.ffcb7cp-5
41			   want 0x1.ffcb82p-5.  */
42VPCS_ATTR float32x4_t V_NAME_F1 (atanh) (float32x4_t x)
43{
44  const struct data *d = ptr_barrier (&data);
45
46  float32x4_t halfsign = vbslq_f32 (AbsMask, v_f32 (0.5), x);
47  float32x4_t ax = vabsq_f32 (x);
48  uint32x4_t iax = vreinterpretq_u32_f32 (ax);
49
50#if WANT_SIMD_EXCEPT
51  uint32x4_t special
52      = vorrq_u32 (vcgeq_u32 (iax, d->one), vcltq_u32 (iax, d->tiny_bound));
53  /* Side-step special cases by setting those lanes to 0, which will trigger no
54     exceptions. These will be fixed up later.  */
55  if (unlikely (v_any_u32 (special)))
56    ax = v_zerofy_f32 (ax, special);
57#else
58  uint32x4_t special = vcgeq_u32 (iax, d->one);
59#endif
60
61  float32x4_t y = vdivq_f32 (vaddq_f32 (ax, ax), vsubq_f32 (v_f32 (1), ax));
62  y = log1pf_inline (y, d->log1pf_consts);
63
64  if (unlikely (v_any_u32 (special)))
65    return special_case (x, vmulq_f32 (halfsign, y), special);
66  return vmulq_f32 (halfsign, y);
67}
68
69PL_SIG (V, F, 1, atanh, -1.0, 1.0)
70PL_TEST_ULP (V_NAME_F1 (atanh), 2.59)
71PL_TEST_EXPECT_FENV (V_NAME_F1 (atanh), WANT_SIMD_EXCEPT)
72/* atanh is asymptotic at 1, which is the default control value - have to set
73 -c 0 specially to ensure fp exceptions are triggered correctly (choice of
74 control lane is irrelevant if fp exceptions are disabled).  */
75PL_TEST_SYM_INTERVAL_C (V_NAME_F1 (atanh), 0, 0x1p-12, 500, 0)
76PL_TEST_SYM_INTERVAL_C (V_NAME_F1 (atanh), 0x1p-12, 1, 200000, 0)
77PL_TEST_SYM_INTERVAL_C (V_NAME_F1 (atanh), 1, inf, 1000, 0)
78