1221175Sgnn/*- 2221175Sgnn * Copyright(c) 2002-2011 Exar Corp. 3221175Sgnn * All rights reserved. 4221175Sgnn * 5221175Sgnn * Redistribution and use in source and binary forms, with or without 6221175Sgnn * modification are permitted provided the following conditions are met: 7221175Sgnn * 8221175Sgnn * 1. Redistributions of source code must retain the above copyright notice, 9221175Sgnn * this list of conditions and the following disclaimer. 10221175Sgnn * 11221175Sgnn * 2. Redistributions in binary form must reproduce the above copyright 12221175Sgnn * notice, this list of conditions and the following disclaimer in the 13221175Sgnn * documentation and/or other materials provided with the distribution. 14221175Sgnn * 15221175Sgnn * 3. Neither the name of the Exar Corporation nor the names of its 16221175Sgnn * contributors may be used to endorse or promote products derived from 17221175Sgnn * this software without specific prior written permission. 18221175Sgnn * 19221175Sgnn * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20221175Sgnn * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21221175Sgnn * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22221175Sgnn * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23221175Sgnn * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24221175Sgnn * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25221175Sgnn * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26221175Sgnn * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27221175Sgnn * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28221175Sgnn * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29221175Sgnn * POSSIBILITY OF SUCH DAMAGE. 30221175Sgnn */ 31221175Sgnn/*$FreeBSD$*/ 32221175Sgnn 33221175Sgnn#ifndef _VXGE_CMN_H_ 34221175Sgnn#define _VXGE_CMN_H_ 35221175Sgnn 36221175Sgnn#include <stdio.h> 37221175Sgnn#include <stdlib.h> 38221175Sgnn#include <string.h> 39221175Sgnn#include <unistd.h> 40221175Sgnn#include <errno.h> 41221175Sgnn#include <sys/types.h> 42221175Sgnn#include <sys/socket.h> 43221175Sgnn#include <sys/ioctl.h> 44221175Sgnn#include <net/if.h> 45221175Sgnn#include <netinet/in.h> 46221175Sgnn#include <arpa/inet.h> 47221175Sgnn#include <fcntl.h> 48221175Sgnn 49221175Sgnn#if BYTE_ORDER == BIG_ENDIAN 50221175Sgnn#define VXGE_OS_HOST_BIG_ENDIAN 51221175Sgnn#else 52221175Sgnn#define VXGE_OS_HOST_LITTLE_ENDIAN 53221175Sgnn#endif 54221175Sgnn 55221175Sgnn#if defined(VXGE_OS_HOST_BIG_ENDIAN) 56221175Sgnn 57221175Sgnn#define GET_OFFSET_STATS(index) statsInfo[(index)].be_offset 58221175Sgnn#define GET_OFFSET_PCICONF(index) pciconfInfo[(index)].be_offset 59221175Sgnn 60221175Sgnn#else 61221175Sgnn 62221175Sgnn#define GET_OFFSET_STATS(index) statsInfo[(index)].le_offset 63221175Sgnn#define GET_OFFSET_PCICONF(index) pciconfInfo[(index)].le_offset 64221175Sgnn 65221175Sgnn#endif 66221175Sgnn 67221175Sgnn#define vxge_mem_free(x) \ 68221175Sgnn if (NULL != x) { free(x); x = NULL; } 69221175Sgnn 70221175Sgnntypedef uint8_t u8; 71221175Sgnntypedef uint16_t u16; 72221175Sgnntypedef uint32_t u32; 73221175Sgnntypedef unsigned long long u64; 74221175Sgnntypedef u_long ulong_t; 75221175Sgnn 76221175Sgnntypedef enum _vxge_query_device_info_e { 77221175Sgnn 78221175Sgnn VXGE_GET_PCI_CONF = 100, 79221175Sgnn VXGE_GET_MRPCIM_STATS = 101, 80221175Sgnn VXGE_GET_DEVICE_STATS = 102, 81221175Sgnn VXGE_GET_DEVICE_HWINFO = 103, 82221175Sgnn VXGE_GET_DRIVER_STATS = 104, 83221175Sgnn VXGE_GET_INTR_STATS = 105, 84221175Sgnn VXGE_GET_VERSION = 106, 85221175Sgnn VXGE_GET_TCODE = 107, 86221175Sgnn VXGE_GET_VPATH_COUNT = 108, 87221175Sgnn VXGE_GET_BANDWIDTH = 109, 88221175Sgnn VXGE_SET_BANDWIDTH = 110, 89221175Sgnn VXGE_GET_PORT_MODE = 111, 90221175Sgnn VXGE_SET_PORT_MODE = 112 91221175Sgnn 92221175Sgnn} vxge_query_device_info_e; 93221175Sgnn 94221175Sgnn/* Register type enumaration */ 95221175Sgnntypedef enum vxge_hal_mgmt_reg_type_e { 96221175Sgnn 97221175Sgnn vxge_hal_mgmt_reg_type_legacy = 0, 98221175Sgnn vxge_hal_mgmt_reg_type_toc = 1, 99221175Sgnn vxge_hal_mgmt_reg_type_common = 2, 100221175Sgnn vxge_hal_mgmt_reg_type_memrepair = 3, 101221175Sgnn vxge_hal_mgmt_reg_type_pcicfgmgmt = 4, 102221175Sgnn vxge_hal_mgmt_reg_type_mrpcim = 5, 103221175Sgnn vxge_hal_mgmt_reg_type_srpcim = 6, 104221175Sgnn vxge_hal_mgmt_reg_type_vpmgmt = 7, 105221175Sgnn vxge_hal_mgmt_reg_type_vpath = 8 106221175Sgnn 107221175Sgnn} vxge_hal_mgmt_reg_type_e; 108221175Sgnn 109221175Sgnntypedef enum vxge_hal_xmac_nwif_dp_mode { 110221175Sgnn 111221175Sgnn VXGE_HAL_DP_NP_MODE_DEFAULT, 112221175Sgnn VXGE_HAL_DP_NP_MODE_LINK_AGGR, 113221175Sgnn VXGE_HAL_DP_NP_MODE_ACTIVE_PASSIVE, 114221175Sgnn VXGE_HAL_DP_NP_MODE_SINGLE_PORT, 115221175Sgnn VXGE_HAL_DP_NP_MODE_DUAL_PORT, 116221175Sgnn VXGE_HAL_DP_NP_MODE_DISABLE_PORT_MGMT 117221175Sgnn 118221175Sgnn} vxge_hal_xmac_nwif_dp_mode; 119221175Sgnn 120221175Sgnntypedef enum vxge_hal_xmac_nwif_behavior_on_failure { 121221175Sgnn 122221175Sgnn VXGE_HAL_XMAC_NWIF_OnFailure_NoMove, 123221175Sgnn VXGE_HAL_XMAC_NWIF_OnFailure_OtherPort, 124221175Sgnn VXGE_HAL_XMAC_NWIF_OnFailure_OtherPortBackOnRestore 125221175Sgnn 126221175Sgnn} vxge_hal_xmac_nwif_behavior_on_failure; 127221175Sgnn 128221175Sgnn#define VXGE_HAL_MGMT_REG_COUNT_LEGACY 7 129221175Sgnn#define VXGE_HAL_MGMT_REG_COUNT_TOC 11 130221175Sgnn#define VXGE_HAL_MGMT_REG_COUNT_COMMON 65 131221175Sgnn#define VXGE_HAL_MGMT_REG_COUNT_PCICFGMGMT 3 132221175Sgnn#define VXGE_HAL_MGMT_REG_COUNT_MRPCIM 1370 133221175Sgnn#define VXGE_HAL_MGMT_REG_COUNT_SRPCIM 48 134221175Sgnn#define VXGE_HAL_MGMT_REG_COUNT_VPMGMT 29 135221175Sgnn#define VXGE_HAL_MGMT_REG_COUNT_VPATH 139 136221175Sgnn#define VXGE_HAL_MGMT_STATS_COUNT_DRIVER 17 137221175Sgnn#define VXGE_HAL_MGMT_STATS_COUNT 160 138221175Sgnn#define VXGE_HAL_MGMT_STATS_COUNT_SW 54 139221175Sgnn#define VXGE_HAL_MGMT_STATS_COUNT_EXTENDED 56 140221175Sgnn#define VXGE_MAX_BANDWIDTH 10000 141221175Sgnn 142221175Sgnn#define VXGE_HAL_MAX_VIRTUAL_PATHS 17 143221175Sgnn#define ETH_LENGTH_OF_ADDRESS 6 144221175Sgnn 145221175Sgnntypedef char macaddr[ETH_LENGTH_OF_ADDRESS]; 146221175Sgnn 147221175Sgnn#define VXGE_PRINT(fd, fmt...) { \ 148221175Sgnn fprintf(fd, fmt); \ 149221175Sgnn fprintf(fd, "\n"); \ 150221175Sgnn printf(fmt); \ 151221175Sgnn printf("\n"); \ 152221175Sgnn} 153221175Sgnn 154221175Sgnn/* Read & Write Register */ 155221175Sgnntypedef struct _vxge_register_info_t { 156221175Sgnn 157221175Sgnn u64 value; 158221175Sgnn u64 offset; 159221175Sgnn char option[2]; 160221175Sgnn 161221175Sgnn} vxge_register_info_t; 162221175Sgnn 163221175Sgnn/* Register Dump */ 164221175Sgnntypedef struct _vxge_pci_bar0_t { 165221175Sgnn char name[64]; 166221175Sgnn u64 offset; 167221175Sgnn u32 size; 168221175Sgnn 169221175Sgnn} vxge_pci_bar0_t; 170221175Sgnn 171221175Sgnntypedef struct _vxge_stats_driver_info_t { 172221175Sgnn 173221175Sgnn char name[32]; 174221175Sgnn u64 value; 175221175Sgnn 176221175Sgnn} vxge_stats_driver_info_t; 177221175Sgnn 178221175Sgnntypedef struct _vxge_hal_device_pmd_info_t { 179221175Sgnn 180221175Sgnn u32 type; 181221175Sgnn u32 unused; 182221175Sgnn char vendor[24]; 183221175Sgnn char part_num[24]; 184221175Sgnn char ser_num[24]; 185221175Sgnn 186221175Sgnn} vxge_hal_device_pmd_info_t; 187221175Sgnn 188221175Sgnntypedef struct _vxge_hal_device_version_t { 189221175Sgnn 190221175Sgnn u32 major; 191221175Sgnn u32 minor; 192221175Sgnn u32 build; 193221175Sgnn char version[32]; 194221175Sgnn 195221175Sgnn} vxge_hal_device_version_t; 196221175Sgnn 197221175Sgnntypedef struct _vxge_hal_device_date_t { 198221175Sgnn 199221175Sgnn u32 day; 200221175Sgnn u32 month; 201221175Sgnn u32 year; 202221175Sgnn char date[16]; 203221175Sgnn 204221175Sgnn} vxge_hal_device_date_t; 205221175Sgnn 206221175Sgnntypedef struct _vxge_hal_device_hw_info_t { 207221175Sgnn 208221175Sgnn u32 host_type; 209221175Sgnn u64 function_mode; 210221175Sgnn u32 func_id; 211221175Sgnn u64 vpath_mask; 212221175Sgnn 213221175Sgnn vxge_hal_device_version_t fw_version; 214221175Sgnn vxge_hal_device_date_t fw_date; 215221175Sgnn vxge_hal_device_version_t flash_version; 216221175Sgnn vxge_hal_device_date_t flash_date; 217221175Sgnn 218221175Sgnn char serial_number[24]; 219221175Sgnn char part_number[24]; 220221175Sgnn char product_description[72]; 221221175Sgnn u32 unused; 222221175Sgnn u32 ports; 223221175Sgnn 224221175Sgnn vxge_hal_device_pmd_info_t pmd_port0; 225221175Sgnn vxge_hal_device_pmd_info_t pmd_port1; 226221175Sgnn 227221175Sgnn macaddr mac_addrs[VXGE_HAL_MAX_VIRTUAL_PATHS]; 228221175Sgnn macaddr mac_addr_masks[VXGE_HAL_MAX_VIRTUAL_PATHS]; 229221175Sgnn 230221175Sgnn} vxge_hal_device_hw_info_t; 231221175Sgnn 232221175Sgnntypedef struct _vxge_device_hw_info_t { 233221175Sgnn 234221175Sgnn vxge_hal_device_hw_info_t hw_info; 235221175Sgnn u32 port_mode; 236221175Sgnn u32 port_failure; 237221175Sgnn 238221175Sgnn} vxge_device_hw_info_t; 239221175Sgnn 240221175Sgnntypedef struct _vxge_bw_info_t { 241221175Sgnn 242221175Sgnn char query; 243221175Sgnn u64 func_id; 244221175Sgnn int priority; 245221175Sgnn int bandwidth; 246221175Sgnn 247221175Sgnn} vxge_bw_info_t; 248221175Sgnn 249221175Sgnntypedef struct _vxge_port_info_t { 250221175Sgnn 251221175Sgnn char query; 252221175Sgnn int port_mode; 253221175Sgnn int port_failure; 254221175Sgnn 255221175Sgnn} vxge_port_info_t; 256221175Sgnn 257221175Sgnnu32 vxge_get_num_vpath(void); 258221175Sgnnvoid vxge_null_terminate(char *, size_t); 259221175Sgnn 260221175Sgnn#endif /* _VXGE_CMN_H_ */ 261