1121986Sjhb/*- 2121986Sjhb * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3121986Sjhb * All rights reserved. 4121986Sjhb * 5121986Sjhb * Redistribution and use in source and binary forms, with or without 6121986Sjhb * modification, are permitted provided that the following conditions 7121986Sjhb * are met: 8121986Sjhb * 1. Redistributions of source code must retain the above copyright 9121986Sjhb * notice, this list of conditions and the following disclaimer. 10121986Sjhb * 2. Redistributions in binary form must reproduce the above copyright 11121986Sjhb * notice, this list of conditions and the following disclaimer in the 12121986Sjhb * documentation and/or other materials provided with the distribution. 13121986Sjhb * 14121986Sjhb * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15121986Sjhb * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16121986Sjhb * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17121986Sjhb * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18121986Sjhb * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19121986Sjhb * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20121986Sjhb * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21121986Sjhb * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22121986Sjhb * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23121986Sjhb * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24121986Sjhb * SUCH DAMAGE. 25121986Sjhb */ 26121986Sjhb 27121986Sjhb#include <sys/cdefs.h> 28121986Sjhb__FBSDID("$FreeBSD$"); 29121986Sjhb 30121986Sjhb#include "opt_isa.h" 31121986Sjhb 32121986Sjhb#include <sys/param.h> 33121986Sjhb#include <sys/systm.h> 34121986Sjhb#include <sys/bus.h> 35121986Sjhb#include <sys/kernel.h> 36167240Sjhb#include <sys/lock.h> 37121986Sjhb#include <sys/malloc.h> 38167240Sjhb#include <sys/module.h> 39121986Sjhb#include <sys/mutex.h> 40148538Sjhb#include <sys/sysctl.h> 41121986Sjhb 42167240Sjhb#include <dev/pci/pcireg.h> 43167240Sjhb#include <dev/pci/pcivar.h> 44167240Sjhb 45121986Sjhb#include <vm/vm.h> 46121986Sjhb#include <vm/pmap.h> 47121986Sjhb 48214631Sjhb#include <x86/apicreg.h> 49121986Sjhb#include <machine/frame.h> 50121986Sjhb#include <machine/intr_machdep.h> 51121986Sjhb#include <machine/apicvar.h> 52167747Sjhb#include <machine/resource.h> 53121986Sjhb#include <machine/segments.h> 54121986Sjhb 55121986Sjhb#define IOAPIC_ISA_INTS 16 56121986Sjhb#define IOAPIC_MEM_REGION 32 57121986Sjhb#define IOAPIC_REDTBL_LO(i) (IOAPIC_REDTBL + (i) * 2) 58121986Sjhb#define IOAPIC_REDTBL_HI(i) (IOAPIC_REDTBL_LO(i) + 1) 59121986Sjhb 60151979Sjhb#define IRQ_EXTINT (NUM_IO_INTS + 1) 61151979Sjhb#define IRQ_NMI (NUM_IO_INTS + 2) 62151979Sjhb#define IRQ_SMI (NUM_IO_INTS + 3) 63151979Sjhb#define IRQ_DISABLED (NUM_IO_INTS + 4) 64121986Sjhb 65151897Srwatsonstatic MALLOC_DEFINE(M_IOAPIC, "io_apic", "I/O APIC structures"); 66121986Sjhb 67121986Sjhb/* 68151979Sjhb * I/O APIC interrupt source driver. Each pin is assigned an IRQ cookie 69151979Sjhb * as laid out in the ACPI System Interrupt number model where each I/O 70151979Sjhb * APIC has a contiguous chunk of the System Interrupt address space. 71151979Sjhb * We assume that IRQs 1 - 15 behave like ISA IRQs and that all other 72151979Sjhb * IRQs behave as PCI IRQs by default. We also assume that the pin for 73151979Sjhb * IRQ 0 is actually an ExtINT pin. The apic enumerators override the 74151979Sjhb * configuration of individual pins as indicated by their tables. 75152461Sandre * 76152461Sandre * Documentation for the I/O APIC: "82093AA I/O Advanced Programmable 77152461Sandre * Interrupt Controller (IOAPIC)", May 1996, Intel Corp. 78152461Sandre * ftp://download.intel.com/design/chipsets/datashts/29056601.pdf 79121986Sjhb */ 80121986Sjhb 81121986Sjhbstruct ioapic_intsrc { 82121986Sjhb struct intsrc io_intsrc; 83151979Sjhb u_int io_irq; 84122124Sjhb u_int io_intpin:8; 85122124Sjhb u_int io_vector:8; 86156124Sjhb u_int io_cpu:8; 87122124Sjhb u_int io_activehi:1; 88122124Sjhb u_int io_edgetrigger:1; 89122124Sjhb u_int io_masked:1; 90130980Sjhb int io_bus:4; 91157541Sjhb uint32_t io_lowreg; 92121986Sjhb}; 93121986Sjhb 94121986Sjhbstruct ioapic { 95121986Sjhb struct pic io_pic; 96121986Sjhb u_int io_id:8; /* logical ID */ 97121986Sjhb u_int io_apic_id:4; 98121986Sjhb u_int io_intbase:8; /* System Interrupt base */ 99121986Sjhb u_int io_numintr:8; 100121986Sjhb volatile ioapic_t *io_addr; /* XXX: should use bus_space */ 101167747Sjhb vm_paddr_t io_paddr; 102121986Sjhb STAILQ_ENTRY(ioapic) io_next; 103121986Sjhb struct ioapic_intsrc io_pins[0]; 104121986Sjhb}; 105121986Sjhb 106121986Sjhbstatic u_int ioapic_read(volatile ioapic_t *apic, int reg); 107121986Sjhbstatic void ioapic_write(volatile ioapic_t *apic, int reg, u_int val); 108130980Sjhbstatic const char *ioapic_bus_string(int bus_type); 109151979Sjhbstatic void ioapic_print_irq(struct ioapic_intsrc *intpin); 110121986Sjhbstatic void ioapic_enable_source(struct intsrc *isrc); 111133017Sscottlstatic void ioapic_disable_source(struct intsrc *isrc, int eoi); 112121986Sjhbstatic void ioapic_eoi_source(struct intsrc *isrc); 113121986Sjhbstatic void ioapic_enable_intr(struct intsrc *isrc); 114169391Sjhbstatic void ioapic_disable_intr(struct intsrc *isrc); 115121986Sjhbstatic int ioapic_vector(struct intsrc *isrc); 116121986Sjhbstatic int ioapic_source_pending(struct intsrc *isrc); 117128931Sjhbstatic int ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig, 118128931Sjhb enum intr_polarity pol); 119163219Sjhbstatic void ioapic_resume(struct pic *pic); 120195249Sjhbstatic int ioapic_assign_cpu(struct intsrc *isrc, u_int apic_id); 121129964Sjhbstatic void ioapic_program_intpin(struct ioapic_intsrc *intpin); 122121986Sjhb 123129097Sjhbstatic STAILQ_HEAD(,ioapic) ioapic_list = STAILQ_HEAD_INITIALIZER(ioapic_list); 124121986Sjhbstruct pic ioapic_template = { ioapic_enable_source, ioapic_disable_source, 125121986Sjhb ioapic_eoi_source, ioapic_enable_intr, 126169391Sjhb ioapic_disable_intr, ioapic_vector, 127169391Sjhb ioapic_source_pending, NULL, ioapic_resume, 128156124Sjhb ioapic_config_intr, ioapic_assign_cpu }; 129121986Sjhb 130156124Sjhbstatic int next_ioapic_base; 131156124Sjhbstatic u_int next_id; 132156124Sjhb 133248085Smariusstatic SYSCTL_NODE(_hw, OID_AUTO, apic, CTLFLAG_RD, 0, "APIC options"); 134148538Sjhbstatic int enable_extint; 135148538SjhbSYSCTL_INT(_hw_apic, OID_AUTO, enable_extint, CTLFLAG_RDTUN, &enable_extint, 0, 136148538Sjhb "Enable the ExtINT pin in the first I/O APIC"); 137148538SjhbTUNABLE_INT("hw.apic.enable_extint", &enable_extint); 138148538Sjhb 139133017Sscottlstatic __inline void 140133017Sscottl_ioapic_eoi_source(struct intsrc *isrc) 141133017Sscottl{ 142133017Sscottl lapic_eoi(); 143133017Sscottl} 144133017Sscottl 145121986Sjhbstatic u_int 146121986Sjhbioapic_read(volatile ioapic_t *apic, int reg) 147121986Sjhb{ 148121986Sjhb 149121986Sjhb mtx_assert(&icu_lock, MA_OWNED); 150121986Sjhb apic->ioregsel = reg; 151121986Sjhb return (apic->iowin); 152121986Sjhb} 153121986Sjhb 154121986Sjhbstatic void 155121986Sjhbioapic_write(volatile ioapic_t *apic, int reg, u_int val) 156121986Sjhb{ 157121986Sjhb 158121986Sjhb mtx_assert(&icu_lock, MA_OWNED); 159121986Sjhb apic->ioregsel = reg; 160121986Sjhb apic->iowin = val; 161121986Sjhb} 162121986Sjhb 163130980Sjhbstatic const char * 164130980Sjhbioapic_bus_string(int bus_type) 165130980Sjhb{ 166130980Sjhb 167130980Sjhb switch (bus_type) { 168130980Sjhb case APIC_BUS_ISA: 169130980Sjhb return ("ISA"); 170130980Sjhb case APIC_BUS_EISA: 171130980Sjhb return ("EISA"); 172130980Sjhb case APIC_BUS_PCI: 173130980Sjhb return ("PCI"); 174130980Sjhb default: 175130980Sjhb return ("unknown"); 176130980Sjhb } 177130980Sjhb} 178130980Sjhb 179121986Sjhbstatic void 180151979Sjhbioapic_print_irq(struct ioapic_intsrc *intpin) 181130980Sjhb{ 182130980Sjhb 183151979Sjhb switch (intpin->io_irq) { 184151979Sjhb case IRQ_DISABLED: 185130980Sjhb printf("disabled"); 186130980Sjhb break; 187151979Sjhb case IRQ_EXTINT: 188130980Sjhb printf("ExtINT"); 189130980Sjhb break; 190151979Sjhb case IRQ_NMI: 191130980Sjhb printf("NMI"); 192130980Sjhb break; 193151979Sjhb case IRQ_SMI: 194130980Sjhb printf("SMI"); 195130980Sjhb break; 196130980Sjhb default: 197130980Sjhb printf("%s IRQ %u", ioapic_bus_string(intpin->io_bus), 198151979Sjhb intpin->io_irq); 199130980Sjhb } 200130980Sjhb} 201130980Sjhb 202130980Sjhbstatic void 203121986Sjhbioapic_enable_source(struct intsrc *isrc) 204121986Sjhb{ 205121986Sjhb struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 206121986Sjhb struct ioapic *io = (struct ioapic *)isrc->is_pic; 207121986Sjhb uint32_t flags; 208121986Sjhb 209121986Sjhb mtx_lock_spin(&icu_lock); 210121986Sjhb if (intpin->io_masked) { 211157541Sjhb flags = intpin->io_lowreg & ~IOART_INTMASK; 212121986Sjhb ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), 213121986Sjhb flags); 214121986Sjhb intpin->io_masked = 0; 215121986Sjhb } 216121986Sjhb mtx_unlock_spin(&icu_lock); 217121986Sjhb} 218121986Sjhb 219121986Sjhbstatic void 220133017Sscottlioapic_disable_source(struct intsrc *isrc, int eoi) 221121986Sjhb{ 222121986Sjhb struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 223121986Sjhb struct ioapic *io = (struct ioapic *)isrc->is_pic; 224121986Sjhb uint32_t flags; 225121986Sjhb 226121986Sjhb mtx_lock_spin(&icu_lock); 227121986Sjhb if (!intpin->io_masked && !intpin->io_edgetrigger) { 228157541Sjhb flags = intpin->io_lowreg | IOART_INTMSET; 229121986Sjhb ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), 230121986Sjhb flags); 231121986Sjhb intpin->io_masked = 1; 232121986Sjhb } 233133017Sscottl 234133017Sscottl if (eoi == PIC_EOI) 235133017Sscottl _ioapic_eoi_source(isrc); 236133017Sscottl 237121986Sjhb mtx_unlock_spin(&icu_lock); 238121986Sjhb} 239121986Sjhb 240121986Sjhbstatic void 241121986Sjhbioapic_eoi_source(struct intsrc *isrc) 242121986Sjhb{ 243122148Sjhb 244133017Sscottl _ioapic_eoi_source(isrc); 245121986Sjhb} 246121986Sjhb 247121986Sjhb/* 248129964Sjhb * Completely program an intpin based on the data in its interrupt source 249129964Sjhb * structure. 250129964Sjhb */ 251129964Sjhbstatic void 252129964Sjhbioapic_program_intpin(struct ioapic_intsrc *intpin) 253129964Sjhb{ 254129964Sjhb struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic; 255129964Sjhb uint32_t low, high, value; 256129964Sjhb 257151979Sjhb /* 258151979Sjhb * If a pin is completely invalid or if it is valid but hasn't 259151979Sjhb * been enabled yet, just ensure that the pin is masked. 260151979Sjhb */ 261208915Sjhb mtx_assert(&icu_lock, MA_OWNED); 262151979Sjhb if (intpin->io_irq == IRQ_DISABLED || (intpin->io_irq < NUM_IO_INTS && 263151979Sjhb intpin->io_vector == 0)) { 264129964Sjhb low = ioapic_read(io->io_addr, 265129964Sjhb IOAPIC_REDTBL_LO(intpin->io_intpin)); 266129964Sjhb if ((low & IOART_INTMASK) == IOART_INTMCLR) 267129964Sjhb ioapic_write(io->io_addr, 268129964Sjhb IOAPIC_REDTBL_LO(intpin->io_intpin), 269129964Sjhb low | IOART_INTMSET); 270129964Sjhb return; 271129964Sjhb } 272129964Sjhb 273129964Sjhb /* Set the destination. */ 274156124Sjhb low = IOART_DESTPHY; 275156124Sjhb high = intpin->io_cpu << APIC_ID_SHIFT; 276129964Sjhb 277129964Sjhb /* Program the rest of the low word. */ 278129964Sjhb if (intpin->io_edgetrigger) 279129964Sjhb low |= IOART_TRGREDG; 280129964Sjhb else 281129964Sjhb low |= IOART_TRGRLVL; 282129964Sjhb if (intpin->io_activehi) 283129964Sjhb low |= IOART_INTAHI; 284129964Sjhb else 285129964Sjhb low |= IOART_INTALO; 286129964Sjhb if (intpin->io_masked) 287129964Sjhb low |= IOART_INTMSET; 288151979Sjhb switch (intpin->io_irq) { 289151979Sjhb case IRQ_EXTINT: 290129964Sjhb KASSERT(intpin->io_edgetrigger, 291148538Sjhb ("ExtINT not edge triggered")); 292129964Sjhb low |= IOART_DELEXINT; 293129964Sjhb break; 294151979Sjhb case IRQ_NMI: 295129964Sjhb KASSERT(intpin->io_edgetrigger, 296129964Sjhb ("NMI not edge triggered")); 297129964Sjhb low |= IOART_DELNMI; 298129964Sjhb break; 299151979Sjhb case IRQ_SMI: 300129964Sjhb KASSERT(intpin->io_edgetrigger, 301129964Sjhb ("SMI not edge triggered")); 302129964Sjhb low |= IOART_DELSMI; 303129964Sjhb break; 304129964Sjhb default: 305151979Sjhb KASSERT(intpin->io_vector != 0, ("No vector for IRQ %u", 306151979Sjhb intpin->io_irq)); 307156124Sjhb low |= IOART_DELFIXED | intpin->io_vector; 308129964Sjhb } 309129964Sjhb 310129964Sjhb /* Write the values to the APIC. */ 311157541Sjhb intpin->io_lowreg = low; 312129964Sjhb ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), low); 313129964Sjhb value = ioapic_read(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin)); 314129964Sjhb value &= ~IOART_DEST; 315129964Sjhb value |= high; 316129964Sjhb ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), value); 317129964Sjhb} 318129964Sjhb 319195249Sjhbstatic int 320156124Sjhbioapic_assign_cpu(struct intsrc *isrc, u_int apic_id) 321121986Sjhb{ 322156124Sjhb struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 323156124Sjhb struct ioapic *io = (struct ioapic *)isrc->is_pic; 324195415Sjhb u_int old_vector, new_vector; 325187880Sjeff u_int old_id; 326121986Sjhb 327187880Sjeff /* 328187880Sjeff * keep 1st core as the destination for NMI 329187880Sjeff */ 330187880Sjeff if (intpin->io_irq == IRQ_NMI) 331187880Sjeff apic_id = 0; 332187880Sjeff 333187880Sjeff /* 334187880Sjeff * Set us up to free the old irq. 335187880Sjeff */ 336187880Sjeff old_vector = intpin->io_vector; 337187880Sjeff old_id = intpin->io_cpu; 338187880Sjeff if (old_vector && apic_id == old_id) 339195249Sjhb return (0); 340187880Sjeff 341187880Sjeff /* 342187880Sjeff * Allocate an APIC vector for this interrupt pin. Once 343187880Sjeff * we have a vector we program the interrupt pin. 344187880Sjeff */ 345195415Sjhb new_vector = apic_alloc_vector(apic_id, intpin->io_irq); 346195415Sjhb if (new_vector == 0) 347195249Sjhb return (ENOSPC); 348195249Sjhb 349208915Sjhb /* 350208915Sjhb * Mask the old intpin if it is enabled while it is migrated. 351208915Sjhb * 352208915Sjhb * At least some level-triggered interrupts seem to need the 353208915Sjhb * extra DELAY() to avoid being stuck in a non-EOI'd state. 354208915Sjhb */ 355208915Sjhb mtx_lock_spin(&icu_lock); 356208991Smav if (!intpin->io_masked && !intpin->io_edgetrigger) { 357208915Sjhb ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), 358208915Sjhb intpin->io_lowreg | IOART_INTMSET); 359216679Sjhb mtx_unlock_spin(&icu_lock); 360208915Sjhb DELAY(100); 361216679Sjhb mtx_lock_spin(&icu_lock); 362208915Sjhb } 363208915Sjhb 364195415Sjhb intpin->io_cpu = apic_id; 365195415Sjhb intpin->io_vector = new_vector; 366195415Sjhb if (isrc->is_handlers > 0) 367195415Sjhb apic_enable_vector(intpin->io_cpu, intpin->io_vector); 368121986Sjhb if (bootverbose) { 369187880Sjeff printf("ioapic%u: routing intpin %u (", io->io_id, 370187880Sjeff intpin->io_intpin); 371151979Sjhb ioapic_print_irq(intpin); 372187880Sjeff printf(") to lapic %u vector %u\n", intpin->io_cpu, 373187880Sjeff intpin->io_vector); 374121986Sjhb } 375129964Sjhb ioapic_program_intpin(intpin); 376208915Sjhb mtx_unlock_spin(&icu_lock); 377208915Sjhb 378187880Sjeff /* 379187880Sjeff * Free the old vector after the new one is established. This is done 380187880Sjeff * to prevent races where we could miss an interrupt. 381187880Sjeff */ 382195415Sjhb if (old_vector) { 383195415Sjhb if (isrc->is_handlers > 0) 384195415Sjhb apic_disable_vector(old_id, old_vector); 385187880Sjeff apic_free_vector(old_id, old_vector, intpin->io_irq); 386195415Sjhb } 387195249Sjhb return (0); 388121986Sjhb} 389121986Sjhb 390121986Sjhbstatic void 391121986Sjhbioapic_enable_intr(struct intsrc *isrc) 392121986Sjhb{ 393121986Sjhb struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 394121986Sjhb 395187880Sjeff if (intpin->io_vector == 0) 396195249Sjhb if (ioapic_assign_cpu(isrc, intr_next_cpu()) != 0) 397195249Sjhb panic("Couldn't find an APIC vector for IRQ %d", 398195249Sjhb intpin->io_irq); 399187880Sjeff apic_enable_vector(intpin->io_cpu, intpin->io_vector); 400121986Sjhb} 401121986Sjhb 402187880Sjeff 403169391Sjhbstatic void 404169391Sjhbioapic_disable_intr(struct intsrc *isrc) 405169391Sjhb{ 406169391Sjhb struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 407169391Sjhb u_int vector; 408169391Sjhb 409169391Sjhb if (intpin->io_vector != 0) { 410169391Sjhb /* Mask this interrupt pin and free its APIC vector. */ 411169391Sjhb vector = intpin->io_vector; 412187880Sjeff apic_disable_vector(intpin->io_cpu, vector); 413208915Sjhb mtx_lock_spin(&icu_lock); 414169391Sjhb intpin->io_masked = 1; 415169391Sjhb intpin->io_vector = 0; 416169391Sjhb ioapic_program_intpin(intpin); 417208915Sjhb mtx_unlock_spin(&icu_lock); 418187880Sjeff apic_free_vector(intpin->io_cpu, vector, intpin->io_irq); 419169391Sjhb } 420169391Sjhb} 421169391Sjhb 422121986Sjhbstatic int 423121986Sjhbioapic_vector(struct intsrc *isrc) 424121986Sjhb{ 425121986Sjhb struct ioapic_intsrc *pin; 426121986Sjhb 427121986Sjhb pin = (struct ioapic_intsrc *)isrc; 428151979Sjhb return (pin->io_irq); 429121986Sjhb} 430121986Sjhb 431121986Sjhbstatic int 432121986Sjhbioapic_source_pending(struct intsrc *isrc) 433121986Sjhb{ 434121986Sjhb struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 435121986Sjhb 436151979Sjhb if (intpin->io_vector == 0) 437151979Sjhb return 0; 438121986Sjhb return (lapic_intr_pending(intpin->io_vector)); 439121986Sjhb} 440121986Sjhb 441128931Sjhbstatic int 442128931Sjhbioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig, 443128931Sjhb enum intr_polarity pol) 444128931Sjhb{ 445128931Sjhb struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc; 446128931Sjhb struct ioapic *io = (struct ioapic *)isrc->is_pic; 447130984Sjhb int changed; 448128931Sjhb 449128931Sjhb KASSERT(!(trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM), 450128931Sjhb ("%s: Conforming trigger or polarity\n", __func__)); 451128931Sjhb 452128931Sjhb /* 453130984Sjhb * EISA interrupts always use active high polarity, so don't allow 454130984Sjhb * them to be set to active low. 455130984Sjhb * 456130984Sjhb * XXX: Should we write to the ELCR if the trigger mode changes for 457140452Sjhb * an EISA IRQ or an ISA IRQ with the ELCR present? 458128931Sjhb */ 459208915Sjhb mtx_lock_spin(&icu_lock); 460130984Sjhb if (intpin->io_bus == APIC_BUS_EISA) 461130984Sjhb pol = INTR_POLARITY_HIGH; 462130984Sjhb changed = 0; 463130984Sjhb if (intpin->io_edgetrigger != (trig == INTR_TRIGGER_EDGE)) { 464130984Sjhb if (bootverbose) 465130984Sjhb printf("ioapic%u: Changing trigger for pin %u to %s\n", 466130984Sjhb io->io_id, intpin->io_intpin, 467130984Sjhb trig == INTR_TRIGGER_EDGE ? "edge" : "level"); 468130984Sjhb intpin->io_edgetrigger = (trig == INTR_TRIGGER_EDGE); 469130984Sjhb changed++; 470130984Sjhb } 471130984Sjhb if (intpin->io_activehi != (pol == INTR_POLARITY_HIGH)) { 472130984Sjhb if (bootverbose) 473130984Sjhb printf("ioapic%u: Changing polarity for pin %u to %s\n", 474130984Sjhb io->io_id, intpin->io_intpin, 475130984Sjhb pol == INTR_POLARITY_HIGH ? "high" : "low"); 476130984Sjhb intpin->io_activehi = (pol == INTR_POLARITY_HIGH); 477130984Sjhb changed++; 478130984Sjhb } 479130984Sjhb if (changed) 480130984Sjhb ioapic_program_intpin(intpin); 481208915Sjhb mtx_unlock_spin(&icu_lock); 482128931Sjhb return (0); 483128931Sjhb} 484128931Sjhb 485121986Sjhbstatic void 486163219Sjhbioapic_resume(struct pic *pic) 487121986Sjhb{ 488163219Sjhb struct ioapic *io = (struct ioapic *)pic; 489163219Sjhb int i; 490121986Sjhb 491208915Sjhb mtx_lock_spin(&icu_lock); 492163219Sjhb for (i = 0; i < io->io_numintr; i++) 493163219Sjhb ioapic_program_intpin(&io->io_pins[i]); 494208915Sjhb mtx_unlock_spin(&icu_lock); 495121986Sjhb} 496121986Sjhb 497121986Sjhb/* 498121986Sjhb * Create a plain I/O APIC object. 499121986Sjhb */ 500121986Sjhbvoid * 501167247Sjhbioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase) 502121986Sjhb{ 503121986Sjhb struct ioapic *io; 504121986Sjhb struct ioapic_intsrc *intpin; 505121986Sjhb volatile ioapic_t *apic; 506121986Sjhb u_int numintr, i; 507121986Sjhb uint32_t value; 508121986Sjhb 509145054Sjhb /* Map the register window so we can access the device. */ 510156920Sjhb apic = pmap_mapdev(addr, IOAPIC_MEM_REGION); 511121986Sjhb mtx_lock_spin(&icu_lock); 512145054Sjhb value = ioapic_read(apic, IOAPIC_VER); 513121986Sjhb mtx_unlock_spin(&icu_lock); 514145054Sjhb 515145054Sjhb /* If it's version register doesn't seem to work, punt. */ 516152528Sjhb if (value == 0xffffffff) { 517145057Sjhb pmap_unmapdev((vm_offset_t)apic, IOAPIC_MEM_REGION); 518145054Sjhb return (NULL); 519145054Sjhb } 520145054Sjhb 521145054Sjhb /* Determine the number of vectors and set the APIC ID. */ 522145054Sjhb numintr = ((value & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1; 523121986Sjhb io = malloc(sizeof(struct ioapic) + 524121986Sjhb numintr * sizeof(struct ioapic_intsrc), M_IOAPIC, M_WAITOK); 525121986Sjhb io->io_pic = ioapic_template; 526121986Sjhb mtx_lock_spin(&icu_lock); 527121986Sjhb io->io_id = next_id++; 528195249Sjhb io->io_apic_id = ioapic_read(apic, IOAPIC_ID) >> APIC_ID_SHIFT; 529121986Sjhb if (apic_id != -1 && io->io_apic_id != apic_id) { 530121986Sjhb ioapic_write(apic, IOAPIC_ID, apic_id << APIC_ID_SHIFT); 531121986Sjhb mtx_unlock_spin(&icu_lock); 532121986Sjhb io->io_apic_id = apic_id; 533121986Sjhb printf("ioapic%u: Changing APIC ID to %d\n", io->io_id, 534121986Sjhb apic_id); 535121986Sjhb } else 536121986Sjhb mtx_unlock_spin(&icu_lock); 537121986Sjhb if (intbase == -1) { 538121986Sjhb intbase = next_ioapic_base; 539121986Sjhb printf("ioapic%u: Assuming intbase of %d\n", io->io_id, 540121986Sjhb intbase); 541170340Sjhb } else if (intbase != next_ioapic_base && bootverbose) 542121986Sjhb printf("ioapic%u: WARNING: intbase %d != expected base %d\n", 543121986Sjhb io->io_id, intbase, next_ioapic_base); 544121986Sjhb io->io_intbase = intbase; 545122124Sjhb next_ioapic_base = intbase + numintr; 546121986Sjhb io->io_numintr = numintr; 547121986Sjhb io->io_addr = apic; 548167747Sjhb io->io_paddr = addr; 549121986Sjhb 550121986Sjhb /* 551121986Sjhb * Initialize pins. Start off with interrupts disabled. Default 552121986Sjhb * to active-hi and edge-triggered for ISA interrupts and active-lo 553121986Sjhb * and level-triggered for all others. 554121986Sjhb */ 555121986Sjhb bzero(io->io_pins, sizeof(struct ioapic_intsrc) * numintr); 556121986Sjhb mtx_lock_spin(&icu_lock); 557121986Sjhb for (i = 0, intpin = io->io_pins; i < numintr; i++, intpin++) { 558121986Sjhb intpin->io_intsrc.is_pic = (struct pic *)io; 559121986Sjhb intpin->io_intpin = i; 560151979Sjhb intpin->io_irq = intbase + i; 561121986Sjhb 562121986Sjhb /* 563145080Sjhb * Assume that pin 0 on the first I/O APIC is an ExtINT pin. 564142256Sjhb * Assume that pins 1-15 are ISA interrupts and that all 565130980Sjhb * other pins are PCI interrupts. 566121986Sjhb */ 567151979Sjhb if (intpin->io_irq == 0) 568130980Sjhb ioapic_set_extint(io, i); 569151979Sjhb else if (intpin->io_irq < IOAPIC_ISA_INTS) { 570130980Sjhb intpin->io_bus = APIC_BUS_ISA; 571121986Sjhb intpin->io_activehi = 1; 572121986Sjhb intpin->io_edgetrigger = 1; 573121986Sjhb intpin->io_masked = 1; 574121986Sjhb } else { 575130980Sjhb intpin->io_bus = APIC_BUS_PCI; 576121986Sjhb intpin->io_activehi = 0; 577121986Sjhb intpin->io_edgetrigger = 0; 578121986Sjhb intpin->io_masked = 1; 579121986Sjhb } 580121986Sjhb 581121986Sjhb /* 582156124Sjhb * Route interrupts to the BSP by default. Interrupts may 583156124Sjhb * be routed to other CPUs later after they are enabled. 584121986Sjhb */ 585156124Sjhb intpin->io_cpu = PCPU_GET(apic_id); 586121986Sjhb value = ioapic_read(apic, IOAPIC_REDTBL_LO(i)); 587121986Sjhb ioapic_write(apic, IOAPIC_REDTBL_LO(i), value | IOART_INTMSET); 588121986Sjhb } 589121986Sjhb mtx_unlock_spin(&icu_lock); 590121986Sjhb 591121986Sjhb return (io); 592121986Sjhb} 593121986Sjhb 594121986Sjhbint 595121986Sjhbioapic_get_vector(void *cookie, u_int pin) 596121986Sjhb{ 597121986Sjhb struct ioapic *io; 598121986Sjhb 599121986Sjhb io = (struct ioapic *)cookie; 600121986Sjhb if (pin >= io->io_numintr) 601121986Sjhb return (-1); 602151979Sjhb return (io->io_pins[pin].io_irq); 603121986Sjhb} 604121986Sjhb 605121986Sjhbint 606121986Sjhbioapic_disable_pin(void *cookie, u_int pin) 607121986Sjhb{ 608121986Sjhb struct ioapic *io; 609121986Sjhb 610121986Sjhb io = (struct ioapic *)cookie; 611121986Sjhb if (pin >= io->io_numintr) 612121986Sjhb return (EINVAL); 613151979Sjhb if (io->io_pins[pin].io_irq == IRQ_DISABLED) 614121986Sjhb return (EINVAL); 615151979Sjhb io->io_pins[pin].io_irq = IRQ_DISABLED; 616121986Sjhb if (bootverbose) 617121986Sjhb printf("ioapic%u: intpin %d disabled\n", io->io_id, pin); 618121986Sjhb return (0); 619121986Sjhb} 620121986Sjhb 621121986Sjhbint 622121986Sjhbioapic_remap_vector(void *cookie, u_int pin, int vector) 623121986Sjhb{ 624121986Sjhb struct ioapic *io; 625121986Sjhb 626121986Sjhb io = (struct ioapic *)cookie; 627121986Sjhb if (pin >= io->io_numintr || vector < 0) 628121986Sjhb return (EINVAL); 629151979Sjhb if (io->io_pins[pin].io_irq >= NUM_IO_INTS) 630121986Sjhb return (EINVAL); 631151979Sjhb io->io_pins[pin].io_irq = vector; 632121986Sjhb if (bootverbose) 633121986Sjhb printf("ioapic%u: Routing IRQ %d -> intpin %d\n", io->io_id, 634121986Sjhb vector, pin); 635121986Sjhb return (0); 636121986Sjhb} 637121986Sjhb 638121986Sjhbint 639130980Sjhbioapic_set_bus(void *cookie, u_int pin, int bus_type) 640130980Sjhb{ 641130980Sjhb struct ioapic *io; 642130980Sjhb 643130980Sjhb if (bus_type < 0 || bus_type > APIC_BUS_MAX) 644130980Sjhb return (EINVAL); 645130980Sjhb io = (struct ioapic *)cookie; 646130980Sjhb if (pin >= io->io_numintr) 647130980Sjhb return (EINVAL); 648151979Sjhb if (io->io_pins[pin].io_irq >= NUM_IO_INTS) 649130980Sjhb return (EINVAL); 650164358Sjhb if (io->io_pins[pin].io_bus == bus_type) 651164358Sjhb return (0); 652130980Sjhb io->io_pins[pin].io_bus = bus_type; 653130980Sjhb if (bootverbose) 654130980Sjhb printf("ioapic%u: intpin %d bus %s\n", io->io_id, pin, 655130980Sjhb ioapic_bus_string(bus_type)); 656130980Sjhb return (0); 657130980Sjhb} 658130980Sjhb 659130980Sjhbint 660121986Sjhbioapic_set_nmi(void *cookie, u_int pin) 661121986Sjhb{ 662121986Sjhb struct ioapic *io; 663121986Sjhb 664121986Sjhb io = (struct ioapic *)cookie; 665121986Sjhb if (pin >= io->io_numintr) 666121986Sjhb return (EINVAL); 667151979Sjhb if (io->io_pins[pin].io_irq == IRQ_NMI) 668130980Sjhb return (0); 669151979Sjhb if (io->io_pins[pin].io_irq >= NUM_IO_INTS) 670121986Sjhb return (EINVAL); 671130980Sjhb io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN; 672151979Sjhb io->io_pins[pin].io_irq = IRQ_NMI; 673121986Sjhb io->io_pins[pin].io_masked = 0; 674121986Sjhb io->io_pins[pin].io_edgetrigger = 1; 675121986Sjhb io->io_pins[pin].io_activehi = 1; 676121986Sjhb if (bootverbose) 677121986Sjhb printf("ioapic%u: Routing NMI -> intpin %d\n", 678121986Sjhb io->io_id, pin); 679121986Sjhb return (0); 680121986Sjhb} 681121986Sjhb 682121986Sjhbint 683121986Sjhbioapic_set_smi(void *cookie, u_int pin) 684121986Sjhb{ 685121986Sjhb struct ioapic *io; 686121986Sjhb 687121986Sjhb io = (struct ioapic *)cookie; 688121986Sjhb if (pin >= io->io_numintr) 689121986Sjhb return (EINVAL); 690151979Sjhb if (io->io_pins[pin].io_irq == IRQ_SMI) 691130980Sjhb return (0); 692151979Sjhb if (io->io_pins[pin].io_irq >= NUM_IO_INTS) 693121986Sjhb return (EINVAL); 694130980Sjhb io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN; 695151979Sjhb io->io_pins[pin].io_irq = IRQ_SMI; 696121986Sjhb io->io_pins[pin].io_masked = 0; 697121986Sjhb io->io_pins[pin].io_edgetrigger = 1; 698121986Sjhb io->io_pins[pin].io_activehi = 1; 699121986Sjhb if (bootverbose) 700121986Sjhb printf("ioapic%u: Routing SMI -> intpin %d\n", 701121986Sjhb io->io_id, pin); 702121986Sjhb return (0); 703121986Sjhb} 704121986Sjhb 705121986Sjhbint 706121986Sjhbioapic_set_extint(void *cookie, u_int pin) 707121986Sjhb{ 708121986Sjhb struct ioapic *io; 709121986Sjhb 710121986Sjhb io = (struct ioapic *)cookie; 711121986Sjhb if (pin >= io->io_numintr) 712121986Sjhb return (EINVAL); 713151979Sjhb if (io->io_pins[pin].io_irq == IRQ_EXTINT) 714130980Sjhb return (0); 715151979Sjhb if (io->io_pins[pin].io_irq >= NUM_IO_INTS) 716121986Sjhb return (EINVAL); 717130980Sjhb io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN; 718151979Sjhb io->io_pins[pin].io_irq = IRQ_EXTINT; 719148538Sjhb if (enable_extint) 720148538Sjhb io->io_pins[pin].io_masked = 0; 721148538Sjhb else 722148538Sjhb io->io_pins[pin].io_masked = 1; 723121986Sjhb io->io_pins[pin].io_edgetrigger = 1; 724121986Sjhb io->io_pins[pin].io_activehi = 1; 725121986Sjhb if (bootverbose) 726121986Sjhb printf("ioapic%u: Routing external 8259A's -> intpin %d\n", 727121986Sjhb io->io_id, pin); 728121986Sjhb return (0); 729121986Sjhb} 730121986Sjhb 731121986Sjhbint 732128930Sjhbioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol) 733121986Sjhb{ 734121986Sjhb struct ioapic *io; 735164358Sjhb int activehi; 736121986Sjhb 737121986Sjhb io = (struct ioapic *)cookie; 738128930Sjhb if (pin >= io->io_numintr || pol == INTR_POLARITY_CONFORM) 739121986Sjhb return (EINVAL); 740151979Sjhb if (io->io_pins[pin].io_irq >= NUM_IO_INTS) 741121986Sjhb return (EINVAL); 742164358Sjhb activehi = (pol == INTR_POLARITY_HIGH); 743164358Sjhb if (io->io_pins[pin].io_activehi == activehi) 744164358Sjhb return (0); 745164358Sjhb io->io_pins[pin].io_activehi = activehi; 746121986Sjhb if (bootverbose) 747121986Sjhb printf("ioapic%u: intpin %d polarity: %s\n", io->io_id, pin, 748128930Sjhb pol == INTR_POLARITY_HIGH ? "high" : "low"); 749121986Sjhb return (0); 750121986Sjhb} 751121986Sjhb 752121986Sjhbint 753128930Sjhbioapic_set_triggermode(void *cookie, u_int pin, enum intr_trigger trigger) 754121986Sjhb{ 755121986Sjhb struct ioapic *io; 756164358Sjhb int edgetrigger; 757121986Sjhb 758121986Sjhb io = (struct ioapic *)cookie; 759128930Sjhb if (pin >= io->io_numintr || trigger == INTR_TRIGGER_CONFORM) 760121986Sjhb return (EINVAL); 761151979Sjhb if (io->io_pins[pin].io_irq >= NUM_IO_INTS) 762121986Sjhb return (EINVAL); 763164358Sjhb edgetrigger = (trigger == INTR_TRIGGER_EDGE); 764164358Sjhb if (io->io_pins[pin].io_edgetrigger == edgetrigger) 765164358Sjhb return (0); 766164358Sjhb io->io_pins[pin].io_edgetrigger = edgetrigger; 767121986Sjhb if (bootverbose) 768121986Sjhb printf("ioapic%u: intpin %d trigger: %s\n", io->io_id, pin, 769128930Sjhb trigger == INTR_TRIGGER_EDGE ? "edge" : "level"); 770121986Sjhb return (0); 771121986Sjhb} 772121986Sjhb 773121986Sjhb/* 774121986Sjhb * Register a complete I/O APIC object with the interrupt subsystem. 775121986Sjhb */ 776121986Sjhbvoid 777121986Sjhbioapic_register(void *cookie) 778121986Sjhb{ 779121986Sjhb struct ioapic_intsrc *pin; 780121986Sjhb struct ioapic *io; 781121986Sjhb volatile ioapic_t *apic; 782121986Sjhb uint32_t flags; 783121986Sjhb int i; 784121986Sjhb 785121986Sjhb io = (struct ioapic *)cookie; 786121986Sjhb apic = io->io_addr; 787121986Sjhb mtx_lock_spin(&icu_lock); 788121986Sjhb flags = ioapic_read(apic, IOAPIC_VER) & IOART_VER_VERSION; 789121986Sjhb STAILQ_INSERT_TAIL(&ioapic_list, io, io_next); 790121986Sjhb mtx_unlock_spin(&icu_lock); 791122064Sjhb printf("ioapic%u <Version %u.%u> irqs %u-%u on motherboard\n", 792122064Sjhb io->io_id, flags >> 4, flags & 0xf, io->io_intbase, 793122064Sjhb io->io_intbase + io->io_numintr - 1); 794151979Sjhb 795151979Sjhb /* Register valid pins as interrupt sources. */ 796163219Sjhb intr_register_pic(&io->io_pic); 797151979Sjhb for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++) 798151979Sjhb if (pin->io_irq < NUM_IO_INTS) 799151979Sjhb intr_register_source(&pin->io_intsrc); 800121986Sjhb} 801167240Sjhb 802167240Sjhb/* A simple new-bus driver to consume PCI I/O APIC devices. */ 803167240Sjhbstatic int 804167240Sjhbioapic_pci_probe(device_t dev) 805167240Sjhb{ 806167240Sjhb 807167240Sjhb if (pci_get_class(dev) == PCIC_BASEPERIPH && 808167240Sjhb pci_get_subclass(dev) == PCIS_BASEPERIPH_PIC) { 809167240Sjhb switch (pci_get_progif(dev)) { 810167240Sjhb case PCIP_BASEPERIPH_PIC_IO_APIC: 811167240Sjhb device_set_desc(dev, "IO APIC"); 812167240Sjhb break; 813167240Sjhb case PCIP_BASEPERIPH_PIC_IOX_APIC: 814167240Sjhb device_set_desc(dev, "IO(x) APIC"); 815167240Sjhb break; 816167240Sjhb default: 817167240Sjhb return (ENXIO); 818167240Sjhb } 819167240Sjhb device_quiet(dev); 820167240Sjhb return (-10000); 821167240Sjhb } 822167240Sjhb return (ENXIO); 823167240Sjhb} 824167240Sjhb 825167240Sjhbstatic int 826167240Sjhbioapic_pci_attach(device_t dev) 827167240Sjhb{ 828167240Sjhb 829167240Sjhb return (0); 830167240Sjhb} 831167240Sjhb 832167240Sjhbstatic device_method_t ioapic_pci_methods[] = { 833167240Sjhb /* Device interface */ 834167240Sjhb DEVMETHOD(device_probe, ioapic_pci_probe), 835167240Sjhb DEVMETHOD(device_attach, ioapic_pci_attach), 836167240Sjhb 837167240Sjhb { 0, 0 } 838167240Sjhb}; 839167240Sjhb 840167240SjhbDEFINE_CLASS_0(ioapic, ioapic_pci_driver, ioapic_pci_methods, 0); 841167240Sjhb 842167240Sjhbstatic devclass_t ioapic_devclass; 843167240SjhbDRIVER_MODULE(ioapic, pci, ioapic_pci_driver, ioapic_devclass, 0, 0); 844167747Sjhb 845167747Sjhb/* 846167747Sjhb * A new-bus driver to consume the memory resources associated with 847167747Sjhb * the APICs in the system. On some systems ACPI or PnPBIOS system 848167747Sjhb * resource devices may already claim these resources. To keep from 849167747Sjhb * breaking those devices, we attach ourself to the nexus device after 850167747Sjhb * legacy0 and acpi0 and ignore any allocation failures. 851167747Sjhb */ 852167747Sjhbstatic void 853167747Sjhbapic_identify(driver_t *driver, device_t parent) 854167747Sjhb{ 855167747Sjhb 856167747Sjhb /* 857167747Sjhb * Add at order 12. acpi0 is probed at order 10 and legacy0 858167747Sjhb * is probed at order 11. 859167747Sjhb */ 860167747Sjhb if (lapic_paddr != 0) 861167747Sjhb BUS_ADD_CHILD(parent, 12, "apic", 0); 862167747Sjhb} 863167747Sjhb 864167747Sjhbstatic int 865167747Sjhbapic_probe(device_t dev) 866167747Sjhb{ 867167747Sjhb 868167747Sjhb device_set_desc(dev, "APIC resources"); 869167747Sjhb device_quiet(dev); 870167747Sjhb return (0); 871167747Sjhb} 872167747Sjhb 873167747Sjhbstatic void 874167747Sjhbapic_add_resource(device_t dev, int rid, vm_paddr_t base, size_t length) 875167747Sjhb{ 876167747Sjhb int error; 877167747Sjhb 878167747Sjhb#ifdef PAE 879167747Sjhb /* 880167747Sjhb * Resources use long's to track resources, so we can't 881167747Sjhb * include memory regions above 4GB. 882167747Sjhb */ 883167747Sjhb if (base >= ~0ul) 884167747Sjhb return; 885167747Sjhb#endif 886167747Sjhb error = bus_set_resource(dev, SYS_RES_MEMORY, rid, base, length); 887167747Sjhb if (error) 888167747Sjhb panic("apic_add_resource: resource %d failed set with %d", rid, 889167747Sjhb error); 890167747Sjhb bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 0); 891167747Sjhb} 892167747Sjhb 893167747Sjhbstatic int 894167747Sjhbapic_attach(device_t dev) 895167747Sjhb{ 896167747Sjhb struct ioapic *io; 897167747Sjhb int i; 898167747Sjhb 899167747Sjhb /* Reserve the local APIC. */ 900167747Sjhb apic_add_resource(dev, 0, lapic_paddr, sizeof(lapic_t)); 901167747Sjhb i = 1; 902167747Sjhb STAILQ_FOREACH(io, &ioapic_list, io_next) { 903167747Sjhb apic_add_resource(dev, i, io->io_paddr, IOAPIC_MEM_REGION); 904167747Sjhb i++; 905167747Sjhb } 906167747Sjhb return (0); 907167747Sjhb} 908167747Sjhb 909167747Sjhbstatic device_method_t apic_methods[] = { 910167747Sjhb /* Device interface */ 911167747Sjhb DEVMETHOD(device_identify, apic_identify), 912167747Sjhb DEVMETHOD(device_probe, apic_probe), 913167747Sjhb DEVMETHOD(device_attach, apic_attach), 914167747Sjhb 915167747Sjhb { 0, 0 } 916167747Sjhb}; 917167747Sjhb 918167747SjhbDEFINE_CLASS_0(apic, apic_driver, apic_methods, 0); 919167747Sjhb 920167747Sjhbstatic devclass_t apic_devclass; 921167747SjhbDRIVER_MODULE(apic, nexus, apic_driver, apic_devclass, 0, 0); 922257496Skib 923257496Skib#include "opt_ddb.h" 924257496Skib 925257496Skib#ifdef DDB 926257496Skib#include <ddb/ddb.h> 927257496Skib 928257496Skibstatic const char * 929257496Skibioapic_delivery_mode(uint32_t mode) 930257496Skib{ 931257496Skib 932257496Skib switch (mode) { 933257496Skib case IOART_DELFIXED: 934257496Skib return ("fixed"); 935257496Skib case IOART_DELLOPRI: 936257496Skib return ("lowestpri"); 937257496Skib case IOART_DELSMI: 938257496Skib return ("SMI"); 939257496Skib case IOART_DELRSV1: 940257496Skib return ("rsrvd1"); 941257496Skib case IOART_DELNMI: 942257496Skib return ("NMI"); 943257496Skib case IOART_DELINIT: 944257496Skib return ("INIT"); 945257496Skib case IOART_DELRSV2: 946257496Skib return ("rsrvd2"); 947257496Skib case IOART_DELEXINT: 948257496Skib return ("ExtINT"); 949257496Skib default: 950257496Skib return (""); 951257496Skib } 952257496Skib} 953257496Skib 954257496Skibstatic u_int 955257496Skibdb_ioapic_read(volatile ioapic_t *apic, int reg) 956257496Skib{ 957257496Skib 958257496Skib apic->ioregsel = reg; 959257496Skib return (apic->iowin); 960257496Skib} 961257496Skib 962257496Skibstatic void 963257496Skibdb_show_ioapic_one(volatile ioapic_t *io_addr) 964257496Skib{ 965257496Skib uint32_t r, lo, hi; 966257496Skib int mre, i; 967257496Skib 968257496Skib r = db_ioapic_read(io_addr, IOAPIC_VER); 969257496Skib mre = (r & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT; 970257496Skib db_printf("Id 0x%08x Ver 0x%02x MRE %d\n", 971257496Skib db_ioapic_read(io_addr, IOAPIC_ID), r & IOART_VER_VERSION, mre); 972257496Skib for (i = 0; i < mre; i++) { 973257496Skib lo = db_ioapic_read(io_addr, IOAPIC_REDTBL_LO(i)); 974257496Skib hi = db_ioapic_read(io_addr, IOAPIC_REDTBL_HI(i)); 975257496Skib db_printf(" pin %d Dest %s/%x %smasked Trig %s RemoteIRR %d " 976257496Skib "Polarity %s Status %s DeliveryMode %s Vec %d\n", i, 977257496Skib (lo & IOART_DESTMOD) == IOART_DESTLOG ? "log" : "phy", 978257496Skib (hi & IOART_DEST) >> 24, 979257496Skib (lo & IOART_INTMASK) == IOART_INTMSET ? "" : "not", 980257496Skib (lo & IOART_TRGRMOD) == IOART_TRGRLVL ? "lvl" : "edge", 981257496Skib (lo & IOART_REM_IRR) == IOART_REM_IRR ? 1 : 0, 982257496Skib (lo & IOART_INTPOL) == IOART_INTALO ? "low" : "high", 983257496Skib (lo & IOART_DELIVS) == IOART_DELIVS ? "pend" : "idle", 984257496Skib ioapic_delivery_mode(lo & IOART_DELMOD), 985257496Skib (lo & IOART_INTVEC)); 986257496Skib } 987257496Skib} 988257496Skib 989257496SkibDB_SHOW_COMMAND(ioapic, db_show_ioapic) 990257496Skib{ 991257496Skib struct ioapic *ioapic; 992257496Skib int idx, i; 993257496Skib 994257496Skib if (!have_addr) { 995257496Skib db_printf("usage: show ioapic index\n"); 996257496Skib return; 997257496Skib } 998257496Skib 999257496Skib idx = (int)addr; 1000257496Skib i = 0; 1001257496Skib STAILQ_FOREACH(ioapic, &ioapic_list, io_next) { 1002257496Skib if (idx == i) { 1003257496Skib db_show_ioapic_one(ioapic->io_addr); 1004257496Skib break; 1005257496Skib } 1006257496Skib i++; 1007257496Skib } 1008257496Skib} 1009257496Skib 1010257496SkibDB_SHOW_ALL_COMMAND(ioapics, db_show_all_ioapics) 1011257496Skib{ 1012257496Skib struct ioapic *ioapic; 1013257496Skib 1014257496Skib STAILQ_FOREACH(ioapic, &ioapic_list, io_next) 1015257496Skib db_show_ioapic_one(ioapic->io_addr); 1016257496Skib} 1017257496Skib#endif 1018