sbus.c revision 145185
1/*- 2 * Copyright (c) 1998 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Paul Kranenburg. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36/*- 37 * Copyright (c) 1992, 1993 38 * The Regents of the University of California. All rights reserved. 39 * 40 * This software was developed by the Computer Systems Engineering group 41 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 42 * contributed to Berkeley. 43 * 44 * All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by the University of 47 * California, Lawrence Berkeley Laboratory. 48 * 49 * Redistribution and use in source and binary forms, with or without 50 * modification, are permitted provided that the following conditions 51 * are met: 52 * 1. Redistributions of source code must retain the above copyright 53 * notice, this list of conditions and the following disclaimer. 54 * 2. Redistributions in binary form must reproduce the above copyright 55 * notice, this list of conditions and the following disclaimer in the 56 * documentation and/or other materials provided with the distribution. 57 * 4. Neither the name of the University nor the names of its contributors 58 * may be used to endorse or promote products derived from this software 59 * without specific prior written permission. 60 * 61 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 62 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 64 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 71 * SUCH DAMAGE. 72 */ 73/*- 74 * Copyright (c) 1999 Eduardo Horvath 75 * Copyright (c) 2002 by Thomas Moestl <tmm@FreeBSD.org>. 76 * All rights reserved. 77 * 78 * Redistribution and use in source and binary forms, with or without 79 * modification, are permitted provided that the following conditions 80 * are met: 81 * 1. Redistributions of source code must retain the above copyright 82 * notice, this list of conditions and the following disclaimer. 83 * 84 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 85 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 86 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 87 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 88 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 89 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 90 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 91 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 92 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 93 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 94 * SUCH DAMAGE. 95 * 96 * from: @(#)sbus.c 8.1 (Berkeley) 6/11/93 97 * from: NetBSD: sbus.c,v 1.46 2001/10/07 20:30:41 eeh Exp 98 */ 99 100#include <sys/cdefs.h> 101__FBSDID("$FreeBSD: head/sys/sparc64/sbus/sbus.c 145185 2005-04-17 11:28:41Z marius $"); 102 103/* 104 * SBus support. 105 */ 106 107#include <sys/param.h> 108#include <sys/systm.h> 109#include <sys/bus.h> 110#include <sys/kernel.h> 111#include <sys/malloc.h> 112#include <sys/module.h> 113#include <sys/pcpu.h> 114#include <sys/reboot.h> 115 116#include <dev/ofw/ofw_bus.h> 117#include <dev/ofw/openfirm.h> 118 119#include <machine/bus.h> 120#include <machine/bus_private.h> 121#include <machine/iommureg.h> 122#include <machine/bus_common.h> 123#include <machine/intr_machdep.h> 124#include <machine/nexusvar.h> 125#include <machine/ofw_upa.h> 126#include <machine/resource.h> 127 128#include <sys/rman.h> 129 130#include <machine/iommuvar.h> 131 132#include <sparc64/sbus/ofw_sbus.h> 133#include <sparc64/sbus/sbusreg.h> 134#include <sparc64/sbus/sbusvar.h> 135 136struct sbus_devinfo { 137 int sdi_burstsz; 138 char *sdi_compat; /* PROM compatible */ 139 char *sdi_model; /* PROM model */ 140 char *sdi_name; /* PROM name */ 141 phandle_t sdi_node; /* PROM node */ 142 int sdi_slot; 143 char *sdi_type; /* PROM device_type */ 144 145 struct resource_list sdi_rl; 146}; 147 148/* Range descriptor, allocated for each sc_range. */ 149struct sbus_rd { 150 bus_addr_t rd_poffset; 151 bus_addr_t rd_pend; 152 int rd_slot; 153 bus_addr_t rd_coffset; 154 bus_addr_t rd_cend; 155 struct rman rd_rman; 156 bus_space_handle_t rd_bushandle; 157 struct resource *rd_res; 158}; 159 160struct sbus_softc { 161 bus_space_tag_t sc_bustag; 162 bus_space_handle_t sc_bushandle; 163 bus_dma_tag_t sc_dmatag; 164 bus_dma_tag_t sc_cdmatag; 165 bus_space_tag_t sc_cbustag; 166 int sc_clockfreq; /* clock frequency (in Hz) */ 167 struct upa_regs *sc_reg; 168 int sc_nreg; 169 int sc_nrange; 170 struct sbus_rd *sc_rd; 171 int sc_burst; /* burst transfer sizes supp. */ 172 173 struct resource *sc_sysio_res; 174 int sc_ign; /* IGN for this sysio */ 175 struct iommu_state sc_is; /* IOMMU state (iommuvar.h) */ 176 177 struct resource *sc_ot_ires; 178 void *sc_ot_ihand; 179 struct resource *sc_pf_ires; 180 void *sc_pf_ihand; 181}; 182 183struct sbus_clr { 184 struct sbus_softc *scl_sc; 185 bus_addr_t scl_clr; /* clear register */ 186 driver_intr_t *scl_handler; /* handler to call */ 187 void *scl_arg; /* argument for the handler */ 188 void *scl_cookie; /* parent bus int. cookie */ 189}; 190 191#define SYSIO_READ8(sc, off) \ 192 bus_space_read_8((sc)->sc_bustag, (sc)->sc_bushandle, (off)) 193#define SYSIO_WRITE8(sc, off, v) \ 194 bus_space_write_8((sc)->sc_bustag, (sc)->sc_bushandle, (off), (v)) 195 196static device_probe_t sbus_probe; 197static bus_print_child_t sbus_print_child; 198static bus_probe_nomatch_t sbus_probe_nomatch; 199static bus_read_ivar_t sbus_read_ivar; 200static bus_get_resource_list_t sbus_get_resource_list; 201static bus_setup_intr_t sbus_setup_intr; 202static bus_teardown_intr_t sbus_teardown_intr; 203static bus_alloc_resource_t sbus_alloc_resource; 204static bus_release_resource_t sbus_release_resource; 205static bus_activate_resource_t sbus_activate_resource; 206static bus_deactivate_resource_t sbus_deactivate_resource; 207static ofw_bus_get_compat_t sbus_get_compat; 208static ofw_bus_get_model_t sbus_get_model; 209static ofw_bus_get_name_t sbus_get_name; 210static ofw_bus_get_node_t sbus_get_node; 211static ofw_bus_get_type_t sbus_get_type; 212 213static struct sbus_devinfo * sbus_setup_dinfo(struct sbus_softc *sc, 214 phandle_t node, char *name); 215static void sbus_destroy_dinfo(struct sbus_devinfo *dinfo); 216static void sbus_intr_stub(void *); 217static bus_space_tag_t sbus_alloc_bustag(struct sbus_softc *); 218static void sbus_overtemp(void *); 219static void sbus_pwrfail(void *); 220 221static device_method_t sbus_methods[] = { 222 /* Device interface */ 223 DEVMETHOD(device_probe, sbus_probe), 224 DEVMETHOD(device_attach, bus_generic_attach), 225 226 /* Bus interface */ 227 DEVMETHOD(bus_print_child, sbus_print_child), 228 DEVMETHOD(bus_probe_nomatch, sbus_probe_nomatch), 229 DEVMETHOD(bus_read_ivar, sbus_read_ivar), 230 DEVMETHOD(bus_setup_intr, sbus_setup_intr), 231 DEVMETHOD(bus_teardown_intr, sbus_teardown_intr), 232 DEVMETHOD(bus_alloc_resource, sbus_alloc_resource), 233 DEVMETHOD(bus_activate_resource, sbus_activate_resource), 234 DEVMETHOD(bus_deactivate_resource, sbus_deactivate_resource), 235 DEVMETHOD(bus_release_resource, sbus_release_resource), 236 DEVMETHOD(bus_get_resource_list, sbus_get_resource_list), 237 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 238 239 /* ofw_bus interface */ 240 DEVMETHOD(ofw_bus_get_compat, sbus_get_compat), 241 DEVMETHOD(ofw_bus_get_model, sbus_get_model), 242 DEVMETHOD(ofw_bus_get_name, sbus_get_name), 243 DEVMETHOD(ofw_bus_get_node, sbus_get_node), 244 DEVMETHOD(ofw_bus_get_type, sbus_get_type), 245 246 { 0, 0 } 247}; 248 249static driver_t sbus_driver = { 250 "sbus", 251 sbus_methods, 252 sizeof(struct sbus_softc), 253}; 254 255static devclass_t sbus_devclass; 256 257DRIVER_MODULE(sbus, nexus, sbus_driver, sbus_devclass, 0, 0); 258 259#define OFW_SBUS_TYPE "sbus" 260#define OFW_SBUS_NAME "sbus" 261 262static int 263sbus_probe(device_t dev) 264{ 265 struct sbus_softc *sc; 266 struct sbus_devinfo *sdi; 267 struct sbus_ranges *range; 268 struct resource *res; 269 device_t cdev; 270 bus_addr_t phys; 271 bus_size_t size; 272 char *name, *cname, *t; 273 phandle_t child, node; 274 u_int64_t mr; 275 int intr, clock, rid, vec, i; 276 277 t = nexus_get_device_type(dev); 278 if (((t == NULL || strcmp(t, OFW_SBUS_TYPE) != 0)) && 279 strcmp(nexus_get_name(dev), OFW_SBUS_NAME) != 0) 280 return (ENXIO); 281 device_set_desc(dev, "U2S UPA-SBus bridge"); 282 283 sc = device_get_softc(dev); 284 node = nexus_get_node(dev); 285 286 if ((sc->sc_nreg = OF_getprop_alloc(node, "reg", sizeof(*sc->sc_reg), 287 (void **)&sc->sc_reg)) == -1) { 288 panic("%s: error getting reg property", __func__); 289 } 290 if (sc->sc_nreg < 1) 291 panic("%s: bogus properties", __func__); 292 phys = UPA_REG_PHYS(&sc->sc_reg[0]); 293 size = UPA_REG_SIZE(&sc->sc_reg[0]); 294 rid = 0; 295 sc->sc_sysio_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, phys, 296 phys + size - 1, size, RF_ACTIVE); 297 if (sc->sc_sysio_res == NULL || 298 rman_get_start(sc->sc_sysio_res) != phys) 299 panic("%s: cannot allocate device memory", __func__); 300 sc->sc_bustag = rman_get_bustag(sc->sc_sysio_res); 301 sc->sc_bushandle = rman_get_bushandle(sc->sc_sysio_res); 302 303 if (OF_getprop(node, "interrupts", &intr, sizeof(intr)) == -1) 304 panic("%s: cannot get IGN", __func__); 305 sc->sc_ign = intr & INTMAP_IGN_MASK; /* Find interrupt group no */ 306 sc->sc_cbustag = sbus_alloc_bustag(sc); 307 308 /* 309 * Record clock frequency for synchronous SCSI. 310 * IS THIS THE CORRECT DEFAULT?? 311 */ 312 if (OF_getprop(node, "clock-frequency", &clock, sizeof(clock)) == -1) 313 clock = 25000000; 314 sc->sc_clockfreq = clock; 315 clock /= 1000; 316 device_printf(dev, "clock %d.%03d MHz\n", clock / 1000, clock % 1000); 317 318 /* 319 * Collect address translations from the OBP. 320 */ 321 if ((sc->sc_nrange = OF_getprop_alloc(node, "ranges", 322 sizeof(*range), (void **)&range)) == -1) { 323 panic("%s: error getting ranges property", __func__); 324 } 325 sc->sc_rd = (struct sbus_rd *)malloc(sizeof(*sc->sc_rd) * sc->sc_nrange, 326 M_DEVBUF, M_NOWAIT); 327 if (sc->sc_rd == NULL) 328 panic("%s: cannot allocate rmans", __func__); 329 /* 330 * Preallocate all space that the SBus bridge decodes, so that nothing 331 * else gets in the way; set up rmans etc. 332 */ 333 for (i = 0; i < sc->sc_nrange; i++) { 334 phys = range[i].poffset | ((bus_addr_t)range[i].pspace << 32); 335 size = range[i].size; 336 sc->sc_rd[i].rd_slot = range[i].cspace; 337 sc->sc_rd[i].rd_coffset = range[i].coffset; 338 sc->sc_rd[i].rd_cend = sc->sc_rd[i].rd_coffset + size; 339 rid = 0; 340 if ((res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, phys, 341 phys + size - 1, size, RF_ACTIVE)) == NULL) 342 panic("%s: cannot allocate decoded range", __func__); 343 sc->sc_rd[i].rd_bushandle = rman_get_bushandle(res); 344 sc->sc_rd[i].rd_rman.rm_type = RMAN_ARRAY; 345 sc->sc_rd[i].rd_rman.rm_descr = "SBus Device Memory"; 346 if (rman_init(&sc->sc_rd[i].rd_rman) != 0 || 347 rman_manage_region(&sc->sc_rd[i].rd_rman, 0, size) != 0) 348 panic("%s: failed to set up memory rman", __func__); 349 sc->sc_rd[i].rd_poffset = phys; 350 sc->sc_rd[i].rd_pend = phys + size; 351 sc->sc_rd[i].rd_res = res; 352 } 353 free(range, M_OFWPROP); 354 355 /* 356 * Get the SBus burst transfer size if burst transfers are supported. 357 * XXX: is the default correct? 358 */ 359 if (OF_getprop(node, "burst-sizes", &sc->sc_burst, 360 sizeof(sc->sc_burst)) == -1 || sc->sc_burst == 0) 361 sc->sc_burst = SBUS_BURST_DEF; 362 363 /* initalise the IOMMU */ 364 365 /* punch in our copies */ 366 sc->sc_is.is_bustag = sc->sc_bustag; 367 sc->sc_is.is_bushandle = sc->sc_bushandle; 368 sc->sc_is.is_iommu = SBR_IOMMU; 369 sc->sc_is.is_dtag = SBR_IOMMU_TLB_TAG_DIAG; 370 sc->sc_is.is_ddram = SBR_IOMMU_TLB_DATA_DIAG; 371 sc->sc_is.is_dqueue = SBR_IOMMU_QUEUE_DIAG; 372 sc->sc_is.is_dva = SBR_IOMMU_SVADIAG; 373 sc->sc_is.is_dtcmp = 0; 374 sc->sc_is.is_sb[0] = SBR_STRBUF; 375 sc->sc_is.is_sb[1] = 0; 376 377 /* give us a nice name.. */ 378 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 379 if (name == NULL) 380 panic("%s: cannot malloc iommu name", __func__); 381 snprintf(name, 32, "%s dvma", device_get_name(dev)); 382 383 /* 384 * Note: the SBus IOMMU ignores the high bits of an address, so a NULL 385 * DMA pointer will be translated by the first page of the IOTSB. 386 * To detect bugs we'll allocate and ignore the first entry. 387 */ 388 iommu_init(name, &sc->sc_is, 3, -1, 1); 389 390 /* Create the DMA tag. */ 391 sc->sc_dmatag = nexus_get_dmatag(dev); 392 if (bus_dma_tag_create(sc->sc_dmatag, 8, 1, 0, 0x3ffffffff, NULL, NULL, 393 0x3ffffffff, 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_cdmatag) != 0) 394 panic("%s: bus_dma_tag_create failed", __func__); 395 /* Customize the tag. */ 396 sc->sc_cdmatag->dt_cookie = &sc->sc_is; 397 sc->sc_cdmatag->dt_mt = &iommu_dma_methods; 398 /* XXX: register as root dma tag (kludge). */ 399 sparc64_root_dma_tag = sc->sc_cdmatag; 400 401 /* Enable the over-temperature and power-fail interrupts. */ 402 rid = 0; 403 mr = SYSIO_READ8(sc, SBR_THERM_INT_MAP); 404 vec = INTVEC(mr); 405 if ((sc->sc_ot_ires = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, vec, 406 vec, 1, RF_ACTIVE)) == NULL) 407 panic("%s: failed to get temperature interrupt", __func__); 408 bus_setup_intr(dev, sc->sc_ot_ires, INTR_TYPE_MISC | INTR_FAST, 409 sbus_overtemp, sc, &sc->sc_ot_ihand); 410 SYSIO_WRITE8(sc, SBR_THERM_INT_MAP, INTMAP_ENABLE(mr, PCPU_GET(mid))); 411 rid = 0; 412 mr = SYSIO_READ8(sc, SBR_POWER_INT_MAP); 413 vec = INTVEC(mr); 414 if ((sc->sc_pf_ires = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, vec, 415 vec, 1, RF_ACTIVE)) == NULL) 416 panic("%s: failed to get power fail interrupt", __func__); 417 bus_setup_intr(dev, sc->sc_pf_ires, INTR_TYPE_MISC | INTR_FAST, 418 sbus_pwrfail, sc, &sc->sc_pf_ihand); 419 SYSIO_WRITE8(sc, SBR_POWER_INT_MAP, INTMAP_ENABLE(mr, PCPU_GET(mid))); 420 421 /* Initialize the counter-timer. */ 422 sparc64_counter_init(sc->sc_bustag, sc->sc_bushandle, SBR_TC0); 423 424 /* 425 * Loop through ROM children, fixing any relative addresses 426 * and then configuring each device. 427 * `specials' is an array of device names that are treated 428 * specially: 429 */ 430 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 431 if ((OF_getprop_alloc(child, "name", 1, (void **)&cname)) == -1) 432 continue; 433 434 if ((sdi = sbus_setup_dinfo(sc, child, cname)) == NULL) { 435 device_printf(dev, "<%s>: incomplete\n", cname); 436 free(cname, M_OFWPROP); 437 continue; 438 } 439 if ((cdev = device_add_child(dev, NULL, -1)) == NULL) 440 panic("%s: device_add_child failed", __func__); 441 device_set_ivars(cdev, sdi); 442 } 443 return (0); 444} 445 446static struct sbus_devinfo * 447sbus_setup_dinfo(struct sbus_softc *sc, phandle_t node, char *name) 448{ 449 struct sbus_devinfo *sdi; 450 struct sbus_regs *reg; 451 u_int32_t base, iv, *intr; 452 int i, nreg, nintr, slot, rslot; 453 454 sdi = malloc(sizeof(*sdi), M_DEVBUF, M_ZERO | M_WAITOK); 455 if (sdi == NULL) 456 return (NULL); 457 resource_list_init(&sdi->sdi_rl); 458 sdi->sdi_name = name; 459 sdi->sdi_node = node; 460 OF_getprop_alloc(node, "compatible", 1, (void **)&sdi->sdi_compat); 461 OF_getprop_alloc(node, "device_type", 1, (void **)&sdi->sdi_type); 462 OF_getprop_alloc(node, "model", 1, (void **)&sdi->sdi_model); 463 slot = -1; 464 nreg = OF_getprop_alloc(node, "reg", sizeof(*reg), (void **)®); 465 if (nreg == -1) { 466 if (sdi->sdi_type == NULL || 467 strcmp(sdi->sdi_type, "hierarchical") != 0) { 468 sbus_destroy_dinfo(sdi); 469 return (NULL); 470 } 471 } else { 472 for (i = 0; i < nreg; i++) { 473 base = reg[i].sbr_offset; 474 if (SBUS_ABS(base)) { 475 rslot = SBUS_ABS_TO_SLOT(base); 476 base = SBUS_ABS_TO_OFFSET(base); 477 } else 478 rslot = reg[i].sbr_slot; 479 if (slot != -1 && slot != rslot) 480 panic("%s: multiple slots", __func__); 481 slot = rslot; 482 483 resource_list_add(&sdi->sdi_rl, SYS_RES_MEMORY, i, 484 base, base + reg[i].sbr_size, reg[i].sbr_size); 485 } 486 free(reg, M_OFWPROP); 487 } 488 sdi->sdi_slot = slot; 489 490 /* 491 * The `interrupts' property contains the SBus interrupt level. 492 */ 493 nintr = OF_getprop_alloc(node, "interrupts", sizeof(*intr), 494 (void **)&intr); 495 if (nintr != -1) { 496 for (i = 0; i < nintr; i++) { 497 iv = intr[i]; 498 /* 499 * SBus card devices need the slot number encoded into 500 * the vector as this is generally not done. 501 */ 502 if ((iv & INTMAP_OBIO_MASK) == 0) 503 iv |= slot << 3; 504 /* Set the ign as appropriate. */ 505 iv |= sc->sc_ign; 506 resource_list_add(&sdi->sdi_rl, SYS_RES_IRQ, i, 507 iv, iv, 1); 508 } 509 free(intr, M_OFWPROP); 510 } 511 if (OF_getprop(node, "burst-sizes", &sdi->sdi_burstsz, 512 sizeof(sdi->sdi_burstsz)) == -1) 513 sdi->sdi_burstsz = sc->sc_burst; 514 else 515 sdi->sdi_burstsz &= sc->sc_burst; 516 517 return (sdi); 518} 519 520/* Free everything except sdi_name, which is handled separately. */ 521static void 522sbus_destroy_dinfo(struct sbus_devinfo *dinfo) 523{ 524 525 resource_list_free(&dinfo->sdi_rl); 526 if (dinfo->sdi_compat != NULL) 527 free(dinfo->sdi_compat, M_OFWPROP); 528 if (dinfo->sdi_model != NULL) 529 free(dinfo->sdi_model, M_OFWPROP); 530 if (dinfo->sdi_type != NULL) 531 free(dinfo->sdi_type, M_OFWPROP); 532 free(dinfo, M_DEVBUF); 533} 534 535static int 536sbus_print_child(device_t dev, device_t child) 537{ 538 struct sbus_devinfo *dinfo; 539 struct resource_list *rl; 540 int rv; 541 542 dinfo = device_get_ivars(child); 543 rl = &dinfo->sdi_rl; 544 rv = bus_print_child_header(dev, child); 545 rv += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 546 rv += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 547 rv += bus_print_child_footer(dev, child); 548 return (rv); 549} 550 551static void 552sbus_probe_nomatch(device_t dev, device_t child) 553{ 554 const char *type; 555 556 if ((type = ofw_bus_get_type(child)) == NULL) 557 type = "(unknown)"; 558 device_printf(dev, "<%s>, type %s (no driver attached)\n", 559 ofw_bus_get_name(child), type); 560} 561 562static int 563sbus_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 564{ 565 struct sbus_softc *sc; 566 struct sbus_devinfo *dinfo; 567 568 sc = device_get_softc(dev); 569 if ((dinfo = device_get_ivars(child)) == NULL) 570 return (ENOENT); 571 switch (which) { 572 case SBUS_IVAR_BURSTSZ: 573 *result = dinfo->sdi_burstsz; 574 break; 575 case SBUS_IVAR_CLOCKFREQ: 576 *result = sc->sc_clockfreq; 577 break; 578 case SBUS_IVAR_SLOT: 579 *result = dinfo->sdi_slot; 580 break; 581 default: 582 return (ENOENT); 583 } 584 return 0; 585} 586 587static struct resource_list * 588sbus_get_resource_list(device_t dev, device_t child) 589{ 590 struct sbus_devinfo *sdi; 591 592 sdi = device_get_ivars(child); 593 return (&sdi->sdi_rl); 594} 595 596/* Write to the correct clr register, and call the actual handler. */ 597static void 598sbus_intr_stub(void *arg) 599{ 600 struct sbus_clr *scl; 601 602 scl = (struct sbus_clr *)arg; 603 scl->scl_handler(scl->scl_arg); 604 SYSIO_WRITE8(scl->scl_sc, scl->scl_clr, 0); 605} 606 607static int 608sbus_setup_intr(device_t dev, device_t child, struct resource *ires, int flags, 609 driver_intr_t *intr, void *arg, void **cookiep) 610{ 611 struct sbus_softc *sc; 612 struct sbus_clr *scl; 613 bus_addr_t intrmapptr, intrclrptr, intrptr; 614 u_int64_t intrmap; 615 u_int32_t inr, slot; 616 int error, i; 617 long vec = rman_get_start(ires); 618 619 sc = device_get_softc(dev); 620 scl = (struct sbus_clr *)malloc(sizeof(*scl), M_DEVBUF, M_NOWAIT); 621 if (scl == NULL) 622 return (0); 623 intrptr = intrmapptr = intrclrptr = 0; 624 intrmap = 0; 625 inr = INTVEC(vec); 626 if ((inr & INTMAP_OBIO_MASK) == 0) { 627 /* 628 * We're in an SBus slot, register the map and clear 629 * intr registers. 630 */ 631 slot = INTSLOT(vec); 632 intrmapptr = SBR_SLOT0_INT_MAP + slot * 8; 633 intrclrptr = SBR_SLOT0_INT_CLR + 634 (slot * 8 * 8) + (INTPRI(vec) * 8); 635 /* Enable the interrupt, insert IGN. */ 636 intrmap = inr | sc->sc_ign; 637 } else { 638 intrptr = SBR_SCSI_INT_MAP; 639 /* Insert IGN */ 640 inr |= sc->sc_ign; 641 for (i = 0; intrptr <= SBR_RESERVED_INT_MAP && 642 INTVEC(intrmap = SYSIO_READ8(sc, intrptr)) != 643 INTVEC(inr); intrptr += 8, i++) 644 ; 645 if (INTVEC(intrmap) == INTVEC(inr)) { 646 /* Register the map and clear intr registers */ 647 intrmapptr = intrptr; 648 intrclrptr = SBR_SCSI_INT_CLR + i * 8; 649 /* Enable the interrupt */ 650 } else 651 panic("%s: IRQ not found!", __func__); 652 } 653 654 scl->scl_sc = sc; 655 scl->scl_arg = arg; 656 scl->scl_handler = intr; 657 scl->scl_clr = intrclrptr; 658 /* Disable the interrupt while we fiddle with it */ 659 SYSIO_WRITE8(sc, intrmapptr, intrmap); 660 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 661 sbus_intr_stub, scl, cookiep); 662 if (error != 0) { 663 free(scl, M_DEVBUF); 664 return (error); 665 } 666 scl->scl_cookie = *cookiep; 667 *cookiep = scl; 668 669 /* 670 * Clear the interrupt, it might have been triggered before it was 671 * set up. 672 */ 673 SYSIO_WRITE8(sc, intrclrptr, 0); 674 /* 675 * Enable the interrupt and program the target module now we have the 676 * handler installed. 677 */ 678 SYSIO_WRITE8(sc, intrmapptr, INTMAP_ENABLE(intrmap, PCPU_GET(mid))); 679 return (error); 680} 681 682static int 683sbus_teardown_intr(device_t dev, device_t child, 684 struct resource *vec, void *cookie) 685{ 686 struct sbus_clr *scl; 687 int error; 688 689 scl = (struct sbus_clr *)cookie; 690 error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, 691 scl->scl_cookie); 692 /* 693 * Don't disable the interrupt for now, so that stray interrupts get 694 * detected... 695 */ 696 if (error != 0) 697 free(scl, M_DEVBUF); 698 return (error); 699} 700 701/* 702 * There is no need to handle pass-throughs here; there are no bridges to 703 * SBuses. 704 */ 705static struct resource * 706sbus_alloc_resource(device_t bus, device_t child, int type, int *rid, 707 u_long start, u_long end, u_long count, u_int flags) 708{ 709 struct sbus_softc *sc; 710 struct sbus_devinfo *sdi; 711 struct rman *rm; 712 struct resource *rv; 713 struct resource_list *rl; 714 struct resource_list_entry *rle; 715 bus_space_handle_t bh; 716 bus_addr_t toffs; 717 bus_size_t tend; 718 int i; 719 int isdefault, needactivate; 720 721 isdefault = (start == 0UL && end == ~0UL); 722 needactivate = flags & RF_ACTIVE; 723 sc = (struct sbus_softc *)device_get_softc(bus); 724 sdi = device_get_ivars(child); 725 rl = &sdi->sdi_rl; 726 rle = resource_list_find(rl, type, *rid); 727 if (rle == NULL) 728 return (NULL); 729 if (rle->res != NULL) 730 panic("%s: resource entry is busy", __func__); 731 if (isdefault) { 732 start = rle->start; 733 count = ulmax(count, rle->count); 734 end = ulmax(rle->end, start + count - 1); 735 } 736 switch (type) { 737 case SYS_RES_IRQ: 738 rv = BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, 739 rid, start, end, count, flags); 740 if (rv == NULL) 741 return (NULL); 742 break; 743 case SYS_RES_MEMORY: 744 rm = NULL; 745 bh = toffs = tend = 0; 746 for (i = 0; i < sc->sc_nrange; i++) { 747 if (sc->sc_rd[i].rd_slot != sdi->sdi_slot || 748 start < sc->sc_rd[i].rd_coffset || 749 start > sc->sc_rd[i].rd_cend) 750 continue; 751 /* Disallow cross-range allocations. */ 752 if (end > sc->sc_rd[i].rd_cend) 753 return (NULL); 754 /* We've found the connection to the parent bus */ 755 toffs = start - sc->sc_rd[i].rd_coffset; 756 tend = end - sc->sc_rd[i].rd_coffset; 757 rm = &sc->sc_rd[i].rd_rman; 758 bh = sc->sc_rd[i].rd_bushandle; 759 } 760 if (toffs == 0L) 761 return (NULL); 762 flags &= ~RF_ACTIVE; 763 rv = rman_reserve_resource(rm, toffs, tend, count, flags, 764 child); 765 if (rv == NULL) 766 return (NULL); 767 rman_set_bustag(rv, sc->sc_cbustag); 768 rman_set_bushandle(rv, bh + rman_get_start(rv)); 769 if (needactivate) { 770 if (bus_activate_resource(child, type, *rid, rv)) { 771 rman_release_resource(rv); 772 return (NULL); 773 } 774 } 775 break; 776 default: 777 return (NULL); 778 } 779 rle->res = rv; 780 return (rv); 781} 782 783static int 784sbus_activate_resource(device_t bus, device_t child, int type, int rid, 785 struct resource *r) 786{ 787 788 if (type == SYS_RES_IRQ) { 789 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), 790 child, type, rid, r)); 791 } 792 return (rman_activate_resource(r)); 793} 794 795static int 796sbus_deactivate_resource(device_t bus, device_t child, int type, int rid, 797 struct resource *r) 798{ 799 800 if (type == SYS_RES_IRQ) { 801 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), 802 child, type, rid, r)); 803 } 804 return (rman_deactivate_resource(r)); 805} 806 807static int 808sbus_release_resource(device_t bus, device_t child, int type, int rid, 809 struct resource *r) 810{ 811 struct sbus_devinfo *sdi; 812 struct resource_list_entry *rle; 813 int error = 0; 814 815 if (type == SYS_RES_IRQ) 816 error = BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 817 type, rid, r); 818 else { 819 if ((rman_get_flags(r) & RF_ACTIVE) != 0) 820 error = bus_deactivate_resource(child, type, rid, r); 821 if (error != 0) 822 return (error); 823 error = rman_release_resource(r); 824 } 825 if (error != 0) 826 return (error); 827 sdi = device_get_ivars(child); 828 rle = resource_list_find(&sdi->sdi_rl, type, rid); 829 if (rle == NULL) 830 panic("%s: cannot find resource", __func__); 831 if (rle->res == NULL) 832 panic("%s: resource entry is not busy", __func__); 833 rle->res = NULL; 834 return (0); 835} 836 837/* 838 * Handle an overtemp situation. 839 * 840 * SPARCs have temperature sensors which generate interrupts 841 * if the machine's temperature exceeds a certain threshold. 842 * This handles the interrupt and powers off the machine. 843 * The same needs to be done to PCI controller drivers. 844 */ 845static void 846sbus_overtemp(void *arg) 847{ 848 849 printf("DANGER: OVER TEMPERATURE detected\nShutting down NOW.\n"); 850 shutdown_nice(RB_POWEROFF); 851} 852 853/* Try to shut down in time in case of power failure. */ 854static void 855sbus_pwrfail(void *arg) 856{ 857 858 printf("Power failure detected\nShutting down NOW.\n"); 859 shutdown_nice(0); 860} 861 862static bus_space_tag_t 863sbus_alloc_bustag(struct sbus_softc *sc) 864{ 865 bus_space_tag_t sbt; 866 867 sbt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 868 M_NOWAIT | M_ZERO); 869 if (sbt == NULL) 870 panic("%s: out of memory", __func__); 871 872 sbt->bst_cookie = sc; 873 sbt->bst_parent = sc->sc_bustag; 874 sbt->bst_type = SBUS_BUS_SPACE; 875 return (sbt); 876} 877 878static const char * 879sbus_get_compat(device_t bus, device_t dev) 880{ 881 struct sbus_devinfo *dinfo; 882 883 dinfo = device_get_ivars(dev); 884 return (dinfo->sdi_compat); 885} 886 887static const char * 888sbus_get_model(device_t bus, device_t dev) 889{ 890 struct sbus_devinfo *dinfo; 891 892 dinfo = device_get_ivars(dev); 893 return (dinfo->sdi_model); 894} 895 896static const char * 897sbus_get_name(device_t bus, device_t dev) 898{ 899 struct sbus_devinfo *dinfo; 900 901 dinfo = device_get_ivars(dev); 902 return (dinfo->sdi_name); 903} 904 905static phandle_t 906sbus_get_node(device_t bus, device_t dev) 907{ 908 struct sbus_devinfo *dinfo; 909 910 dinfo = device_get_ivars(dev); 911 return (dinfo->sdi_node); 912} 913 914static const char * 915sbus_get_type(device_t bus, device_t dev) 916{ 917 struct sbus_devinfo *dinfo; 918 919 dinfo = device_get_ivars(dev); 920 return (dinfo->sdi_type); 921} 922