sbus.c revision 100188
190618Stmm/*- 290618Stmm * Copyright (c) 1998 The NetBSD Foundation, Inc. 390618Stmm * All rights reserved. 490618Stmm * 590618Stmm * This code is derived from software contributed to The NetBSD Foundation 690618Stmm * by Paul Kranenburg. 790618Stmm * 890618Stmm * Redistribution and use in source and binary forms, with or without 990618Stmm * modification, are permitted provided that the following conditions 1090618Stmm * are met: 1190618Stmm * 1. Redistributions of source code must retain the above copyright 1290618Stmm * notice, this list of conditions and the following disclaimer. 1390618Stmm * 2. Redistributions in binary form must reproduce the above copyright 1490618Stmm * notice, this list of conditions and the following disclaimer in the 1590618Stmm * documentation and/or other materials provided with the distribution. 1690618Stmm * 3. All advertising materials mentioning features or use of this software 1790618Stmm * must display the following acknowledgement: 1890618Stmm * This product includes software developed by the NetBSD 1990618Stmm * Foundation, Inc. and its contributors. 2090618Stmm * 4. Neither the name of The NetBSD Foundation nor the names of its 2190618Stmm * contributors may be used to endorse or promote products derived 2290618Stmm * from this software without specific prior written permission. 2390618Stmm * 2490618Stmm * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 2590618Stmm * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 2690618Stmm * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 2790618Stmm * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 2890618Stmm * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2990618Stmm * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 3090618Stmm * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 3190618Stmm * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 3290618Stmm * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3390618Stmm * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3490618Stmm * POSSIBILITY OF SUCH DAMAGE. 3590618Stmm */ 3690618Stmm/* 3790618Stmm * Copyright (c) 1992, 1993 3890618Stmm * The Regents of the University of California. All rights reserved. 3990618Stmm * 4090618Stmm * This software was developed by the Computer Systems Engineering group 4190618Stmm * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 4290618Stmm * contributed to Berkeley. 4390618Stmm * 4490618Stmm * All advertising materials mentioning features or use of this software 4590618Stmm * must display the following acknowledgement: 4690618Stmm * This product includes software developed by the University of 4790618Stmm * California, Lawrence Berkeley Laboratory. 4890618Stmm * 4990618Stmm * Redistribution and use in source and binary forms, with or without 5090618Stmm * modification, are permitted provided that the following conditions 5190618Stmm * are met: 5290618Stmm * 1. Redistributions of source code must retain the above copyright 5390618Stmm * notice, this list of conditions and the following disclaimer. 5490618Stmm * 2. Redistributions in binary form must reproduce the above copyright 5590618Stmm * notice, this list of conditions and the following disclaimer in the 5690618Stmm * documentation and/or other materials provided with the distribution. 5790618Stmm * 3. All advertising materials mentioning features or use of this software 5890618Stmm * must display the following acknowledgement: 5990618Stmm * This product includes software developed by the University of 6090618Stmm * California, Berkeley and its contributors. 6190618Stmm * 4. Neither the name of the University nor the names of its contributors 6290618Stmm * may be used to endorse or promote products derived from this software 6390618Stmm * without specific prior written permission. 6490618Stmm * 6590618Stmm * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 6690618Stmm * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 6790618Stmm * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 6890618Stmm * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 6990618Stmm * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 7090618Stmm * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 7190618Stmm * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 7290618Stmm * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 7390618Stmm * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 7490618Stmm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 7590618Stmm * SUCH DAMAGE. 7690618Stmm */ 7790618Stmm/* 7890618Stmm * Copyright (c) 1999 Eduardo Horvath 7990618Stmm * Copyright (c) 2002 by Thomas Moestl <tmm@FreeBSD.org>. 8090618Stmm * All rights reserved. 8190618Stmm * 8290618Stmm * Redistribution and use in source and binary forms, with or without 8390618Stmm * modification, are permitted provided that the following conditions 8490618Stmm * are met: 8590618Stmm * 1. Redistributions of source code must retain the above copyright 8690618Stmm * notice, this list of conditions and the following disclaimer. 8790618Stmm * 8890618Stmm * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 8990618Stmm * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 9090618Stmm * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 9190618Stmm * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 9290618Stmm * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 9390618Stmm * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 9490618Stmm * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 9590618Stmm * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 9690618Stmm * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 9790618Stmm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 9890618Stmm * SUCH DAMAGE. 9990618Stmm * 10090618Stmm * from: @(#)sbus.c 8.1 (Berkeley) 6/11/93 10190618Stmm * from: NetBSD: sbus.c,v 1.46 2001/10/07 20:30:41 eeh Exp 10290618Stmm * 10390618Stmm * $FreeBSD: head/sys/sparc64/sbus/sbus.c 100188 2002-07-16 18:17:03Z tmm $ 10490618Stmm */ 10590618Stmm 10690618Stmm/* 10790618Stmm * Sbus support. 10890618Stmm */ 10990618Stmm#include <sys/param.h> 11090618Stmm#include <sys/systm.h> 11190618Stmm#include <sys/bus.h> 11290618Stmm#include <sys/kernel.h> 11390618Stmm#include <sys/malloc.h> 11490618Stmm#include <sys/reboot.h> 11590618Stmm 11690618Stmm#include <ofw/openfirm.h> 11790618Stmm 11890618Stmm#include <machine/bus.h> 11990618Stmm#include <machine/iommureg.h> 12090618Stmm#include <machine/bus_common.h> 12190618Stmm#include <machine/frame.h> 12290618Stmm#include <machine/intr_machdep.h> 12390618Stmm#include <machine/nexusvar.h> 12490618Stmm#include <machine/ofw_upa.h> 12590618Stmm#include <machine/resource.h> 12690618Stmm 12790618Stmm#include <sys/rman.h> 12890618Stmm 12990618Stmm#include <machine/iommuvar.h> 13090618Stmm 13190618Stmm#include <sparc64/sbus/ofw_sbus.h> 13290618Stmm#include <sparc64/sbus/sbusreg.h> 13390618Stmm#include <sparc64/sbus/sbusvar.h> 13490618Stmm 13590618Stmm 13690618Stmm#ifdef DEBUG 13790618Stmm#define SDB_DVMA 0x1 13890618Stmm#define SDB_INTR 0x2 13990618Stmmint sbus_debug = 0; 14090618Stmm#define DPRINTF(l, s) do { if (sbus_debug & l) printf s; } while (0) 14190618Stmm#else 14290618Stmm#define DPRINTF(l, s) 14390618Stmm#endif 14490618Stmm 14590618Stmmstruct sbus_devinfo { 14690618Stmm int sdi_burstsz; 14790618Stmm char *sdi_compat; 14890618Stmm char *sdi_name; /* PROM name */ 14990618Stmm phandle_t sdi_node; /* PROM node */ 15090618Stmm int sdi_slot; 15190618Stmm char *sdi_type; /* PROM name */ 15290618Stmm 15390618Stmm struct resource_list sdi_rl; 15490618Stmm}; 15590618Stmm 15690618Stmm/* Range descriptor, allocated for each sc_range. */ 15790618Stmmstruct sbus_rd { 15890618Stmm bus_addr_t rd_poffset; 15990618Stmm bus_addr_t rd_pend; 16090618Stmm int rd_slot; 16190618Stmm bus_addr_t rd_coffset; 16290618Stmm bus_addr_t rd_cend; 16390618Stmm struct rman rd_rman; 16490618Stmm bus_space_handle_t rd_bushandle; 16590618Stmm struct resource *rd_res; 16690618Stmm}; 16790618Stmm 16890618Stmmstruct sbus_softc { 16990618Stmm bus_space_tag_t sc_bustag; 17090618Stmm bus_space_handle_t sc_bushandle; 17190618Stmm bus_dma_tag_t sc_dmatag; 17290618Stmm bus_dma_tag_t sc_cdmatag; 17390618Stmm bus_space_tag_t sc_cbustag; 17490618Stmm int sc_clockfreq; /* clock frequency (in Hz) */ 17590618Stmm struct upa_regs *sc_reg; 17690618Stmm int sc_nreg; 17790618Stmm int sc_nrange; 17890618Stmm struct sbus_rd *sc_rd; 17990618Stmm int sc_burst; /* burst transfer sizes supported */ 18090618Stmm int *sc_intr_compat;/* `intr' property to sbus compat */ 18190618Stmm 18290618Stmm struct resource *sc_sysio_res; 18390618Stmm int sc_ign; /* Interrupt group number for this sysio */ 18490618Stmm struct iommu_state sc_is; /* IOMMU state, see iommureg.h */ 18590618Stmm 18690618Stmm struct resource *sc_ot_ires; 18790618Stmm void *sc_ot_ihand; 18890618Stmm struct resource *sc_pf_ires; 18990618Stmm void *sc_pf_ihand; 19090618Stmm}; 19190618Stmm 19290618Stmmstruct sbus_clr { 19390618Stmm struct sbus_softc *scl_sc; 19490618Stmm bus_addr_t scl_clr; /* clear register */ 19590618Stmm driver_intr_t *scl_handler; /* handler to call */ 19690618Stmm void *scl_arg; /* argument for the handler */ 19790618Stmm void *scl_cookie; /* interrupt cookie of parent bus */ 19890618Stmm}; 19990618Stmm 20090618Stmm#define SYSIO_READ8(sc, off) \ 20190618Stmm bus_space_read_8((sc)->sc_bustag, (sc)->sc_bushandle, (off)) 20290618Stmm#define SYSIO_WRITE8(sc, off, v) \ 20390618Stmm bus_space_write_8((sc)->sc_bustag, (sc)->sc_bushandle, (off), (v)) 20490618Stmm 20590618Stmmstatic int sbus_probe(device_t dev); 20690618Stmmstatic int sbus_print_child(device_t dev, device_t child); 20790618Stmmstatic void sbus_probe_nomatch(device_t dev, device_t child); 20890618Stmmstatic int sbus_read_ivar(device_t, device_t, int, u_long *); 20990618Stmmstatic struct resource_list *sbus_get_resource_list(device_t dev, 21090618Stmm device_t child); 21190618Stmmstatic int sbus_setup_intr(device_t, device_t, struct resource *, int, 21290618Stmm driver_intr_t *, void *, void **); 21390618Stmmstatic int sbus_teardown_intr(device_t, device_t, struct resource *, void *); 21490618Stmmstatic struct resource *sbus_alloc_resource(device_t, device_t, int, int *, 21590618Stmm u_long, u_long, u_long, u_int); 21690618Stmmstatic int sbus_activate_resource(device_t, device_t, int, int, 21790618Stmm struct resource *); 21890618Stmmstatic int sbus_deactivate_resource(device_t, device_t, int, int, 21990618Stmm struct resource *); 22090618Stmmstatic int sbus_release_resource(device_t, device_t, int, int, 22190618Stmm struct resource *); 22290618Stmm 22390618Stmmstatic struct sbus_devinfo * sbus_setup_dinfo(struct sbus_softc *sc, 22490618Stmm phandle_t node, char *name); 22590618Stmmstatic void sbus_destroy_dinfo(struct sbus_devinfo *dinfo); 22690618Stmmstatic void sbus_intr_stub(void *); 22790618Stmmstatic bus_space_tag_t sbus_alloc_bustag(struct sbus_softc *); 22890618Stmmstatic void sbus_overtemp(void *); 22990618Stmmstatic void sbus_pwrfail(void *); 23090618Stmm 23190618Stmm/* 23290618Stmm * DVMA routines 23390618Stmm */ 23493070Stmmstatic int sbus_dmamap_create(bus_dma_tag_t, bus_dma_tag_t, int, 23593070Stmm bus_dmamap_t *); 23693070Stmmstatic int sbus_dmamap_destroy(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 23793070Stmmstatic int sbus_dmamap_load(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, void *, 23893070Stmm bus_size_t, bus_dmamap_callback_t *, void *, int); 23993070Stmmstatic void sbus_dmamap_unload(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t); 24093070Stmmstatic void sbus_dmamap_sync(bus_dma_tag_t, bus_dma_tag_t, bus_dmamap_t, 24193070Stmm bus_dmasync_op_t); 24293070Stmmstatic int sbus_dmamem_alloc(bus_dma_tag_t, bus_dma_tag_t, void **, int, 24393070Stmm bus_dmamap_t *); 24493070Stmmstatic void sbus_dmamem_free(bus_dma_tag_t, bus_dma_tag_t, void *, 24593070Stmm bus_dmamap_t); 24690618Stmm 24790618Stmmstatic device_method_t sbus_methods[] = { 24890618Stmm /* Device interface */ 24990618Stmm DEVMETHOD(device_probe, sbus_probe), 25090618Stmm DEVMETHOD(device_attach, bus_generic_attach), 25190618Stmm 25290618Stmm /* Bus interface */ 25390618Stmm DEVMETHOD(bus_print_child, sbus_print_child), 25490618Stmm DEVMETHOD(bus_probe_nomatch, sbus_probe_nomatch), 25590618Stmm DEVMETHOD(bus_read_ivar, sbus_read_ivar), 25690618Stmm DEVMETHOD(bus_setup_intr, sbus_setup_intr), 25790618Stmm DEVMETHOD(bus_teardown_intr, sbus_teardown_intr), 25890618Stmm DEVMETHOD(bus_alloc_resource, sbus_alloc_resource), 25990618Stmm DEVMETHOD(bus_activate_resource, sbus_activate_resource), 26090618Stmm DEVMETHOD(bus_deactivate_resource, sbus_deactivate_resource), 26190618Stmm DEVMETHOD(bus_release_resource, sbus_release_resource), 26290618Stmm DEVMETHOD(bus_get_resource_list, sbus_get_resource_list), 26390618Stmm DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 26490618Stmm 26590618Stmm { 0, 0 } 26690618Stmm}; 26790618Stmm 26890618Stmmstatic driver_t sbus_driver = { 26990618Stmm "sbus", 27090618Stmm sbus_methods, 27190618Stmm sizeof(struct sbus_softc), 27290618Stmm}; 27390618Stmm 27490618Stmmstatic devclass_t sbus_devclass; 27590618Stmm 27690618StmmDRIVER_MODULE(sbus, nexus, sbus_driver, sbus_devclass, 0, 0); 27790618Stmm 27890618Stmm/* 27990618Stmm * This value is or'ed into the attach args' interrupt level cookie 28090618Stmm * if the interrupt level comes from an `intr' property, i.e. it is 28190618Stmm * not an Sbus interrupt level. 28290618Stmm */ 28390618Stmm#define SBUS_INTR_COMPAT 0x80000000 28490618Stmm#define SBUS_MEM_SIZE 0x100000000 28590618Stmm#define OFW_SBUS_TYPE "sbus" 28690618Stmm#define OFW_SBUS_NAME "sbus" 28790618Stmm 28890618Stmmstatic int 28990618Stmmsbus_probe(device_t dev) 29090618Stmm{ 29190618Stmm struct sbus_softc *sc = device_get_softc(dev); 29290618Stmm struct sbus_devinfo *sdi; 29390618Stmm struct sbus_ranges *range; 29490618Stmm struct resource *res; 29590618Stmm device_t cdev; 29690618Stmm bus_addr_t phys; 29790618Stmm bus_size_t size; 29890618Stmm char *name, *cname, *t; 29990618Stmm phandle_t child, node = nexus_get_node(dev); 30090618Stmm u_int64_t mr; 30190618Stmm int intr, clock, rid, vec, i; 30290618Stmm 30390618Stmm t = nexus_get_device_type(dev); 30490618Stmm if (((t == NULL || strcmp(t, OFW_SBUS_TYPE) != 0)) && 30590618Stmm strcmp(nexus_get_name(dev), OFW_SBUS_NAME) != 0) 30690618Stmm return (ENXIO); 30790618Stmm device_set_desc(dev, "U2S UPA-SBus bridge"); 30890618Stmm 30990618Stmm if ((sc->sc_nreg = OF_getprop_alloc(node, "reg", sizeof(*sc->sc_reg), 31090618Stmm (void **)&sc->sc_reg)) == -1) { 31190618Stmm panic("sbus_probe: error getting reg property"); 31290618Stmm } 31390618Stmm if (sc->sc_nreg < 1) 31490618Stmm panic("sbus_probe: bogus properties"); 31590618Stmm phys = UPA_REG_PHYS(&sc->sc_reg[0]); 31690618Stmm size = UPA_REG_SIZE(&sc->sc_reg[0]); 31790618Stmm rid = 0; 31890618Stmm sc->sc_sysio_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, phys, 31990618Stmm phys + size - 1, size, RF_ACTIVE); 32090618Stmm if (sc->sc_sysio_res == NULL || 32190618Stmm rman_get_start(sc->sc_sysio_res) != phys) 32290618Stmm panic("sbus_probe: can't allocate device memory"); 32390618Stmm sc->sc_bustag = rman_get_bustag(sc->sc_sysio_res); 32490618Stmm sc->sc_bushandle = rman_get_bushandle(sc->sc_sysio_res); 32590618Stmm 32690618Stmm if (OF_getprop(node, "interrupts", &intr, sizeof(intr)) == -1) 32790618Stmm panic("sbus_probe: cannot get IGN"); 32890618Stmm sc->sc_ign = intr & INTMAP_IGN; /* Find interrupt group no */ 32990618Stmm sc->sc_cbustag = sbus_alloc_bustag(sc); 33090618Stmm 33190618Stmm /* 33290618Stmm * Record clock frequency for synchronous SCSI. 33390618Stmm * IS THIS THE CORRECT DEFAULT?? 33490618Stmm */ 33590618Stmm if (OF_getprop(node, "clock-frequency", &clock, sizeof(clock)) == -1) 33690618Stmm clock = 25000000; 33790618Stmm sc->sc_clockfreq = clock; 33890618Stmm clock /= 1000; 33990618Stmm device_printf(dev, "clock %d.%03d MHz\n", clock / 1000, clock % 1000); 34090618Stmm 34190618Stmm sc->sc_dmatag = nexus_get_dmatag(dev); 34290618Stmm if (bus_dma_tag_create(sc->sc_dmatag, 8, 1, 0, 0x3ffffffff, NULL, NULL, 34390618Stmm 0x3ffffffff, 0xff, 0xffffffff, 0, &sc->sc_cdmatag) != 0) 34490618Stmm panic("bus_dma_tag_create failed"); 34590618Stmm /* Customize the tag */ 34690618Stmm sc->sc_cdmatag->cookie = sc; 34790618Stmm sc->sc_cdmatag->dmamap_create = sbus_dmamap_create; 34890618Stmm sc->sc_cdmatag->dmamap_destroy = sbus_dmamap_destroy; 34990618Stmm sc->sc_cdmatag->dmamap_load = sbus_dmamap_load; 35090618Stmm sc->sc_cdmatag->dmamap_unload = sbus_dmamap_unload; 35190618Stmm sc->sc_cdmatag->dmamap_sync = sbus_dmamap_sync; 35290618Stmm sc->sc_cdmatag->dmamem_alloc = sbus_dmamem_alloc; 35390618Stmm sc->sc_cdmatag->dmamem_free = sbus_dmamem_free; 35490618Stmm /* XXX: register as root dma tag (kluge). */ 35590618Stmm sparc64_root_dma_tag = sc->sc_cdmatag; 35690618Stmm 35790618Stmm /* 35890618Stmm * Collect address translations from the OBP. 35990618Stmm */ 36090618Stmm if ((sc->sc_nrange = OF_getprop_alloc(node, "ranges", 36190618Stmm sizeof(*range), (void **)&range)) == -1) { 36290618Stmm panic("%s: error getting ranges property", 36390618Stmm device_get_name(dev)); 36490618Stmm } 36590618Stmm sc->sc_rd = (struct sbus_rd *)malloc(sizeof(*sc->sc_rd) * sc->sc_nrange, 36690618Stmm M_DEVBUF, M_NOWAIT); 36790618Stmm if (sc->sc_rd == NULL) 36890618Stmm panic("sbus_probe: could not allocate rmans"); 36990618Stmm /* 37090618Stmm * Preallocate all space that the SBus bridge decodes, so that nothing 37190618Stmm * else gets in the way; set up rmans etc. 37290618Stmm */ 37390618Stmm for (i = 0; i < sc->sc_nrange; i++) { 37490618Stmm phys = range[i].poffset | ((bus_addr_t)range[i].pspace << 32); 37590618Stmm size = range[i].size; 37690618Stmm sc->sc_rd[i].rd_slot = range[i].cspace; 37790618Stmm sc->sc_rd[i].rd_coffset = range[i].coffset; 37890618Stmm sc->sc_rd[i].rd_cend = sc->sc_rd[i].rd_coffset + size; 37990618Stmm rid = 0; 38090618Stmm if ((res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, phys, 38190618Stmm phys + size - 1, size, RF_ACTIVE)) == NULL) 38290618Stmm panic("sbus_probe: could not allocate decoded range"); 38390618Stmm sc->sc_rd[i].rd_bushandle = rman_get_bushandle(res); 38490618Stmm sc->sc_rd[i].rd_rman.rm_type = RMAN_ARRAY; 38590618Stmm sc->sc_rd[i].rd_rman.rm_descr = "SBus Device Memory"; 38690618Stmm if (rman_init(&sc->sc_rd[i].rd_rman) != 0 || 38790618Stmm rman_manage_region(&sc->sc_rd[i].rd_rman, 0, size) != 0) 38890618Stmm panic("psycho_probe: failed to set up memory rman"); 38990618Stmm sc->sc_rd[i].rd_poffset = phys; 39090618Stmm sc->sc_rd[i].rd_pend = phys + size; 39190618Stmm sc->sc_rd[i].rd_res = res; 39290618Stmm } 39390618Stmm free(range, M_OFWPROP); 39490618Stmm 39590618Stmm /* 39690618Stmm * Get the SBus burst transfer size if burst transfers are supported. 39790618Stmm * XXX: is the default correct? 39890618Stmm */ 39990618Stmm if (OF_getprop(node, "burst-sizes", &sc->sc_burst, 40090618Stmm sizeof(sc->sc_burst)) == -1 || sc->sc_burst == 0) 40190618Stmm sc->sc_burst = SBUS_BURST_DEF; 40290618Stmm 40390618Stmm /* initalise the IOMMU */ 40490618Stmm 40590618Stmm /* punch in our copies */ 40690618Stmm sc->sc_is.is_bustag = sc->sc_bustag; 40790618Stmm sc->sc_is.is_bushandle = sc->sc_bushandle; 40890618Stmm sc->sc_is.is_iommu = SBR_IOMMU; 40990618Stmm sc->sc_is.is_dtag = SBR_IOMMU_TLB_TAG_DIAG; 41090618Stmm sc->sc_is.is_ddram = SBR_IOMMU_TLB_DATA_DIAG; 41190618Stmm sc->sc_is.is_dqueue = SBR_IOMMU_QUEUE_DIAG; 41290618Stmm sc->sc_is.is_dva = SBR_IOMMU_SVADIAG; 41390618Stmm sc->sc_is.is_dtcmp = 0; 41490618Stmm sc->sc_is.is_sb[0] = SBR_STRBUF; 41590618Stmm sc->sc_is.is_sb[1] = NULL; 41690618Stmm 41790618Stmm /* give us a nice name.. */ 41890618Stmm name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 41990618Stmm if (name == 0) 42090618Stmm panic("sbus_probe: couldn't malloc iommu name"); 42190618Stmm snprintf(name, 32, "%s dvma", device_get_name(dev)); 42290618Stmm 423100188Stmm /* 424100188Stmm * Note: the SBus IOMMU ignores the high bits of an address, so a NULL 425100188Stmm * DMA pointer will be translated by the first page of the IOTSB. 426100188Stmm * To detect bugs we'll allocate and ignore the first entry. 427100188Stmm */ 428100188Stmm iommu_init(name, &sc->sc_is, 0, -1, 1); 42990618Stmm 43090618Stmm /* Enable the over-temperature and power-fail intrrupts. */ 43190618Stmm rid = 0; 43290618Stmm mr = SYSIO_READ8(sc, SBR_THERM_INT_MAP); 43390618Stmm vec = INTVEC(mr); 43490618Stmm if ((sc->sc_ot_ires = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, vec, 43590618Stmm vec, 1, RF_ACTIVE)) == NULL) 43690618Stmm panic("sbus_probe: failed to get temperature interrupt"); 43790618Stmm bus_setup_intr(dev, sc->sc_ot_ires, INTR_TYPE_MISC | INTR_FAST, 43890618Stmm sbus_overtemp, sc, &sc->sc_ot_ihand); 43990618Stmm SYSIO_WRITE8(sc, SBR_THERM_INT_MAP, mr | INTMAP_V); 44090618Stmm rid = 0; 44190618Stmm mr = SYSIO_READ8(sc, SBR_POWER_INT_MAP); 44290618Stmm vec = INTVEC(mr); 44390618Stmm if ((sc->sc_pf_ires = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, vec, 44490618Stmm vec, 1, RF_ACTIVE)) == NULL) 44590618Stmm panic("sbus_probe: failed to get power fail interrupt"); 44690618Stmm bus_setup_intr(dev, sc->sc_pf_ires, INTR_TYPE_MISC | INTR_FAST, 44790618Stmm sbus_pwrfail, sc, &sc->sc_pf_ihand); 44890618Stmm SYSIO_WRITE8(sc, SBR_POWER_INT_MAP, mr | INTMAP_V); 44990618Stmm 45090618Stmm /* Initialize the counter-timer. */ 45190618Stmm sparc64_counter_init(sc->sc_bustag, sc->sc_bushandle, SBR_TC0); 45290618Stmm 45390618Stmm /* 45490618Stmm * Loop through ROM children, fixing any relative addresses 45590618Stmm * and then configuring each device. 45690618Stmm * `specials' is an array of device names that are treated 45790618Stmm * specially: 45890618Stmm */ 45990618Stmm for (child = OF_child(node); child != 0; child = OF_peer(child)) { 46090618Stmm if ((OF_getprop_alloc(child, "name", 1, (void **)&cname)) == -1) 46190618Stmm continue; 46290618Stmm 46390618Stmm if ((sdi = sbus_setup_dinfo(sc, child, cname)) == NULL) { 46490618Stmm device_printf(dev, "<%s>: incomplete\n", cname); 46590618Stmm free(cname, M_OFWPROP); 46690618Stmm continue; 46790618Stmm } 46890618Stmm if ((cdev = device_add_child(dev, NULL, -1)) == NULL) 46990618Stmm panic("sbus_probe: device_add_child failed"); 47090618Stmm device_set_ivars(cdev, sdi); 47190618Stmm } 47290618Stmm return (0); 47390618Stmm} 47490618Stmm 47590618Stmmstatic struct sbus_devinfo * 47690618Stmmsbus_setup_dinfo(struct sbus_softc *sc, phandle_t node, char *name) 47790618Stmm{ 47890618Stmm struct sbus_devinfo *sdi; 47990618Stmm struct sbus_regs *reg; 48090618Stmm u_int32_t base, iv, *intr; 48190618Stmm int i, nreg, nintr, slot, rslot; 48290618Stmm 48390618Stmm sdi = malloc(sizeof(*sdi), M_DEVBUF, M_ZERO | M_WAITOK); 48490618Stmm if (sdi == NULL) 48590618Stmm return (NULL); 48690618Stmm resource_list_init(&sdi->sdi_rl); 48790618Stmm sdi->sdi_name = name; 48890618Stmm sdi->sdi_node = node; 48990618Stmm OF_getprop_alloc(node, "compat", 1, (void **)&sdi->sdi_compat); 49090618Stmm OF_getprop_alloc(node, "device_type", 1, (void **)&sdi->sdi_type); 49190618Stmm slot = -1; 49290618Stmm nreg = OF_getprop_alloc(node, "reg", sizeof(*reg), (void **)®); 49390618Stmm if (nreg == -1) { 49490618Stmm if (sdi->sdi_type == NULL || 49590618Stmm strcmp(sdi->sdi_type, "hierarchical") != 0) { 49690618Stmm sbus_destroy_dinfo(sdi); 49790618Stmm return (NULL); 49890618Stmm } 49990618Stmm } else { 50090618Stmm for (i = 0; i < nreg; i++) { 50190618Stmm base = reg[i].sbr_offset; 50290618Stmm if (SBUS_ABS(base)) { 50390618Stmm rslot = SBUS_ABS_TO_SLOT(base); 50490618Stmm base = SBUS_ABS_TO_OFFSET(base); 50590618Stmm } else 50690618Stmm rslot = reg[i].sbr_slot; 50790618Stmm if (slot != -1 && slot != rslot) 50890618Stmm panic("sbus_setup_dinfo: multiple slots"); 50990618Stmm slot = rslot; 51090618Stmm 51190618Stmm resource_list_add(&sdi->sdi_rl, SYS_RES_MEMORY, i, 51290618Stmm base, base + reg[i].sbr_size, reg[i].sbr_size); 51390618Stmm } 51490618Stmm free(reg, M_OFWPROP); 51590618Stmm } 51690618Stmm sdi->sdi_slot = slot; 51790618Stmm 51890618Stmm /* 51990618Stmm * The `interrupts' property contains the Sbus interrupt level. 52090618Stmm */ 52190618Stmm nintr = OF_getprop_alloc(node, "interrupts", sizeof(*intr), (void **)&intr); 52290618Stmm if (nintr != -1) { 52390618Stmm for (i = 0; i < nintr; i++) { 52490618Stmm iv = intr[i]; 52590618Stmm /* 52690618Stmm * Sbus card devices need the slot number encoded into 52790618Stmm * the vector as this is generally not done. 52890618Stmm */ 52990618Stmm if ((iv & INTMAP_OBIO) == 0) 53090618Stmm iv |= slot << 3; 53190618Stmm /* Set the ign as appropriate. */ 53290618Stmm iv |= sc->sc_ign; 53390618Stmm resource_list_add(&sdi->sdi_rl, SYS_RES_IRQ, i, 53490618Stmm iv, iv, 1); 53590618Stmm } 53690618Stmm free(intr, M_OFWPROP); 53790618Stmm } 53890618Stmm if (OF_getprop(node, "burst-sizes", &sdi->sdi_burstsz, 53990618Stmm sizeof(sdi->sdi_burstsz)) == -1) 54090618Stmm sdi->sdi_burstsz = sc->sc_burst; 54190618Stmm else 54290618Stmm sdi->sdi_burstsz &= sc->sc_burst; 54390618Stmm 54490618Stmm return (sdi); 54590618Stmm} 54690618Stmm 54790618Stmm/* Free everything except sdi_name, which is handled separately. */ 54890618Stmmstatic void 54990618Stmmsbus_destroy_dinfo(struct sbus_devinfo *dinfo) 55090618Stmm{ 55190618Stmm 55290618Stmm resource_list_free(&dinfo->sdi_rl); 55390618Stmm if (dinfo->sdi_compat != NULL) 55490618Stmm free(dinfo->sdi_compat, M_OFWPROP); 55590618Stmm if (dinfo->sdi_type != NULL) 55690618Stmm free(dinfo->sdi_type, M_OFWPROP); 55790618Stmm free(dinfo, M_DEVBUF); 55890618Stmm} 55990618Stmm 56090618Stmmstatic int 56190618Stmmsbus_print_child(device_t dev, device_t child) 56290618Stmm{ 56390618Stmm struct sbus_devinfo *dinfo; 56490618Stmm struct resource_list *rl; 56590618Stmm int rv; 56690618Stmm 56790618Stmm dinfo = device_get_ivars(child); 56890618Stmm rl = &dinfo->sdi_rl; 56990618Stmm rv = bus_print_child_header(dev, child); 57090618Stmm rv += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 57190618Stmm rv += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 57290618Stmm rv += bus_print_child_footer(dev, child); 57390618Stmm return (rv); 57490618Stmm} 57590618Stmm 57690618Stmmstatic void 57790618Stmmsbus_probe_nomatch(device_t dev, device_t child) 57890618Stmm{ 57990618Stmm char *name; 58090618Stmm char *type; 58190618Stmm 58290618Stmm if (BUS_READ_IVAR(dev, child, SBUS_IVAR_NAME, 58390618Stmm (uintptr_t *)&name) != 0 || 58490618Stmm BUS_READ_IVAR(dev, child, SBUS_IVAR_DEVICE_TYPE, 58590618Stmm (uintptr_t *)&type) != 0) 58690618Stmm return; 58790618Stmm 58890618Stmm if (type == NULL) 58990618Stmm type = "(unknown)"; 59090618Stmm device_printf(dev, "<%s>, type %s (no driver attached)\n", 59190618Stmm name, type); 59290618Stmm} 59390618Stmm 59490618Stmmstatic int 59590618Stmmsbus_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 59690618Stmm{ 59790618Stmm struct sbus_softc *sc = device_get_softc(dev); 59890618Stmm struct sbus_devinfo *dinfo; 59990618Stmm 60090618Stmm if ((dinfo = device_get_ivars(child)) == NULL) 60190618Stmm return (ENOENT); 60290618Stmm switch (which) { 60390618Stmm case SBUS_IVAR_BURSTSZ: 60490618Stmm *result = dinfo->sdi_burstsz; 60590618Stmm break; 60690618Stmm case SBUS_IVAR_CLOCKFREQ: 60790618Stmm *result = sc->sc_clockfreq; 60890618Stmm break; 60990618Stmm case SBUS_IVAR_COMPAT: 61090618Stmm *result = (uintptr_t)dinfo->sdi_compat; 61190618Stmm break; 61290618Stmm case SBUS_IVAR_NAME: 61390618Stmm *result = (uintptr_t)dinfo->sdi_name; 61490618Stmm break; 61590618Stmm case SBUS_IVAR_NODE: 61690618Stmm *result = dinfo->sdi_node; 61790618Stmm break; 61890618Stmm case SBUS_IVAR_SLOT: 61990618Stmm *result = dinfo->sdi_slot; 62090618Stmm break; 62190618Stmm case SBUS_IVAR_DEVICE_TYPE: 62290618Stmm *result = (uintptr_t)dinfo->sdi_type; 62390618Stmm break; 62490618Stmm default: 62590618Stmm return (ENOENT); 62690618Stmm } 62790618Stmm return 0; 62890618Stmm} 62990618Stmm 63090618Stmmstatic struct resource_list * 63190618Stmmsbus_get_resource_list(device_t dev, device_t child) 63290618Stmm{ 63390618Stmm struct sbus_devinfo *sdi; 63490618Stmm 63590618Stmm sdi = device_get_ivars(child); 63690618Stmm return (&sdi->sdi_rl); 63790618Stmm} 63890618Stmm 63990618Stmm/* Write to the correct clr register, and call the actual handler. */ 64090618Stmmstatic void 64190618Stmmsbus_intr_stub(void *arg) 64290618Stmm{ 64390618Stmm struct sbus_clr *scl; 64490618Stmm 64590618Stmm scl = (struct sbus_clr *)arg; 64690618Stmm scl->scl_handler(scl->scl_arg); 64790618Stmm SYSIO_WRITE8(scl->scl_sc, scl->scl_clr, 0); 64890618Stmm} 64990618Stmm 65090618Stmmstatic int 65190618Stmmsbus_setup_intr(device_t dev, device_t child, 65290618Stmm struct resource *ires, int flags, driver_intr_t *intr, void *arg, 65390618Stmm void **cookiep) 65490618Stmm{ 65590618Stmm struct sbus_softc *sc; 65690618Stmm struct sbus_clr *scl; 65790618Stmm bus_addr_t intrmapptr, intrclrptr, intrptr; 65890618Stmm u_int64_t intrmap; 65990618Stmm u_int32_t inr, slot; 66090618Stmm int error, i; 66190618Stmm long vec = rman_get_start(ires); 66290618Stmm 66390618Stmm sc = (struct sbus_softc *)device_get_softc(dev); 66490618Stmm scl = (struct sbus_clr *)malloc(sizeof(*scl), M_DEVBUF, M_NOWAIT); 66590618Stmm if (scl == NULL) 66690618Stmm return (NULL); 66790618Stmm intrptr = intrmapptr = intrclrptr = 0; 66890618Stmm intrmap = 0; 66990618Stmm if ((vec & SBUS_INTR_COMPAT) == 0) { 67090618Stmm inr = INTVEC(vec); 67190618Stmm if ((inr & INTMAP_OBIO) == 0) { 67290618Stmm /* 67390618Stmm * We're in an SBUS slot, register the map and clear 67490618Stmm * intr registers. 67590618Stmm */ 67690618Stmm slot = INTSLOT(vec); 67790618Stmm 67890618Stmm intrmapptr = SBR_SLOT0_INT_MAP + slot * 8; 67990618Stmm intrclrptr = SBR_SLOT0_INT_CLR + inr * 8; 68090618Stmm /* Enable the interrupt, insert IGN. */ 68190618Stmm intrmap = inr | sc->sc_ign; 68290618Stmm } else { 68390618Stmm intrptr = SBR_SCSI_INT_MAP; 68490618Stmm /* Insert IGN */ 68590618Stmm inr |= sc->sc_ign; 68690618Stmm for (i = 0; intrptr <= SBR_RESERVED_INT_MAP && 68790618Stmm INTVEC(intrmap = SYSIO_READ8(sc, intrptr)) != 68890618Stmm INTVEC(inr); intrptr += 8, i++) 68990618Stmm ; 69090618Stmm if (INTVEC(intrmap) == INTVEC(inr)) { 69190618Stmm /* Register the map and clear intr registers */ 69290618Stmm intrmapptr = intrptr; 69390618Stmm intrclrptr = SBR_SCSI_INT_CLR + i * 8; 69490618Stmm /* Enable the interrupt */ 69590618Stmm } else 69690618Stmm panic("sbus_setup_intr: IRQ not found!"); 69790618Stmm } 69890618Stmm } else 69990618Stmm panic("sbus_setup_intr: XXX: compat"); 70090618Stmm 70190618Stmm scl->scl_sc = sc; 70290618Stmm scl->scl_arg = arg; 70390618Stmm scl->scl_handler = intr; 70490618Stmm scl->scl_clr = intrclrptr; 70590618Stmm /* Disable the interrupt while we fiddle with it */ 70690618Stmm if (intrmapptr != 0) 70790618Stmm SYSIO_WRITE8(sc, intrmapptr, intrmap); 70890618Stmm error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 70990618Stmm sbus_intr_stub, scl, cookiep); 71090618Stmm if (error != 0) { 71190618Stmm free(scl, M_DEVBUF); 71290618Stmm return (error); 71390618Stmm } 71490618Stmm scl->scl_cookie = *cookiep; 71590618Stmm *cookiep = scl; 71690618Stmm 71790618Stmm /* 71890618Stmm * Clear the interrupt, it might have been triggered before it was 71990618Stmm * set up. 72090618Stmm */ 72190618Stmm if (intrclrptr != 0) 72290618Stmm SYSIO_WRITE8(sc, intrclrptr, 0); 72390618Stmm /* 72490618Stmm * Enable the interrupt now we have the handler installed. 72590618Stmm * Read the current value as we can't change it besides the 72690618Stmm * valid bit so so make sure only this bit is changed. 72790618Stmm */ 72890618Stmm if (intrmapptr != NULL) 72990618Stmm SYSIO_WRITE8(sc, intrmapptr, intrmap | INTMAP_V); 73090618Stmm return (error); 73190618Stmm} 73290618Stmm 73390618Stmmstatic int 73490618Stmmsbus_teardown_intr(device_t dev, device_t child, 73590618Stmm struct resource *vec, void *cookie) 73690618Stmm{ 73790618Stmm struct sbus_clr *scl; 73890618Stmm int error; 73990618Stmm 74090618Stmm scl = (struct sbus_clr *)cookie; 74190618Stmm error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, 74290618Stmm scl->scl_cookie); 74390618Stmm /* 74490618Stmm * Don't disable the interrupt for now, so that stray interupts get 74590618Stmm * detected... 74690618Stmm */ 74790618Stmm if (error != 0) 74890618Stmm free(scl, M_DEVBUF); 74990618Stmm return (error); 75090618Stmm} 75190618Stmm 75290618Stmmstatic struct resource * 75390618Stmmsbus_alloc_resource(device_t bus, device_t child, int type, int *rid, 75490618Stmm u_long start, u_long end, u_long count, u_int flags) 75590618Stmm{ 75690618Stmm struct sbus_softc *sc; 75790618Stmm struct sbus_devinfo *sdi; 75890618Stmm struct rman *rm; 75990618Stmm struct resource *rv; 76090618Stmm struct resource_list *rl; 76190618Stmm struct resource_list_entry *rle; 76290618Stmm bus_space_handle_t bh; 76390618Stmm bus_addr_t toffs; 76490618Stmm bus_size_t tend; 76590618Stmm int i; 76690618Stmm int isdefault = (start == 0UL && end == ~0UL); 76790618Stmm int needactivate = flags & RF_ACTIVE; 76890618Stmm 76990618Stmm sc = (struct sbus_softc *)device_get_softc(bus); 77090618Stmm sdi = device_get_ivars(child); 77190618Stmm rl = &sdi->sdi_rl; 77290618Stmm rle = resource_list_find(rl, type, *rid); 77390618Stmm if (rle == NULL) 77490618Stmm return (NULL); 77590618Stmm if (rle->res != NULL) 77690618Stmm panic("sbus_alloc_resource: resource entry is busy"); 77790618Stmm if (isdefault) { 77890618Stmm start = rle->start; 77990618Stmm count = ulmax(count, rle->count); 78090618Stmm end = ulmax(rle->end, start + count - 1); 78190618Stmm } 78290618Stmm switch (type) { 78390618Stmm case SYS_RES_IRQ: 78490618Stmm rv = bus_alloc_resource(bus, type, rid, start, end, 78590618Stmm count, flags); 78690618Stmm if (rv == NULL) 78790618Stmm return (NULL); 78890618Stmm break; 78990618Stmm case SYS_RES_MEMORY: 79090618Stmm rm = NULL; 79190618Stmm bh = toffs = tend = 0; 79290618Stmm for (i = 0; i < sc->sc_nrange; i++) { 79390618Stmm if (sc->sc_rd[i].rd_slot != sdi->sdi_slot || 79490618Stmm start < sc->sc_rd[i].rd_coffset || 79590618Stmm start > sc->sc_rd[i].rd_cend) 79690618Stmm continue; 79790618Stmm /* Disallow cross-range allocations. */ 79890618Stmm if (end > sc->sc_rd[i].rd_cend) 79990618Stmm return (NULL); 80090618Stmm /* We've found the connection to the parent bus */ 80190618Stmm toffs = start - sc->sc_rd[i].rd_coffset; 80290618Stmm tend = end - sc->sc_rd[i].rd_coffset; 80390618Stmm rm = &sc->sc_rd[i].rd_rman; 80490618Stmm bh = sc->sc_rd[i].rd_bushandle; 80590618Stmm } 80690618Stmm if (toffs == NULL) 80790618Stmm return (NULL); 80890618Stmm flags &= ~RF_ACTIVE; 80990618Stmm rv = rman_reserve_resource(rm, toffs, tend, count, flags, 81090618Stmm child); 81190618Stmm if (rv == NULL) 81290618Stmm return (NULL); 81390618Stmm rman_set_bustag(rv, sc->sc_cbustag); 81490618Stmm rman_set_bushandle(rv, bh + rman_get_start(rv)); 81590618Stmm if (needactivate) { 81690618Stmm if (bus_activate_resource(child, type, *rid, rv)) { 81790618Stmm rman_release_resource(rv); 81890618Stmm return (NULL); 81990618Stmm } 82090618Stmm } 82190618Stmm break; 82290618Stmm default: 82390618Stmm return (NULL); 82490618Stmm } 82590618Stmm rle->res = rv; 82690618Stmm return (rv); 82790618Stmm} 82890618Stmm 82990618Stmmstatic int 83090618Stmmsbus_activate_resource(device_t bus, device_t child, int type, int rid, 83190618Stmm struct resource *r) 83290618Stmm{ 83390618Stmm 83490618Stmm if (type == SYS_RES_IRQ) 83590618Stmm return (bus_activate_resource(bus, type, rid, r)); 83690618Stmm return (rman_activate_resource(r)); 83790618Stmm} 83890618Stmm 83990618Stmmstatic int 84090618Stmmsbus_deactivate_resource(device_t bus, device_t child, int type, int rid, 84190618Stmm struct resource *r) 84290618Stmm{ 84390618Stmm 84490618Stmm if (type == SYS_RES_IRQ) 84590618Stmm return (bus_deactivate_resource(bus, type, rid, r)); 84690618Stmm return (rman_deactivate_resource(r)); 84790618Stmm} 84890618Stmm 84990618Stmmstatic int 85090618Stmmsbus_release_resource(device_t bus, device_t child, int type, int rid, 85190618Stmm struct resource *r) 85290618Stmm{ 85390618Stmm int error; 85490618Stmm 85590618Stmm if (type == SYS_RES_IRQ) 85690618Stmm return (bus_release_resource(bus, type, rid, r)); 85790618Stmm if (rman_get_flags(r) & RF_ACTIVE) { 85890618Stmm error = bus_deactivate_resource(child, type, rid, r); 85990618Stmm if (error) 86090618Stmm return error; 86190618Stmm } 86290618Stmm return (rman_release_resource(r)); 86390618Stmm} 86490618Stmm 86590618Stmm/* 86690618Stmm * Handle an overtemp situation. 86790618Stmm * 86890618Stmm * SPARCs have temperature sensors which generate interrupts 86990618Stmm * if the machine's temperature exceeds a certain threshold. 87090618Stmm * This handles the interrupt and powers off the machine. 87190618Stmm * The same needs to be done to PCI controller drivers. 87290618Stmm */ 87390618Stmmstatic void 87490618Stmmsbus_overtemp(void *arg) 87590618Stmm{ 87690618Stmm 87790618Stmm printf("DANGER: OVER TEMPERATURE detected\nShutting down NOW.\n"); 87890618Stmm shutdown_nice(RB_POWEROFF); 87990618Stmm} 88090618Stmm 88190618Stmm/* Try to shut down in time in case of power failure. */ 88290618Stmmstatic void 88390618Stmmsbus_pwrfail(void *arg) 88490618Stmm{ 88590618Stmm 88690618Stmm printf("Power failure detected\nShutting down NOW.\n"); 88790618Stmm shutdown_nice(0); 88890618Stmm} 88990618Stmm 89090618Stmmstatic bus_space_tag_t 89190618Stmmsbus_alloc_bustag(struct sbus_softc *sc) 89290618Stmm{ 89390618Stmm bus_space_tag_t sbt; 89490618Stmm 89590618Stmm sbt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 89690618Stmm M_NOWAIT | M_ZERO); 89790618Stmm if (sbt == NULL) 89890618Stmm panic("sbus_alloc_bustag: out of memory"); 89990618Stmm 90090618Stmm bzero(sbt, sizeof *sbt); 90190618Stmm sbt->cookie = sc; 90290618Stmm sbt->parent = sc->sc_bustag; 90390618Stmm sbt->type = SBUS_BUS_SPACE; 90490618Stmm return (sbt); 90590618Stmm} 90690618Stmm 90790618Stmmstatic int 90893070Stmmsbus_dmamap_create(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, int flags, 90993070Stmm bus_dmamap_t *mapp) 91090618Stmm{ 91193070Stmm struct sbus_softc *sc = (struct sbus_softc *)pdmat->cookie; 91290618Stmm 91393070Stmm return (iommu_dvmamap_create(pdmat, ddmat, &sc->sc_is, flags, mapp)); 91490618Stmm 91590618Stmm} 91690618Stmm 91790618Stmmstatic int 91893070Stmmsbus_dmamap_destroy(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map) 91990618Stmm{ 92093070Stmm struct sbus_softc *sc = (struct sbus_softc *)pdmat->cookie; 92190618Stmm 92293070Stmm return (iommu_dvmamap_destroy(pdmat, ddmat, &sc->sc_is, map)); 92390618Stmm} 92490618Stmm 92590618Stmmstatic int 92693070Stmmsbus_dmamap_load(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map, 92793070Stmm void *buf, bus_size_t buflen, bus_dmamap_callback_t *callback, 92893070Stmm void *callback_arg, int flags) 92990618Stmm{ 93093070Stmm struct sbus_softc *sc = (struct sbus_softc *)pdmat->cookie; 93190618Stmm 93293070Stmm return (iommu_dvmamap_load(pdmat, ddmat, &sc->sc_is, map, buf, buflen, 93393070Stmm callback, callback_arg, flags)); 93490618Stmm} 93590618Stmm 93690618Stmmstatic void 93793070Stmmsbus_dmamap_unload(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map) 93890618Stmm{ 93993070Stmm struct sbus_softc *sc = (struct sbus_softc *)pdmat->cookie; 94090618Stmm 94193070Stmm iommu_dvmamap_unload(pdmat, ddmat, &sc->sc_is, map); 94290618Stmm} 94390618Stmm 94490618Stmmstatic void 94593070Stmmsbus_dmamap_sync(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map, 94690618Stmm bus_dmasync_op_t op) 94790618Stmm{ 94893070Stmm struct sbus_softc *sc = (struct sbus_softc *)pdmat->cookie; 94990618Stmm 95093070Stmm iommu_dvmamap_sync(pdmat, ddmat, &sc->sc_is, map, op); 95190618Stmm} 95290618Stmm 95390618Stmmstatic int 95493070Stmmsbus_dmamem_alloc(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, void **vaddr, 95593070Stmm int flags, bus_dmamap_t *mapp) 95690618Stmm{ 95793070Stmm struct sbus_softc *sc = (struct sbus_softc *)pdmat->cookie; 95890618Stmm 95993070Stmm return (iommu_dvmamem_alloc(pdmat, ddmat, &sc->sc_is, vaddr, flags, 96093070Stmm mapp)); 96190618Stmm} 96290618Stmm 96390618Stmmstatic void 96493070Stmmsbus_dmamem_free(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, void *vaddr, 96593070Stmm bus_dmamap_t map) 96690618Stmm{ 96793070Stmm struct sbus_softc *sc = (struct sbus_softc *)pdmat->cookie; 96890618Stmm 96993070Stmm iommu_dvmamem_free(pdmat, ddmat, &sc->sc_is, vaddr, map); 97090618Stmm} 971