schizoreg.h revision 185133
1183423Smarius/*- 2183423Smarius * Copyright (c) 2002 Jason L. Wright (jason@thought.net) 3183423Smarius * Copyright (c) 2005 by Marius Strobl <marius@FreeBSD.org> 4183423Smarius * All rights reserved. 5183423Smarius * 6183423Smarius * Redistribution and use in source and binary forms, with or without 7183423Smarius * modification, are permitted provided that the following conditions 8183423Smarius * are met: 9183423Smarius * 1. Redistributions of source code must retain the above copyright 10183423Smarius * notice, this list of conditions and the following disclaimer. 11183423Smarius * 2. Redistributions in binary form must reproduce the above copyright 12183423Smarius * notice, this list of conditions and the following disclaimer in the 13183423Smarius * documentation and/or other materials provided with the distribution. 14183423Smarius * 15183423Smarius * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16183423Smarius * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17183423Smarius * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULLAR PURPOSE ARE 18183423Smarius * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19183423Smarius * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20183423Smarius * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21183423Smarius * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22183423Smarius * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23183423Smarius * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24183423Smarius * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25183423Smarius * POSSIBILITY OF SUCH DAMAGE. 26183423Smarius * 27183423Smarius * from: OpenBSD: schizoreg.h,v 1.8 2005/05/19 18:28:59 mickey Exp 28183423Smarius * $FreeBSD: head/sys/sparc64/pci/schizoreg.h 185133 2008-11-20 18:44:09Z marius $ 29183423Smarius */ 30183423Smarius 31183423Smarius#ifndef _SPARC64_PCI_SCHIZOREG_H_ 32183423Smarius#define _SPARC64_PCI_SCHIZOREG_H_ 33183423Smarius 34185133Smarius#define STX_NINTR 5 /* 4 via OFW + 1 CDMA */ 35183423Smarius#define STX_NRANGE 4 36183423Smarius#define SCZ_NREG 3 37183423Smarius#define TOM_NREG 4 38183423Smarius 39183423Smarius#define STX_PCI 0 40183423Smarius#define STX_CTRL 1 41183423Smarius#define STX_PCICFG 2 42183423Smarius#define STX_ICON 3 43183423Smarius 44183423Smarius/* PCI configuration and status registers */ 45183423Smarius#define STX_PCI_IOMMU 0x00200 46183423Smarius#define STX_PCI_IOMMU_CTXFLUSH 0x00218 47183423Smarius#define STX_PCI_IMAP_BASE 0x01000 48183423Smarius#define STX_PCI_ICLR_BASE 0x01400 49183423Smarius#define STX_PCI_INTR_RETRY_TIM 0x01a00 50183423Smarius#define SCZ_PCI_DMA_SYNC 0x01a08 51183423Smarius#define TOM_PCI_DMA_SYNC_COMP 0x01a10 52183423Smarius#define TOMXMS_PCI_DMA_SYNC_PEND 0x01a18 53183423Smarius#define STX_PCI_CTRL 0x02000 54183423Smarius#define STX_PCI_AFSR 0x02010 55183423Smarius#define STX_PCI_AFAR 0x02018 56183423Smarius#define STX_PCI_DIAG 0x02020 57183423Smarius#define TOM_PCI_IOC_CSR 0x02248 58183423Smarius#define TOM_PCI_IOC_TAG 0x02290 59183423Smarius#define TOM_PCI_IOC_DATA 0x02290 60183423Smarius#define STX_PCI_STRBUF 0x02800 61183423Smarius#define STX_PCI_STRBUF_CTXFLUSH 0x02818 62183423Smarius#define STX_PCI_IOMMU_SVADIAG 0x0a400 63183423Smarius#define STX_PCI_IOMMU_TLB_CMP_DIAG 0x0a408 64183423Smarius#define STX_PCI_IOMMU_QUEUE_DIAG 0x0a500 65183423Smarius#define STX_PCI_IOMMU_TLB_TAG_DIAG 0x0a580 66183423Smarius#define STX_PCI_IOMMU_TLB_DATA_DIAG 0x0a600 67183423Smarius#define STX_PCI_IOBIO_DIAG 0x0a808 68183423Smarius#define STX_PCI_STRBUF_CTXMATCH 0x10000 69183423Smarius 70183423Smarius/* PCI IOMMU control registers */ 71183423Smarius#define TOM_PCI_IOMMU_ERR_BAD_VA 0x0000000010000000ULL 72183423Smarius#define TOM_PCI_IOMMU_ERR_ILLTSBTBW 0x0000000008000000ULL 73183423Smarius#define TOM_PCI_IOMMU_ECC_ERR 0x0000000006000000ULL 74183423Smarius#define TOM_PCI_IOMMU_TIMEOUT_ERR 0x0000000004000000ULL 75183423Smarius#define TOM_PCI_IOMMU_INVALID_ERR 0x0000000002000000ULL 76183423Smarius#define TOM_PCI_IOMMU_PROTECTION_ERR 0x0000000000000000ULL 77183423Smarius#define TOM_PCI_IOMMU_ERRMASK \ 78183423Smarius (TOM_PCI_IOMMU_PROTECTION_ERR | TOM_PCI_IOMMU_INVALID_ERR | \ 79183423Smarius TOM_PCI_IOMMU_TIMEOUT_ERR | TOM_PCI_IOMMU_ECC_ERR) 80183423Smarius#define TOM_PCI_IOMMU_ERR 0x0000000001000000ULL 81183423Smarius 82183423Smarius/* PCI control/status register */ 83183423Smarius#define SCZ_PCI_CTRL_BUS_UNUS 0x8000000000000000ULL 84183423Smarius#define TOM_PCI_CTRL_DTO_ERR 0x4000000000000000ULL 85183423Smarius#define TOM_PCI_CTRL_DTO_IEN 0x2000000000000000ULL 86183423Smarius#define SCZ_PCI_CTRL_ESLCK 0x0008000000000000ULL 87183423Smarius#define SCZ_PCI_CTRL_ERRSLOT 0x0007000000000000ULL 88183423Smarius#define STX_PCI_CTRL_TTO_ERR 0x0000004000000000ULL 89183423Smarius#define STX_PCI_CTRL_RTRY_ERR 0x0000002000000000ULL 90183423Smarius#define STX_PCI_CTRL_MMU_ERR 0x0000001000000000ULL 91183423Smarius#define SCZ_PCI_CTRL_SBH_ERR 0x0000000800000000ULL 92183423Smarius#define STX_PCI_CTRL_SERR 0x0000000400000000ULL 93183423Smarius#define SCZ_PCI_CTRL_PCISPD 0x0000000200000000ULL 94183423Smarius#define TOM_PCI_CTRL_PRM 0x0000000040000000ULL 95183423Smarius#define TOM_PCI_CTRL_PRO 0x0000000020000000ULL 96183423Smarius#define TOM_PCI_CTRL_PRL 0x0000000010000000ULL 97183423Smarius#define STX_PCI_CTRL_PTO 0x0000000003000000ULL 98183423Smarius#define STX_PCI_CTRL_MMU_IEN 0x0000000000080000ULL 99183423Smarius#define STX_PCI_CTRL_SBH_IEN 0x0000000000040000ULL 100183423Smarius#define STX_PCI_CTRL_ERR_IEN 0x0000000000020000ULL 101183423Smarius#define STX_PCI_CTRL_ARB_PARK 0x0000000000010000ULL 102183423Smarius#define SCZ_PCI_CTRL_PCIRST 0x0000000000000100ULL 103183423Smarius#define STX_PCI_CTRL_ARB_MASK 0x00000000000000ffULL 104183423Smarius 105183423Smarius/* PCI asynchronous fault status register */ 106183423Smarius#define STX_PCI_AFSR_P_MA 0x8000000000000000ULL 107183423Smarius#define STX_PCI_AFSR_P_TA 0x4000000000000000ULL 108183423Smarius#define STX_PCI_AFSR_P_RTRY 0x2000000000000000ULL 109183423Smarius#define STX_PCI_AFSR_P_PERR 0x1000000000000000ULL 110183423Smarius#define STX_PCI_AFSR_P_TTO 0x0800000000000000ULL 111183423Smarius#define STX_PCI_AFSR_P_UNUS 0x0400000000000000ULL 112183423Smarius#define STX_PCI_AFSR_S_MA 0x0200000000000000ULL 113183423Smarius#define STX_PCI_AFSR_S_TA 0x0100000000000000ULL 114183423Smarius#define STX_PCI_AFSR_S_RTRY 0x0080000000000000ULL 115183423Smarius#define STX_PCI_AFSR_S_PERR 0x0040000000000000ULL 116183423Smarius#define STX_PCI_AFSR_S_TTO 0x0020000000000000ULL 117183423Smarius#define STX_PCI_AFSR_S_UNUS 0x0010000000000000ULL 118183423Smarius#define STX_PCI_AFSR_DWMASK 0x0000030000000000ULL 119183423Smarius#define STX_PCI_AFSR_BMASK 0x000000ff00000000ULL 120183423Smarius#define STX_PCI_AFSR_BLK 0x0000000080000000ULL 121183423Smarius#define STX_PCI_AFSR_CFG 0x0000000040000000ULL 122183423Smarius#define STX_PCI_AFSR_MEM 0x0000000020000000ULL 123183423Smarius#define STX_PCI_AFSR_IO 0x0000000010000000ULL 124183423Smarius 125183423Smarius/* PCI diagnostic register */ 126183423Smarius#define SCZ_PCI_DIAG_BADECC_DIS 0x0000000000000400ULL 127183423Smarius#define STX_PCI_DIAG_BYPASS_DIS 0x0000000000000200ULL 128183423Smarius#define STX_PCI_DIAG_TTO_DIS 0x0000000000000100ULL 129183423Smarius#define SCZ_PCI_DIAG_RTRYARB_DIS 0x0000000000000080ULL 130183423Smarius#define STX_PCI_DIAG_RETRY_DIS 0x0000000000000040ULL 131183423Smarius#define STX_PCI_DIAG_INTRSYNC_DIS 0x0000000000000020ULL 132183423Smarius#define STX_PCI_DIAG_DMAPARITY_INV 0x0000000000000008ULL 133183423Smarius#define STX_PCI_DIAG_PIODPARITY_INV 0x0000000000000004ULL 134183423Smarius#define STX_PCI_DIAG_PIOAPARITY_INV 0x0000000000000002ULL 135183423Smarius 136183423Smarius/* Tomatillo I/O cache register */ 137183423Smarius#define TOM_PCI_IOC_PW 0x0000000000080000ULL 138183423Smarius#define TOM_PCI_IOC_PRM 0x0000000000040000ULL 139183423Smarius#define TOM_PCI_IOC_PRO 0x0000000000020000ULL 140183423Smarius#define TOM_PCI_IOC_PRL 0x0000000000010000ULL 141183423Smarius#define TOM_PCI_IOC_PRM_LEN 0x000000000000c000ULL 142183423Smarius#define TOM_PCI_IOC_PRM_LEN_SHIFT 14 143183423Smarius#define TOM_PCI_IOC_PRO_LEN 0x0000000000003000ULL 144183423Smarius#define TOM_PCI_IOC_PRO_LEN_SHIFT 12 145183423Smarius#define TOM_PCI_IOC_PRL_LEN 0x0000000000000c00ULL 146183423Smarius#define TOM_PCI_IOC_PRL_LEN_SHIFT 10 147183423Smarius#define TOM_PCI_IOC_PREF_OFF 0x0000000000000038ULL 148183423Smarius#define TOM_PCI_IOC_PREF_OFF_SHIFT 3 149183423Smarius#define TOM_PCI_IOC_CPRM 0x0000000000000004ULL 150183423Smarius#define TOM_PCI_IOC_CPRO 0x0000000000000002ULL 151183423Smarius#define TOM_PCI_IOC_CPRL 0x0000000000000001ULL 152183423Smarius 153183423Smarius/* Controller configuration and status registers */ 154183423Smarius/* Note that these are shared on Schizo but per-PBM on Tomatillo. */ 155183423Smarius#define STX_CTRL_BUS_ERRLOG 0x00018 156183423Smarius#define STX_CTRL_ECCCTRL 0x00020 157183423Smarius#define STX_CTRL_UE_AFSR 0x00030 158183423Smarius#define STX_CTRL_UE_AFAR 0x00038 159183423Smarius#define STX_CTRL_CE_AFSR 0x00040 160183423Smarius#define STX_CTRL_CE_AFAR 0x00048 161183423Smarius#define STX_CTRL_PERF 0x07000 162183423Smarius#define STX_CTRL_PERF_CNT 0x07008 163183423Smarius 164183423Smarius/* Safari/JBus error log register */ 165183423Smarius#define STX_CTRL_BUS_ERRLOG_BADCMD 0x4000000000000000ULL 166183423Smarius#define SCZ_CTRL_BUS_ERRLOG_SSMDIS 0x2000000000000000ULL 167183423Smarius#define SCZ_CTRL_BUS_ERRLOG_BADMA 0x1000000000000000ULL 168183423Smarius#define SCZ_CTRL_BUS_ERRLOG_BADMB 0x0800000000000000ULL 169183423Smarius#define SCZ_CTRL_BUS_ERRLOG_BADMC 0x0400000000000000ULL 170183423Smarius#define TOM_CTRL_BUS_ERRLOG_SNOOP_GR 0x0000000000200000ULL 171183423Smarius#define TOM_CTRL_BUS_ERRLOG_SNOOP_PCI 0x0000000000100000ULL 172183423Smarius#define TOM_CTRL_BUS_ERRLOG_SNOOP_RD 0x0000000000080000ULL 173183423Smarius#define TOM_CTRL_BUS_ERRLOG_SNOOP_RDS 0x0000000000020000ULL 174183423Smarius#define TOM_CTRL_BUS_ERRLOG_SNOOP_RDSA 0x0000000000010000ULL 175183423Smarius#define TOM_CTRL_BUS_ERRLOG_SNOOP_OWN 0x0000000000008000ULL 176183423Smarius#define TOM_CTRL_BUS_ERRLOG_SNOOP_RDO 0x0000000000004000ULL 177183423Smarius#define SCZ_CTRL_BUS_ERRLOG_CPU1PS 0x0000000000002000ULL 178183423Smarius#define TOM_CTRL_BUS_ERRLOG_WDATA_PERR 0x0000000000002000ULL 179183423Smarius#define SCZ_CTRL_BUS_ERRLOG_CPU1PB 0x0000000000001000ULL 180183423Smarius#define TOM_CTRL_BUS_ERRLOG_CTRL_PERR 0x0000000000001000ULL 181183423Smarius#define SCZ_CTRL_BUS_ERRLOG_CPU0PS 0x0000000000000800ULL 182183423Smarius#define TOM_CTRL_BUS_ERRLOG_SNOOP_ERR 0x0000000000000800ULL 183183423Smarius#define SCZ_CTRL_BUS_ERRLOG_CPU0PB 0x0000000000000400ULL 184183423Smarius#define TOM_CTRL_BUS_ERRLOG_JBUS_ILL_B 0x0000000000000400ULL 185183423Smarius#define SCZ_CTRL_BUS_ERRLOG_CIQTO 0x0000000000000200ULL 186183423Smarius#define SCZ_CTRL_BUS_ERRLOG_LPQTO 0x0000000000000100ULL 187183423Smarius#define TOM_CTRL_BUS_ERRLOG_JBUS_ILL_C 0x0000000000000100ULL 188183423Smarius#define SCZ_CTRL_BUS_ERRLOG_SFPQTO 0x0000000000000080ULL 189183423Smarius#define SCZ_CTRL_BUS_ERRLOG_UFPQTO 0x0000000000000040ULL 190183423Smarius#define TOM_CTRL_BUS_ERRLOG_RD_PERR 0x0000000000000040ULL 191183423Smarius#define STX_CTRL_BUS_ERRLOG_APERR 0x0000000000000020ULL 192183423Smarius#define STX_CTRL_BUS_ERRLOG_UNMAP 0x0000000000000010ULL 193183423Smarius#define STX_CTRL_BUS_ERRLOG_BUSERR 0x0000000000000004ULL 194183423Smarius#define STX_CTRL_BUS_ERRLOG_TIMEOUT 0x0000000000000002ULL 195183423Smarius#define SCZ_CTRL_BUS_ERRLOG_ILL 0x0000000000000001ULL 196183423Smarius 197183423Smarius/* ECC control register */ 198183423Smarius#define STX_CTRL_ECCCTRL_EE 0x8000000000000000ULL 199183423Smarius#define STX_CTRL_ECCCTRL_UE 0x4000000000000000ULL 200183423Smarius#define STX_CTRL_ECCCTRL_CE 0x2000000000000000ULL 201183423Smarius 202183423Smarius/* Uncorrectable error asynchronous fault status register */ 203183423Smarius#define STX_CTRL_UE_AFSR_P_PIO 0x8000000000000000ULL 204183423Smarius#define STX_CTRL_UE_AFSR_P_DRD 0x4000000000000000ULL 205183423Smarius#define STX_CTRL_UE_AFSR_P_DWR 0x2000000000000000ULL 206183423Smarius#define STX_CTRL_UE_AFSR_S_PIO 0x1000000000000000ULL 207183423Smarius#define STX_CTRL_UE_AFSR_S_DRD 0x0800000000000000ULL 208183423Smarius#define STX_CTRL_UE_AFSR_S_DWR 0x0400000000000000ULL 209183423Smarius#define STX_CTRL_UE_AFSR_ERRPNDG 0x0300000000000000ULL 210183423Smarius#define STX_CTRL_UE_AFSR_BMASK 0x000003ff00000000ULL 211183423Smarius#define STX_CTRL_UE_AFSR_QOFF 0x00000000c0000000ULL 212183423Smarius#define STX_CTRL_UE_AFSR_AID 0x000000001f000000ULL 213183423Smarius#define STX_CTRL_UE_AFSR_PARTIAL 0x0000000000800000ULL 214183423Smarius#define STX_CTRL_UE_AFSR_OWNEDIN 0x0000000000400000ULL 215183423Smarius#define STX_CTRL_UE_AFSR_MTAGSYND 0x00000000000f0000ULL 216183423Smarius#define STX_CTRL_UE_AFSR_MTAG 0x000000000000e000ULL 217183423Smarius#define STX_CTRL_UE_AFSR_ECCSYND 0x00000000000001ffULL 218183423Smarius 219183423Smarius/* Correctable error asynchronous fault status register */ 220183423Smarius#define STX_CTRL_CE_AFSR_P_PIO 0x8000000000000000ULL 221183423Smarius#define STX_CTRL_CE_AFSR_P_DRD 0x4000000000000000ULL 222183423Smarius#define STX_CTRL_CE_AFSR_P_DWR 0x2000000000000000ULL 223183423Smarius#define STX_CTRL_CE_AFSR_S_PIO 0x1000000000000000ULL 224183423Smarius#define STX_CTRL_CE_AFSR_S_DRD 0x0800000000000000ULL 225183423Smarius#define STX_CTRL_CE_AFSR_S_DWR 0x0400000000000000ULL 226183423Smarius#define STX_CTRL_CE_AFSR_ERRPNDG 0x0300000000000000ULL 227183423Smarius#define STX_CTRL_CE_AFSR_BMASK 0x000003ff00000000ULL 228183423Smarius#define STX_CTRL_CE_AFSR_QOFF 0x00000000c0000000ULL 229183423Smarius#define STX_CTRL_CE_AFSR_AID 0x000000001f000000ULL 230183423Smarius#define STX_CTRL_CE_AFSR_PARTIAL 0x0000000000800000ULL 231183423Smarius#define STX_CTRL_CE_AFSR_OWNEDIN 0x0000000000400000ULL 232183423Smarius#define STX_CTRL_CE_AFSR_MTAGSYND 0x00000000000f0000ULL 233183423Smarius#define STX_CTRL_CE_AFSR_MTAG 0x000000000000e000ULL 234183423Smarius#define STX_CTRL_CE_AFSR_ECCSYND 0x00000000000001ffULL 235183423Smarius 236183423Smarius/* 237183423Smarius * Safari/JBus performance control register 238183423Smarius * NB: for Tomatillo only events 0x00 through 0x08 are documented as 239183423Smarius * implemented. 240183423Smarius */ 241183423Smarius#define SCZ_CTRL_PERF_ZDATA_OUT 0x0000000000000016ULL 242183423Smarius#define SCZ_CTRL_PERF_ZDATA_IN 0x0000000000000015ULL 243183423Smarius#define SCZ_CTRL_PERF_ORQFULL 0x0000000000000014ULL 244183423Smarius#define SCZ_CTRL_PERF_DVMA_WR 0x0000000000000013ULL 245183423Smarius#define SCZ_CTRL_PERF_DVMA_RD 0x0000000000000012ULL 246183423Smarius#define SCZ_CTRL_PERF_CYCPSESYS 0x0000000000000011ULL 247183423Smarius#define STX_CTRL_PERF_PCI_B 0x000000000000000fULL 248183423Smarius#define STX_CTRL_PERF_PCI_A 0x000000000000000eULL 249183423Smarius#define STX_CTRL_PERF_UPA 0x000000000000000dULL 250183423Smarius#define STX_CTRL_PERF_PIOINTRNL 0x000000000000000cULL 251183423Smarius#define TOM_CTRL_PERF_WRI_WRIS 0x000000000000000bULL 252183423Smarius#define STX_CTRL_PERF_INTRS 0x000000000000000aULL 253183423Smarius#define STX_CTRL_PERF_PRTLWRMRGBUF 0x0000000000000009ULL 254183423Smarius#define STX_CTRL_PERF_FGN_IO_HITS 0x0000000000000008ULL 255183423Smarius#define STX_CTRL_PERF_FGN_IO_TRNS 0x0000000000000007ULL 256183423Smarius#define STX_CTRL_PERF_OWN_CHRNT_HITS 0x0000000000000006ULL 257183423Smarius#define STX_CTRL_PERF_OWN_CHRNT_TRNS 0x0000000000000005ULL 258183423Smarius#define SCZ_CTRL_PERF_FGN_CHRNT_HITS 0x0000000000000004ULL 259183423Smarius#define STX_CTRL_PERF_FGN_CHRNT_TRNS 0x0000000000000003ULL 260183423Smarius#define STX_CTRL_PERF_CYCLES_PAUSE 0x0000000000000002ULL 261183423Smarius#define STX_CTRL_PERF_BUSCYC 0x0000000000000001ULL 262183423Smarius#define STX_CTRL_PERF_DIS 0x0000000000000000ULL 263183423Smarius#define STX_CTRL_PERF_CNT1_SHIFT 11 264183423Smarius#define STX_CTRL_PERF_CNT0_SHIFT 4 265183423Smarius 266183423Smarius/* Safari/JBus performance counter register */ 267183423Smarius#define STX_CTRL_PERF_CNT_MASK 0x00000000ffffffffULL 268183423Smarius#define STX_CTRL_PERF_CNT_CNT1_SHIFT 32 269183423Smarius#define STX_CTRL_PERF_CNT_CNT0_SHIFT 0 270183423Smarius 271183423Smarius/* INO defines */ 272183423Smarius#define STX_FB0_INO 0x2a /* FB0 int. shared w/ UPA64s */ 273183423Smarius#define STX_FB1_INO 0x2b /* FB1 int. shared w/ UPA64s */ 274183423Smarius#define STX_UE_INO 0x30 /* uncorrectable error */ 275183423Smarius#define STX_CE_INO 0x31 /* correctable error */ 276183423Smarius#define STX_PCIERR_A_INO 0x32 /* PCI bus A error */ 277183423Smarius#define STX_PCIERR_B_INO 0x33 /* PCI bus B error */ 278183423Smarius#define STX_BUS_INO 0x34 /* Safari/JBus error */ 279185133Smarius#define STX_CDMA_A_INO 0x35 /* PCI bus A CDMA */ 280185133Smarius#define STX_CDMA_B_INO 0x36 /* PCI bus B CDMA */ 281183423Smarius#define STX_MAX_INO 0x37 282183423Smarius 283183423Smarius/* Device space defines */ 284183423Smarius#define STX_CONF_SIZE 0x1000000 285183423Smarius#define STX_CONF_BUS_SHIFT 16 286183423Smarius#define STX_CONF_DEV_SHIFT 11 287183423Smarius#define STX_CONF_FUNC_SHIFT 8 288183423Smarius#define STX_CONF_REG_SHIFT 0 289183423Smarius#define STX_IO_SIZE 0x1000000 290183423Smarius#define STX_MEM_SIZE 0x100000000 291183423Smarius 292183423Smarius#define STX_CONF_OFF(bus, slot, func, reg) \ 293183423Smarius (((bus) << STX_CONF_BUS_SHIFT) | \ 294183423Smarius ((slot) << STX_CONF_DEV_SHIFT) | \ 295183423Smarius ((func) << STX_CONF_FUNC_SHIFT) | \ 296183423Smarius ((reg) << STX_CONF_REG_SHIFT)) 297183423Smarius 298183423Smarius/* Definitions for the Schizo/Tomatillo configuration space */ 299183423Smarius#define STX_CS_DEVICE 0 /* bridge CS device number */ 300183423Smarius#define STX_CS_FUNC 0 /* brdige CS function number */ 301183423Smarius 302183423Smarius/* Non-Standard registers in the configration space */ 303183423Smarius/* 304183423Smarius * NB: for Tomatillo the secondary and subordinate bus number registers 305183423Smarius * apparently are read-only although documented otherwise; writing to 306183423Smarius * them just triggers a PCI bus error interrupt or has no effect at best. 307183423Smarius */ 308183423Smarius#define STX_CSR_SECBUS 0x40 /* secondary bus number */ 309183423Smarius#define STX_CSR_SUBBUS 0x41 /* subordinate bus number */ 310183423Smarius 311183423Smarius/* Width of the physical addresses the IOMMU translates to */ 312183423Smarius#define STX_IOMMU_BITS 43 313183423Smarius 314183423Smarius#endif /* !_SPARC64_PCI_SCHIZOREG_H_ */ 315