1183423Smarius/*- 2183423Smarius * Copyright (c) 2002 Jason L. Wright (jason@thought.net) 3183423Smarius * Copyright (c) 2005 by Marius Strobl <marius@FreeBSD.org> 4183423Smarius * All rights reserved. 5183423Smarius * 6183423Smarius * Redistribution and use in source and binary forms, with or without 7183423Smarius * modification, are permitted provided that the following conditions 8183423Smarius * are met: 9183423Smarius * 1. Redistributions of source code must retain the above copyright 10183423Smarius * notice, this list of conditions and the following disclaimer. 11183423Smarius * 2. Redistributions in binary form must reproduce the above copyright 12183423Smarius * notice, this list of conditions and the following disclaimer in the 13183423Smarius * documentation and/or other materials provided with the distribution. 14183423Smarius * 15183423Smarius * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16183423Smarius * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17183423Smarius * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULLAR PURPOSE ARE 18183423Smarius * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19183423Smarius * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20183423Smarius * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21183423Smarius * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22183423Smarius * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23183423Smarius * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24183423Smarius * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25183423Smarius * POSSIBILITY OF SUCH DAMAGE. 26183423Smarius * 27183423Smarius * from: OpenBSD: schizoreg.h,v 1.8 2005/05/19 18:28:59 mickey Exp 28183423Smarius * $FreeBSD$ 29183423Smarius */ 30183423Smarius 31183423Smarius#ifndef _SPARC64_PCI_SCHIZOREG_H_ 32183423Smarius#define _SPARC64_PCI_SCHIZOREG_H_ 33183423Smarius 34185133Smarius#define STX_NINTR 5 /* 4 via OFW + 1 CDMA */ 35183423Smarius#define STX_NRANGE 4 36183423Smarius#define SCZ_NREG 3 37183423Smarius#define TOM_NREG 4 38183423Smarius 39183423Smarius#define STX_PCI 0 40183423Smarius#define STX_CTRL 1 41183423Smarius#define STX_PCICFG 2 42183423Smarius#define STX_ICON 3 43183423Smarius 44183423Smarius/* PCI configuration and status registers */ 45208097Smarius#define SX_PCI_CFG_ICD 0x00110 46183423Smarius#define STX_PCI_IOMMU 0x00200 47183423Smarius#define STX_PCI_IOMMU_CTXFLUSH 0x00218 48183423Smarius#define STX_PCI_IMAP_BASE 0x01000 49183423Smarius#define STX_PCI_ICLR_BASE 0x01400 50183423Smarius#define STX_PCI_INTR_RETRY_TIM 0x01a00 51183423Smarius#define SCZ_PCI_DMA_SYNC 0x01a08 52183423Smarius#define TOM_PCI_DMA_SYNC_COMP 0x01a10 53183423Smarius#define TOMXMS_PCI_DMA_SYNC_PEND 0x01a18 54183423Smarius#define STX_PCI_CTRL 0x02000 55183423Smarius#define STX_PCI_AFSR 0x02010 56183423Smarius#define STX_PCI_AFAR 0x02018 57183423Smarius#define STX_PCI_DIAG 0x02020 58220038Smarius#define XMS_PCI_PARITY_DETECT 0x02040 59183423Smarius#define TOM_PCI_IOC_CSR 0x02248 60183423Smarius#define TOM_PCI_IOC_TAG 0x02290 61183423Smarius#define TOM_PCI_IOC_DATA 0x02290 62220038Smarius#define XMS_PCI_X_ERR_STAT 0x02300 63220038Smarius#define XMS_PCI_X_DIAG 0x02308 64220038Smarius#define XMS_PCI_UPPER_RETRY_COUNTER 0x02310 65183423Smarius#define STX_PCI_STRBUF 0x02800 66183423Smarius#define STX_PCI_STRBUF_CTXFLUSH 0x02818 67183423Smarius#define STX_PCI_IOMMU_SVADIAG 0x0a400 68183423Smarius#define STX_PCI_IOMMU_TLB_CMP_DIAG 0x0a408 69183423Smarius#define STX_PCI_IOMMU_QUEUE_DIAG 0x0a500 70183423Smarius#define STX_PCI_IOMMU_TLB_TAG_DIAG 0x0a580 71183423Smarius#define STX_PCI_IOMMU_TLB_DATA_DIAG 0x0a600 72183423Smarius#define STX_PCI_IOBIO_DIAG 0x0a808 73183423Smarius#define STX_PCI_STRBUF_CTXMATCH 0x10000 74183423Smarius 75220038Smarius/* PCI configuration/idle check diagnostic register */ 76208097Smarius#define SX_PCI_CFG_ICD_PCI_2_0_COMPAT 0x0000000000008000ULL 77208097Smarius#define SX_PCI_CFG_ICD_DMAW_PERR_IEN 0x0000000000004000ULL 78208097Smarius#define SX_PCI_CFG_ICD_IFC_NOT_IDLE 0x0000000000000010ULL 79208097Smarius#define SX_PCI_CFG_ICD_MDU_NOT_IDLE 0x0000000000000008ULL 80208097Smarius#define SX_PCI_CFG_ICD_MMU_NOT_IDLE 0x0000000000000004ULL 81208097Smarius#define SX_PCI_CFG_ICD_PBM_NOT_IDLE 0x0000000000000002ULL 82208097Smarius#define SX_PCI_CFG_ICD_STC_NOT_IDLE 0x0000000000000001ULL 83208097Smarius 84220038Smarius/* PCI IOMMU control register */ 85183423Smarius#define TOM_PCI_IOMMU_ERR_BAD_VA 0x0000000010000000ULL 86183423Smarius#define TOM_PCI_IOMMU_ERR_ILLTSBTBW 0x0000000008000000ULL 87183423Smarius#define TOM_PCI_IOMMU_ECC_ERR 0x0000000006000000ULL 88183423Smarius#define TOM_PCI_IOMMU_TIMEOUT_ERR 0x0000000004000000ULL 89183423Smarius#define TOM_PCI_IOMMU_INVALID_ERR 0x0000000002000000ULL 90183423Smarius#define TOM_PCI_IOMMU_PROTECTION_ERR 0x0000000000000000ULL 91183423Smarius#define TOM_PCI_IOMMU_ERRMASK \ 92183423Smarius (TOM_PCI_IOMMU_PROTECTION_ERR | TOM_PCI_IOMMU_INVALID_ERR | \ 93183423Smarius TOM_PCI_IOMMU_TIMEOUT_ERR | TOM_PCI_IOMMU_ECC_ERR) 94183423Smarius#define TOM_PCI_IOMMU_ERR 0x0000000001000000ULL 95183423Smarius 96183423Smarius/* PCI control/status register */ 97183423Smarius#define SCZ_PCI_CTRL_BUS_UNUS 0x8000000000000000ULL 98183423Smarius#define TOM_PCI_CTRL_DTO_ERR 0x4000000000000000ULL 99183423Smarius#define TOM_PCI_CTRL_DTO_IEN 0x2000000000000000ULL 100183423Smarius#define SCZ_PCI_CTRL_ESLCK 0x0008000000000000ULL 101220038Smarius#define XMS_PCI_CTRL_DMA_WR_PERR 0x0008000000000000ULL 102183423Smarius#define SCZ_PCI_CTRL_ERRSLOT 0x0007000000000000ULL 103183423Smarius#define STX_PCI_CTRL_TTO_ERR 0x0000004000000000ULL 104183423Smarius#define STX_PCI_CTRL_RTRY_ERR 0x0000002000000000ULL 105183423Smarius#define STX_PCI_CTRL_MMU_ERR 0x0000001000000000ULL 106183423Smarius#define SCZ_PCI_CTRL_SBH_ERR 0x0000000800000000ULL 107183423Smarius#define STX_PCI_CTRL_SERR 0x0000000400000000ULL 108183423Smarius#define SCZ_PCI_CTRL_PCISPD 0x0000000200000000ULL 109220038Smarius#define XMS_PCI_CTRL_X_MODE 0x0000000100000000ULL 110183423Smarius#define TOM_PCI_CTRL_PRM 0x0000000040000000ULL 111183423Smarius#define TOM_PCI_CTRL_PRO 0x0000000020000000ULL 112183423Smarius#define TOM_PCI_CTRL_PRL 0x0000000010000000ULL 113183423Smarius#define STX_PCI_CTRL_PTO 0x0000000003000000ULL 114220038Smarius#define XMS_PCI_CTRL_X_ERRINT_EN 0x0000000000100000ULL 115183423Smarius#define STX_PCI_CTRL_MMU_IEN 0x0000000000080000ULL 116183423Smarius#define STX_PCI_CTRL_SBH_IEN 0x0000000000040000ULL 117183423Smarius#define STX_PCI_CTRL_ERR_IEN 0x0000000000020000ULL 118183423Smarius#define STX_PCI_CTRL_ARB_PARK 0x0000000000010000ULL 119183423Smarius#define SCZ_PCI_CTRL_PCIRST 0x0000000000000100ULL 120183423Smarius#define STX_PCI_CTRL_ARB_MASK 0x00000000000000ffULL 121220038Smarius#define XMS_PCI_CTRL_XMITS10_ARB_MASK 0x000000000000000fULL 122183423Smarius 123183423Smarius/* PCI asynchronous fault status register */ 124183423Smarius#define STX_PCI_AFSR_P_MA 0x8000000000000000ULL 125183423Smarius#define STX_PCI_AFSR_P_TA 0x4000000000000000ULL 126183423Smarius#define STX_PCI_AFSR_P_RTRY 0x2000000000000000ULL 127183423Smarius#define STX_PCI_AFSR_P_PERR 0x1000000000000000ULL 128183423Smarius#define STX_PCI_AFSR_P_TTO 0x0800000000000000ULL 129183423Smarius#define STX_PCI_AFSR_P_UNUS 0x0400000000000000ULL 130183423Smarius#define STX_PCI_AFSR_S_MA 0x0200000000000000ULL 131183423Smarius#define STX_PCI_AFSR_S_TA 0x0100000000000000ULL 132183423Smarius#define STX_PCI_AFSR_S_RTRY 0x0080000000000000ULL 133183423Smarius#define STX_PCI_AFSR_S_PERR 0x0040000000000000ULL 134183423Smarius#define STX_PCI_AFSR_S_TTO 0x0020000000000000ULL 135183423Smarius#define STX_PCI_AFSR_S_UNUS 0x0010000000000000ULL 136183423Smarius#define STX_PCI_AFSR_DWMASK 0x0000030000000000ULL 137183423Smarius#define STX_PCI_AFSR_BMASK 0x000000ff00000000ULL 138183423Smarius#define STX_PCI_AFSR_BLK 0x0000000080000000ULL 139183423Smarius#define STX_PCI_AFSR_CFG 0x0000000040000000ULL 140183423Smarius#define STX_PCI_AFSR_MEM 0x0000000020000000ULL 141183423Smarius#define STX_PCI_AFSR_IO 0x0000000010000000ULL 142183423Smarius 143183423Smarius/* PCI diagnostic register */ 144183423Smarius#define SCZ_PCI_DIAG_BADECC_DIS 0x0000000000000400ULL 145183423Smarius#define STX_PCI_DIAG_BYPASS_DIS 0x0000000000000200ULL 146183423Smarius#define STX_PCI_DIAG_TTO_DIS 0x0000000000000100ULL 147183423Smarius#define SCZ_PCI_DIAG_RTRYARB_DIS 0x0000000000000080ULL 148183423Smarius#define STX_PCI_DIAG_RETRY_DIS 0x0000000000000040ULL 149183423Smarius#define STX_PCI_DIAG_INTRSYNC_DIS 0x0000000000000020ULL 150183423Smarius#define STX_PCI_DIAG_DMAPARITY_INV 0x0000000000000008ULL 151183423Smarius#define STX_PCI_DIAG_PIODPARITY_INV 0x0000000000000004ULL 152183423Smarius#define STX_PCI_DIAG_PIOAPARITY_INV 0x0000000000000002ULL 153183423Smarius 154183423Smarius/* Tomatillo I/O cache register */ 155183423Smarius#define TOM_PCI_IOC_PW 0x0000000000080000ULL 156183423Smarius#define TOM_PCI_IOC_PRM 0x0000000000040000ULL 157183423Smarius#define TOM_PCI_IOC_PRO 0x0000000000020000ULL 158183423Smarius#define TOM_PCI_IOC_PRL 0x0000000000010000ULL 159183423Smarius#define TOM_PCI_IOC_PRM_LEN 0x000000000000c000ULL 160183423Smarius#define TOM_PCI_IOC_PRM_LEN_SHIFT 14 161183423Smarius#define TOM_PCI_IOC_PRO_LEN 0x0000000000003000ULL 162183423Smarius#define TOM_PCI_IOC_PRO_LEN_SHIFT 12 163183423Smarius#define TOM_PCI_IOC_PRL_LEN 0x0000000000000c00ULL 164183423Smarius#define TOM_PCI_IOC_PRL_LEN_SHIFT 10 165183423Smarius#define TOM_PCI_IOC_PREF_OFF 0x0000000000000038ULL 166183423Smarius#define TOM_PCI_IOC_PREF_OFF_SHIFT 3 167183423Smarius#define TOM_PCI_IOC_CPRM 0x0000000000000004ULL 168183423Smarius#define TOM_PCI_IOC_CPRO 0x0000000000000002ULL 169183423Smarius#define TOM_PCI_IOC_CPRL 0x0000000000000001ULL 170183423Smarius 171220038Smarius/* XMITS PCI-X error status register */ 172220038Smarius#define XMS_PCI_X_ERR_STAT_P_SC_DSCRD 0x8000000000000000ULL 173220038Smarius#define XMS_PCI_X_ERR_STAT_P_SC_TTO 0x4000000000000000ULL 174220038Smarius#define XMS_PCI_X_ERR_STAT_P_SDSTAT 0x2000000000000000ULL 175220038Smarius#define XMS_PCI_X_ERR_STAT_P_SMMU 0x1000000000000000ULL 176220038Smarius#define XMS_PCI_X_ERR_STAT_P_CDSTAT 0x0800000000000000ULL 177220038Smarius#define XMS_PCI_X_ERR_STAT_P_CMMU 0x0400000000000000ULL 178220038Smarius#define XMS_PCI_X_ERR_STAT_S_SC_DSCRD 0x0080000000000000ULL 179220038Smarius#define XMS_PCI_X_ERR_STAT_S_SC_TTO 0x0040000000000000ULL 180220038Smarius#define XMS_PCI_X_ERR_STAT_S_SDSTAT 0x0020000000000000ULL 181220038Smarius#define XMS_PCI_X_ERR_STAT_S_SMMU 0x0010000000000000ULL 182220038Smarius#define XMS_PCI_X_ERR_STAT_S_CDSTAT 0x0008000000000000ULL 183220038Smarius#define XMS_PCI_X_ERR_STAT_S_CMMU 0x0004000000000000ULL 184220038Smarius#define XMS_PCI_X_ERR_STAT_PERR_RCV_IEN 0x0000000400000000ULL 185220038Smarius#define XMS_PCI_X_ERR_STAT_PERR_RCV 0x0000000200000000ULL 186220038Smarius#define XMS_PCI_X_ERR_STAT_SERR_ON_PERR 0x0000000100000000ULL 187220038Smarius 188220038Smarius/* XMITS PCI-X diagnostic register */ 189220038Smarius#define XMS_PCI_X_DIAG_DIS_FAIR 0x0000000000080000ULL 190220038Smarius#define XMS_PCI_X_DIAG_CRCQ_VALID 0x0000000000040000ULL 191220038Smarius#define XMS_PCI_X_DIAG_SRCQ_ONE 0x0000000000000200ULL 192220038Smarius#define XMS_PCI_X_DIAG_CRCQ_FLUSH 0x0000000000000100ULL 193220038Smarius#define XMS_PCI_X_DIAG_BUGCNTL_MASK 0x0000ffff00000000ULL 194220038Smarius#define XMS_PCI_X_DIAG_BUGCNTL_SHIFT 32 195220038Smarius#define XMS_PCI_X_DIAG_SRCQ_MASK 0x00000000000000ffULL 196220038Smarius 197183423Smarius/* Controller configuration and status registers */ 198183423Smarius/* Note that these are shared on Schizo but per-PBM on Tomatillo. */ 199183423Smarius#define STX_CTRL_BUS_ERRLOG 0x00018 200183423Smarius#define STX_CTRL_ECCCTRL 0x00020 201183423Smarius#define STX_CTRL_UE_AFSR 0x00030 202183423Smarius#define STX_CTRL_UE_AFAR 0x00038 203183423Smarius#define STX_CTRL_CE_AFSR 0x00040 204183423Smarius#define STX_CTRL_CE_AFAR 0x00048 205183423Smarius#define STX_CTRL_PERF 0x07000 206183423Smarius#define STX_CTRL_PERF_CNT 0x07008 207183423Smarius 208183423Smarius/* Safari/JBus error log register */ 209183423Smarius#define STX_CTRL_BUS_ERRLOG_BADCMD 0x4000000000000000ULL 210183423Smarius#define SCZ_CTRL_BUS_ERRLOG_SSMDIS 0x2000000000000000ULL 211183423Smarius#define SCZ_CTRL_BUS_ERRLOG_BADMA 0x1000000000000000ULL 212183423Smarius#define SCZ_CTRL_BUS_ERRLOG_BADMB 0x0800000000000000ULL 213183423Smarius#define SCZ_CTRL_BUS_ERRLOG_BADMC 0x0400000000000000ULL 214183423Smarius#define TOM_CTRL_BUS_ERRLOG_SNOOP_GR 0x0000000000200000ULL 215183423Smarius#define TOM_CTRL_BUS_ERRLOG_SNOOP_PCI 0x0000000000100000ULL 216183423Smarius#define TOM_CTRL_BUS_ERRLOG_SNOOP_RD 0x0000000000080000ULL 217183423Smarius#define TOM_CTRL_BUS_ERRLOG_SNOOP_RDS 0x0000000000020000ULL 218183423Smarius#define TOM_CTRL_BUS_ERRLOG_SNOOP_RDSA 0x0000000000010000ULL 219183423Smarius#define TOM_CTRL_BUS_ERRLOG_SNOOP_OWN 0x0000000000008000ULL 220183423Smarius#define TOM_CTRL_BUS_ERRLOG_SNOOP_RDO 0x0000000000004000ULL 221183423Smarius#define SCZ_CTRL_BUS_ERRLOG_CPU1PS 0x0000000000002000ULL 222183423Smarius#define TOM_CTRL_BUS_ERRLOG_WDATA_PERR 0x0000000000002000ULL 223183423Smarius#define SCZ_CTRL_BUS_ERRLOG_CPU1PB 0x0000000000001000ULL 224183423Smarius#define TOM_CTRL_BUS_ERRLOG_CTRL_PERR 0x0000000000001000ULL 225183423Smarius#define SCZ_CTRL_BUS_ERRLOG_CPU0PS 0x0000000000000800ULL 226183423Smarius#define TOM_CTRL_BUS_ERRLOG_SNOOP_ERR 0x0000000000000800ULL 227183423Smarius#define SCZ_CTRL_BUS_ERRLOG_CPU0PB 0x0000000000000400ULL 228183423Smarius#define TOM_CTRL_BUS_ERRLOG_JBUS_ILL_B 0x0000000000000400ULL 229183423Smarius#define SCZ_CTRL_BUS_ERRLOG_CIQTO 0x0000000000000200ULL 230183423Smarius#define SCZ_CTRL_BUS_ERRLOG_LPQTO 0x0000000000000100ULL 231183423Smarius#define TOM_CTRL_BUS_ERRLOG_JBUS_ILL_C 0x0000000000000100ULL 232183423Smarius#define SCZ_CTRL_BUS_ERRLOG_SFPQTO 0x0000000000000080ULL 233183423Smarius#define SCZ_CTRL_BUS_ERRLOG_UFPQTO 0x0000000000000040ULL 234183423Smarius#define TOM_CTRL_BUS_ERRLOG_RD_PERR 0x0000000000000040ULL 235183423Smarius#define STX_CTRL_BUS_ERRLOG_APERR 0x0000000000000020ULL 236183423Smarius#define STX_CTRL_BUS_ERRLOG_UNMAP 0x0000000000000010ULL 237183423Smarius#define STX_CTRL_BUS_ERRLOG_BUSERR 0x0000000000000004ULL 238183423Smarius#define STX_CTRL_BUS_ERRLOG_TIMEOUT 0x0000000000000002ULL 239183423Smarius#define SCZ_CTRL_BUS_ERRLOG_ILL 0x0000000000000001ULL 240183423Smarius 241183423Smarius/* ECC control register */ 242183423Smarius#define STX_CTRL_ECCCTRL_EE 0x8000000000000000ULL 243183423Smarius#define STX_CTRL_ECCCTRL_UE 0x4000000000000000ULL 244183423Smarius#define STX_CTRL_ECCCTRL_CE 0x2000000000000000ULL 245183423Smarius 246183423Smarius/* Uncorrectable error asynchronous fault status register */ 247183423Smarius#define STX_CTRL_UE_AFSR_P_PIO 0x8000000000000000ULL 248183423Smarius#define STX_CTRL_UE_AFSR_P_DRD 0x4000000000000000ULL 249183423Smarius#define STX_CTRL_UE_AFSR_P_DWR 0x2000000000000000ULL 250183423Smarius#define STX_CTRL_UE_AFSR_S_PIO 0x1000000000000000ULL 251183423Smarius#define STX_CTRL_UE_AFSR_S_DRD 0x0800000000000000ULL 252183423Smarius#define STX_CTRL_UE_AFSR_S_DWR 0x0400000000000000ULL 253183423Smarius#define STX_CTRL_UE_AFSR_ERRPNDG 0x0300000000000000ULL 254183423Smarius#define STX_CTRL_UE_AFSR_BMASK 0x000003ff00000000ULL 255183423Smarius#define STX_CTRL_UE_AFSR_QOFF 0x00000000c0000000ULL 256183423Smarius#define STX_CTRL_UE_AFSR_AID 0x000000001f000000ULL 257183423Smarius#define STX_CTRL_UE_AFSR_PARTIAL 0x0000000000800000ULL 258183423Smarius#define STX_CTRL_UE_AFSR_OWNEDIN 0x0000000000400000ULL 259183423Smarius#define STX_CTRL_UE_AFSR_MTAGSYND 0x00000000000f0000ULL 260183423Smarius#define STX_CTRL_UE_AFSR_MTAG 0x000000000000e000ULL 261183423Smarius#define STX_CTRL_UE_AFSR_ECCSYND 0x00000000000001ffULL 262183423Smarius 263183423Smarius/* Correctable error asynchronous fault status register */ 264183423Smarius#define STX_CTRL_CE_AFSR_P_PIO 0x8000000000000000ULL 265183423Smarius#define STX_CTRL_CE_AFSR_P_DRD 0x4000000000000000ULL 266183423Smarius#define STX_CTRL_CE_AFSR_P_DWR 0x2000000000000000ULL 267183423Smarius#define STX_CTRL_CE_AFSR_S_PIO 0x1000000000000000ULL 268183423Smarius#define STX_CTRL_CE_AFSR_S_DRD 0x0800000000000000ULL 269183423Smarius#define STX_CTRL_CE_AFSR_S_DWR 0x0400000000000000ULL 270183423Smarius#define STX_CTRL_CE_AFSR_ERRPNDG 0x0300000000000000ULL 271183423Smarius#define STX_CTRL_CE_AFSR_BMASK 0x000003ff00000000ULL 272183423Smarius#define STX_CTRL_CE_AFSR_QOFF 0x00000000c0000000ULL 273183423Smarius#define STX_CTRL_CE_AFSR_AID 0x000000001f000000ULL 274183423Smarius#define STX_CTRL_CE_AFSR_PARTIAL 0x0000000000800000ULL 275183423Smarius#define STX_CTRL_CE_AFSR_OWNEDIN 0x0000000000400000ULL 276183423Smarius#define STX_CTRL_CE_AFSR_MTAGSYND 0x00000000000f0000ULL 277183423Smarius#define STX_CTRL_CE_AFSR_MTAG 0x000000000000e000ULL 278183423Smarius#define STX_CTRL_CE_AFSR_ECCSYND 0x00000000000001ffULL 279183423Smarius 280183423Smarius/* 281183423Smarius * Safari/JBus performance control register 282183423Smarius * NB: for Tomatillo only events 0x00 through 0x08 are documented as 283183423Smarius * implemented. 284183423Smarius */ 285183423Smarius#define SCZ_CTRL_PERF_ZDATA_OUT 0x0000000000000016ULL 286183423Smarius#define SCZ_CTRL_PERF_ZDATA_IN 0x0000000000000015ULL 287183423Smarius#define SCZ_CTRL_PERF_ORQFULL 0x0000000000000014ULL 288183423Smarius#define SCZ_CTRL_PERF_DVMA_WR 0x0000000000000013ULL 289183423Smarius#define SCZ_CTRL_PERF_DVMA_RD 0x0000000000000012ULL 290183423Smarius#define SCZ_CTRL_PERF_CYCPSESYS 0x0000000000000011ULL 291183423Smarius#define STX_CTRL_PERF_PCI_B 0x000000000000000fULL 292183423Smarius#define STX_CTRL_PERF_PCI_A 0x000000000000000eULL 293183423Smarius#define STX_CTRL_PERF_UPA 0x000000000000000dULL 294183423Smarius#define STX_CTRL_PERF_PIOINTRNL 0x000000000000000cULL 295183423Smarius#define TOM_CTRL_PERF_WRI_WRIS 0x000000000000000bULL 296183423Smarius#define STX_CTRL_PERF_INTRS 0x000000000000000aULL 297183423Smarius#define STX_CTRL_PERF_PRTLWRMRGBUF 0x0000000000000009ULL 298183423Smarius#define STX_CTRL_PERF_FGN_IO_HITS 0x0000000000000008ULL 299183423Smarius#define STX_CTRL_PERF_FGN_IO_TRNS 0x0000000000000007ULL 300183423Smarius#define STX_CTRL_PERF_OWN_CHRNT_HITS 0x0000000000000006ULL 301183423Smarius#define STX_CTRL_PERF_OWN_CHRNT_TRNS 0x0000000000000005ULL 302183423Smarius#define SCZ_CTRL_PERF_FGN_CHRNT_HITS 0x0000000000000004ULL 303183423Smarius#define STX_CTRL_PERF_FGN_CHRNT_TRNS 0x0000000000000003ULL 304183423Smarius#define STX_CTRL_PERF_CYCLES_PAUSE 0x0000000000000002ULL 305183423Smarius#define STX_CTRL_PERF_BUSCYC 0x0000000000000001ULL 306183423Smarius#define STX_CTRL_PERF_DIS 0x0000000000000000ULL 307183423Smarius#define STX_CTRL_PERF_CNT1_SHIFT 11 308183423Smarius#define STX_CTRL_PERF_CNT0_SHIFT 4 309183423Smarius 310183423Smarius/* Safari/JBus performance counter register */ 311183423Smarius#define STX_CTRL_PERF_CNT_MASK 0x00000000ffffffffULL 312183423Smarius#define STX_CTRL_PERF_CNT_CNT1_SHIFT 32 313183423Smarius#define STX_CTRL_PERF_CNT_CNT0_SHIFT 0 314183423Smarius 315183423Smarius/* INO defines */ 316183423Smarius#define STX_FB0_INO 0x2a /* FB0 int. shared w/ UPA64s */ 317183423Smarius#define STX_FB1_INO 0x2b /* FB1 int. shared w/ UPA64s */ 318183423Smarius#define STX_UE_INO 0x30 /* uncorrectable error */ 319183423Smarius#define STX_CE_INO 0x31 /* correctable error */ 320183423Smarius#define STX_PCIERR_A_INO 0x32 /* PCI bus A error */ 321183423Smarius#define STX_PCIERR_B_INO 0x33 /* PCI bus B error */ 322183423Smarius#define STX_BUS_INO 0x34 /* Safari/JBus error */ 323185133Smarius#define STX_CDMA_A_INO 0x35 /* PCI bus A CDMA */ 324185133Smarius#define STX_CDMA_B_INO 0x36 /* PCI bus B CDMA */ 325183423Smarius#define STX_MAX_INO 0x37 326183423Smarius 327183423Smarius/* Device space defines */ 328183423Smarius#define STX_CONF_SIZE 0x1000000 329183423Smarius#define STX_CONF_BUS_SHIFT 16 330183423Smarius#define STX_CONF_DEV_SHIFT 11 331183423Smarius#define STX_CONF_FUNC_SHIFT 8 332183423Smarius#define STX_CONF_REG_SHIFT 0 333183423Smarius#define STX_IO_SIZE 0x1000000 334183423Smarius#define STX_MEM_SIZE 0x100000000 335183423Smarius 336183423Smarius#define STX_CONF_OFF(bus, slot, func, reg) \ 337183423Smarius (((bus) << STX_CONF_BUS_SHIFT) | \ 338183423Smarius ((slot) << STX_CONF_DEV_SHIFT) | \ 339183423Smarius ((func) << STX_CONF_FUNC_SHIFT) | \ 340183423Smarius ((reg) << STX_CONF_REG_SHIFT)) 341183423Smarius 342183423Smarius/* Definitions for the Schizo/Tomatillo configuration space */ 343183423Smarius#define STX_CS_DEVICE 0 /* bridge CS device number */ 344183423Smarius#define STX_CS_FUNC 0 /* brdige CS function number */ 345183423Smarius 346183423Smarius/* Non-Standard registers in the configration space */ 347183423Smarius/* 348183423Smarius * NB: for Tomatillo the secondary and subordinate bus number registers 349183423Smarius * apparently are read-only although documented otherwise; writing to 350183423Smarius * them just triggers a PCI bus error interrupt or has no effect at best. 351183423Smarius */ 352183423Smarius#define STX_CSR_SECBUS 0x40 /* secondary bus number */ 353183423Smarius#define STX_CSR_SUBBUS 0x41 /* subordinate bus number */ 354183423Smarius 355183423Smarius/* Width of the physical addresses the IOMMU translates to */ 356183423Smarius#define STX_IOMMU_BITS 43 357183423Smarius 358183423Smarius#endif /* !_SPARC64_PCI_SCHIZOREG_H_ */ 359