ofw_pcib_subr.c revision 163260 
1/*-
2 * Copyright (c) 2003 by Thomas Moestl <tmm@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
21 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
23 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26#include <sys/cdefs.h>
27__FBSDID("$FreeBSD: head/sys/sparc64/pci/ofw_pcib_subr.c 163260 2006-10-12 04:44:01Z kmacy $");
28
29#include "opt_ofw_pci.h"
30#include "opt_global.h"
31
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/bus.h>
35
36#include <dev/ofw/ofw_bus.h>
37#include <dev/ofw/ofw_pci.h>
38#include <dev/ofw/openfirm.h>
39
40#include <machine/bus.h>
41#include <machine/ofw_bus.h>
42
43#include <dev/pci/pcireg.h>
44#include <dev/pci/pcivar.h>
45#include <dev/pci/pcib_private.h>
46
47#include "pcib_if.h"
48
49#include <sparc64/pci/ofw_pci.h>
50#include <sparc64/pci/ofw_pcib_subr.h>
51
52void
53ofw_pcib_gen_setup(device_t bridge)
54{
55	struct ofw_pcib_gen_softc *sc;
56#ifndef SUN4V
57	u_int secbus;
58
59#endif
60	sc = device_get_softc(bridge);
61	sc->ops_pcib_sc.dev = bridge;
62	sc->ops_node = ofw_bus_get_node(bridge);
63	KASSERT(sc->ops_node != 0,
64	    ("ofw_pcib_gen_setup: no ofw pci parent bus!"));
65
66	/*
67	 * Setup the secondary bus number register, by allocating a new unique
68	 * bus number for it; the firmware preset does not always seem to be
69	 * correct.
70	 */
71#ifndef SUN4V
72	secbus = ofw_pci_alloc_busno(sc->ops_node);
73	pci_write_config(bridge, PCIR_PRIBUS_1, pci_get_bus(bridge), 1);
74	pci_write_config(bridge, PCIR_SECBUS_1, secbus, 1);
75	pci_write_config(bridge, PCIR_SUBBUS_1, secbus, 1);
76	sc->ops_pcib_sc.subbus = sc->ops_pcib_sc.secbus = secbus;
77	/* Notify parent bridges. */
78	OFW_PCI_ADJUST_BUSRANGE(device_get_parent(bridge), secbus);
79
80#endif
81	ofw_bus_setup_iinfo(sc->ops_node, &sc->ops_iinfo,
82	    sizeof(ofw_pci_intr_t));
83}
84
85int
86ofw_pcib_gen_route_interrupt(device_t bridge, device_t dev, int intpin)
87{
88	struct ofw_pcib_gen_softc *sc;
89	struct ofw_bus_iinfo *ii;
90	struct ofw_pci_register reg;
91	ofw_pci_intr_t pintr, mintr;
92	uint8_t maskbuf[sizeof(reg) + sizeof(pintr)];
93
94	sc = device_get_softc(bridge);
95	ii = &sc->ops_iinfo;
96	if (ii->opi_imapsz > 0) {
97		pintr = intpin;
98		if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), ii, &reg,
99		    sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr),
100		    maskbuf)) {
101			/*
102			 * If we've found a mapping, return it and don't map
103			 * it again on higher levels - that causes problems
104			 * in some cases, and never seems to be required.
105			 */
106			return (mintr);
107		}
108	} else if (intpin >= 1 && intpin <= 4) {
109		/*
110		 * When an interrupt map is missing, we need to do the
111		 * standard PCI swizzle and continue mapping at the parent.
112		 */
113		return (pcib_route_interrupt(bridge, dev, intpin));
114	}
115	/* Try at the parent. */
116	return (PCIB_ROUTE_INTERRUPT(device_get_parent(device_get_parent(
117	    bridge)), bridge, intpin));
118}
119
120phandle_t
121ofw_pcib_gen_get_node(device_t bridge, device_t dev)
122{
123	struct ofw_pcib_gen_softc *sc;
124
125	sc = device_get_softc(bridge);
126	return (sc->ops_node);
127}
128
129void
130ofw_pcib_gen_adjust_busrange(device_t bridge, u_int subbus)
131{
132	struct ofw_pcib_gen_softc *sc;
133
134	sc = device_get_softc(bridge);
135	if (subbus > sc->ops_pcib_sc.subbus) {
136#ifdef OFW_PCI_DEBUG
137		device_printf(bridge,
138		    "adjusting secondary bus number from %d to %d\n",
139		    sc->ops_pcib_sc.subbus, subbus);
140#endif
141		pci_write_config(bridge, PCIR_SUBBUS_1, subbus, 1);
142		sc->ops_pcib_sc.subbus = subbus;
143		/* Notify parent bridges. */
144		OFW_PCI_ADJUST_BUSRANGE(device_get_parent(bridge), subbus);
145	}
146}
147