ofw_pcib_subr.c revision 119291
1/*- 2 * Copyright (c) 2003 by Thomas Moestl <tmm@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 21 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 23 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 * 25 * $FreeBSD: head/sys/sparc64/pci/ofw_pcib_subr.c 117119 2003-07-01 14:52:47Z tmm $ 26 */ 27 28#include "opt_ofw_pci.h" 29#include <sys/param.h> 30#include <sys/systm.h> 31#include <sys/bus.h> 32 33#include <dev/ofw/openfirm.h> 34#include <dev/ofw/ofw_pci.h> 35 36#include <machine/bus.h> 37#include <machine/ofw_bus.h> 38 39#include <dev/pci/pcireg.h> 40#include <dev/pci/pcivar.h> 41#include <dev/pci/pcib_private.h> 42 43#include "pcib_if.h" 44 45#include <sparc64/pci/ofw_pci.h> 46#include <sparc64/pci/ofw_pcib_subr.h> 47 48void 49ofw_pcib_gen_setup(device_t bridge) 50{ 51 struct ofw_pcib_gen_softc *sc = device_get_softc(bridge); 52 u_int secbus; 53 54 sc->ops_pcib_sc.dev = bridge; 55 sc->ops_node = ofw_pci_get_node(bridge); 56 KASSERT(sc->ops_node != 0, 57 ("ofw_pcib_gen_setup: no ofw pci parent bus!")); 58 59 /* 60 * Setup the secondary bus number register, by allocating a new unique 61 * bus number for it; the firmware preset does not always seem to be 62 * correct. 63 */ 64 secbus = ofw_pci_alloc_busno(sc->ops_node); 65 pci_write_config(bridge, PCIR_PRIBUS_1, pci_get_bus(bridge), 1); 66 pci_write_config(bridge, PCIR_SECBUS_1, secbus, 1); 67 pci_write_config(bridge, PCIR_SUBBUS_1, secbus, 1); 68 sc->ops_pcib_sc.subbus = sc->ops_pcib_sc.secbus = secbus; 69 /* Notify parent bridges. */ 70 OFW_PCI_ADJUST_BUSRANGE(device_get_parent(bridge), secbus); 71 72 ofw_bus_setup_iinfo(sc->ops_node, &sc->ops_iinfo, 73 sizeof(ofw_pci_intr_t)); 74} 75 76int 77ofw_pcib_gen_route_interrupt(device_t bridge, device_t dev, int intpin) 78{ 79 struct ofw_pcib_gen_softc *sc = device_get_softc(bridge); 80 struct ofw_bus_iinfo *ii = &sc->ops_iinfo; 81 struct ofw_pci_register reg; 82 device_t pbridge = device_get_parent(device_get_parent(bridge)); 83 phandle_t node = ofw_pci_get_node(dev); 84 ofw_pci_intr_t pintr, mintr; 85 u_int8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 86 87 if (ii->opi_imapsz > 0) { 88 pintr = intpin; 89 if (ofw_bus_lookup_imap(node, ii, ®, sizeof(reg), &pintr, 90 sizeof(pintr), &mintr, sizeof(mintr), maskbuf)) { 91 /* 92 * If we've found a mapping, return it and don't map 93 * it again on higher levels - that causes problems 94 * in some cases, and never seems to be required. 95 */ 96 return (mintr); 97 } 98 } else if (intpin >= 1 && intpin <= 4) { 99 /* 100 * When an interrupt map is missing, we need to do the 101 * standard PCI swizzle and continue mapping at the parent. 102 */ 103 return (pcib_route_interrupt(bridge, dev, intpin)); 104 } 105 /* Try at the parent. */ 106 return (PCIB_ROUTE_INTERRUPT(pbridge, bridge, intpin)); 107} 108 109phandle_t 110ofw_pcib_gen_get_node(device_t bridge, device_t dev) 111{ 112 struct ofw_pcib_gen_softc *sc = device_get_softc(bridge); 113 114 return (sc->ops_node); 115} 116 117void 118ofw_pcib_gen_adjust_busrange(device_t bridge, u_int subbus) 119{ 120 struct ofw_pcib_gen_softc *sc = device_get_softc(bridge); 121 122 if (subbus > sc->ops_pcib_sc.subbus) { 123#ifdef OFW_PCI_DEBUG 124 device_printf(bridge, 125 "adjusting secondary bus number from %d to %d\n", 126 sc->ops_pcib_sc.subbus, subbus); 127#endif 128 pci_write_config(bridge, PCIR_SUBBUS_1, subbus, 1); 129 sc->ops_pcib_sc.subbus = subbus; 130 /* Notify parent bridges. */ 131 OFW_PCI_ADJUST_BUSRANGE(device_get_parent(bridge), subbus); 132 } 133} 134 135