1182768Smarius/*- 2182768Smarius * Copyright (c) 2008 Marius Strobl <marius@FreeBSD.org> 3182768Smarius * All rights reserved. 4182768Smarius * 5182768Smarius * Redistribution and use in source and binary forms, with or without 6182768Smarius * modification, are permitted provided that the following conditions 7182768Smarius * are met: 8182768Smarius * 1. Redistributions of source code must retain the above copyright 9182768Smarius * notice, this list of conditions and the following disclaimer. 10182768Smarius * 2. Redistributions in binary form must reproduce the above copyright 11182768Smarius * notice, this list of conditions and the following disclaimer in the 12182768Smarius * documentation and/or other materials provided with the distribution. 13182768Smarius * 14182768Smarius * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15182768Smarius * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16182768Smarius * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17182768Smarius * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18182768Smarius * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19182768Smarius * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20182768Smarius * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21182768Smarius * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22182768Smarius * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23182768Smarius * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24182768Smarius * SUCH DAMAGE. 25182768Smarius * 26182768Smarius * $FreeBSD$ 27182768Smarius */ 28182768Smarius 29182768Smarius#ifndef _MACHINE_DCR_H_ 30182768Smarius#define _MACHINE_DCR_H_ 31182768Smarius 32182768Smarius/* 33182768Smarius * Definitions for the UltraSPARC-III Depatch Control Register (ASR 18). 34182768Smarius */ 35182768Smarius#define DCR_MS (1UL << 0) 36182768Smarius#define DCR_IFPOE (1UL << 1) 37182768Smarius#define DCR_SI (1UL << 3) 38182768Smarius#define DCR_RPE (1UL << 4) 39182768Smarius#define DCR_BPE (1UL << 5) 40182768Smarius 41182768Smarius#define DCR_OBSDATA_SHIFT 6 42182768Smarius#define DCR_OBSDATA_CT_BITS 8 43182768Smarius#define DCR_OBSDATA_CT_MASK \ 44182768Smarius (((1UL << DCR_OBSDATA_CT_BITS) - 1) << DCR_OBSDATA_SHIFT) 45182768Smarius 46206450Smarius/* The following bits are valid for the UltraSPARC-III++/IV+ only. */ 47206450Smarius#define DCR_IPE (1UL << 2) 48182768Smarius 49182768Smarius#define DCR_OBSDATA_CTP_BITS 6 50182768Smarius#define DCR_OBSDATA_CTP_MASK \ 51182768Smarius (((1UL << DCR_OBSDATA_CTP_BITS) - 1) << DCR_OBSDATA_SHIFT) 52182768Smarius 53182768Smarius#define DCR_DPE (1UL << 12) 54182768Smarius 55182768Smarius/* The following bits are valid for the UltraSPARC-IV+ only. */ 56182768Smarius#define DCR_BPM_SHIFT 13 57182768Smarius#define DCR_BPM_BITS 2 58182768Smarius#define DCR_BPM_MASK \ 59182768Smarius (((1UL << DCR_BPM_BITS) - 1) << DCR_BPM_SHIFT) 60205269Smarius#define DCR_BPM_1HIST_GSHARE (0UL << DCR_BPM_SHIFT) 61205269Smarius#define DCR_BPM_2HIST_GSHARE (1UL << DCR_BPM_SHIFT) 62205269Smarius#define DCR_BPM_PC (2UL << DCR_BPM_SHIFT) 63205269Smarius#define DCR_BPM_2HIST_MIXED (3UL << DCR_BPM_SHIFT) 64182768Smarius 65182768Smarius#define DCR_JPE (1UL << 15) 66182768Smarius#define DCR_ITPE (1UL << 16) 67182768Smarius#define DCR_DTPE (1UL << 17) 68182768Smarius#define DCR_PPE (1UL << 18) 69182768Smarius 70182768Smarius#endif /* _MACHINE_DCR_H_ */ 71