1139825Simp/*- 299663Sbenno * Copyright (C) 2002 Benno Rice. 399663Sbenno * All rights reserved. 499663Sbenno * 599663Sbenno * Redistribution and use in source and binary forms, with or without 699663Sbenno * modification, are permitted provided that the following conditions 799663Sbenno * are met: 899663Sbenno * 1. Redistributions of source code must retain the above copyright 999663Sbenno * notice, this list of conditions and the following disclaimer. 1099663Sbenno * 2. Redistributions in binary form must reproduce the above copyright 1199663Sbenno * notice, this list of conditions and the following disclaimer in the 1299663Sbenno * documentation and/or other materials provided with the distribution. 1399663Sbenno * 1499663Sbenno * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 1599663Sbenno * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1699663Sbenno * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1799663Sbenno * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 1899663Sbenno * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 1999663Sbenno * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 2099663Sbenno * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 2199663Sbenno * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 2299663Sbenno * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 2399663Sbenno * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2499663Sbenno * 2599663Sbenno * $FreeBSD$ 2699663Sbenno */ 2799663Sbenno 2899663Sbenno#ifndef _POWERPC_POWERMAC_UNINORTHVAR_H_ 2999663Sbenno#define _POWERPC_POWERMAC_UNINORTHVAR_H_ 3099663Sbenno 31235060Snwhitehorn#include <powerpc/ofw/ofw_pci.h> 3299663Sbenno 3399663Sbennostruct uninorth_softc { 34235060Snwhitehorn struct ofw_pci_softc pci_sc; 3599663Sbenno vm_offset_t sc_addr; 3699663Sbenno vm_offset_t sc_data; 37208149Snwhitehorn int sc_ver; 3899663Sbenno}; 3999663Sbenno 40103618Sgrehanstruct unin_chip_softc { 41208149Snwhitehorn u_int32_t sc_physaddr; 42103618Sgrehan vm_offset_t sc_addr; 43208149Snwhitehorn u_int32_t sc_size; 44208149Snwhitehorn struct rman sc_mem_rman; 45103618Sgrehan int sc_version; 46103618Sgrehan}; 47103618Sgrehan 48103618Sgrehan/* 49208149Snwhitehorn * Format of a unin reg property entry. 50208149Snwhitehorn */ 51208149Snwhitehornstruct unin_chip_reg { 52208149Snwhitehorn u_int32_t mr_base; 53208149Snwhitehorn u_int32_t mr_size; 54208149Snwhitehorn}; 55208149Snwhitehorn 56208149Snwhitehorn/* 57208149Snwhitehorn * Per unin device structure. 58208149Snwhitehorn */ 59208149Snwhitehornstruct unin_chip_devinfo { 60208149Snwhitehorn int udi_interrupts[6]; 61208149Snwhitehorn int udi_ninterrupts; 62208149Snwhitehorn int udi_base; 63208149Snwhitehorn struct ofw_bus_devinfo udi_obdinfo; 64208149Snwhitehorn struct resource_list udi_resources; 65208149Snwhitehorn}; 66208149Snwhitehorn 67208149Snwhitehorn/* 68103618Sgrehan * Version register 69103618Sgrehan */ 70103618Sgrehan#define UNIN_VERS 0x0 71103618Sgrehan 72103618Sgrehan/* 73103618Sgrehan * Clock-control register 74103618Sgrehan */ 75208149Snwhitehorn#define UNIN_CLOCKCNTL 0x20 76208149Snwhitehorn#define UNIN_CLOCKCNTL_GMAC 0x2 77103618Sgrehan 78208149Snwhitehorn/* 79208149Snwhitehorn * Toggle registers 80208149Snwhitehorn */ 81208149Snwhitehorn#define UNIN_TOGGLE_REG 0xe0 82208149Snwhitehorn#define UNIN_MPIC_RESET 0x2 83208149Snwhitehorn#define UNIN_MPIC_OUTPUT_ENABLE 0x4 84208149Snwhitehorn 85103618Sgrehan#endif /* _POWERPC_POWERMAC_UNINORTHVAR_H_ */ 86