1139825Simp/*- 2116965Sgrehan * Copyright 2003 by Peter Grehan. All rights reserved. 3116965Sgrehan * 4116965Sgrehan * Redistribution and use in source and binary forms, with or without 5116965Sgrehan * modification, are permitted provided that the following conditions 6116965Sgrehan * are met: 7116965Sgrehan * 1. Redistributions of source code must retain the above copyright 8116965Sgrehan * notice, this list of conditions and the following disclaimer. 9116965Sgrehan * 2. Redistributions in binary form must reproduce the above copyright 10116965Sgrehan * notice, this list of conditions and the following disclaimer in the 11116965Sgrehan * documentation and/or other materials provided with the distribution. 12116965Sgrehan * 3. The name of the author may not be used to endorse or promote products 13116965Sgrehan * derived from this software without specific prior written permission. 14116965Sgrehan * 15116965Sgrehan * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16116965Sgrehan * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17116965Sgrehan * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18116965Sgrehan * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19116965Sgrehan * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20116965Sgrehan * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21116965Sgrehan * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22116965Sgrehan * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23116965Sgrehan * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24116965Sgrehan * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25116965Sgrehan * SUCH DAMAGE. 26116965Sgrehan * 27116965Sgrehan * $FreeBSD$ 28116965Sgrehan */ 29116965Sgrehan 30116965Sgrehan#ifndef _POWERPC_POWERMAC_HROWPICVAR_H_ 31116965Sgrehan#define _POWERPC_POWERMAC_HROWPICVAR_H_ 32116965Sgrehan 33116965Sgrehan#define HROWPIC_IRQMAX 64 34116965Sgrehan#define HROWPIC_IRQ_REGNUM 32 /* irqs per register */ 35116965Sgrehan#define HROWPIC_IRQ_SHIFT 5 /* high or low irq word */ 36116965Sgrehan#define HROWPIC_IRQ_MASK ((HROWPIC_IRQMAX-1) >> 1) /* irq bit pos in word */ 37116965Sgrehan 38116965Sgrehan/* 39116965Sgrehan * Register offsets within bank. There are two identical banks, 40116965Sgrehan * separated by 16 bytes. Interrupts 0->31 are processed in the 41116965Sgrehan * second bank, and 32->63 in the first bank. 42116965Sgrehan */ 43116965Sgrehan#define HPIC_STATUS 0x00 /* active interrupt sources */ 44116965Sgrehan#define HPIC_ENABLE 0x04 /* interrupt asserts ppc EXTINT */ 45116965Sgrehan#define HPIC_CLEAR 0x08 /* clear int source */ 46116965Sgrehan#define HPIC_TRIGGER 0x0c /* edge/level int trigger */ 47116965Sgrehan 48116965Sgrehan#define HPIC_PRIMARY 1 /* primary register bank */ 49116965Sgrehan#define HPIC_SECONDARY 0 /* secondary register bank */ 50116965Sgrehan 51116965Sgrehan/* 52116965Sgrehan * Convert an interrupt into a prim/sec bank number 53116965Sgrehan */ 54116965Sgrehan#define HPIC_INT_TO_BANK(x) \ 55116965Sgrehan (((x) >> HROWPIC_IRQ_SHIFT) ^ 1) 56116965Sgrehan 57116965Sgrehan/* 58116965Sgrehan * Convert an interrupt into the bit number within a bank register 59116965Sgrehan */ 60116965Sgrehan#define HPIC_INT_TO_REGBIT(x) \ 61116965Sgrehan ((x) & HROWPIC_IRQ_MASK) 62116965Sgrehan 63116965Sgrehan#define HPIC_1ST_OFFSET 0x10 /* offset to primary reg bank */ 64116965Sgrehan 65116965Sgrehanstruct hrowpic_softc { 66171805Smarcel device_t sc_dev; /* macio device */ 67171805Smarcel struct resource *sc_rres; /* macio bus resource */ 68116965Sgrehan bus_space_tag_t sc_bt; /* macio bus tag/handle */ 69116965Sgrehan bus_space_handle_t sc_bh; 70171805Smarcel int sc_rrid; 71171805Smarcel uint32_t sc_softreg[2]; /* ENABLE reg copy */ 72171805Smarcel u_int sc_vector[HROWPIC_IRQMAX]; 73116965Sgrehan}; 74116965Sgrehan 75116965Sgrehan#endif /* _POWERPC_POWERMAC_HROWPICVAR_H_ */ 76