cuda.c revision 267654
140516Swpaul/*- 240516Swpaul * Copyright (c) 2006 Michael Lorenz 340516Swpaul * Copyright 2008 by Nathan Whitehorn 440516Swpaul * All rights reserved. 540516Swpaul * 640516Swpaul * Redistribution and use in source and binary forms, with or without 740516Swpaul * modification, are permitted provided that the following conditions 840516Swpaul * are met: 940516Swpaul * 1. Redistributions of source code must retain the above copyright 1040516Swpaul * notice, this list of conditions and the following disclaimer. 1140516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1240516Swpaul * notice, this list of conditions and the following disclaimer in the 1340516Swpaul * documentation and/or other materials provided with the distribution. 1440516Swpaul * 3. The name of the author may not be used to endorse or promote products 1540516Swpaul * derived from this software without specific prior written permission. 1640516Swpaul * 1740516Swpaul * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1840516Swpaul * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1940516Swpaul * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2040516Swpaul * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2140516Swpaul * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 2240516Swpaul * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 2340516Swpaul * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 2440516Swpaul * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 2540516Swpaul * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2640516Swpaul * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2740516Swpaul * SUCH DAMAGE. 2840516Swpaul * 2940516Swpaul */ 3040516Swpaul 3140516Swpaul#include <sys/cdefs.h> 3250477Speter__FBSDID("$FreeBSD: releng/9.3/sys/powerpc/powermac/cuda.c 229093 2011-12-31 14:12:12Z hselasky $"); 3340516Swpaul 3440516Swpaul#include <sys/param.h> 3540516Swpaul#include <sys/systm.h> 3640516Swpaul#include <sys/module.h> 3740516Swpaul#include <sys/bus.h> 3840516Swpaul#include <sys/conf.h> 3940516Swpaul#include <sys/kernel.h> 4040516Swpaul#include <sys/clock.h> 4140516Swpaul#include <sys/reboot.h> 4240516Swpaul 4340516Swpaul#include <dev/ofw/ofw_bus.h> 4440516Swpaul#include <dev/ofw/openfirm.h> 4540516Swpaul 4640516Swpaul#include <machine/bus.h> 4740516Swpaul#include <machine/intr_machdep.h> 4840516Swpaul#include <machine/md_var.h> 4940516Swpaul#include <machine/pio.h> 5040516Swpaul#include <machine/resource.h> 5140516Swpaul 5240516Swpaul#include <vm/vm.h> 5340516Swpaul#include <vm/pmap.h> 5440516Swpaul 5540516Swpaul#include <sys/rman.h> 5641569Swpaul 5740516Swpaul#include <dev/adb/adb.h> 5840516Swpaul 5940516Swpaul#include "clock_if.h" 6040516Swpaul#include "cudavar.h" 6140516Swpaul#include "viareg.h" 6240516Swpaul 6340516Swpaul/* 6440516Swpaul * MacIO interface 6540516Swpaul */ 6640516Swpaulstatic int cuda_probe(device_t); 6740516Swpaulstatic int cuda_attach(device_t); 6840516Swpaulstatic int cuda_detach(device_t); 6940516Swpaul 7040516Swpaulstatic u_int cuda_adb_send(device_t dev, u_char command_byte, int len, 7140516Swpaul u_char *data, u_char poll); 7240516Swpaulstatic u_int cuda_adb_autopoll(device_t dev, uint16_t mask); 7340516Swpaulstatic u_int cuda_poll(device_t dev); 7440516Swpaulstatic void cuda_send_inbound(struct cuda_softc *sc); 7540516Swpaulstatic void cuda_send_outbound(struct cuda_softc *sc); 7640516Swpaulstatic void cuda_shutdown(void *xsc, int howto); 7740516Swpaul 7840516Swpaul/* 7940516Swpaul * Clock interface 8040516Swpaul */ 8140516Swpaulstatic int cuda_gettime(device_t dev, struct timespec *ts); 8240516Swpaulstatic int cuda_settime(device_t dev, struct timespec *ts); 8340516Swpaul 8440516Swpaulstatic device_method_t cuda_methods[] = { 8540516Swpaul /* Device interface */ 8640516Swpaul DEVMETHOD(device_probe, cuda_probe), 87108729Sjake DEVMETHOD(device_attach, cuda_attach), 8840516Swpaul DEVMETHOD(device_detach, cuda_detach), 8940516Swpaul DEVMETHOD(device_shutdown, bus_generic_shutdown), 9040516Swpaul DEVMETHOD(device_suspend, bus_generic_suspend), 9140516Swpaul DEVMETHOD(device_resume, bus_generic_resume), 9240516Swpaul 9340516Swpaul /* ADB bus interface */ 9440516Swpaul DEVMETHOD(adb_hb_send_raw_packet, cuda_adb_send), 9540516Swpaul DEVMETHOD(adb_hb_controller_poll, cuda_poll), 9640516Swpaul DEVMETHOD(adb_hb_set_autopoll_mask, cuda_adb_autopoll), 9740516Swpaul 9840516Swpaul /* Clock interface */ 9940516Swpaul DEVMETHOD(clock_gettime, cuda_gettime), 10040516Swpaul DEVMETHOD(clock_settime, cuda_settime), 10140516Swpaul 10240516Swpaul DEVMETHOD_END 10341569Swpaul}; 10441569Swpaul 10541569Swpaulstatic driver_t cuda_driver = { 10650703Swpaul "cuda", 10750703Swpaul cuda_methods, 10850703Swpaul sizeof(struct cuda_softc), 10940516Swpaul}; 11050703Swpaul 11150703Swpaulstatic devclass_t cuda_devclass; 11250703Swpaul 11340516SwpaulDRIVER_MODULE(cuda, macio, cuda_driver, cuda_devclass, 0, 0); 11440516SwpaulDRIVER_MODULE(adb, cuda, adb_driver, adb_devclass, 0, 0); 11540516Swpaul 11659758Speterstatic void cuda_intr(void *arg); 11759758Speterstatic uint8_t cuda_read_reg(struct cuda_softc *sc, u_int offset); 11851089Speterstatic void cuda_write_reg(struct cuda_softc *sc, u_int offset, uint8_t value); 11950703Swpaulstatic void cuda_idle(struct cuda_softc *); 12050703Swpaulstatic void cuda_tip(struct cuda_softc *); 12140516Swpaulstatic void cuda_clear_tip(struct cuda_softc *); 12240516Swpaulstatic void cuda_in(struct cuda_softc *); 12340516Swpaulstatic void cuda_out(struct cuda_softc *); 12440516Swpaulstatic void cuda_toggle_ack(struct cuda_softc *); 12540516Swpaulstatic void cuda_ack_off(struct cuda_softc *); 12640516Swpaulstatic int cuda_intr_state(struct cuda_softc *); 12740516Swpaul 12840516Swpaulstatic int 12940516Swpaulcuda_probe(device_t dev) 13040516Swpaul{ 13140516Swpaul const char *type = ofw_bus_get_type(dev); 13240516Swpaul 13340516Swpaul if (strcmp(type, "via-cuda") != 0) 13441591Sarchie return (ENXIO); 13550477Speter 13640516Swpaul device_set_desc(dev, CUDA_DEVSTR); 13740516Swpaul return (0); 13840516Swpaul} 13940516Swpaul 14040516Swpaulstatic int 14140516Swpaulcuda_attach(device_t dev) 14240516Swpaul{ 14340516Swpaul struct cuda_softc *sc; 14440516Swpaul 14540516Swpaul volatile int i; 14667771Swpaul uint8_t reg; 14767771Swpaul phandle_t node,child; 14841243Swpaul 14941243Swpaul sc = device_get_softc(dev); 15044238Swpaul sc->sc_dev = dev; 15144238Swpaul 15244238Swpaul sc->sc_memrid = 0; 15344238Swpaul sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 15472813Swpaul &sc->sc_memrid, RF_ACTIVE); 15572813Swpaul 15696112Sjhb if (sc->sc_memr == NULL) { 15796112Sjhb device_printf(dev, "Could not alloc mem resource!\n"); 15894400Swpaul return (ENXIO); 15994400Swpaul } 160103020Siwasaki 161103020Siwasaki sc->sc_irqrid = 0; 16240516Swpaul sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irqrid, 16340516Swpaul RF_ACTIVE); 16440516Swpaul if (sc->sc_irq == NULL) { 16592739Salfred device_printf(dev, "could not allocate interrupt\n"); 16692739Salfred return (ENXIO); 16792739Salfred } 16840516Swpaul 16992739Salfred if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC | INTR_MPSAFE 17040516Swpaul | INTR_ENTROPY, NULL, cuda_intr, dev, &sc->sc_ih) != 0) { 17192739Salfred device_printf(dev, "could not setup interrupt\n"); 17292739Salfred bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irqrid, 17392739Salfred sc->sc_irq); 17492739Salfred return (ENXIO); 17592739Salfred } 17692739Salfred 17792739Salfred mtx_init(&sc->sc_mutex,"cuda",NULL,MTX_DEF | MTX_RECURSE); 17892739Salfred 17992739Salfred sc->sc_sent = 0; 18092739Salfred sc->sc_received = 0; 18192739Salfred sc->sc_waiting = 0; 18292739Salfred sc->sc_polling = 0; 18392739Salfred sc->sc_state = CUDA_NOTREADY; 18492739Salfred sc->sc_autopoll = 0; 18540516Swpaul sc->sc_rtc = -1; 18692739Salfred 18792739Salfred STAILQ_INIT(&sc->sc_inq); 18892739Salfred STAILQ_INIT(&sc->sc_outq); 18992739Salfred STAILQ_INIT(&sc->sc_freeq); 19092739Salfred 19192739Salfred for (i = 0; i < CUDA_MAXPACKETS; i++) 19292739Salfred STAILQ_INSERT_TAIL(&sc->sc_freeq, &sc->sc_pkts[i], pkt_q); 19340516Swpaul 19492739Salfred /* Init CUDA */ 19592739Salfred 19692739Salfred reg = cuda_read_reg(sc, vDirB); 19740516Swpaul reg |= 0x30; /* register B bits 4 and 5: outputs */ 19892739Salfred cuda_write_reg(sc, vDirB, reg); 19992739Salfred 20092739Salfred reg = cuda_read_reg(sc, vDirB); 20192739Salfred reg &= 0xf7; /* register B bit 3: input */ 20240516Swpaul cuda_write_reg(sc, vDirB, reg); 20392739Salfred 20492739Salfred reg = cuda_read_reg(sc, vACR); 20581713Swpaul reg &= ~vSR_OUT; /* make sure SR is set to IN */ 20650703Swpaul cuda_write_reg(sc, vACR, reg); 20750703Swpaul 20850703Swpaul cuda_write_reg(sc, vACR, (cuda_read_reg(sc, vACR) | 0x0c) & ~0x10); 20950703Swpaul 21050703Swpaul sc->sc_state = CUDA_IDLE; /* used by all types of hardware */ 21150703Swpaul 21250703Swpaul cuda_write_reg(sc, vIER, 0x84); /* make sure VIA interrupts are on */ 21350703Swpaul 21450703Swpaul cuda_idle(sc); /* reset ADB */ 21550703Swpaul 21650703Swpaul /* Reset CUDA */ 21750703Swpaul 21850703Swpaul i = cuda_read_reg(sc, vSR); /* clear interrupt */ 21986822Siwasaki cuda_write_reg(sc, vIER, 0x04); /* no interrupts while clearing */ 22086822Siwasaki cuda_idle(sc); /* reset state to idle */ 22150703Swpaul DELAY(150); 22250703Swpaul cuda_tip(sc); /* signal start of frame */ 22350703Swpaul DELAY(150); 22450703Swpaul cuda_toggle_ack(sc); 22550703Swpaul DELAY(150); 22650703Swpaul cuda_clear_tip(sc); 22750703Swpaul DELAY(150); 22850703Swpaul cuda_idle(sc); /* back to idle state */ 22950703Swpaul i = cuda_read_reg(sc, vSR); /* clear interrupt */ 23050703Swpaul cuda_write_reg(sc, vIER, 0x84); /* ints ok now */ 23150703Swpaul 23250703Swpaul /* Initialize child buses (ADB) */ 23350703Swpaul node = ofw_bus_get_node(dev); 23450703Swpaul 23550703Swpaul for (child = OF_child(node); child != 0; child = OF_peer(child)) { 23651455Swpaul char name[32]; 23750703Swpaul 23850703Swpaul memset(name, 0, sizeof(name)); 23950703Swpaul OF_getprop(child, "name", name, sizeof(name)); 24050703Swpaul 24150703Swpaul if (bootverbose) 24250703Swpaul device_printf(dev, "CUDA child <%s>\n",name); 24351533Swpaul 24467931Swpaul if (strncmp(name, "adb", 4) == 0) { 24551473Swpaul sc->adb_bus = device_add_child(dev,"adb",-1); 24650703Swpaul } 24740516Swpaul } 24840516Swpaul 24940516Swpaul clock_register(dev, 1000); 25040516Swpaul EVENTHANDLER_REGISTER(shutdown_final, cuda_shutdown, sc, 25140516Swpaul SHUTDOWN_PRI_LAST); 25240516Swpaul 25340516Swpaul return (bus_generic_attach(dev)); 25440516Swpaul} 25581713Swpaul 25681713Swpaulstatic int cuda_detach(device_t dev) { 25781713Swpaul struct cuda_softc *sc; 25881713Swpaul 25981713Swpaul sc = device_get_softc(dev); 26081713Swpaul 26181713Swpaul bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 26281713Swpaul bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irqrid, sc->sc_irq); 26381713Swpaul bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid, sc->sc_memr); 26481713Swpaul mtx_destroy(&sc->sc_mutex); 26581713Swpaul 26681713Swpaul return (bus_generic_detach(dev)); 26781713Swpaul} 26881713Swpaul 26981713Swpaulstatic uint8_t 27081713Swpaulcuda_read_reg(struct cuda_softc *sc, u_int offset) { 27181713Swpaul return (bus_read_1(sc->sc_memr, offset)); 27281713Swpaul} 27381713Swpaul 27481713Swpaulstatic void 27581713Swpaulcuda_write_reg(struct cuda_softc *sc, u_int offset, uint8_t value) { 27681713Swpaul bus_write_1(sc->sc_memr, offset, value); 27781713Swpaul} 27881713Swpaul 27981713Swpaulstatic void 28081713Swpaulcuda_idle(struct cuda_softc *sc) 28181713Swpaul{ 28281713Swpaul uint8_t reg; 28340516Swpaul 28440516Swpaul reg = cuda_read_reg(sc, vBufB); 28540516Swpaul reg |= (vPB4 | vPB5); 286102335Salfred cuda_write_reg(sc, vBufB, reg); 287102335Salfred} 28840516Swpaul 28941656Swpaulstatic void 29040516Swpaulcuda_tip(struct cuda_softc *sc) 29140516Swpaul{ 29240516Swpaul uint8_t reg; 29367931Swpaul 29440516Swpaul reg = cuda_read_reg(sc, vBufB); 29540516Swpaul reg &= ~vPB5; 29655170Sbillf cuda_write_reg(sc, vBufB, reg); 29740516Swpaul} 29840516Swpaul 29940516Swpaulstatic void 30040516Swpaulcuda_clear_tip(struct cuda_softc *sc) 30140516Swpaul{ 30240516Swpaul uint8_t reg; 30340516Swpaul 30440516Swpaul reg = cuda_read_reg(sc, vBufB); 30540516Swpaul reg |= vPB5; 30640516Swpaul cuda_write_reg(sc, vBufB, reg); 30740516Swpaul} 30840516Swpaul 30940516Swpaulstatic void 31040516Swpaulcuda_in(struct cuda_softc *sc) 31140516Swpaul{ 31240516Swpaul uint8_t reg; 31340516Swpaul 31440516Swpaul reg = cuda_read_reg(sc, vACR); 31540516Swpaul reg &= ~vSR_OUT; 31640516Swpaul cuda_write_reg(sc, vACR, reg); 317102335Salfred} 318102335Salfred 31940516Swpaulstatic void 32041656Swpaulcuda_out(struct cuda_softc *sc) 32140516Swpaul{ 32240516Swpaul uint8_t reg; 32340516Swpaul 32440516Swpaul reg = cuda_read_reg(sc, vACR); 32540516Swpaul reg |= vSR_OUT; 32640516Swpaul cuda_write_reg(sc, vACR, reg); 32740516Swpaul} 32840516Swpaul 32940516Swpaulstatic void 33040516Swpaulcuda_toggle_ack(struct cuda_softc *sc) 33140516Swpaul{ 33240516Swpaul uint8_t reg; 33340516Swpaul 33440516Swpaul reg = cuda_read_reg(sc, vBufB); 33540516Swpaul reg ^= vPB4; 33640516Swpaul cuda_write_reg(sc, vBufB, reg); 33740516Swpaul} 33840516Swpaul 33940516Swpaulstatic void 34040516Swpaulcuda_ack_off(struct cuda_softc *sc) 34140516Swpaul{ 34240516Swpaul uint8_t reg; 34340516Swpaul 34440516Swpaul reg = cuda_read_reg(sc, vBufB); 34540516Swpaul reg |= vPB4; 34640516Swpaul cuda_write_reg(sc, vBufB, reg); 34740516Swpaul} 34840516Swpaul 34940516Swpaulstatic int 35040516Swpaulcuda_intr_state(struct cuda_softc *sc) 35140516Swpaul{ 35240516Swpaul return ((cuda_read_reg(sc, vBufB) & vPB3) == 0); 35340516Swpaul} 35440516Swpaul 35540516Swpaulstatic int 35640516Swpaulcuda_send(void *cookie, int poll, int length, uint8_t *msg) 35740516Swpaul{ 35840516Swpaul struct cuda_softc *sc = cookie; 359102335Salfred device_t dev = sc->sc_dev; 360102335Salfred struct cuda_packet *pkt; 36140516Swpaul 36240516Swpaul if (sc->sc_state == CUDA_NOTREADY) 36340516Swpaul return (-1); 36440516Swpaul 36540516Swpaul mtx_lock(&sc->sc_mutex); 36640516Swpaul 36740516Swpaul pkt = STAILQ_FIRST(&sc->sc_freeq); 36840516Swpaul if (pkt == NULL) { 36940516Swpaul mtx_unlock(&sc->sc_mutex); 37040516Swpaul return (-1); 37140516Swpaul } 37240516Swpaul 37340516Swpaul pkt->len = length - 1; 37440516Swpaul pkt->type = msg[0]; 37540516Swpaul memcpy(pkt->data, &msg[1], pkt->len); 37640516Swpaul 37740516Swpaul STAILQ_REMOVE_HEAD(&sc->sc_freeq, pkt_q); 37840516Swpaul STAILQ_INSERT_TAIL(&sc->sc_outq, pkt, pkt_q); 37940516Swpaul 38040516Swpaul /* 38140516Swpaul * If we already are sending a packet, we should bail now that this 38240516Swpaul * one has been added to the queue. 38340516Swpaul */ 38440516Swpaul 38540516Swpaul if (sc->sc_waiting) { 38640516Swpaul mtx_unlock(&sc->sc_mutex); 38740516Swpaul return (0); 38840516Swpaul } 38940516Swpaul 39040516Swpaul cuda_send_outbound(sc); 391105221Sphk mtx_unlock(&sc->sc_mutex); 39240516Swpaul 39340516Swpaul if (sc->sc_polling || poll || cold) 39440516Swpaul cuda_poll(dev); 395105221Sphk 39640516Swpaul return (0); 39740516Swpaul} 39840516Swpaul 39940516Swpaulstatic void 400102335Salfredcuda_send_outbound(struct cuda_softc *sc) 401102335Salfred{ 40240516Swpaul struct cuda_packet *pkt; 40340516Swpaul 40440516Swpaul mtx_assert(&sc->sc_mutex, MA_OWNED); 40540516Swpaul 40640516Swpaul pkt = STAILQ_FIRST(&sc->sc_outq); 40740516Swpaul if (pkt == NULL) 40840516Swpaul return; 40940516Swpaul 41040516Swpaul sc->sc_out_length = pkt->len + 1; 41140516Swpaul memcpy(sc->sc_out, &pkt->type, pkt->len + 1); 41240516Swpaul sc->sc_sent = 0; 41340516Swpaul 41440516Swpaul STAILQ_REMOVE_HEAD(&sc->sc_outq, pkt_q); 41540516Swpaul STAILQ_INSERT_TAIL(&sc->sc_freeq, pkt, pkt_q); 41640516Swpaul 41740516Swpaul sc->sc_waiting = 1; 41840516Swpaul 41940516Swpaul cuda_poll(sc->sc_dev); 42040516Swpaul 421102335Salfred DELAY(150); 422102335Salfred 42340516Swpaul if (sc->sc_state == CUDA_IDLE && !cuda_intr_state(sc)) { 42440516Swpaul sc->sc_state = CUDA_OUT; 42540516Swpaul cuda_out(sc); 42640516Swpaul cuda_write_reg(sc, vSR, sc->sc_out[0]); 42740516Swpaul cuda_ack_off(sc); 42840516Swpaul cuda_tip(sc); 42940516Swpaul } 43040516Swpaul} 43140516Swpaul 43240516Swpaulstatic void 43340516Swpaulcuda_send_inbound(struct cuda_softc *sc) 43440516Swpaul{ 43540516Swpaul device_t dev; 43640516Swpaul struct cuda_packet *pkt; 43740516Swpaul 43840516Swpaul dev = sc->sc_dev; 43940516Swpaul 44040516Swpaul mtx_lock(&sc->sc_mutex); 44140516Swpaul 44240516Swpaul while ((pkt = STAILQ_FIRST(&sc->sc_inq)) != NULL) { 44340516Swpaul STAILQ_REMOVE_HEAD(&sc->sc_inq, pkt_q); 44440516Swpaul 44540516Swpaul mtx_unlock(&sc->sc_mutex); 44640516Swpaul 447102335Salfred /* check if we have a handler for this message */ 448102335Salfred switch (pkt->type) { 44940516Swpaul case CUDA_ADB: 45040516Swpaul if (pkt->len > 2) { 45140516Swpaul adb_receive_raw_packet(sc->adb_bus, 45240516Swpaul pkt->data[0],pkt->data[1], 45367087Swpaul pkt->len - 2,&pkt->data[2]); 45440516Swpaul } else { 45567087Swpaul adb_receive_raw_packet(sc->adb_bus, 45640516Swpaul pkt->data[0],pkt->data[1],0,NULL); 45740516Swpaul } 45840516Swpaul break; 45940516Swpaul case CUDA_PSEUDO: 46040516Swpaul mtx_lock(&sc->sc_mutex); 46140516Swpaul switch (pkt->data[1]) { 46240516Swpaul case CMD_AUTOPOLL: 46340516Swpaul sc->sc_autopoll = 1; 46440516Swpaul break; 46540516Swpaul case CMD_READ_RTC: 46640516Swpaul memcpy(&sc->sc_rtc, &pkt->data[2], 46740516Swpaul sizeof(sc->sc_rtc)); 46840516Swpaul wakeup(&sc->sc_rtc); 46940516Swpaul break; 47040516Swpaul case CMD_WRITE_RTC: 47140516Swpaul break; 47240516Swpaul } 47340516Swpaul mtx_unlock(&sc->sc_mutex); 47440516Swpaul break; 47540516Swpaul case CUDA_ERROR: 47640516Swpaul /* 47740516Swpaul * CUDA will throw errors if we miss a race between 47840516Swpaul * sending and receiving packets. This is already 47940516Swpaul * handled when we abort packet output to handle 48040516Swpaul * this packet in cuda_intr(). Thus, we ignore 48140516Swpaul * these messages. 48240516Swpaul */ 48340516Swpaul break; 48440516Swpaul default: 48540516Swpaul device_printf(dev,"unknown CUDA command %d\n", 48640516Swpaul pkt->type); 48740516Swpaul break; 48840516Swpaul } 48940516Swpaul 49040516Swpaul mtx_lock(&sc->sc_mutex); 49140516Swpaul 49240516Swpaul STAILQ_INSERT_TAIL(&sc->sc_freeq, pkt, pkt_q); 49340516Swpaul } 49440516Swpaul 49540516Swpaul mtx_unlock(&sc->sc_mutex); 49640516Swpaul} 49740516Swpaul 49840516Swpaulstatic u_int 49940516Swpaulcuda_poll(device_t dev) 50040516Swpaul{ 50140516Swpaul struct cuda_softc *sc = device_get_softc(dev); 50240516Swpaul 50340516Swpaul if (sc->sc_state == CUDA_IDLE && !cuda_intr_state(sc) && 50440516Swpaul !sc->sc_waiting) 50540516Swpaul return (0); 50640516Swpaul 50740516Swpaul cuda_intr(dev); 50840516Swpaul return (0); 50940516Swpaul} 51040516Swpaul 51140516Swpaulstatic void 51240516Swpaulcuda_intr(void *arg) 51340516Swpaul{ 51440516Swpaul device_t dev; 51540516Swpaul struct cuda_softc *sc; 51640516Swpaul 51740516Swpaul int i, ending, restart_send, process_inbound; 51840516Swpaul uint8_t reg; 51940516Swpaul 52040516Swpaul dev = (device_t)arg; 52140516Swpaul sc = device_get_softc(dev); 52240516Swpaul 52340516Swpaul mtx_lock(&sc->sc_mutex); 52440516Swpaul 52540516Swpaul restart_send = 0; 52640516Swpaul process_inbound = 0; 52740516Swpaul reg = cuda_read_reg(sc, vIFR); 52840516Swpaul if ((reg & vSR_INT) != vSR_INT) { 52940516Swpaul mtx_unlock(&sc->sc_mutex); 53040516Swpaul return; 53167087Swpaul } 53240516Swpaul 53340516Swpaul cuda_write_reg(sc, vIFR, 0x7f); /* Clear interrupt */ 53440516Swpaul 53540516Swpaulswitch_start: 53640516Swpaul switch (sc->sc_state) { 53740516Swpaul case CUDA_IDLE: 53840516Swpaul /* 53940516Swpaul * This is an unexpected packet, so grab the first (dummy) 54040516Swpaul * byte, set up the proper vars, and tell the chip we are 541102335Salfred * starting to receive the packet by setting the TIP bit. 542102335Salfred */ 54340516Swpaul sc->sc_in[1] = cuda_read_reg(sc, vSR); 54440516Swpaul 54540516Swpaul if (cuda_intr_state(sc) == 0) { 54640516Swpaul /* must have been a fake start */ 54767087Swpaul 54840516Swpaul if (sc->sc_waiting) { 54940516Swpaul /* start over */ 55040516Swpaul DELAY(150); 55140516Swpaul sc->sc_state = CUDA_OUT; 55240516Swpaul sc->sc_sent = 0; 55340516Swpaul cuda_out(sc); 55440516Swpaul cuda_write_reg(sc, vSR, sc->sc_out[1]); 55540516Swpaul cuda_ack_off(sc); 55640516Swpaul cuda_tip(sc); 55740516Swpaul } 55840516Swpaul break; 55940516Swpaul } 56040516Swpaul 56140516Swpaul cuda_in(sc); 56240516Swpaul cuda_tip(sc); 56340516Swpaul 56440516Swpaul sc->sc_received = 1; 56540516Swpaul sc->sc_state = CUDA_IN; 56640516Swpaul break; 56740516Swpaul 56840516Swpaul case CUDA_IN: 56940516Swpaul sc->sc_in[sc->sc_received] = cuda_read_reg(sc, vSR); 57040516Swpaul ending = 0; 57140516Swpaul 57240516Swpaul if (sc->sc_received > 255) { 57340516Swpaul /* bitch only once */ 57440516Swpaul if (sc->sc_received == 256) { 57540516Swpaul device_printf(dev,"input overflow\n"); 57640516Swpaul ending = 1; 57740516Swpaul } 57840516Swpaul } else 57940516Swpaul sc->sc_received++; 58040516Swpaul 58140516Swpaul /* intr off means this is the last byte (end of frame) */ 58267087Swpaul if (cuda_intr_state(sc) == 0) { 58340516Swpaul ending = 1; 58440516Swpaul } else { 58540516Swpaul cuda_toggle_ack(sc); 58640516Swpaul } 587102335Salfred 588102335Salfred if (ending == 1) { /* end of message? */ 58950703Swpaul struct cuda_packet *pkt; 59050703Swpaul 59150703Swpaul /* reset vars and signal the end of this frame */ 59240516Swpaul cuda_idle(sc); 59340516Swpaul 59440516Swpaul /* Queue up the packet */ 59540516Swpaul pkt = STAILQ_FIRST(&sc->sc_freeq); 59640516Swpaul if (pkt != NULL) { 59750703Swpaul /* If we have a free packet, process it */ 59867087Swpaul 59950703Swpaul pkt->len = sc->sc_received - 2; 60040516Swpaul pkt->type = sc->sc_in[1]; 60150703Swpaul memcpy(pkt->data, &sc->sc_in[2], pkt->len); 60267087Swpaul 60367087Swpaul STAILQ_REMOVE_HEAD(&sc->sc_freeq, pkt_q); 60450703Swpaul STAILQ_INSERT_TAIL(&sc->sc_inq, pkt, pkt_q); 60567087Swpaul 60640516Swpaul process_inbound = 1; 60750703Swpaul } 60840516Swpaul 60940516Swpaul sc->sc_state = CUDA_IDLE; 61050703Swpaul sc->sc_received = 0; 61140516Swpaul 61240516Swpaul /* 61350703Swpaul * If there is something waiting to be sent out, 61440516Swpaul * set everything up and send the first byte. 61540516Swpaul */ 61650703Swpaul if (sc->sc_waiting == 1) { 61750703Swpaul DELAY(1500); /* required */ 61850703Swpaul sc->sc_sent = 0; 61950703Swpaul sc->sc_state = CUDA_OUT; 62040516Swpaul 62140516Swpaul /* 62250703Swpaul * If the interrupt is on, we were too slow 62350703Swpaul * and the chip has already started to send 62467087Swpaul * something to us, so back out of the write 62550703Swpaul * and start a read cycle. 62650703Swpaul */ 62794149Swpaul if (cuda_intr_state(sc)) { 62894149Swpaul cuda_in(sc); 62994149Swpaul cuda_idle(sc); 63094149Swpaul sc->sc_sent = 0; 63194149Swpaul sc->sc_state = CUDA_IDLE; 63294149Swpaul sc->sc_received = 0; 63394149Swpaul DELAY(150); 63494149Swpaul goto switch_start; 63594149Swpaul } 63694149Swpaul 63794149Swpaul /* 63840516Swpaul * If we got here, it's ok to start sending 63940516Swpaul * so load the first byte and tell the chip 64067087Swpaul * we want to send. 64140516Swpaul */ 64240516Swpaul cuda_out(sc); 64340516Swpaul cuda_write_reg(sc, vSR, 64467087Swpaul sc->sc_out[sc->sc_sent]); 64540516Swpaul cuda_ack_off(sc); 64640516Swpaul cuda_tip(sc); 64740516Swpaul } 64840516Swpaul } 64940516Swpaul break; 65050703Swpaul 65140516Swpaul case CUDA_OUT: 65240516Swpaul i = cuda_read_reg(sc, vSR); /* reset SR-intr in IFR */ 65367087Swpaul 65440516Swpaul sc->sc_sent++; 65540516Swpaul if (cuda_intr_state(sc)) { /* ADB intr low during write */ 65640516Swpaul cuda_in(sc); /* make sure SR is set to IN */ 65740516Swpaul cuda_idle(sc); 658102335Salfred sc->sc_sent = 0; /* must start all over */ 659102335Salfred sc->sc_state = CUDA_IDLE; /* new state */ 66050703Swpaul sc->sc_received = 0; 66150703Swpaul sc->sc_waiting = 1; /* must retry when done with 66250703Swpaul * read */ 66340516Swpaul DELAY(150); 66440516Swpaul goto switch_start; /* process next state right 66540516Swpaul * now */ 66640516Swpaul break; 66750703Swpaul } 66867087Swpaul if (sc->sc_out_length == sc->sc_sent) { /* check for done */ 66950703Swpaul sc->sc_waiting = 0; /* done writing */ 67040516Swpaul sc->sc_state = CUDA_IDLE; /* signal bus is idle */ 67150703Swpaul cuda_in(sc); 67267087Swpaul cuda_idle(sc); 67367087Swpaul } else { 67450703Swpaul /* send next byte */ 67567087Swpaul cuda_write_reg(sc, vSR, sc->sc_out[sc->sc_sent]); 67640516Swpaul cuda_toggle_ack(sc); /* signal byte ready to 67750703Swpaul * shift */ 67840516Swpaul } 67940516Swpaul break; 68050703Swpaul 68140516Swpaul case CUDA_NOTREADY: 68240516Swpaul break; 68350703Swpaul 68440516Swpaul default: 68540516Swpaul break; 68650703Swpaul } 68750703Swpaul 68850703Swpaul mtx_unlock(&sc->sc_mutex); 68950703Swpaul 69040516Swpaul if (process_inbound) 69140516Swpaul cuda_send_inbound(sc); 69250703Swpaul 69350703Swpaul mtx_lock(&sc->sc_mutex); 69467087Swpaul /* If we have another packet waiting, set it up */ 69550703Swpaul if (!sc->sc_waiting && sc->sc_state == CUDA_IDLE) 69650703Swpaul cuda_send_outbound(sc); 69740516Swpaul 69840516Swpaul mtx_unlock(&sc->sc_mutex); 69967087Swpaul 70050703Swpaul} 70140516Swpaul 70240516Swpaulstatic u_int 70367087Swpaulcuda_adb_send(device_t dev, u_char command_byte, int len, u_char *data, 70450703Swpaul u_char poll) 70540516Swpaul{ 70640516Swpaul struct cuda_softc *sc = device_get_softc(dev); 70740516Swpaul uint8_t packet[16]; 70840516Swpaul int i; 70950703Swpaul 71040516Swpaul /* construct an ADB command packet and send it */ 71140516Swpaul packet[0] = CUDA_ADB; 71240516Swpaul packet[1] = command_byte; 71340516Swpaul for (i = 0; i < len; i++) 71440516Swpaul packet[i + 2] = data[i]; 71567087Swpaul 71650703Swpaul cuda_send(sc, poll, len + 2, packet); 71750703Swpaul 71850703Swpaul return (0); 719102335Salfred} 720102335Salfred 72150703Swpaulstatic u_int 72250703Swpaulcuda_adb_autopoll(device_t dev, uint16_t mask) { 72340516Swpaul struct cuda_softc *sc = device_get_softc(dev); 72440516Swpaul 72540516Swpaul uint8_t cmd[] = {CUDA_PSEUDO, CMD_AUTOPOLL, mask != 0}; 72640516Swpaul 72743062Swpaul mtx_lock(&sc->sc_mutex); 72840516Swpaul 729102335Salfred if (cmd[2] == sc->sc_autopoll) { 730102335Salfred mtx_unlock(&sc->sc_mutex); 73141656Swpaul return (0); 73240516Swpaul } 73340516Swpaul 73440516Swpaul sc->sc_autopoll = -1; 73540516Swpaul cuda_send(sc, 1, 3, cmd); 73640516Swpaul 73740516Swpaul mtx_unlock(&sc->sc_mutex); 73840516Swpaul 73940516Swpaul return (0); 74040516Swpaul} 74140516Swpaul 74240516Swpaulstatic void 74340516Swpaulcuda_shutdown(void *xsc, int howto) 74440516Swpaul{ 74540516Swpaul struct cuda_softc *sc = xsc; 74640516Swpaul uint8_t cmd[] = {CUDA_PSEUDO, 0}; 74740516Swpaul 74840516Swpaul cmd[1] = (howto & RB_HALT) ? CMD_POWEROFF : CMD_RESET; 74940516Swpaul cuda_poll(sc->sc_dev); 75040516Swpaul cuda_send(sc, 1, 2, cmd); 75140516Swpaul 75243062Swpaul while (1) 75340516Swpaul cuda_poll(sc->sc_dev); 75440516Swpaul} 75540516Swpaul 75640516Swpaul#define DIFF19041970 2082844800 75740516Swpaul 758102335Salfredstatic int 759102335Salfredcuda_gettime(device_t dev, struct timespec *ts) 76040516Swpaul{ 76140516Swpaul struct cuda_softc *sc = device_get_softc(dev); 76240516Swpaul uint8_t cmd[] = {CUDA_PSEUDO, CMD_READ_RTC}; 76340516Swpaul 76440516Swpaul mtx_lock(&sc->sc_mutex); 76540516Swpaul sc->sc_rtc = -1; 76640516Swpaul cuda_send(sc, 1, 2, cmd); 76740516Swpaul if (sc->sc_rtc == -1) 76840516Swpaul mtx_sleep(&sc->sc_rtc, &sc->sc_mutex, 0, "rtc", 100); 76940516Swpaul 77040516Swpaul ts->tv_sec = sc->sc_rtc - DIFF19041970; 77140516Swpaul ts->tv_nsec = 0; 77240516Swpaul mtx_unlock(&sc->sc_mutex); 77343062Swpaul 77440516Swpaul return (0); 77540516Swpaul} 77640516Swpaul 77740516Swpaulstatic int 77840516Swpaulcuda_settime(device_t dev, struct timespec *ts) 77940516Swpaul{ 78040516Swpaul struct cuda_softc *sc = device_get_softc(dev); 78140516Swpaul uint8_t cmd[] = {CUDA_PSEUDO, CMD_WRITE_RTC, 0, 0, 0, 0}; 78240516Swpaul uint32_t sec; 78340516Swpaul 78440516Swpaul sec = ts->tv_sec + DIFF19041970; 78540516Swpaul memcpy(&cmd[2], &sec, sizeof(sec)); 78672084Sphk 78740516Swpaul mtx_lock(&sc->sc_mutex); 78840516Swpaul cuda_send(sc, 0, 6, cmd); 78940516Swpaul mtx_unlock(&sc->sc_mutex); 79040516Swpaul 79140516Swpaul return (0); 79240516Swpaul} 79340516Swpaul 79440516Swpaul