1176771Sraj/*- 2192532Sraj * Copyright (C) 2006-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3176771Sraj * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4176771Sraj * Copyright (C) 2006 Juniper Networks, Inc. 5176771Sraj * All rights reserved. 6176771Sraj * 7176771Sraj * Redistribution and use in source and binary forms, with or without 8176771Sraj * modification, are permitted provided that the following conditions 9176771Sraj * are met: 10176771Sraj * 1. Redistributions of source code must retain the above copyright 11176771Sraj * notice, this list of conditions and the following disclaimer. 12176771Sraj * 2. Redistributions in binary form must reproduce the above copyright 13176771Sraj * notice, this list of conditions and the following disclaimer in the 14176771Sraj * documentation and/or other materials provided with the distribution. 15176771Sraj * 3. The name of the author may not be used to endorse or promote products 16176771Sraj * derived from this software without specific prior written permission. 17176771Sraj * 18176771Sraj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19176771Sraj * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20176771Sraj * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 21176771Sraj * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22176771Sraj * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 23176771Sraj * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 24176771Sraj * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 25176771Sraj * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 26176771Sraj * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 27176771Sraj * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28176771Sraj * 29176771Sraj * $FreeBSD$ 30176771Sraj */ 31176771Sraj/*- 32176771Sraj * Copyright (C) 1995, 1996 Wolfgang Solfrank. 33176771Sraj * Copyright (C) 1995, 1996 TooLs GmbH. 34176771Sraj * All rights reserved. 35176771Sraj * 36176771Sraj * Redistribution and use in source and binary forms, with or without 37176771Sraj * modification, are permitted provided that the following conditions 38176771Sraj * are met: 39176771Sraj * 1. Redistributions of source code must retain the above copyright 40176771Sraj * notice, this list of conditions and the following disclaimer. 41176771Sraj * 2. Redistributions in binary form must reproduce the above copyright 42176771Sraj * notice, this list of conditions and the following disclaimer in the 43176771Sraj * documentation and/or other materials provided with the distribution. 44176771Sraj * 3. All advertising materials mentioning features or use of this software 45176771Sraj * must display the following acknowledgement: 46176771Sraj * This product includes software developed by TooLs GmbH. 47176771Sraj * 4. The name of TooLs GmbH may not be used to endorse or promote products 48176771Sraj * derived from this software without specific prior written permission. 49176771Sraj * 50176771Sraj * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 51176771Sraj * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 52176771Sraj * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 53176771Sraj * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 54176771Sraj * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 55176771Sraj * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 56176771Sraj * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 57176771Sraj * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 58176771Sraj * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 59176771Sraj * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60176771Sraj * 61176771Sraj * from: $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ 62176771Sraj */ 63176771Sraj 64176771Sraj/* 65176771Sraj * NOTICE: This is not a standalone file. to use it, #include it in 66176771Sraj * your port's locore.S, like so: 67176771Sraj * 68176771Sraj * #include <powerpc/booke/trap_subr.S> 69176771Sraj */ 70176771Sraj 71176771Sraj/* 72176771Sraj * SPRG usage notes 73176771Sraj * 74176771Sraj * SPRG0 - pcpu pointer 75176771Sraj * SPRG1 - all interrupts except TLB miss, critical, machine check 76176771Sraj * SPRG2 - critical 77176771Sraj * SPRG3 - machine check 78192532Sraj * SPRG4-6 - scratch 79176771Sraj * 80176771Sraj */ 81176771Sraj 82176771Sraj/* Get the per-CPU data structure */ 83176771Sraj#define GET_CPUINFO(r) mfsprg0 r 84176771Sraj 85192532Sraj#define RES_GRANULE 32 86192532Sraj#define RES_LOCK 0 /* offset to the 'lock' word */ 87192532Sraj#define RES_RECURSE 4 /* offset to the 'recurse' word */ 88192532Sraj 89176771Sraj/* 90176771Sraj * Standard interrupt prolog 91176771Sraj * 92176771Sraj * sprg_sp - SPRG{1-3} reg used to temporarily store the SP 93176771Sraj * savearea - temp save area (pc_{tempsave, disisave, critsave, mchksave}) 94176771Sraj * isrr0-1 - save restore registers with CPU state at interrupt time (may be 95176771Sraj * SRR0-1, CSRR0-1, MCSRR0-1 96176771Sraj * 97176771Sraj * 1. saves in the given savearea: 98176771Sraj * - R30-31 99176771Sraj * - DEAR, ESR 100176771Sraj * - xSRR0-1 101176771Sraj * 102176771Sraj * 2. saves CR -> R30 103176771Sraj * 104176771Sraj * 3. switches to kstack if needed 105176771Sraj * 106176771Sraj * 4. notes: 107176771Sraj * - R31 can be used as scratch register until a new frame is layed on 108176771Sraj * the stack with FRAME_SETUP 109176771Sraj * 110176771Sraj * - potential TLB miss: NO. Saveareas are always acessible via TLB1 111176771Sraj * permanent entries, and within this prolog we do not dereference any 112176771Sraj * locations potentially not in the TLB 113176771Sraj */ 114176771Sraj#define STANDARD_PROLOG(sprg_sp, savearea, isrr0, isrr1) \ 115176771Sraj mtspr sprg_sp, %r1; /* Save SP */ \ 116176771Sraj GET_CPUINFO(%r1); /* Per-cpu structure */ \ 117176771Sraj stw %r30, (savearea+CPUSAVE_R30)(%r1); \ 118176771Sraj stw %r31, (savearea+CPUSAVE_R31)(%r1); \ 119176771Sraj mfdear %r30; \ 120176771Sraj mfesr %r31; \ 121176771Sraj stw %r30, (savearea+CPUSAVE_BOOKE_DEAR)(%r1); \ 122176771Sraj stw %r31, (savearea+CPUSAVE_BOOKE_ESR)(%r1); \ 123176771Sraj mfspr %r30, isrr0; \ 124176771Sraj mfspr %r31, isrr1; /* MSR at interrupt time */ \ 125176771Sraj stw %r30, (savearea+CPUSAVE_SRR0)(%r1); \ 126176771Sraj stw %r31, (savearea+CPUSAVE_SRR1)(%r1); \ 127176771Sraj isync; \ 128176771Sraj mfspr %r1, sprg_sp; /* Restore SP */ \ 129176771Sraj mfcr %r30; /* Save CR */ \ 130176771Sraj /* switch to per-thread kstack if intr taken in user mode */ \ 131176771Sraj mtcr %r31; /* MSR at interrupt time */ \ 132176771Sraj bf 17, 1f; \ 133176771Sraj GET_CPUINFO(%r1); /* Per-cpu structure */ \ 134176771Sraj lwz %r1, PC_CURPCB(%r1); /* Per-thread kernel stack */ \ 135187153Sraj1: 136176771Sraj 137176771Sraj#define STANDARD_CRIT_PROLOG(sprg_sp, savearea, isrr0, isrr1) \ 138176771Sraj mtspr sprg_sp, %r1; /* Save SP */ \ 139176771Sraj GET_CPUINFO(%r1); /* Per-cpu structure */ \ 140176771Sraj stw %r30, (savearea+CPUSAVE_R30)(%r1); \ 141176771Sraj stw %r31, (savearea+CPUSAVE_R31)(%r1); \ 142176771Sraj mfdear %r30; \ 143176771Sraj mfesr %r31; \ 144176771Sraj stw %r30, (savearea+CPUSAVE_BOOKE_DEAR)(%r1); \ 145176771Sraj stw %r31, (savearea+CPUSAVE_BOOKE_ESR)(%r1); \ 146176771Sraj mfspr %r30, isrr0; \ 147176771Sraj mfspr %r31, isrr1; /* MSR at interrupt time */ \ 148176771Sraj stw %r30, (savearea+CPUSAVE_SRR0)(%r1); \ 149176771Sraj stw %r31, (savearea+CPUSAVE_SRR1)(%r1); \ 150176771Sraj mfspr %r30, SPR_SRR0; \ 151176771Sraj mfspr %r31, SPR_SRR1; /* MSR at interrupt time */ \ 152176771Sraj stw %r30, (savearea+CPUSAVE_SRR0+8)(%r1); \ 153176771Sraj stw %r31, (savearea+CPUSAVE_SRR1+8)(%r1); \ 154176771Sraj isync; \ 155176771Sraj mfspr %r1, sprg_sp; /* Restore SP */ \ 156176771Sraj mfcr %r30; /* Save CR */ \ 157176771Sraj /* switch to per-thread kstack if intr taken in user mode */ \ 158176771Sraj mtcr %r31; /* MSR at interrupt time */ \ 159176771Sraj bf 17, 1f; \ 160176771Sraj GET_CPUINFO(%r1); /* Per-cpu structure */ \ 161176771Sraj lwz %r1, PC_CURPCB(%r1); /* Per-thread kernel stack */ \ 162176771Sraj1: 163176771Sraj 164176771Sraj/* 165176771Sraj * FRAME_SETUP assumes: 166176771Sraj * SPRG{1-3} SP at the time interrupt occured 167176771Sraj * savearea r30-r31, DEAR, ESR, xSRR0-1 168176771Sraj * r30 CR 169176771Sraj * r31 scratch 170176771Sraj * r1 kernel stack 171176771Sraj * 172176771Sraj * sprg_sp - SPRG reg containing SP at the time interrupt occured 173176771Sraj * savearea - temp save 174176771Sraj * exc - exception number (EXC_xxx) 175176771Sraj * 176176771Sraj * 1. sets a new frame 177176771Sraj * 2. saves in the frame: 178176771Sraj * - R0, R1 (SP at the time of interrupt), R2, LR, CR 179176771Sraj * - R3-31 (R30-31 first restored from savearea) 180176771Sraj * - XER, CTR, DEAR, ESR (from savearea), xSRR0-1 181176771Sraj * 182176771Sraj * Notes: 183176771Sraj * - potential TLB miss: YES, since we make dereferences to kstack, which 184176771Sraj * can happen not covered (we can have up to two DTLB misses if fortunate 185176771Sraj * enough i.e. when kstack crosses page boundary and both pages are 186176771Sraj * untranslated) 187176771Sraj */ 188176771Sraj#define FRAME_SETUP(sprg_sp, savearea, exc) \ 189176771Sraj mfspr %r31, sprg_sp; /* get saved SP */ \ 190176771Sraj /* establish a new stack frame and put everything on it */ \ 191176771Sraj stwu %r31, -FRAMELEN(%r1); \ 192176771Sraj stw %r0, FRAME_0+8(%r1); /* save r0 in the trapframe */ \ 193176771Sraj stw %r31, FRAME_1+8(%r1); /* save SP " " */ \ 194176771Sraj stw %r2, FRAME_2+8(%r1); /* save r2 " " */ \ 195176771Sraj mflr %r31; \ 196176771Sraj stw %r31, FRAME_LR+8(%r1); /* save LR " " */ \ 197176771Sraj stw %r30, FRAME_CR+8(%r1); /* save CR " " */ \ 198176771Sraj GET_CPUINFO(%r2); \ 199176771Sraj lwz %r30, (savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \ 200176771Sraj lwz %r31, (savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \ 201176771Sraj /* save R3-31 */ \ 202176771Sraj stmw %r3, FRAME_3+8(%r1) ; \ 203176771Sraj /* save DEAR, ESR */ \ 204176771Sraj lwz %r28, (savearea+CPUSAVE_BOOKE_DEAR)(%r2); \ 205176771Sraj lwz %r29, (savearea+CPUSAVE_BOOKE_ESR)(%r2); \ 206189101Sraj stw %r28, FRAME_BOOKE_DEAR+8(%r1); \ 207189101Sraj stw %r29, FRAME_BOOKE_ESR+8(%r1); \ 208176771Sraj /* save XER, CTR, exc number */ \ 209176771Sraj mfxer %r3; \ 210176771Sraj mfctr %r4; \ 211189101Sraj stw %r3, FRAME_XER+8(%r1); \ 212189101Sraj stw %r4, FRAME_CTR+8(%r1); \ 213176771Sraj li %r5, exc; \ 214189101Sraj stw %r5, FRAME_EXC+8(%r1); \ 215189100Sraj /* save DBCR0 */ \ 216189100Sraj mfspr %r3, SPR_DBCR0; \ 217189101Sraj stw %r3, FRAME_BOOKE_DBCR0+8(%r1); \ 218176771Sraj /* save xSSR0-1 */ \ 219176771Sraj lwz %r30, (savearea+CPUSAVE_SRR0)(%r2); \ 220176771Sraj lwz %r31, (savearea+CPUSAVE_SRR1)(%r2); \ 221189101Sraj stw %r30, FRAME_SRR0+8(%r1); \ 222189101Sraj stw %r31, FRAME_SRR1+8(%r1) 223176771Sraj 224176771Sraj/* 225176771Sraj * 226176771Sraj * isrr0-1 - save restore registers to restore CPU state to (may be 227176771Sraj * SRR0-1, CSRR0-1, MCSRR0-1 228176771Sraj * 229176771Sraj * Notes: 230176771Sraj * - potential TLB miss: YES. The deref'd kstack may be not covered 231176771Sraj */ 232176771Sraj#define FRAME_LEAVE(isrr0, isrr1) \ 233176771Sraj /* restore CTR, XER, LR, CR */ \ 234176771Sraj lwz %r4, FRAME_CTR+8(%r1); \ 235176771Sraj lwz %r5, FRAME_XER+8(%r1); \ 236176771Sraj lwz %r6, FRAME_LR+8(%r1); \ 237176771Sraj lwz %r7, FRAME_CR+8(%r1); \ 238176771Sraj mtctr %r4; \ 239176771Sraj mtxer %r5; \ 240176771Sraj mtlr %r6; \ 241176771Sraj mtcr %r7; \ 242189100Sraj /* restore DBCR0 */ \ 243189100Sraj lwz %r4, FRAME_BOOKE_DBCR0+8(%r1); \ 244189100Sraj mtspr SPR_DBCR0, %r4; \ 245176771Sraj /* restore xSRR0-1 */ \ 246176771Sraj lwz %r30, FRAME_SRR0+8(%r1); \ 247176771Sraj lwz %r31, FRAME_SRR1+8(%r1); \ 248176771Sraj mtspr isrr0, %r30; \ 249176771Sraj mtspr isrr1, %r31; \ 250176771Sraj /* restore R2-31, SP */ \ 251176771Sraj lmw %r2, FRAME_2+8(%r1) ; \ 252176771Sraj lwz %r0, FRAME_0+8(%r1); \ 253176771Sraj lwz %r1, FRAME_1+8(%r1); \ 254176771Sraj isync 255176771Sraj 256176771Sraj/* 257176771Sraj * TLB miss prolog 258176771Sraj * 259176771Sraj * saves LR, CR, SRR0-1, R20-31 in the TLBSAVE area 260176771Sraj * 261176771Sraj * Notes: 262176771Sraj * - potential TLB miss: NO. It is crucial that we do not generate a TLB 263187153Sraj * miss within the TLB prolog itself! 264176771Sraj * - TLBSAVE is always translated 265176771Sraj */ 266176771Sraj#define TLB_PROLOG \ 267176771Sraj mtsprg4 %r1; /* Save SP */ \ 268176771Sraj mtsprg5 %r28; \ 269176771Sraj mtsprg6 %r29; \ 270176771Sraj /* calculate TLB nesting level and TLBSAVE instance address */ \ 271176771Sraj GET_CPUINFO(%r1); /* Per-cpu structure */ \ 272176771Sraj lwz %r28, PC_BOOKE_TLB_LEVEL(%r1); \ 273192532Sraj rlwinm %r29, %r28, 6, 23, 25; /* 4 x TLBSAVE_LEN */ \ 274176771Sraj addi %r28, %r28, 1; \ 275176771Sraj stw %r28, PC_BOOKE_TLB_LEVEL(%r1); \ 276176771Sraj addi %r29, %r29, PC_BOOKE_TLBSAVE@l; \ 277176771Sraj add %r1, %r1, %r29; /* current TLBSAVE ptr */ \ 278176771Sraj \ 279176771Sraj /* save R20-31 */ \ 280176771Sraj mfsprg5 %r28; \ 281176771Sraj mfsprg6 %r29; \ 282176771Sraj stmw %r20, (TLBSAVE_BOOKE_R20)(%r1); \ 283176771Sraj /* save LR, CR */ \ 284176771Sraj mflr %r30; \ 285176771Sraj mfcr %r31; \ 286176771Sraj stw %r30, (TLBSAVE_BOOKE_LR)(%r1); \ 287176771Sraj stw %r31, (TLBSAVE_BOOKE_CR)(%r1); \ 288176771Sraj /* save SRR0-1 */ \ 289176771Sraj mfsrr0 %r30; /* execution addr at interrupt time */ \ 290176771Sraj mfsrr1 %r31; /* MSR at interrupt time*/ \ 291176771Sraj stw %r30, (TLBSAVE_BOOKE_SRR0)(%r1); /* save SRR0 */ \ 292176771Sraj stw %r31, (TLBSAVE_BOOKE_SRR1)(%r1); /* save SRR1 */ \ 293176771Sraj isync; \ 294176771Sraj mfsprg4 %r1 295176771Sraj 296176771Sraj/* 297176771Sraj * restores LR, CR, SRR0-1, R20-31 from the TLBSAVE area 298176771Sraj * 299176771Sraj * same notes as for the TLB_PROLOG 300176771Sraj */ 301176771Sraj#define TLB_RESTORE \ 302176771Sraj mtsprg4 %r1; /* Save SP */ \ 303176771Sraj GET_CPUINFO(%r1); /* Per-cpu structure */ \ 304176771Sraj /* calculate TLB nesting level and TLBSAVE instance addr */ \ 305176771Sraj lwz %r28, PC_BOOKE_TLB_LEVEL(%r1); \ 306176771Sraj subi %r28, %r28, 1; \ 307176771Sraj stw %r28, PC_BOOKE_TLB_LEVEL(%r1); \ 308192532Sraj rlwinm %r29, %r28, 6, 23, 25; /* 4 x TLBSAVE_LEN */ \ 309176771Sraj addi %r29, %r29, PC_BOOKE_TLBSAVE@l; \ 310176771Sraj add %r1, %r1, %r29; \ 311176771Sraj \ 312176771Sraj /* restore LR, CR */ \ 313176771Sraj lwz %r30, (TLBSAVE_BOOKE_LR)(%r1); \ 314176771Sraj lwz %r31, (TLBSAVE_BOOKE_CR)(%r1); \ 315176771Sraj mtlr %r30; \ 316176771Sraj mtcr %r31; \ 317176771Sraj /* restore SRR0-1 */ \ 318176771Sraj lwz %r30, (TLBSAVE_BOOKE_SRR0)(%r1); \ 319176771Sraj lwz %r31, (TLBSAVE_BOOKE_SRR1)(%r1); \ 320176771Sraj mtsrr0 %r30; \ 321176771Sraj mtsrr1 %r31; \ 322176771Sraj /* restore R20-31 */ \ 323176771Sraj lmw %r20, (TLBSAVE_BOOKE_R20)(%r1); \ 324176771Sraj mfsprg4 %r1 325176771Sraj 326192532Sraj#ifdef SMP 327192532Sraj#define TLB_LOCK \ 328192532Sraj GET_CPUINFO(%r20); \ 329192532Sraj lwz %r21, PC_CURTHREAD(%r20); \ 330192532Sraj lwz %r22, PC_BOOKE_TLB_LOCK(%r20); \ 331192532Sraj \ 332192532Sraj1: lwarx %r23, 0, %r22; \ 333215119Sraj cmpwi %r23, TLB_UNLOCKED; \ 334192532Sraj beq 2f; \ 335192532Sraj \ 336192532Sraj /* check if this is recursion */ \ 337192532Sraj cmplw cr0, %r21, %r23; \ 338192532Sraj bne- 1b; \ 339192532Sraj \ 340192532Sraj2: /* try to acquire lock */ \ 341192532Sraj stwcx. %r21, 0, %r22; \ 342192532Sraj bne- 1b; \ 343192532Sraj \ 344192532Sraj /* got it, update recursion counter */ \ 345192532Sraj lwz %r21, RES_RECURSE(%r22); \ 346192532Sraj addi %r21, %r21, 1; \ 347192532Sraj stw %r21, RES_RECURSE(%r22); \ 348192532Sraj isync; \ 349192532Sraj msync 350176771Sraj 351192532Sraj#define TLB_UNLOCK \ 352192532Sraj GET_CPUINFO(%r20); \ 353192532Sraj lwz %r21, PC_CURTHREAD(%r20); \ 354192532Sraj lwz %r22, PC_BOOKE_TLB_LOCK(%r20); \ 355192532Sraj \ 356192532Sraj /* update recursion counter */ \ 357192532Sraj lwz %r23, RES_RECURSE(%r22); \ 358192532Sraj subi %r23, %r23, 1; \ 359192532Sraj stw %r23, RES_RECURSE(%r22); \ 360192532Sraj \ 361192532Sraj cmpwi %r23, 0; \ 362192532Sraj bne 1f; \ 363192532Sraj isync; \ 364192532Sraj msync; \ 365192532Sraj \ 366192532Sraj /* release the lock */ \ 367215119Sraj li %r23, TLB_UNLOCKED; \ 368192532Sraj stw %r23, 0(%r22); \ 369192532Sraj1: isync; \ 370192532Sraj msync 371192532Sraj#else 372192532Sraj#define TLB_LOCK 373192532Sraj#define TLB_UNLOCK 374192532Sraj#endif /* SMP */ 375192532Sraj 376176771Sraj#define INTERRUPT(label) \ 377176771Sraj .globl label; \ 378176771Sraj .align 5; \ 379176771Sraj CNAME(label): 380176771Sraj 381176771Sraj/* 382176771Sraj * Interrupt handling routines in BookE can be flexibly placed and do not have 383176771Sraj * to live in pre-defined vectors location. Note they need to be TLB-mapped at 384176771Sraj * all times in order to be able to handle exceptions. We thus arrange for 385176771Sraj * them to be part of kernel text which is always TLB-accessible. 386176771Sraj * 387176771Sraj * The interrupt handling routines have to be 16 bytes aligned: we align them 388176771Sraj * to 32 bytes (cache line length) which supposedly performs better. 389176771Sraj * 390176771Sraj */ 391176771Sraj .text 392176771Sraj .globl CNAME(interrupt_vector_base) 393176771Sraj .align 5 394176771Srajinterrupt_vector_base: 395176771Sraj 396187153Sraj/***************************************************************************** 397176771Sraj * Critical input interrupt 398187153Sraj ****************************************************************************/ 399176771SrajINTERRUPT(int_critical_input) 400176771Sraj STANDARD_PROLOG(SPR_SPRG2, PC_BOOKE_CRITSAVE, SPR_CSRR0, SPR_CSRR1) 401176771Sraj FRAME_SETUP(SPR_SPRG2, PC_BOOKE_CRITSAVE, EXC_CRIT) 402176771Sraj addi %r3, %r1, 8 403176771Sraj bl CNAME(powerpc_crit_interrupt) 404176771Sraj FRAME_LEAVE(SPR_CSRR0, SPR_CSRR1) 405176771Sraj rfci 406176771Sraj 407176771Sraj 408187153Sraj/***************************************************************************** 409176771Sraj * Machine check interrupt 410187153Sraj ****************************************************************************/ 411176771SrajINTERRUPT(int_machine_check) 412176771Sraj STANDARD_PROLOG(SPR_SPRG3, PC_BOOKE_MCHKSAVE, SPR_MCSRR0, SPR_MCSRR1) 413176771Sraj FRAME_SETUP(SPR_SPRG3, PC_BOOKE_MCHKSAVE, EXC_MCHK) 414176771Sraj addi %r3, %r1, 8 415176771Sraj bl CNAME(powerpc_mchk_interrupt) 416176771Sraj FRAME_LEAVE(SPR_MCSRR0, SPR_MCSRR1) 417176771Sraj rfmci 418176771Sraj 419176771Sraj 420187153Sraj/***************************************************************************** 421176771Sraj * Data storage interrupt 422187153Sraj ****************************************************************************/ 423176771SrajINTERRUPT(int_data_storage) 424176771Sraj STANDARD_PROLOG(SPR_SPRG1, PC_DISISAVE, SPR_SRR0, SPR_SRR1) 425176771Sraj FRAME_SETUP(SPR_SPRG1, PC_DISISAVE, EXC_DSI) 426176771Sraj b trap_common 427176771Sraj 428176771Sraj 429187153Sraj/***************************************************************************** 430176771Sraj * Instruction storage interrupt 431187153Sraj ****************************************************************************/ 432176771SrajINTERRUPT(int_instr_storage) 433176771Sraj STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 434176771Sraj FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_ISI) 435176771Sraj b trap_common 436176771Sraj 437176771Sraj 438187153Sraj/***************************************************************************** 439176771Sraj * External input interrupt 440187153Sraj ****************************************************************************/ 441176771SrajINTERRUPT(int_external_input) 442176771Sraj STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 443176771Sraj FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_EXI) 444205495Smarcel addi %r3, %r1, 8 445176771Sraj bl CNAME(powerpc_extr_interrupt) 446176771Sraj b trapexit 447176771Sraj 448176771Sraj 449176771SrajINTERRUPT(int_alignment) 450176771Sraj STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 451176771Sraj FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_ALI) 452176771Sraj b trap_common 453176771Sraj 454176771Sraj 455176771SrajINTERRUPT(int_program) 456176771Sraj STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 457176771Sraj FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_PGM) 458176771Sraj b trap_common 459176771Sraj 460176771Sraj 461187153Sraj/***************************************************************************** 462176771Sraj * System call 463187153Sraj ****************************************************************************/ 464176771SrajINTERRUPT(int_syscall) 465176771Sraj STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 466176771Sraj FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_SC) 467176771Sraj b trap_common 468176771Sraj 469176771Sraj 470187153Sraj/***************************************************************************** 471176771Sraj * Decrementer interrupt 472187153Sraj ****************************************************************************/ 473176771SrajINTERRUPT(int_decrementer) 474176771Sraj STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 475176771Sraj FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_DECR) 476176771Sraj addi %r3, %r1, 8 477176771Sraj bl CNAME(powerpc_decr_interrupt) 478176771Sraj b trapexit 479176771Sraj 480176771Sraj 481187153Sraj/***************************************************************************** 482176771Sraj * Fixed interval timer 483187153Sraj ****************************************************************************/ 484176771SrajINTERRUPT(int_fixed_interval_timer) 485176771Sraj STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 486176771Sraj FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_FIT) 487176771Sraj b trap_common 488176771Sraj 489176771Sraj 490187153Sraj/***************************************************************************** 491176771Sraj * Watchdog interrupt 492187153Sraj ****************************************************************************/ 493176771SrajINTERRUPT(int_watchdog) 494176771Sraj STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 495176771Sraj FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_WDOG) 496176771Sraj b trap_common 497176771Sraj 498176771Sraj 499187153Sraj/***************************************************************************** 500176771Sraj * Data TLB miss interrupt 501176771Sraj * 502187153Sraj * There can be nested TLB misses - while handling a TLB miss we reference 503187153Sraj * data structures that may be not covered by translations. We support up to 504176771Sraj * TLB_NESTED_MAX-1 nested misses. 505176771Sraj * 506176771Sraj * Registers use: 507176771Sraj * r31 - dear 508187153Sraj * r30 - unused 509176771Sraj * r29 - saved mas0 510176771Sraj * r28 - saved mas1 511176771Sraj * r27 - saved mas2 512176771Sraj * r26 - pmap address 513176771Sraj * r25 - pte address 514176771Sraj * 515176771Sraj * r20:r23 - scratch registers 516187153Sraj ****************************************************************************/ 517176771SrajINTERRUPT(int_data_tlb_error) 518176771Sraj TLB_PROLOG 519192532Sraj TLB_LOCK 520176771Sraj 521176771Sraj mfdear %r31 522176771Sraj 523176771Sraj /* 524187149Sraj * Save MAS0-MAS2 registers. There might be another tlb miss during 525187149Sraj * pte lookup overwriting current contents (which was hw filled). 526176771Sraj */ 527176771Sraj mfspr %r29, SPR_MAS0 528176771Sraj mfspr %r28, SPR_MAS1 529176771Sraj mfspr %r27, SPR_MAS2 530176771Sraj 531176771Sraj /* Check faulting address. */ 532176771Sraj lis %r21, VM_MAXUSER_ADDRESS@h 533176771Sraj ori %r21, %r21, VM_MAXUSER_ADDRESS@l 534176771Sraj cmplw cr0, %r31, %r21 535176771Sraj blt search_user_pmap 536176771Sraj 537176771Sraj /* If it's kernel address, allow only supervisor mode misses. */ 538176771Sraj mfsrr1 %r21 539176771Sraj mtcr %r21 540176771Sraj bt 17, search_failed /* check MSR[PR] */ 541176771Sraj 542176771Srajsearch_kernel_pmap: 543176771Sraj /* Load r26 with kernel_pmap address */ 544176771Sraj lis %r26, kernel_pmap_store@h 545176771Sraj ori %r26, %r26, kernel_pmap_store@l 546176771Sraj 547176771Sraj /* Force kernel tid, set TID to 0 in MAS1. */ 548176771Sraj li %r21, 0 549176771Sraj rlwimi %r28, %r21, 0, 8, 15 /* clear TID bits */ 550176771Sraj 551176771Srajtlb_miss_handle: 552176771Sraj /* This may result in nested tlb miss. */ 553176771Sraj bl pte_lookup /* returns PTE address in R25 */ 554176771Sraj 555176771Sraj cmpwi %r25, 0 /* pte found? */ 556176771Sraj beq search_failed 557176771Sraj 558176771Sraj /* Finish up, write TLB entry. */ 559176771Sraj bl tlb_fill_entry 560176771Sraj 561176771Srajtlb_miss_return: 562192532Sraj TLB_UNLOCK 563176771Sraj TLB_RESTORE 564176771Sraj rfi 565176771Sraj 566176771Srajsearch_user_pmap: 567176771Sraj /* Load r26 with current user space process pmap */ 568176771Sraj GET_CPUINFO(%r26) 569176771Sraj lwz %r26, PC_CURPMAP(%r26) 570176771Sraj 571176771Sraj b tlb_miss_handle 572176771Sraj 573176771Srajsearch_failed: 574176771Sraj /* 575176771Sraj * Whenever we don't find a TLB mapping in PT, set a TLB0 entry with 576176771Sraj * the faulting virtual address anyway, but put a fake RPN and no 577176771Sraj * access rights. This should cause a following {D,I}SI exception. 578176771Sraj */ 579176771Sraj lis %r23, 0xffff0000@h /* revoke all permissions */ 580176771Sraj 581176771Sraj /* Load MAS registers. */ 582176771Sraj mtspr SPR_MAS0, %r29 583176771Sraj isync 584176771Sraj mtspr SPR_MAS1, %r28 585176771Sraj isync 586176771Sraj mtspr SPR_MAS2, %r27 587176771Sraj isync 588176771Sraj mtspr SPR_MAS3, %r23 589176771Sraj isync 590176771Sraj 591176771Sraj tlbwe 592176771Sraj msync 593176771Sraj isync 594176771Sraj b tlb_miss_return 595176771Sraj 596187149Sraj/***************************************************************************** 597176771Sraj * 598187149Sraj * Return pte address that corresponds to given pmap/va. If there is no valid 599187149Sraj * entry return 0. 600176771Sraj * 601176771Sraj * input: r26 - pmap 602176771Sraj * input: r31 - dear 603176771Sraj * output: r25 - pte address 604176771Sraj * 605176771Sraj * scratch regs used: r21 606187149Sraj * 607187149Sraj ****************************************************************************/ 608176771Srajpte_lookup: 609176771Sraj cmpwi %r26, 0 610176771Sraj beq 1f /* fail quickly if pmap is invalid */ 611176771Sraj 612176771Sraj srwi %r21, %r31, PDIR_SHIFT /* pdir offset */ 613176771Sraj slwi %r21, %r21, PDIR_ENTRY_SHIFT /* multiply by pdir entry size */ 614176771Sraj 615176771Sraj addi %r25, %r26, PM_PDIR /* pmap pm_dir[] address */ 616176771Sraj add %r25, %r25, %r21 /* offset within pm_pdir[] table */ 617187153Sraj /* 618187153Sraj * Get ptbl address, i.e. pmap->pm_pdir[pdir_idx] 619187153Sraj * This load may cause a Data TLB miss for non-kernel pmap! 620187153Sraj */ 621187153Sraj lwz %r25, 0(%r25) 622176771Sraj cmpwi %r25, 0 623176771Sraj beq 2f 624176771Sraj 625176771Sraj lis %r21, PTBL_MASK@h 626176771Sraj ori %r21, %r21, PTBL_MASK@l 627176771Sraj and %r21, %r21, %r31 628176771Sraj 629176771Sraj /* ptbl offset, multiply by ptbl entry size */ 630176771Sraj srwi %r21, %r21, (PTBL_SHIFT - PTBL_ENTRY_SHIFT) 631176771Sraj 632176771Sraj add %r25, %r25, %r21 /* address of pte entry */ 633187153Sraj /* 634187153Sraj * Get pte->flags 635187153Sraj * This load may cause a Data TLB miss for non-kernel pmap! 636187153Sraj */ 637187153Sraj lwz %r21, PTE_FLAGS(%r25) 638176771Sraj andis. %r21, %r21, PTE_VALID@h 639176771Sraj bne 2f 640176771Sraj1: 641176771Sraj li %r25, 0 642176771Sraj2: 643176771Sraj blr 644176771Sraj 645187149Sraj/***************************************************************************** 646176771Sraj * 647187149Sraj * Load MAS1-MAS3 registers with data, write TLB entry 648187149Sraj * 649176771Sraj * input: 650176771Sraj * r29 - mas0 651176771Sraj * r28 - mas1 652176771Sraj * r27 - mas2 653176771Sraj * r25 - pte 654176771Sraj * 655176771Sraj * output: none 656176771Sraj * 657176771Sraj * scratch regs: r21-r23 658187149Sraj * 659187149Sraj ****************************************************************************/ 660176771Srajtlb_fill_entry: 661187149Sraj /* 662187149Sraj * Update PTE flags: we have to do it atomically, as pmap_protect() 663187149Sraj * running on other CPUs could attempt to update the flags at the same 664187149Sraj * time. 665187149Sraj */ 666187149Sraj li %r23, PTE_FLAGS 667187149Sraj1: 668187149Sraj lwarx %r21, %r23, %r25 /* get pte->flags */ 669176771Sraj oris %r21, %r21, PTE_REFERENCED@h /* set referenced bit */ 670176771Sraj 671176771Sraj andi. %r22, %r21, (PTE_UW | PTE_UW)@l /* check if writable */ 672187149Sraj beq 2f 673176771Sraj oris %r21, %r21, PTE_MODIFIED@h /* set modified bit */ 674187149Sraj2: 675187149Sraj stwcx. %r21, %r23, %r25 /* write it back */ 676187149Sraj bne- 1b 677176771Sraj 678176771Sraj /* Update MAS2. */ 679176771Sraj rlwimi %r27, %r21, 0, 27, 30 /* insert WIMG bits from pte */ 680176771Sraj 681176771Sraj /* Setup MAS3 value in r23. */ 682176771Sraj lwz %r23, PTE_RPN(%r25) /* get pte->rpn */ 683176771Sraj 684176771Sraj rlwimi %r23, %r21, 24, 26, 31 /* insert protection bits from pte */ 685176771Sraj 686176771Sraj /* Load MAS registers. */ 687176771Sraj mtspr SPR_MAS0, %r29 688176771Sraj isync 689176771Sraj mtspr SPR_MAS1, %r28 690176771Sraj isync 691176771Sraj mtspr SPR_MAS2, %r27 692176771Sraj isync 693176771Sraj mtspr SPR_MAS3, %r23 694176771Sraj isync 695176771Sraj 696176771Sraj tlbwe 697176771Sraj isync 698176771Sraj msync 699176771Sraj blr 700176771Sraj 701187153Sraj/***************************************************************************** 702176771Sraj * Instruction TLB miss interrupt 703176771Sraj * 704176771Sraj * Same notes as for the Data TLB miss 705187153Sraj ****************************************************************************/ 706176771SrajINTERRUPT(int_inst_tlb_error) 707176771Sraj TLB_PROLOG 708192532Sraj TLB_LOCK 709176771Sraj 710176771Sraj mfsrr0 %r31 /* faulting address */ 711176771Sraj 712176771Sraj /* 713176771Sraj * Save MAS0-MAS2 registers. There might be another tlb miss during pte 714176771Sraj * lookup overwriting current contents (which was hw filled). 715176771Sraj */ 716176771Sraj mfspr %r29, SPR_MAS0 717176771Sraj mfspr %r28, SPR_MAS1 718176771Sraj mfspr %r27, SPR_MAS2 719176771Sraj 720176771Sraj mfsrr1 %r21 721176771Sraj mtcr %r21 722176771Sraj 723176771Sraj /* check MSR[PR] */ 724176771Sraj bt 17, search_user_pmap 725176771Sraj b search_kernel_pmap 726176771Sraj 727176771Sraj 728176771Sraj .globl interrupt_vector_top 729176771Srajinterrupt_vector_top: 730176771Sraj 731187153Sraj/***************************************************************************** 732176771Sraj * Debug interrupt 733187153Sraj ****************************************************************************/ 734176771SrajINTERRUPT(int_debug) 735176771Sraj STANDARD_CRIT_PROLOG(SPR_SPRG2, PC_BOOKE_CRITSAVE, SPR_CSRR0, SPR_CSRR1) 736176771Sraj FRAME_SETUP(SPR_SPRG2, PC_BOOKE_CRITSAVE, EXC_DEBUG) 737176771Sraj lwz %r3, (PC_BOOKE_CRITSAVE+CPUSAVE_SRR0)(%r2); 738176771Sraj lis %r4, interrupt_vector_base@ha 739176771Sraj addi %r4, %r4, interrupt_vector_base@l 740176771Sraj cmplw cr0, %r3, %r4 741176771Sraj blt 1f 742176771Sraj lis %r4, interrupt_vector_top@ha 743176771Sraj addi %r4, %r4, interrupt_vector_top@l 744176771Sraj cmplw cr0, %r3, %r4 745176771Sraj bge 1f 746176771Sraj /* Disable single-stepping for the interrupt handlers. */ 747176771Sraj lwz %r3, FRAME_SRR1+8(%r1); 748187153Sraj rlwinm %r3, %r3, 0, 23, 21 749176771Sraj stw %r3, FRAME_SRR1+8(%r1); 750176771Sraj /* Restore srr0 and srr1 as they could have been clobbered. */ 751176771Sraj lwz %r3, (PC_BOOKE_CRITSAVE+CPUSAVE_SRR0+8)(%r2); 752176771Sraj mtspr SPR_SRR0, %r3 753176771Sraj lwz %r4, (PC_BOOKE_CRITSAVE+CPUSAVE_SRR1+8)(%r2); 754176771Sraj mtspr SPR_SRR1, %r4 755176771Sraj b 9f 756176771Sraj1: 757176771Sraj addi %r3, %r1, 8 758176771Sraj bl CNAME(trap) 759176771Sraj /* 760176771Sraj * Handle ASTs, needed for proper support of single-stepping. 761176771Sraj * We actually need to return to the process with an rfi. 762176771Sraj */ 763176771Sraj b trapexit 764176771Sraj9: 765176771Sraj FRAME_LEAVE(SPR_CSRR0, SPR_CSRR1) 766176771Sraj rfci 767176771Sraj 768176771Sraj 769187153Sraj/***************************************************************************** 770176771Sraj * Common trap code 771187153Sraj ****************************************************************************/ 772176771Srajtrap_common: 773176771Sraj /* Call C trap dispatcher */ 774176771Sraj addi %r3, %r1, 8 775176771Sraj bl CNAME(trap) 776176771Sraj 777176771Sraj .globl CNAME(trapexit) /* exported for db_backtrace use */ 778176771SrajCNAME(trapexit): 779176771Sraj /* disable interrupts */ 780176771Sraj wrteei 0 781176771Sraj 782176771Sraj /* Test AST pending - makes sense for user process only */ 783176771Sraj lwz %r5, FRAME_SRR1+8(%r1) 784176771Sraj mtcr %r5 785176771Sraj bf 17, 1f 786176771Sraj 787176771Sraj GET_CPUINFO(%r3) 788176771Sraj lwz %r4, PC_CURTHREAD(%r3) 789176771Sraj lwz %r4, TD_FLAGS(%r4) 790187153Sraj lis %r5, (TDF_ASTPENDING | TDF_NEEDRESCHED)@h 791187153Sraj ori %r5, %r5, (TDF_ASTPENDING | TDF_NEEDRESCHED)@l 792176771Sraj and. %r4, %r4, %r5 793176771Sraj beq 1f 794176771Sraj 795176771Sraj /* re-enable interrupts before calling ast() */ 796176771Sraj wrteei 1 797176771Sraj 798176771Sraj addi %r3, %r1, 8 799176771Sraj bl CNAME(ast) 800176771Sraj .globl CNAME(asttrapexit) /* db_backtrace code sentinel #2 */ 801176771SrajCNAME(asttrapexit): 802176771Sraj b trapexit /* test ast ret value ? */ 803176771Sraj1: 804176771Sraj FRAME_LEAVE(SPR_SRR0, SPR_SRR1) 805176771Sraj rfi 806176771Sraj 807176771Sraj 808176771Sraj#if defined(KDB) 809176771Sraj/* 810176771Sraj * Deliberate entry to dbtrap 811176771Sraj */ 812178628Smarcel .globl CNAME(breakpoint) 813178628SmarcelCNAME(breakpoint): 814176771Sraj mtsprg1 %r1 815176771Sraj mfmsr %r3 816176771Sraj mtsrr1 %r3 817187153Sraj andi. %r3, %r3, ~(PSL_EE | PSL_ME)@l 818176771Sraj mtmsr %r3 /* disable interrupts */ 819176771Sraj isync 820176771Sraj GET_CPUINFO(%r3) 821187153Sraj stw %r30, (PC_DBSAVE+CPUSAVE_R30)(%r3) 822187153Sraj stw %r31, (PC_DBSAVE+CPUSAVE_R31)(%r3) 823176771Sraj 824176771Sraj mflr %r31 825176771Sraj mtsrr0 %r31 826176771Sraj 827176771Sraj mfdear %r30 828176771Sraj mfesr %r31 829176771Sraj stw %r30, (PC_DBSAVE+CPUSAVE_BOOKE_DEAR)(%r3) 830176771Sraj stw %r31, (PC_DBSAVE+CPUSAVE_BOOKE_ESR)(%r3) 831176771Sraj 832176771Sraj mfsrr0 %r30 833176771Sraj mfsrr1 %r31 834176771Sraj stw %r30, (PC_DBSAVE+CPUSAVE_SRR0)(%r3) 835176771Sraj stw %r31, (PC_DBSAVE+CPUSAVE_SRR1)(%r3) 836176771Sraj isync 837176771Sraj 838176771Sraj mfcr %r30 839176771Sraj 840176771Sraj/* 841176771Sraj * Now the kdb trap catching code. 842176771Sraj */ 843176771Srajdbtrap: 844176771Sraj FRAME_SETUP(SPR_SPRG1, PC_DBSAVE, EXC_DEBUG) 845176771Sraj/* Call C trap code: */ 846187153Sraj addi %r3, %r1, 8 847176771Sraj bl CNAME(db_trap_glue) 848187153Sraj or. %r3, %r3, %r3 849176771Sraj bne dbleave 850176771Sraj/* This wasn't for KDB, so switch to real trap: */ 851176771Sraj b trap_common 852176771Sraj 853176771Srajdbleave: 854176771Sraj FRAME_LEAVE(SPR_SRR0, SPR_SRR1) 855176771Sraj rfi 856176771Sraj#endif /* KDB */ 857192532Sraj 858192532Sraj#ifdef SMP 859192532SrajENTRY(tlb_lock) 860192532Sraj GET_CPUINFO(%r5) 861192532Sraj lwz %r5, PC_CURTHREAD(%r5) 862192532Sraj1: lwarx %r4, 0, %r3 863215119Sraj cmpwi %r4, TLB_UNLOCKED 864192532Sraj bne 1b 865192532Sraj stwcx. %r5, 0, %r3 866192532Sraj bne- 1b 867192532Sraj isync 868192532Sraj msync 869192532Sraj blr 870192532Sraj 871192532SrajENTRY(tlb_unlock) 872192532Sraj isync 873192532Sraj msync 874215119Sraj li %r4, TLB_UNLOCKED 875192532Sraj stw %r4, 0(%r3) 876192532Sraj isync 877192532Sraj msync 878192532Sraj blr 879215119Sraj 880192532Sraj/* 881192532Sraj * TLB miss spin locks. For each CPU we have a reservation granule (32 bytes); 882192532Sraj * only a single word from this granule will actually be used as a spin lock 883192532Sraj * for mutual exclusion between TLB miss handler and pmap layer that 884192532Sraj * manipulates page table contents. 885192532Sraj */ 886192532Sraj .data 887192532Sraj .align 5 888192532SrajGLOBAL(tlb0_miss_locks) 889192532Sraj .space RES_GRANULE * MAXCPU 890192532Sraj#endif 891