pmap.c revision 222400
1/*- 2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * Some hw specific parts of this pmap were derived or influenced 27 * by NetBSD's ibm4xx pmap module. More generic code is shared with 28 * a few other pmap modules from the FreeBSD tree. 29 */ 30 31 /* 32 * VM layout notes: 33 * 34 * Kernel and user threads run within one common virtual address space 35 * defined by AS=0. 36 * 37 * Virtual address space layout: 38 * ----------------------------- 39 * 0x0000_0000 - 0xafff_ffff : user process 40 * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 41 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 42 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 43 * 0xc100_0000 - 0xfeef_ffff : KVA 44 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 45 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 46 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 47 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 48 * 0xfef0_0000 - 0xffff_ffff : I/O devices region 49 */ 50 51#include <sys/cdefs.h> 52__FBSDID("$FreeBSD: head/sys/powerpc/booke/pmap.c 222400 2011-05-28 04:10:44Z marcel $"); 53 54#include <sys/types.h> 55#include <sys/param.h> 56#include <sys/malloc.h> 57#include <sys/ktr.h> 58#include <sys/proc.h> 59#include <sys/user.h> 60#include <sys/queue.h> 61#include <sys/systm.h> 62#include <sys/kernel.h> 63#include <sys/msgbuf.h> 64#include <sys/lock.h> 65#include <sys/mutex.h> 66#include <sys/smp.h> 67#include <sys/vmmeter.h> 68 69#include <vm/vm.h> 70#include <vm/vm_page.h> 71#include <vm/vm_kern.h> 72#include <vm/vm_pageout.h> 73#include <vm/vm_extern.h> 74#include <vm/vm_object.h> 75#include <vm/vm_param.h> 76#include <vm/vm_map.h> 77#include <vm/vm_pager.h> 78#include <vm/uma.h> 79 80#include <machine/cpu.h> 81#include <machine/pcb.h> 82#include <machine/platform.h> 83 84#include <machine/tlb.h> 85#include <machine/spr.h> 86#include <machine/vmparam.h> 87#include <machine/md_var.h> 88#include <machine/mmuvar.h> 89#include <machine/pmap.h> 90#include <machine/pte.h> 91 92#include "mmu_if.h" 93 94#ifdef DEBUG 95#define debugf(fmt, args...) printf(fmt, ##args) 96#else 97#define debugf(fmt, args...) 98#endif 99 100#define TODO panic("%s: not implemented", __func__); 101 102#include "opt_sched.h" 103#ifndef SCHED_4BSD 104#error "e500 only works with SCHED_4BSD which uses a global scheduler lock." 105#endif 106extern struct mtx sched_lock; 107 108extern int dumpsys_minidump; 109 110extern unsigned char _etext[]; 111extern unsigned char _end[]; 112 113/* Kernel physical load address. */ 114extern uint32_t kernload; 115vm_offset_t kernstart; 116vm_size_t kernsize; 117 118/* Message buffer and tables. */ 119static vm_offset_t data_start; 120static vm_size_t data_end; 121 122/* Phys/avail memory regions. */ 123static struct mem_region *availmem_regions; 124static int availmem_regions_sz; 125static struct mem_region *physmem_regions; 126static int physmem_regions_sz; 127 128/* Reserved KVA space and mutex for mmu_booke_zero_page. */ 129static vm_offset_t zero_page_va; 130static struct mtx zero_page_mutex; 131 132static struct mtx tlbivax_mutex; 133 134/* 135 * Reserved KVA space for mmu_booke_zero_page_idle. This is used 136 * by idle thred only, no lock required. 137 */ 138static vm_offset_t zero_page_idle_va; 139 140/* Reserved KVA space and mutex for mmu_booke_copy_page. */ 141static vm_offset_t copy_page_src_va; 142static vm_offset_t copy_page_dst_va; 143static struct mtx copy_page_mutex; 144 145/**************************************************************************/ 146/* PMAP */ 147/**************************************************************************/ 148 149static void mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 150 vm_prot_t, boolean_t); 151 152unsigned int kptbl_min; /* Index of the first kernel ptbl. */ 153unsigned int kernel_ptbls; /* Number of KVA ptbls. */ 154 155/* 156 * If user pmap is processed with mmu_booke_remove and the resident count 157 * drops to 0, there are no more pages to remove, so we need not continue. 158 */ 159#define PMAP_REMOVE_DONE(pmap) \ 160 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 161 162extern void tid_flush(tlbtid_t); 163 164/**************************************************************************/ 165/* TLB and TID handling */ 166/**************************************************************************/ 167 168/* Translation ID busy table */ 169static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 170 171/* 172 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 173 * core revisions and should be read from h/w registers during early config. 174 */ 175uint32_t tlb0_entries; 176uint32_t tlb0_ways; 177uint32_t tlb0_entries_per_way; 178 179#define TLB0_ENTRIES (tlb0_entries) 180#define TLB0_WAYS (tlb0_ways) 181#define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 182 183#define TLB1_ENTRIES 16 184 185/* In-ram copy of the TLB1 */ 186static tlb_entry_t tlb1[TLB1_ENTRIES]; 187 188/* Next free entry in the TLB1 */ 189static unsigned int tlb1_idx; 190 191static tlbtid_t tid_alloc(struct pmap *); 192 193static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 194 195static int tlb1_set_entry(vm_offset_t, vm_offset_t, vm_size_t, uint32_t); 196static void tlb1_write_entry(unsigned int); 197static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 198static vm_size_t tlb1_mapin_region(vm_offset_t, vm_offset_t, vm_size_t); 199 200static vm_size_t tsize2size(unsigned int); 201static unsigned int size2tsize(vm_size_t); 202static unsigned int ilog2(unsigned int); 203 204static void set_mas4_defaults(void); 205 206static inline void tlb0_flush_entry(vm_offset_t); 207static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 208 209/**************************************************************************/ 210/* Page table management */ 211/**************************************************************************/ 212 213/* Data for the pv entry allocation mechanism */ 214static uma_zone_t pvzone; 215static struct vm_object pvzone_obj; 216static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 217 218#define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 219 220#ifndef PMAP_SHPGPERPROC 221#define PMAP_SHPGPERPROC 200 222#endif 223 224static void ptbl_init(void); 225static struct ptbl_buf *ptbl_buf_alloc(void); 226static void ptbl_buf_free(struct ptbl_buf *); 227static void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 228 229static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int); 230static void ptbl_free(mmu_t, pmap_t, unsigned int); 231static void ptbl_hold(mmu_t, pmap_t, unsigned int); 232static int ptbl_unhold(mmu_t, pmap_t, unsigned int); 233 234static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 235static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 236static void pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t); 237static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t); 238 239static pv_entry_t pv_alloc(void); 240static void pv_free(pv_entry_t); 241static void pv_insert(pmap_t, vm_offset_t, vm_page_t); 242static void pv_remove(pmap_t, vm_offset_t, vm_page_t); 243 244/* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 245#define PTBL_BUFS (128 * 16) 246 247struct ptbl_buf { 248 TAILQ_ENTRY(ptbl_buf) link; /* list link */ 249 vm_offset_t kva; /* va of mapping */ 250}; 251 252/* ptbl free list and a lock used for access synchronization. */ 253static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 254static struct mtx ptbl_buf_freelist_lock; 255 256/* Base address of kva space allocated fot ptbl bufs. */ 257static vm_offset_t ptbl_buf_pool_vabase; 258 259/* Pointer to ptbl_buf structures. */ 260static struct ptbl_buf *ptbl_bufs; 261 262void pmap_bootstrap_ap(volatile uint32_t *); 263 264/* 265 * Kernel MMU interface 266 */ 267static void mmu_booke_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 268static void mmu_booke_clear_modify(mmu_t, vm_page_t); 269static void mmu_booke_clear_reference(mmu_t, vm_page_t); 270static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t, 271 vm_size_t, vm_offset_t); 272static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 273static void mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 274 vm_prot_t, boolean_t); 275static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 276 vm_page_t, vm_prot_t); 277static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 278 vm_prot_t); 279static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 280static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 281 vm_prot_t); 282static void mmu_booke_init(mmu_t); 283static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 284static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 285static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t); 286static boolean_t mmu_booke_ts_referenced(mmu_t, vm_page_t); 287static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, 288 int); 289static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t, 290 vm_paddr_t *); 291static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 292 vm_object_t, vm_pindex_t, vm_size_t); 293static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 294static void mmu_booke_page_init(mmu_t, vm_page_t); 295static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 296static void mmu_booke_pinit(mmu_t, pmap_t); 297static void mmu_booke_pinit0(mmu_t, pmap_t); 298static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 299 vm_prot_t); 300static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 301static void mmu_booke_qremove(mmu_t, vm_offset_t, int); 302static void mmu_booke_release(mmu_t, pmap_t); 303static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 304static void mmu_booke_remove_all(mmu_t, vm_page_t); 305static void mmu_booke_remove_write(mmu_t, vm_page_t); 306static void mmu_booke_zero_page(mmu_t, vm_page_t); 307static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 308static void mmu_booke_zero_page_idle(mmu_t, vm_page_t); 309static void mmu_booke_activate(mmu_t, struct thread *); 310static void mmu_booke_deactivate(mmu_t, struct thread *); 311static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 312static void *mmu_booke_mapdev(mmu_t, vm_offset_t, vm_size_t); 313static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 314static vm_offset_t mmu_booke_kextract(mmu_t, vm_offset_t); 315static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_offset_t); 316static void mmu_booke_kremove(mmu_t, vm_offset_t); 317static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 318static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t, 319 vm_size_t); 320static vm_offset_t mmu_booke_dumpsys_map(mmu_t, struct pmap_md *, 321 vm_size_t, vm_size_t *); 322static void mmu_booke_dumpsys_unmap(mmu_t, struct pmap_md *, 323 vm_size_t, vm_offset_t); 324static struct pmap_md *mmu_booke_scan_md(mmu_t, struct pmap_md *); 325 326static mmu_method_t mmu_booke_methods[] = { 327 /* pmap dispatcher interface */ 328 MMUMETHOD(mmu_change_wiring, mmu_booke_change_wiring), 329 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 330 MMUMETHOD(mmu_clear_reference, mmu_booke_clear_reference), 331 MMUMETHOD(mmu_copy, mmu_booke_copy), 332 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 333 MMUMETHOD(mmu_enter, mmu_booke_enter), 334 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 335 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 336 MMUMETHOD(mmu_extract, mmu_booke_extract), 337 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 338 MMUMETHOD(mmu_init, mmu_booke_init), 339 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 340 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 341 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced), 342 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 343 MMUMETHOD(mmu_map, mmu_booke_map), 344 MMUMETHOD(mmu_mincore, mmu_booke_mincore), 345 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 346 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 347 MMUMETHOD(mmu_page_init, mmu_booke_page_init), 348 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 349 MMUMETHOD(mmu_pinit, mmu_booke_pinit), 350 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 351 MMUMETHOD(mmu_protect, mmu_booke_protect), 352 MMUMETHOD(mmu_qenter, mmu_booke_qenter), 353 MMUMETHOD(mmu_qremove, mmu_booke_qremove), 354 MMUMETHOD(mmu_release, mmu_booke_release), 355 MMUMETHOD(mmu_remove, mmu_booke_remove), 356 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 357 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 358 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache), 359 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 360 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 361 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle), 362 MMUMETHOD(mmu_activate, mmu_booke_activate), 363 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 364 365 /* Internal interfaces */ 366 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 367 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 368 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 369 MMUMETHOD(mmu_kenter, mmu_booke_kenter), 370 MMUMETHOD(mmu_kextract, mmu_booke_kextract), 371/* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */ 372 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 373 374 /* dumpsys() support */ 375 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map), 376 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap), 377 MMUMETHOD(mmu_scan_md, mmu_booke_scan_md), 378 379 { 0, 0 } 380}; 381 382MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0); 383 384static inline void 385tlb_miss_lock(void) 386{ 387#ifdef SMP 388 struct pcpu *pc; 389 390 if (!smp_started) 391 return; 392 393 SLIST_FOREACH(pc, &cpuhead, pc_allcpu) { 394 if (pc != pcpup) { 395 396 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 397 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock); 398 399 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 400 ("tlb_miss_lock: tried to lock self")); 401 402 tlb_lock(pc->pc_booke_tlb_lock); 403 404 CTR1(KTR_PMAP, "%s: locked", __func__); 405 } 406 } 407#endif 408} 409 410static inline void 411tlb_miss_unlock(void) 412{ 413#ifdef SMP 414 struct pcpu *pc; 415 416 if (!smp_started) 417 return; 418 419 SLIST_FOREACH(pc, &cpuhead, pc_allcpu) { 420 if (pc != pcpup) { 421 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 422 __func__, pc->pc_cpuid); 423 424 tlb_unlock(pc->pc_booke_tlb_lock); 425 426 CTR1(KTR_PMAP, "%s: unlocked", __func__); 427 } 428 } 429#endif 430} 431 432/* Return number of entries in TLB0. */ 433static __inline void 434tlb0_get_tlbconf(void) 435{ 436 uint32_t tlb0_cfg; 437 438 tlb0_cfg = mfspr(SPR_TLB0CFG); 439 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 440 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 441 tlb0_entries_per_way = tlb0_entries / tlb0_ways; 442} 443 444/* Initialize pool of kva ptbl buffers. */ 445static void 446ptbl_init(void) 447{ 448 int i; 449 450 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__, 451 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 452 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)", 453 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 454 455 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 456 TAILQ_INIT(&ptbl_buf_freelist); 457 458 for (i = 0; i < PTBL_BUFS; i++) { 459 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 460 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 461 } 462} 463 464/* Get a ptbl_buf from the freelist. */ 465static struct ptbl_buf * 466ptbl_buf_alloc(void) 467{ 468 struct ptbl_buf *buf; 469 470 mtx_lock(&ptbl_buf_freelist_lock); 471 buf = TAILQ_FIRST(&ptbl_buf_freelist); 472 if (buf != NULL) 473 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 474 mtx_unlock(&ptbl_buf_freelist_lock); 475 476 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 477 478 return (buf); 479} 480 481/* Return ptbl buff to free pool. */ 482static void 483ptbl_buf_free(struct ptbl_buf *buf) 484{ 485 486 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 487 488 mtx_lock(&ptbl_buf_freelist_lock); 489 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 490 mtx_unlock(&ptbl_buf_freelist_lock); 491} 492 493/* 494 * Search the list of allocated ptbl bufs and find on list of allocated ptbls 495 */ 496static void 497ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 498{ 499 struct ptbl_buf *pbuf; 500 501 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 502 503 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 504 505 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) 506 if (pbuf->kva == (vm_offset_t)ptbl) { 507 /* Remove from pmap ptbl buf list. */ 508 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 509 510 /* Free corresponding ptbl buf. */ 511 ptbl_buf_free(pbuf); 512 break; 513 } 514} 515 516/* Allocate page table. */ 517static pte_t * 518ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 519{ 520 vm_page_t mtbl[PTBL_PAGES]; 521 vm_page_t m; 522 struct ptbl_buf *pbuf; 523 unsigned int pidx; 524 pte_t *ptbl; 525 int i; 526 527 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 528 (pmap == kernel_pmap), pdir_idx); 529 530 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 531 ("ptbl_alloc: invalid pdir_idx")); 532 KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 533 ("pte_alloc: valid ptbl entry exists!")); 534 535 pbuf = ptbl_buf_alloc(); 536 if (pbuf == NULL) 537 panic("pte_alloc: couldn't alloc kernel virtual memory"); 538 539 ptbl = (pte_t *)pbuf->kva; 540 541 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl); 542 543 /* Allocate ptbl pages, this will sleep! */ 544 for (i = 0; i < PTBL_PAGES; i++) { 545 pidx = (PTBL_PAGES * pdir_idx) + i; 546 while ((m = vm_page_alloc(NULL, pidx, 547 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 548 549 PMAP_UNLOCK(pmap); 550 vm_page_unlock_queues(); 551 VM_WAIT; 552 vm_page_lock_queues(); 553 PMAP_LOCK(pmap); 554 } 555 mtbl[i] = m; 556 } 557 558 /* Map allocated pages into kernel_pmap. */ 559 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES); 560 561 /* Zero whole ptbl. */ 562 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE); 563 564 /* Add pbuf to the pmap ptbl bufs list. */ 565 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 566 567 return (ptbl); 568} 569 570/* Free ptbl pages and invalidate pdir entry. */ 571static void 572ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 573{ 574 pte_t *ptbl; 575 vm_paddr_t pa; 576 vm_offset_t va; 577 vm_page_t m; 578 int i; 579 580 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 581 (pmap == kernel_pmap), pdir_idx); 582 583 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 584 ("ptbl_free: invalid pdir_idx")); 585 586 ptbl = pmap->pm_pdir[pdir_idx]; 587 588 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 589 590 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 591 592 /* 593 * Invalidate the pdir entry as soon as possible, so that other CPUs 594 * don't attempt to look up the page tables we are releasing. 595 */ 596 mtx_lock_spin(&tlbivax_mutex); 597 tlb_miss_lock(); 598 599 pmap->pm_pdir[pdir_idx] = NULL; 600 601 tlb_miss_unlock(); 602 mtx_unlock_spin(&tlbivax_mutex); 603 604 for (i = 0; i < PTBL_PAGES; i++) { 605 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 606 pa = pte_vatopa(mmu, kernel_pmap, va); 607 m = PHYS_TO_VM_PAGE(pa); 608 vm_page_free_zero(m); 609 atomic_subtract_int(&cnt.v_wire_count, 1); 610 mmu_booke_kremove(mmu, va); 611 } 612 613 ptbl_free_pmap_ptbl(pmap, ptbl); 614} 615 616/* 617 * Decrement ptbl pages hold count and attempt to free ptbl pages. 618 * Called when removing pte entry from ptbl. 619 * 620 * Return 1 if ptbl pages were freed. 621 */ 622static int 623ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 624{ 625 pte_t *ptbl; 626 vm_paddr_t pa; 627 vm_page_t m; 628 int i; 629 630 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 631 (pmap == kernel_pmap), pdir_idx); 632 633 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 634 ("ptbl_unhold: invalid pdir_idx")); 635 KASSERT((pmap != kernel_pmap), 636 ("ptbl_unhold: unholding kernel ptbl!")); 637 638 ptbl = pmap->pm_pdir[pdir_idx]; 639 640 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 641 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 642 ("ptbl_unhold: non kva ptbl")); 643 644 /* decrement hold count */ 645 for (i = 0; i < PTBL_PAGES; i++) { 646 pa = pte_vatopa(mmu, kernel_pmap, 647 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 648 m = PHYS_TO_VM_PAGE(pa); 649 m->wire_count--; 650 } 651 652 /* 653 * Free ptbl pages if there are no pte etries in this ptbl. 654 * wire_count has the same value for all ptbl pages, so check the last 655 * page. 656 */ 657 if (m->wire_count == 0) { 658 ptbl_free(mmu, pmap, pdir_idx); 659 660 //debugf("ptbl_unhold: e (freed ptbl)\n"); 661 return (1); 662 } 663 664 return (0); 665} 666 667/* 668 * Increment hold count for ptbl pages. This routine is used when a new pte 669 * entry is being inserted into the ptbl. 670 */ 671static void 672ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 673{ 674 vm_paddr_t pa; 675 pte_t *ptbl; 676 vm_page_t m; 677 int i; 678 679 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap, 680 pdir_idx); 681 682 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 683 ("ptbl_hold: invalid pdir_idx")); 684 KASSERT((pmap != kernel_pmap), 685 ("ptbl_hold: holding kernel ptbl!")); 686 687 ptbl = pmap->pm_pdir[pdir_idx]; 688 689 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 690 691 for (i = 0; i < PTBL_PAGES; i++) { 692 pa = pte_vatopa(mmu, kernel_pmap, 693 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 694 m = PHYS_TO_VM_PAGE(pa); 695 m->wire_count++; 696 } 697} 698 699/* Allocate pv_entry structure. */ 700pv_entry_t 701pv_alloc(void) 702{ 703 pv_entry_t pv; 704 705 pv_entry_count++; 706 if (pv_entry_count > pv_entry_high_water) 707 pagedaemon_wakeup(); 708 pv = uma_zalloc(pvzone, M_NOWAIT); 709 710 return (pv); 711} 712 713/* Free pv_entry structure. */ 714static __inline void 715pv_free(pv_entry_t pve) 716{ 717 718 pv_entry_count--; 719 uma_zfree(pvzone, pve); 720} 721 722 723/* Allocate and initialize pv_entry structure. */ 724static void 725pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 726{ 727 pv_entry_t pve; 728 729 //int su = (pmap == kernel_pmap); 730 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 731 // (u_int32_t)pmap, va, (u_int32_t)m); 732 733 pve = pv_alloc(); 734 if (pve == NULL) 735 panic("pv_insert: no pv entries!"); 736 737 pve->pv_pmap = pmap; 738 pve->pv_va = va; 739 740 /* add to pv_list */ 741 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 742 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 743 744 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 745 746 //debugf("pv_insert: e\n"); 747} 748 749/* Destroy pv entry. */ 750static void 751pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 752{ 753 pv_entry_t pve; 754 755 //int su = (pmap == kernel_pmap); 756 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 757 758 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 759 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 760 761 /* find pv entry */ 762 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 763 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 764 /* remove from pv_list */ 765 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 766 if (TAILQ_EMPTY(&m->md.pv_list)) 767 vm_page_flag_clear(m, PG_WRITEABLE); 768 769 /* free pv entry struct */ 770 pv_free(pve); 771 break; 772 } 773 } 774 775 //debugf("pv_remove: e\n"); 776} 777 778/* 779 * Clean pte entry, try to free page table page if requested. 780 * 781 * Return 1 if ptbl pages were freed, otherwise return 0. 782 */ 783static int 784pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags) 785{ 786 unsigned int pdir_idx = PDIR_IDX(va); 787 unsigned int ptbl_idx = PTBL_IDX(va); 788 vm_page_t m; 789 pte_t *ptbl; 790 pte_t *pte; 791 792 //int su = (pmap == kernel_pmap); 793 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 794 // su, (u_int32_t)pmap, va, flags); 795 796 ptbl = pmap->pm_pdir[pdir_idx]; 797 KASSERT(ptbl, ("pte_remove: null ptbl")); 798 799 pte = &ptbl[ptbl_idx]; 800 801 if (pte == NULL || !PTE_ISVALID(pte)) 802 return (0); 803 804 if (PTE_ISWIRED(pte)) 805 pmap->pm_stats.wired_count--; 806 807 /* Handle managed entry. */ 808 if (PTE_ISMANAGED(pte)) { 809 /* Get vm_page_t for mapped pte. */ 810 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 811 812 if (PTE_ISMODIFIED(pte)) 813 vm_page_dirty(m); 814 815 if (PTE_ISREFERENCED(pte)) 816 vm_page_flag_set(m, PG_REFERENCED); 817 818 pv_remove(pmap, va, m); 819 } 820 821 mtx_lock_spin(&tlbivax_mutex); 822 tlb_miss_lock(); 823 824 tlb0_flush_entry(va); 825 pte->flags = 0; 826 pte->rpn = 0; 827 828 tlb_miss_unlock(); 829 mtx_unlock_spin(&tlbivax_mutex); 830 831 pmap->pm_stats.resident_count--; 832 833 if (flags & PTBL_UNHOLD) { 834 //debugf("pte_remove: e (unhold)\n"); 835 return (ptbl_unhold(mmu, pmap, pdir_idx)); 836 } 837 838 //debugf("pte_remove: e\n"); 839 return (0); 840} 841 842/* 843 * Insert PTE for a given page and virtual address. 844 */ 845static void 846pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags) 847{ 848 unsigned int pdir_idx = PDIR_IDX(va); 849 unsigned int ptbl_idx = PTBL_IDX(va); 850 pte_t *ptbl, *pte; 851 852 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__, 853 pmap == kernel_pmap, pmap, va); 854 855 /* Get the page table pointer. */ 856 ptbl = pmap->pm_pdir[pdir_idx]; 857 858 if (ptbl == NULL) { 859 /* Allocate page table pages. */ 860 ptbl = ptbl_alloc(mmu, pmap, pdir_idx); 861 } else { 862 /* 863 * Check if there is valid mapping for requested 864 * va, if there is, remove it. 865 */ 866 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 867 if (PTE_ISVALID(pte)) { 868 pte_remove(mmu, pmap, va, PTBL_HOLD); 869 } else { 870 /* 871 * pte is not used, increment hold count 872 * for ptbl pages. 873 */ 874 if (pmap != kernel_pmap) 875 ptbl_hold(mmu, pmap, pdir_idx); 876 } 877 } 878 879 /* 880 * Insert pv_entry into pv_list for mapped page if part of managed 881 * memory. 882 */ 883 if ((m->flags & PG_FICTITIOUS) == 0) { 884 if ((m->flags & PG_UNMANAGED) == 0) { 885 flags |= PTE_MANAGED; 886 887 /* Create and insert pv entry. */ 888 pv_insert(pmap, va, m); 889 } 890 } 891 892 pmap->pm_stats.resident_count++; 893 894 mtx_lock_spin(&tlbivax_mutex); 895 tlb_miss_lock(); 896 897 tlb0_flush_entry(va); 898 if (pmap->pm_pdir[pdir_idx] == NULL) { 899 /* 900 * If we just allocated a new page table, hook it in 901 * the pdir. 902 */ 903 pmap->pm_pdir[pdir_idx] = ptbl; 904 } 905 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 906 pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK; 907 pte->flags |= (PTE_VALID | flags); 908 909 tlb_miss_unlock(); 910 mtx_unlock_spin(&tlbivax_mutex); 911} 912 913/* Return the pa for the given pmap/va. */ 914static vm_paddr_t 915pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 916{ 917 vm_paddr_t pa = 0; 918 pte_t *pte; 919 920 pte = pte_find(mmu, pmap, va); 921 if ((pte != NULL) && PTE_ISVALID(pte)) 922 pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 923 return (pa); 924} 925 926/* Get a pointer to a PTE in a page table. */ 927static pte_t * 928pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 929{ 930 unsigned int pdir_idx = PDIR_IDX(va); 931 unsigned int ptbl_idx = PTBL_IDX(va); 932 933 KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 934 935 if (pmap->pm_pdir[pdir_idx]) 936 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 937 938 return (NULL); 939} 940 941/**************************************************************************/ 942/* PMAP related */ 943/**************************************************************************/ 944 945/* 946 * This is called during booke_init, before the system is really initialized. 947 */ 948static void 949mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend) 950{ 951 vm_offset_t phys_kernelend; 952 struct mem_region *mp, *mp1; 953 int cnt, i, j; 954 u_int s, e, sz; 955 u_int phys_avail_count; 956 vm_size_t physsz, hwphyssz, kstack0_sz; 957 vm_offset_t kernel_pdir, kstack0, va; 958 vm_paddr_t kstack0_phys; 959 void *dpcpu; 960 pte_t *pte; 961 962 debugf("mmu_booke_bootstrap: entered\n"); 963 964 /* Initialize invalidation mutex */ 965 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 966 967 /* Read TLB0 size and associativity. */ 968 tlb0_get_tlbconf(); 969 970 /* Align kernel start and end address (kernel image). */ 971 kernstart = trunc_page(start); 972 data_start = round_page(kernelend); 973 kernsize = data_start - kernstart; 974 975 data_end = data_start; 976 977 /* Allocate space for the message buffer. */ 978 msgbufp = (struct msgbuf *)data_end; 979 data_end += msgbufsize; 980 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp, 981 data_end); 982 983 data_end = round_page(data_end); 984 985 /* Allocate the dynamic per-cpu area. */ 986 dpcpu = (void *)data_end; 987 data_end += DPCPU_SIZE; 988 dpcpu_init(dpcpu, 0); 989 990 /* Allocate space for ptbl_bufs. */ 991 ptbl_bufs = (struct ptbl_buf *)data_end; 992 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS; 993 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs, 994 data_end); 995 996 data_end = round_page(data_end); 997 998 /* Allocate PTE tables for kernel KVA. */ 999 kernel_pdir = data_end; 1000 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS + 1001 PDIR_SIZE - 1) / PDIR_SIZE; 1002 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 1003 debugf(" kernel ptbls: %d\n", kernel_ptbls); 1004 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end); 1005 1006 debugf(" data_end: 0x%08x\n", data_end); 1007 if (data_end - kernstart > 0x1000000) { 1008 data_end = (data_end + 0x3fffff) & ~0x3fffff; 1009 tlb1_mapin_region(kernstart + 0x1000000, 1010 kernload + 0x1000000, data_end - kernstart - 0x1000000); 1011 } else 1012 data_end = (data_end + 0xffffff) & ~0xffffff; 1013 1014 debugf(" updated data_end: 0x%08x\n", data_end); 1015 1016 kernsize += data_end - data_start; 1017 1018 /* 1019 * Clear the structures - note we can only do it safely after the 1020 * possible additional TLB1 translations are in place (above) so that 1021 * all range up to the currently calculated 'data_end' is covered. 1022 */ 1023 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 1024 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1025 1026 /*******************************************************/ 1027 /* Set the start and end of kva. */ 1028 /*******************************************************/ 1029 virtual_avail = round_page(data_end); 1030 virtual_end = VM_MAX_KERNEL_ADDRESS; 1031 1032 /* Allocate KVA space for page zero/copy operations. */ 1033 zero_page_va = virtual_avail; 1034 virtual_avail += PAGE_SIZE; 1035 zero_page_idle_va = virtual_avail; 1036 virtual_avail += PAGE_SIZE; 1037 copy_page_src_va = virtual_avail; 1038 virtual_avail += PAGE_SIZE; 1039 copy_page_dst_va = virtual_avail; 1040 virtual_avail += PAGE_SIZE; 1041 debugf("zero_page_va = 0x%08x\n", zero_page_va); 1042 debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va); 1043 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va); 1044 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va); 1045 1046 /* Initialize page zero/copy mutexes. */ 1047 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 1048 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 1049 1050 /* Allocate KVA space for ptbl bufs. */ 1051 ptbl_buf_pool_vabase = virtual_avail; 1052 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 1053 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n", 1054 ptbl_buf_pool_vabase, virtual_avail); 1055 1056 /* Calculate corresponding physical addresses for the kernel region. */ 1057 phys_kernelend = kernload + kernsize; 1058 debugf("kernel image and allocated data:\n"); 1059 debugf(" kernload = 0x%08x\n", kernload); 1060 debugf(" kernstart = 0x%08x\n", kernstart); 1061 debugf(" kernsize = 0x%08x\n", kernsize); 1062 1063 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz) 1064 panic("mmu_booke_bootstrap: phys_avail too small"); 1065 1066 /* 1067 * Remove kernel physical address range from avail regions list. Page 1068 * align all regions. Non-page aligned memory isn't very interesting 1069 * to us. Also, sort the entries for ascending addresses. 1070 */ 1071 1072 /* Retrieve phys/avail mem regions */ 1073 mem_regions(&physmem_regions, &physmem_regions_sz, 1074 &availmem_regions, &availmem_regions_sz); 1075 sz = 0; 1076 cnt = availmem_regions_sz; 1077 debugf("processing avail regions:\n"); 1078 for (mp = availmem_regions; mp->mr_size; mp++) { 1079 s = mp->mr_start; 1080 e = mp->mr_start + mp->mr_size; 1081 debugf(" %08x-%08x -> ", s, e); 1082 /* Check whether this region holds all of the kernel. */ 1083 if (s < kernload && e > phys_kernelend) { 1084 availmem_regions[cnt].mr_start = phys_kernelend; 1085 availmem_regions[cnt++].mr_size = e - phys_kernelend; 1086 e = kernload; 1087 } 1088 /* Look whether this regions starts within the kernel. */ 1089 if (s >= kernload && s < phys_kernelend) { 1090 if (e <= phys_kernelend) 1091 goto empty; 1092 s = phys_kernelend; 1093 } 1094 /* Now look whether this region ends within the kernel. */ 1095 if (e > kernload && e <= phys_kernelend) { 1096 if (s >= kernload) 1097 goto empty; 1098 e = kernload; 1099 } 1100 /* Now page align the start and size of the region. */ 1101 s = round_page(s); 1102 e = trunc_page(e); 1103 if (e < s) 1104 e = s; 1105 sz = e - s; 1106 debugf("%08x-%08x = %x\n", s, e, sz); 1107 1108 /* Check whether some memory is left here. */ 1109 if (sz == 0) { 1110 empty: 1111 memmove(mp, mp + 1, 1112 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1113 cnt--; 1114 mp--; 1115 continue; 1116 } 1117 1118 /* Do an insertion sort. */ 1119 for (mp1 = availmem_regions; mp1 < mp; mp1++) 1120 if (s < mp1->mr_start) 1121 break; 1122 if (mp1 < mp) { 1123 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1124 mp1->mr_start = s; 1125 mp1->mr_size = sz; 1126 } else { 1127 mp->mr_start = s; 1128 mp->mr_size = sz; 1129 } 1130 } 1131 availmem_regions_sz = cnt; 1132 1133 /*******************************************************/ 1134 /* Steal physical memory for kernel stack from the end */ 1135 /* of the first avail region */ 1136 /*******************************************************/ 1137 kstack0_sz = KSTACK_PAGES * PAGE_SIZE; 1138 kstack0_phys = availmem_regions[0].mr_start + 1139 availmem_regions[0].mr_size; 1140 kstack0_phys -= kstack0_sz; 1141 availmem_regions[0].mr_size -= kstack0_sz; 1142 1143 /*******************************************************/ 1144 /* Fill in phys_avail table, based on availmem_regions */ 1145 /*******************************************************/ 1146 phys_avail_count = 0; 1147 physsz = 0; 1148 hwphyssz = 0; 1149 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1150 1151 debugf("fill in phys_avail:\n"); 1152 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1153 1154 debugf(" region: 0x%08x - 0x%08x (0x%08x)\n", 1155 availmem_regions[i].mr_start, 1156 availmem_regions[i].mr_start + 1157 availmem_regions[i].mr_size, 1158 availmem_regions[i].mr_size); 1159 1160 if (hwphyssz != 0 && 1161 (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1162 debugf(" hw.physmem adjust\n"); 1163 if (physsz < hwphyssz) { 1164 phys_avail[j] = availmem_regions[i].mr_start; 1165 phys_avail[j + 1] = 1166 availmem_regions[i].mr_start + 1167 hwphyssz - physsz; 1168 physsz = hwphyssz; 1169 phys_avail_count++; 1170 } 1171 break; 1172 } 1173 1174 phys_avail[j] = availmem_regions[i].mr_start; 1175 phys_avail[j + 1] = availmem_regions[i].mr_start + 1176 availmem_regions[i].mr_size; 1177 phys_avail_count++; 1178 physsz += availmem_regions[i].mr_size; 1179 } 1180 physmem = btoc(physsz); 1181 1182 /* Calculate the last available physical address. */ 1183 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1184 ; 1185 Maxmem = powerpc_btop(phys_avail[i + 1]); 1186 1187 debugf("Maxmem = 0x%08lx\n", Maxmem); 1188 debugf("phys_avail_count = %d\n", phys_avail_count); 1189 debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem, 1190 physmem); 1191 1192 /*******************************************************/ 1193 /* Initialize (statically allocated) kernel pmap. */ 1194 /*******************************************************/ 1195 PMAP_LOCK_INIT(kernel_pmap); 1196 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1197 1198 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap); 1199 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls); 1200 debugf("kernel pdir range: 0x%08x - 0x%08x\n", 1201 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1); 1202 1203 /* Initialize kernel pdir */ 1204 for (i = 0; i < kernel_ptbls; i++) 1205 kernel_pmap->pm_pdir[kptbl_min + i] = 1206 (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1207 1208 for (i = 0; i < MAXCPU; i++) { 1209 kernel_pmap->pm_tid[i] = TID_KERNEL; 1210 1211 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 1212 tidbusy[i][0] = kernel_pmap; 1213 } 1214 1215 /* 1216 * Fill in PTEs covering kernel code and data. They are not required 1217 * for address translation, as this area is covered by static TLB1 1218 * entries, but for pte_vatopa() to work correctly with kernel area 1219 * addresses. 1220 */ 1221 for (va = KERNBASE; va < data_end; va += PAGE_SIZE) { 1222 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]); 1223 pte->rpn = kernload + (va - KERNBASE); 1224 pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | 1225 PTE_VALID; 1226 } 1227 /* Mark kernel_pmap active on all CPUs */ 1228 kernel_pmap->pm_active = ~0; 1229 1230 /*******************************************************/ 1231 /* Final setup */ 1232 /*******************************************************/ 1233 1234 /* Enter kstack0 into kernel map, provide guard page */ 1235 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1236 thread0.td_kstack = kstack0; 1237 thread0.td_kstack_pages = KSTACK_PAGES; 1238 1239 debugf("kstack_sz = 0x%08x\n", kstack0_sz); 1240 debugf("kstack0_phys at 0x%08x - 0x%08x\n", 1241 kstack0_phys, kstack0_phys + kstack0_sz); 1242 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz); 1243 1244 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 1245 for (i = 0; i < KSTACK_PAGES; i++) { 1246 mmu_booke_kenter(mmu, kstack0, kstack0_phys); 1247 kstack0 += PAGE_SIZE; 1248 kstack0_phys += PAGE_SIZE; 1249 } 1250 1251 debugf("virtual_avail = %08x\n", virtual_avail); 1252 debugf("virtual_end = %08x\n", virtual_end); 1253 1254 debugf("mmu_booke_bootstrap: exit\n"); 1255} 1256 1257void 1258pmap_bootstrap_ap(volatile uint32_t *trcp __unused) 1259{ 1260 int i; 1261 1262 /* 1263 * Finish TLB1 configuration: the BSP already set up its TLB1 and we 1264 * have the snapshot of its contents in the s/w tlb1[] table, so use 1265 * these values directly to (re)program AP's TLB1 hardware. 1266 */ 1267 for (i = 0; i < tlb1_idx; i ++) { 1268 /* Skip invalid entries */ 1269 if (!(tlb1[i].mas1 & MAS1_VALID)) 1270 continue; 1271 1272 tlb1_write_entry(i); 1273 } 1274 1275 set_mas4_defaults(); 1276} 1277 1278/* 1279 * Get the physical page address for the given pmap/virtual address. 1280 */ 1281static vm_paddr_t 1282mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1283{ 1284 vm_paddr_t pa; 1285 1286 PMAP_LOCK(pmap); 1287 pa = pte_vatopa(mmu, pmap, va); 1288 PMAP_UNLOCK(pmap); 1289 1290 return (pa); 1291} 1292 1293/* 1294 * Extract the physical page address associated with the given 1295 * kernel virtual address. 1296 */ 1297static vm_paddr_t 1298mmu_booke_kextract(mmu_t mmu, vm_offset_t va) 1299{ 1300 1301 return (pte_vatopa(mmu, kernel_pmap, va)); 1302} 1303 1304/* 1305 * Initialize the pmap module. 1306 * Called by vm_init, to initialize any structures that the pmap 1307 * system needs to map virtual memory. 1308 */ 1309static void 1310mmu_booke_init(mmu_t mmu) 1311{ 1312 int shpgperproc = PMAP_SHPGPERPROC; 1313 1314 /* 1315 * Initialize the address space (zone) for the pv entries. Set a 1316 * high water mark so that the system can recover from excessive 1317 * numbers of pv entries. 1318 */ 1319 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1320 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1321 1322 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1323 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 1324 1325 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1326 pv_entry_high_water = 9 * (pv_entry_max / 10); 1327 1328 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 1329 1330 /* Pre-fill pvzone with initial number of pv entries. */ 1331 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1332 1333 /* Initialize ptbl allocation. */ 1334 ptbl_init(); 1335} 1336 1337/* 1338 * Map a list of wired pages into kernel virtual address space. This is 1339 * intended for temporary mappings which do not need page modification or 1340 * references recorded. Existing mappings in the region are overwritten. 1341 */ 1342static void 1343mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1344{ 1345 vm_offset_t va; 1346 1347 va = sva; 1348 while (count-- > 0) { 1349 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1350 va += PAGE_SIZE; 1351 m++; 1352 } 1353} 1354 1355/* 1356 * Remove page mappings from kernel virtual address space. Intended for 1357 * temporary mappings entered by mmu_booke_qenter. 1358 */ 1359static void 1360mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 1361{ 1362 vm_offset_t va; 1363 1364 va = sva; 1365 while (count-- > 0) { 1366 mmu_booke_kremove(mmu, va); 1367 va += PAGE_SIZE; 1368 } 1369} 1370 1371/* 1372 * Map a wired page into kernel virtual address space. 1373 */ 1374static void 1375mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1376{ 1377 unsigned int pdir_idx = PDIR_IDX(va); 1378 unsigned int ptbl_idx = PTBL_IDX(va); 1379 uint32_t flags; 1380 pte_t *pte; 1381 1382 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1383 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 1384 1385 flags = 0; 1386 flags |= (PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID); 1387 flags |= PTE_M; 1388 1389 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1390 1391 mtx_lock_spin(&tlbivax_mutex); 1392 tlb_miss_lock(); 1393 1394 if (PTE_ISVALID(pte)) { 1395 1396 CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 1397 1398 /* Flush entry from TLB0 */ 1399 tlb0_flush_entry(va); 1400 } 1401 1402 pte->rpn = pa & ~PTE_PA_MASK; 1403 pte->flags = flags; 1404 1405 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1406 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1407 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1408 1409 /* Flush the real memory from the instruction cache. */ 1410 if ((flags & (PTE_I | PTE_G)) == 0) { 1411 __syncicache((void *)va, PAGE_SIZE); 1412 } 1413 1414 tlb_miss_unlock(); 1415 mtx_unlock_spin(&tlbivax_mutex); 1416} 1417 1418/* 1419 * Remove a page from kernel page table. 1420 */ 1421static void 1422mmu_booke_kremove(mmu_t mmu, vm_offset_t va) 1423{ 1424 unsigned int pdir_idx = PDIR_IDX(va); 1425 unsigned int ptbl_idx = PTBL_IDX(va); 1426 pte_t *pte; 1427 1428// CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va)); 1429 1430 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1431 (va <= VM_MAX_KERNEL_ADDRESS)), 1432 ("mmu_booke_kremove: invalid va")); 1433 1434 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1435 1436 if (!PTE_ISVALID(pte)) { 1437 1438 CTR1(KTR_PMAP, "%s: invalid pte", __func__); 1439 1440 return; 1441 } 1442 1443 mtx_lock_spin(&tlbivax_mutex); 1444 tlb_miss_lock(); 1445 1446 /* Invalidate entry in TLB0, update PTE. */ 1447 tlb0_flush_entry(va); 1448 pte->flags = 0; 1449 pte->rpn = 0; 1450 1451 tlb_miss_unlock(); 1452 mtx_unlock_spin(&tlbivax_mutex); 1453} 1454 1455/* 1456 * Initialize pmap associated with process 0. 1457 */ 1458static void 1459mmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 1460{ 1461 1462 mmu_booke_pinit(mmu, pmap); 1463 PCPU_SET(curpmap, pmap); 1464} 1465 1466/* 1467 * Initialize a preallocated and zeroed pmap structure, 1468 * such as one in a vmspace structure. 1469 */ 1470static void 1471mmu_booke_pinit(mmu_t mmu, pmap_t pmap) 1472{ 1473 int i; 1474 1475 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap, 1476 curthread->td_proc->p_pid, curthread->td_proc->p_comm); 1477 1478 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap")); 1479 1480 PMAP_LOCK_INIT(pmap); 1481 for (i = 0; i < MAXCPU; i++) 1482 pmap->pm_tid[i] = TID_NONE; 1483 pmap->pm_active = 0; 1484 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1485 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 1486 TAILQ_INIT(&pmap->pm_ptbl_list); 1487} 1488 1489/* 1490 * Release any resources held by the given physical map. 1491 * Called when a pmap initialized by mmu_booke_pinit is being released. 1492 * Should only be called if the map contains no valid mappings. 1493 */ 1494static void 1495mmu_booke_release(mmu_t mmu, pmap_t pmap) 1496{ 1497 1498 KASSERT(pmap->pm_stats.resident_count == 0, 1499 ("pmap_release: pmap resident count %ld != 0", 1500 pmap->pm_stats.resident_count)); 1501 1502 PMAP_LOCK_DESTROY(pmap); 1503} 1504 1505/* 1506 * Insert the given physical page at the specified virtual address in the 1507 * target physical map with the protection requested. If specified the page 1508 * will be wired down. 1509 */ 1510static void 1511mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1512 vm_prot_t prot, boolean_t wired) 1513{ 1514 1515 vm_page_lock_queues(); 1516 PMAP_LOCK(pmap); 1517 mmu_booke_enter_locked(mmu, pmap, va, m, prot, wired); 1518 vm_page_unlock_queues(); 1519 PMAP_UNLOCK(pmap); 1520} 1521 1522static void 1523mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1524 vm_prot_t prot, boolean_t wired) 1525{ 1526 pte_t *pte; 1527 vm_paddr_t pa; 1528 uint32_t flags; 1529 int su, sync; 1530 1531 pa = VM_PAGE_TO_PHYS(m); 1532 su = (pmap == kernel_pmap); 1533 sync = 0; 1534 1535 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1536 // "pa=0x%08x prot=0x%08x wired=%d)\n", 1537 // (u_int32_t)pmap, su, pmap->pm_tid, 1538 // (u_int32_t)m, va, pa, prot, wired); 1539 1540 if (su) { 1541 KASSERT(((va >= virtual_avail) && 1542 (va <= VM_MAX_KERNEL_ADDRESS)), 1543 ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1544 } else { 1545 KASSERT((va <= VM_MAXUSER_ADDRESS), 1546 ("mmu_booke_enter_locked: user pmap, non user va")); 1547 } 1548 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1549 (m->oflags & VPO_BUSY) != 0 || VM_OBJECT_LOCKED(m->object), 1550 ("mmu_booke_enter_locked: page %p is not busy", m)); 1551 1552 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1553 1554 /* 1555 * If there is an existing mapping, and the physical address has not 1556 * changed, must be protection or wiring change. 1557 */ 1558 if (((pte = pte_find(mmu, pmap, va)) != NULL) && 1559 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1560 1561 /* 1562 * Before actually updating pte->flags we calculate and 1563 * prepare its new value in a helper var. 1564 */ 1565 flags = pte->flags; 1566 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1567 1568 /* Wiring change, just update stats. */ 1569 if (wired) { 1570 if (!PTE_ISWIRED(pte)) { 1571 flags |= PTE_WIRED; 1572 pmap->pm_stats.wired_count++; 1573 } 1574 } else { 1575 if (PTE_ISWIRED(pte)) { 1576 flags &= ~PTE_WIRED; 1577 pmap->pm_stats.wired_count--; 1578 } 1579 } 1580 1581 if (prot & VM_PROT_WRITE) { 1582 /* Add write permissions. */ 1583 flags |= PTE_SW; 1584 if (!su) 1585 flags |= PTE_UW; 1586 1587 if ((flags & PTE_MANAGED) != 0) 1588 vm_page_flag_set(m, PG_WRITEABLE); 1589 } else { 1590 /* Handle modified pages, sense modify status. */ 1591 1592 /* 1593 * The PTE_MODIFIED flag could be set by underlying 1594 * TLB misses since we last read it (above), possibly 1595 * other CPUs could update it so we check in the PTE 1596 * directly rather than rely on that saved local flags 1597 * copy. 1598 */ 1599 if (PTE_ISMODIFIED(pte)) 1600 vm_page_dirty(m); 1601 } 1602 1603 if (prot & VM_PROT_EXECUTE) { 1604 flags |= PTE_SX; 1605 if (!su) 1606 flags |= PTE_UX; 1607 1608 /* 1609 * Check existing flags for execute permissions: if we 1610 * are turning execute permissions on, icache should 1611 * be flushed. 1612 */ 1613 if ((pte->flags & (PTE_UX | PTE_SX)) == 0) 1614 sync++; 1615 } 1616 1617 flags &= ~PTE_REFERENCED; 1618 1619 /* 1620 * The new flags value is all calculated -- only now actually 1621 * update the PTE. 1622 */ 1623 mtx_lock_spin(&tlbivax_mutex); 1624 tlb_miss_lock(); 1625 1626 tlb0_flush_entry(va); 1627 pte->flags = flags; 1628 1629 tlb_miss_unlock(); 1630 mtx_unlock_spin(&tlbivax_mutex); 1631 1632 } else { 1633 /* 1634 * If there is an existing mapping, but it's for a different 1635 * physical address, pte_enter() will delete the old mapping. 1636 */ 1637 //if ((pte != NULL) && PTE_ISVALID(pte)) 1638 // debugf("mmu_booke_enter_locked: replace\n"); 1639 //else 1640 // debugf("mmu_booke_enter_locked: new\n"); 1641 1642 /* Now set up the flags and install the new mapping. */ 1643 flags = (PTE_SR | PTE_VALID); 1644 flags |= PTE_M; 1645 1646 if (!su) 1647 flags |= PTE_UR; 1648 1649 if (prot & VM_PROT_WRITE) { 1650 flags |= PTE_SW; 1651 if (!su) 1652 flags |= PTE_UW; 1653 1654 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) 1655 vm_page_flag_set(m, PG_WRITEABLE); 1656 } 1657 1658 if (prot & VM_PROT_EXECUTE) { 1659 flags |= PTE_SX; 1660 if (!su) 1661 flags |= PTE_UX; 1662 } 1663 1664 /* If its wired update stats. */ 1665 if (wired) { 1666 pmap->pm_stats.wired_count++; 1667 flags |= PTE_WIRED; 1668 } 1669 1670 pte_enter(mmu, pmap, m, va, flags); 1671 1672 /* Flush the real memory from the instruction cache. */ 1673 if (prot & VM_PROT_EXECUTE) 1674 sync++; 1675 } 1676 1677 if (sync && (su || pmap == PCPU_GET(curpmap))) { 1678 __syncicache((void *)va, PAGE_SIZE); 1679 sync = 0; 1680 } 1681} 1682 1683/* 1684 * Maps a sequence of resident pages belonging to the same object. 1685 * The sequence begins with the given page m_start. This page is 1686 * mapped at the given virtual address start. Each subsequent page is 1687 * mapped at a virtual address that is offset from start by the same 1688 * amount as the page is offset from m_start within the object. The 1689 * last page in the sequence is the page with the largest offset from 1690 * m_start that can be mapped at a virtual address less than the given 1691 * virtual address end. Not every virtual page between start and end 1692 * is mapped; only those for which a resident page exists with the 1693 * corresponding offset from m_start are mapped. 1694 */ 1695static void 1696mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 1697 vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1698{ 1699 vm_page_t m; 1700 vm_pindex_t diff, psize; 1701 1702 psize = atop(end - start); 1703 m = m_start; 1704 vm_page_lock_queues(); 1705 PMAP_LOCK(pmap); 1706 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1707 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, 1708 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1709 m = TAILQ_NEXT(m, listq); 1710 } 1711 vm_page_unlock_queues(); 1712 PMAP_UNLOCK(pmap); 1713} 1714 1715static void 1716mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1717 vm_prot_t prot) 1718{ 1719 1720 vm_page_lock_queues(); 1721 PMAP_LOCK(pmap); 1722 mmu_booke_enter_locked(mmu, pmap, va, m, 1723 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1724 vm_page_unlock_queues(); 1725 PMAP_UNLOCK(pmap); 1726} 1727 1728/* 1729 * Remove the given range of addresses from the specified map. 1730 * 1731 * It is assumed that the start and end are properly rounded to the page size. 1732 */ 1733static void 1734mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1735{ 1736 pte_t *pte; 1737 uint8_t hold_flag; 1738 1739 int su = (pmap == kernel_pmap); 1740 1741 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1742 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1743 1744 if (su) { 1745 KASSERT(((va >= virtual_avail) && 1746 (va <= VM_MAX_KERNEL_ADDRESS)), 1747 ("mmu_booke_remove: kernel pmap, non kernel va")); 1748 } else { 1749 KASSERT((va <= VM_MAXUSER_ADDRESS), 1750 ("mmu_booke_remove: user pmap, non user va")); 1751 } 1752 1753 if (PMAP_REMOVE_DONE(pmap)) { 1754 //debugf("mmu_booke_remove: e (empty)\n"); 1755 return; 1756 } 1757 1758 hold_flag = PTBL_HOLD_FLAG(pmap); 1759 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1760 1761 vm_page_lock_queues(); 1762 PMAP_LOCK(pmap); 1763 for (; va < endva; va += PAGE_SIZE) { 1764 pte = pte_find(mmu, pmap, va); 1765 if ((pte != NULL) && PTE_ISVALID(pte)) 1766 pte_remove(mmu, pmap, va, hold_flag); 1767 } 1768 PMAP_UNLOCK(pmap); 1769 vm_page_unlock_queues(); 1770 1771 //debugf("mmu_booke_remove: e\n"); 1772} 1773 1774/* 1775 * Remove physical page from all pmaps in which it resides. 1776 */ 1777static void 1778mmu_booke_remove_all(mmu_t mmu, vm_page_t m) 1779{ 1780 pv_entry_t pv, pvn; 1781 uint8_t hold_flag; 1782 1783 vm_page_lock_queues(); 1784 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 1785 pvn = TAILQ_NEXT(pv, pv_link); 1786 1787 PMAP_LOCK(pv->pv_pmap); 1788 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1789 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 1790 PMAP_UNLOCK(pv->pv_pmap); 1791 } 1792 vm_page_flag_clear(m, PG_WRITEABLE); 1793 vm_page_unlock_queues(); 1794} 1795 1796/* 1797 * Map a range of physical addresses into kernel virtual address space. 1798 */ 1799static vm_offset_t 1800mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1801 vm_offset_t pa_end, int prot) 1802{ 1803 vm_offset_t sva = *virt; 1804 vm_offset_t va = sva; 1805 1806 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 1807 // sva, pa_start, pa_end); 1808 1809 while (pa_start < pa_end) { 1810 mmu_booke_kenter(mmu, va, pa_start); 1811 va += PAGE_SIZE; 1812 pa_start += PAGE_SIZE; 1813 } 1814 *virt = va; 1815 1816 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 1817 return (sva); 1818} 1819 1820/* 1821 * The pmap must be activated before it's address space can be accessed in any 1822 * way. 1823 */ 1824static void 1825mmu_booke_activate(mmu_t mmu, struct thread *td) 1826{ 1827 pmap_t pmap; 1828 1829 pmap = &td->td_proc->p_vmspace->vm_pmap; 1830 1831 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)", 1832 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1833 1834 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1835 1836 mtx_lock_spin(&sched_lock); 1837 1838 atomic_set_int(&pmap->pm_active, PCPU_GET(cpumask)); 1839 PCPU_SET(curpmap, pmap); 1840 1841 if (pmap->pm_tid[PCPU_GET(cpuid)] == TID_NONE) 1842 tid_alloc(pmap); 1843 1844 /* Load PID0 register with pmap tid value. */ 1845 mtspr(SPR_PID0, pmap->pm_tid[PCPU_GET(cpuid)]); 1846 __asm __volatile("isync"); 1847 1848 mtx_unlock_spin(&sched_lock); 1849 1850 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 1851 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 1852} 1853 1854/* 1855 * Deactivate the specified process's address space. 1856 */ 1857static void 1858mmu_booke_deactivate(mmu_t mmu, struct thread *td) 1859{ 1860 pmap_t pmap; 1861 1862 pmap = &td->td_proc->p_vmspace->vm_pmap; 1863 1864 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x", 1865 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1866 1867 atomic_clear_int(&pmap->pm_active, PCPU_GET(cpumask)); 1868 PCPU_SET(curpmap, NULL); 1869} 1870 1871/* 1872 * Copy the range specified by src_addr/len 1873 * from the source map to the range dst_addr/len 1874 * in the destination map. 1875 * 1876 * This routine is only advisory and need not do anything. 1877 */ 1878static void 1879mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap, 1880 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr) 1881{ 1882 1883} 1884 1885/* 1886 * Set the physical protection on the specified range of this map as requested. 1887 */ 1888static void 1889mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1890 vm_prot_t prot) 1891{ 1892 vm_offset_t va; 1893 vm_page_t m; 1894 pte_t *pte; 1895 1896 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1897 mmu_booke_remove(mmu, pmap, sva, eva); 1898 return; 1899 } 1900 1901 if (prot & VM_PROT_WRITE) 1902 return; 1903 1904 vm_page_lock_queues(); 1905 PMAP_LOCK(pmap); 1906 for (va = sva; va < eva; va += PAGE_SIZE) { 1907 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 1908 if (PTE_ISVALID(pte)) { 1909 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1910 1911 mtx_lock_spin(&tlbivax_mutex); 1912 tlb_miss_lock(); 1913 1914 /* Handle modified pages. */ 1915 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte)) 1916 vm_page_dirty(m); 1917 1918 tlb0_flush_entry(va); 1919 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 1920 1921 tlb_miss_unlock(); 1922 mtx_unlock_spin(&tlbivax_mutex); 1923 } 1924 } 1925 } 1926 PMAP_UNLOCK(pmap); 1927 vm_page_unlock_queues(); 1928} 1929 1930/* 1931 * Clear the write and modified bits in each of the given page's mappings. 1932 */ 1933static void 1934mmu_booke_remove_write(mmu_t mmu, vm_page_t m) 1935{ 1936 pv_entry_t pv; 1937 pte_t *pte; 1938 1939 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1940 ("mmu_booke_remove_write: page %p is not managed", m)); 1941 1942 /* 1943 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 1944 * another thread while the object is locked. Thus, if PG_WRITEABLE 1945 * is clear, no page table entries need updating. 1946 */ 1947 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1948 if ((m->oflags & VPO_BUSY) == 0 && 1949 (m->flags & PG_WRITEABLE) == 0) 1950 return; 1951 vm_page_lock_queues(); 1952 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1953 PMAP_LOCK(pv->pv_pmap); 1954 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 1955 if (PTE_ISVALID(pte)) { 1956 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1957 1958 mtx_lock_spin(&tlbivax_mutex); 1959 tlb_miss_lock(); 1960 1961 /* Handle modified pages. */ 1962 if (PTE_ISMODIFIED(pte)) 1963 vm_page_dirty(m); 1964 1965 /* Flush mapping from TLB0. */ 1966 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 1967 1968 tlb_miss_unlock(); 1969 mtx_unlock_spin(&tlbivax_mutex); 1970 } 1971 } 1972 PMAP_UNLOCK(pv->pv_pmap); 1973 } 1974 vm_page_flag_clear(m, PG_WRITEABLE); 1975 vm_page_unlock_queues(); 1976} 1977 1978static void 1979mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 1980{ 1981 pte_t *pte; 1982 pmap_t pmap; 1983 vm_page_t m; 1984 vm_offset_t addr; 1985 vm_paddr_t pa; 1986 int active, valid; 1987 1988 va = trunc_page(va); 1989 sz = round_page(sz); 1990 1991 vm_page_lock_queues(); 1992 pmap = PCPU_GET(curpmap); 1993 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0; 1994 while (sz > 0) { 1995 PMAP_LOCK(pm); 1996 pte = pte_find(mmu, pm, va); 1997 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0; 1998 if (valid) 1999 pa = PTE_PA(pte); 2000 PMAP_UNLOCK(pm); 2001 if (valid) { 2002 if (!active) { 2003 /* Create a mapping in the active pmap. */ 2004 addr = 0; 2005 m = PHYS_TO_VM_PAGE(pa); 2006 PMAP_LOCK(pmap); 2007 pte_enter(mmu, pmap, m, addr, 2008 PTE_SR | PTE_VALID | PTE_UR); 2009 __syncicache((void *)addr, PAGE_SIZE); 2010 pte_remove(mmu, pmap, addr, PTBL_UNHOLD); 2011 PMAP_UNLOCK(pmap); 2012 } else 2013 __syncicache((void *)va, PAGE_SIZE); 2014 } 2015 va += PAGE_SIZE; 2016 sz -= PAGE_SIZE; 2017 } 2018 vm_page_unlock_queues(); 2019} 2020 2021/* 2022 * Atomically extract and hold the physical page with the given 2023 * pmap and virtual address pair if that mapping permits the given 2024 * protection. 2025 */ 2026static vm_page_t 2027mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 2028 vm_prot_t prot) 2029{ 2030 pte_t *pte; 2031 vm_page_t m; 2032 uint32_t pte_wbit; 2033 vm_paddr_t pa; 2034 2035 m = NULL; 2036 pa = 0; 2037 PMAP_LOCK(pmap); 2038retry: 2039 pte = pte_find(mmu, pmap, va); 2040 if ((pte != NULL) && PTE_ISVALID(pte)) { 2041 if (pmap == kernel_pmap) 2042 pte_wbit = PTE_SW; 2043 else 2044 pte_wbit = PTE_UW; 2045 2046 if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 2047 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa)) 2048 goto retry; 2049 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2050 vm_page_hold(m); 2051 } 2052 } 2053 2054 PA_UNLOCK_COND(pa); 2055 PMAP_UNLOCK(pmap); 2056 return (m); 2057} 2058 2059/* 2060 * Initialize a vm_page's machine-dependent fields. 2061 */ 2062static void 2063mmu_booke_page_init(mmu_t mmu, vm_page_t m) 2064{ 2065 2066 TAILQ_INIT(&m->md.pv_list); 2067} 2068 2069/* 2070 * mmu_booke_zero_page_area zeros the specified hardware page by 2071 * mapping it into virtual memory and using bzero to clear 2072 * its contents. 2073 * 2074 * off and size must reside within a single page. 2075 */ 2076static void 2077mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 2078{ 2079 vm_offset_t va; 2080 2081 /* XXX KASSERT off and size are within a single page? */ 2082 2083 mtx_lock(&zero_page_mutex); 2084 va = zero_page_va; 2085 2086 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2087 bzero((caddr_t)va + off, size); 2088 mmu_booke_kremove(mmu, va); 2089 2090 mtx_unlock(&zero_page_mutex); 2091} 2092 2093/* 2094 * mmu_booke_zero_page zeros the specified hardware page. 2095 */ 2096static void 2097mmu_booke_zero_page(mmu_t mmu, vm_page_t m) 2098{ 2099 2100 mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE); 2101} 2102 2103/* 2104 * mmu_booke_copy_page copies the specified (machine independent) page by 2105 * mapping the page into virtual memory and using memcopy to copy the page, 2106 * one machine dependent page at a time. 2107 */ 2108static void 2109mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 2110{ 2111 vm_offset_t sva, dva; 2112 2113 sva = copy_page_src_va; 2114 dva = copy_page_dst_va; 2115 2116 mtx_lock(©_page_mutex); 2117 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 2118 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 2119 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 2120 mmu_booke_kremove(mmu, dva); 2121 mmu_booke_kremove(mmu, sva); 2122 mtx_unlock(©_page_mutex); 2123} 2124 2125/* 2126 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it 2127 * into virtual memory and using bzero to clear its contents. This is intended 2128 * to be called from the vm_pagezero process only and outside of Giant. No 2129 * lock is required. 2130 */ 2131static void 2132mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m) 2133{ 2134 vm_offset_t va; 2135 2136 va = zero_page_idle_va; 2137 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2138 bzero((caddr_t)va, PAGE_SIZE); 2139 mmu_booke_kremove(mmu, va); 2140} 2141 2142/* 2143 * Return whether or not the specified physical page was modified 2144 * in any of physical maps. 2145 */ 2146static boolean_t 2147mmu_booke_is_modified(mmu_t mmu, vm_page_t m) 2148{ 2149 pte_t *pte; 2150 pv_entry_t pv; 2151 boolean_t rv; 2152 2153 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2154 ("mmu_booke_is_modified: page %p is not managed", m)); 2155 rv = FALSE; 2156 2157 /* 2158 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 2159 * concurrently set while the object is locked. Thus, if PG_WRITEABLE 2160 * is clear, no PTEs can be modified. 2161 */ 2162 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2163 if ((m->oflags & VPO_BUSY) == 0 && 2164 (m->flags & PG_WRITEABLE) == 0) 2165 return (rv); 2166 vm_page_lock_queues(); 2167 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2168 PMAP_LOCK(pv->pv_pmap); 2169 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2170 PTE_ISVALID(pte)) { 2171 if (PTE_ISMODIFIED(pte)) 2172 rv = TRUE; 2173 } 2174 PMAP_UNLOCK(pv->pv_pmap); 2175 if (rv) 2176 break; 2177 } 2178 vm_page_unlock_queues(); 2179 return (rv); 2180} 2181 2182/* 2183 * Return whether or not the specified virtual address is eligible 2184 * for prefault. 2185 */ 2186static boolean_t 2187mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2188{ 2189 2190 return (FALSE); 2191} 2192 2193/* 2194 * Return whether or not the specified physical page was referenced 2195 * in any physical maps. 2196 */ 2197static boolean_t 2198mmu_booke_is_referenced(mmu_t mmu, vm_page_t m) 2199{ 2200 pte_t *pte; 2201 pv_entry_t pv; 2202 boolean_t rv; 2203 2204 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2205 ("mmu_booke_is_referenced: page %p is not managed", m)); 2206 rv = FALSE; 2207 vm_page_lock_queues(); 2208 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2209 PMAP_LOCK(pv->pv_pmap); 2210 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2211 PTE_ISVALID(pte)) { 2212 if (PTE_ISREFERENCED(pte)) 2213 rv = TRUE; 2214 } 2215 PMAP_UNLOCK(pv->pv_pmap); 2216 if (rv) 2217 break; 2218 } 2219 vm_page_unlock_queues(); 2220 return (rv); 2221} 2222 2223/* 2224 * Clear the modify bits on the specified physical page. 2225 */ 2226static void 2227mmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 2228{ 2229 pte_t *pte; 2230 pv_entry_t pv; 2231 2232 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2233 ("mmu_booke_clear_modify: page %p is not managed", m)); 2234 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2235 KASSERT((m->oflags & VPO_BUSY) == 0, 2236 ("mmu_booke_clear_modify: page %p is busy", m)); 2237 2238 /* 2239 * If the page is not PG_WRITEABLE, then no PTEs can be modified. 2240 * If the object containing the page is locked and the page is not 2241 * VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 2242 */ 2243 if ((m->flags & PG_WRITEABLE) == 0) 2244 return; 2245 vm_page_lock_queues(); 2246 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2247 PMAP_LOCK(pv->pv_pmap); 2248 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2249 PTE_ISVALID(pte)) { 2250 mtx_lock_spin(&tlbivax_mutex); 2251 tlb_miss_lock(); 2252 2253 if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 2254 tlb0_flush_entry(pv->pv_va); 2255 pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 2256 PTE_REFERENCED); 2257 } 2258 2259 tlb_miss_unlock(); 2260 mtx_unlock_spin(&tlbivax_mutex); 2261 } 2262 PMAP_UNLOCK(pv->pv_pmap); 2263 } 2264 vm_page_unlock_queues(); 2265} 2266 2267/* 2268 * Return a count of reference bits for a page, clearing those bits. 2269 * It is not necessary for every reference bit to be cleared, but it 2270 * is necessary that 0 only be returned when there are truly no 2271 * reference bits set. 2272 * 2273 * XXX: The exact number of bits to check and clear is a matter that 2274 * should be tested and standardized at some point in the future for 2275 * optimal aging of shared pages. 2276 */ 2277static int 2278mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 2279{ 2280 pte_t *pte; 2281 pv_entry_t pv; 2282 int count; 2283 2284 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2285 ("mmu_booke_ts_referenced: page %p is not managed", m)); 2286 count = 0; 2287 vm_page_lock_queues(); 2288 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2289 PMAP_LOCK(pv->pv_pmap); 2290 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2291 PTE_ISVALID(pte)) { 2292 if (PTE_ISREFERENCED(pte)) { 2293 mtx_lock_spin(&tlbivax_mutex); 2294 tlb_miss_lock(); 2295 2296 tlb0_flush_entry(pv->pv_va); 2297 pte->flags &= ~PTE_REFERENCED; 2298 2299 tlb_miss_unlock(); 2300 mtx_unlock_spin(&tlbivax_mutex); 2301 2302 if (++count > 4) { 2303 PMAP_UNLOCK(pv->pv_pmap); 2304 break; 2305 } 2306 } 2307 } 2308 PMAP_UNLOCK(pv->pv_pmap); 2309 } 2310 vm_page_unlock_queues(); 2311 return (count); 2312} 2313 2314/* 2315 * Clear the reference bit on the specified physical page. 2316 */ 2317static void 2318mmu_booke_clear_reference(mmu_t mmu, vm_page_t m) 2319{ 2320 pte_t *pte; 2321 pv_entry_t pv; 2322 2323 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2324 ("mmu_booke_clear_reference: page %p is not managed", m)); 2325 vm_page_lock_queues(); 2326 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2327 PMAP_LOCK(pv->pv_pmap); 2328 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2329 PTE_ISVALID(pte)) { 2330 if (PTE_ISREFERENCED(pte)) { 2331 mtx_lock_spin(&tlbivax_mutex); 2332 tlb_miss_lock(); 2333 2334 tlb0_flush_entry(pv->pv_va); 2335 pte->flags &= ~PTE_REFERENCED; 2336 2337 tlb_miss_unlock(); 2338 mtx_unlock_spin(&tlbivax_mutex); 2339 } 2340 } 2341 PMAP_UNLOCK(pv->pv_pmap); 2342 } 2343 vm_page_unlock_queues(); 2344} 2345 2346/* 2347 * Change wiring attribute for a map/virtual-address pair. 2348 */ 2349static void 2350mmu_booke_change_wiring(mmu_t mmu, pmap_t pmap, vm_offset_t va, boolean_t wired) 2351{ 2352 pte_t *pte; 2353 2354 PMAP_LOCK(pmap); 2355 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2356 if (wired) { 2357 if (!PTE_ISWIRED(pte)) { 2358 pte->flags |= PTE_WIRED; 2359 pmap->pm_stats.wired_count++; 2360 } 2361 } else { 2362 if (PTE_ISWIRED(pte)) { 2363 pte->flags &= ~PTE_WIRED; 2364 pmap->pm_stats.wired_count--; 2365 } 2366 } 2367 } 2368 PMAP_UNLOCK(pmap); 2369} 2370 2371/* 2372 * Return true if the pmap's pv is one of the first 16 pvs linked to from this 2373 * page. This count may be changed upwards or downwards in the future; it is 2374 * only necessary that true be returned for a small subset of pmaps for proper 2375 * page aging. 2376 */ 2377static boolean_t 2378mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2379{ 2380 pv_entry_t pv; 2381 int loops; 2382 boolean_t rv; 2383 2384 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2385 ("mmu_booke_page_exists_quick: page %p is not managed", m)); 2386 loops = 0; 2387 rv = FALSE; 2388 vm_page_lock_queues(); 2389 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2390 if (pv->pv_pmap == pmap) { 2391 rv = TRUE; 2392 break; 2393 } 2394 if (++loops >= 16) 2395 break; 2396 } 2397 vm_page_unlock_queues(); 2398 return (rv); 2399} 2400 2401/* 2402 * Return the number of managed mappings to the given physical page that are 2403 * wired. 2404 */ 2405static int 2406mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 2407{ 2408 pv_entry_t pv; 2409 pte_t *pte; 2410 int count = 0; 2411 2412 if ((m->flags & PG_FICTITIOUS) != 0) 2413 return (count); 2414 vm_page_lock_queues(); 2415 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2416 PMAP_LOCK(pv->pv_pmap); 2417 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 2418 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2419 count++; 2420 PMAP_UNLOCK(pv->pv_pmap); 2421 } 2422 vm_page_unlock_queues(); 2423 return (count); 2424} 2425 2426static int 2427mmu_booke_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2428{ 2429 int i; 2430 vm_offset_t va; 2431 2432 /* 2433 * This currently does not work for entries that 2434 * overlap TLB1 entries. 2435 */ 2436 for (i = 0; i < tlb1_idx; i ++) { 2437 if (tlb1_iomapped(i, pa, size, &va) == 0) 2438 return (0); 2439 } 2440 2441 return (EFAULT); 2442} 2443 2444vm_offset_t 2445mmu_booke_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2446 vm_size_t *sz) 2447{ 2448 vm_paddr_t pa, ppa; 2449 vm_offset_t va; 2450 vm_size_t gran; 2451 2452 /* Raw physical memory dumps don't have a virtual address. */ 2453 if (md->md_vaddr == ~0UL) { 2454 /* We always map a 256MB page at 256M. */ 2455 gran = 256 * 1024 * 1024; 2456 pa = md->md_paddr + ofs; 2457 ppa = pa & ~(gran - 1); 2458 ofs = pa - ppa; 2459 va = gran; 2460 tlb1_set_entry(va, ppa, gran, _TLB_ENTRY_IO); 2461 if (*sz > (gran - ofs)) 2462 *sz = gran - ofs; 2463 return (va + ofs); 2464 } 2465 2466 /* Minidumps are based on virtual memory addresses. */ 2467 va = md->md_vaddr + ofs; 2468 if (va >= kernstart + kernsize) { 2469 gran = PAGE_SIZE - (va & PAGE_MASK); 2470 if (*sz > gran) 2471 *sz = gran; 2472 } 2473 return (va); 2474} 2475 2476void 2477mmu_booke_dumpsys_unmap(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2478 vm_offset_t va) 2479{ 2480 2481 /* Raw physical memory dumps don't have a virtual address. */ 2482 if (md->md_vaddr == ~0UL) { 2483 tlb1_idx--; 2484 tlb1[tlb1_idx].mas1 = 0; 2485 tlb1[tlb1_idx].mas2 = 0; 2486 tlb1[tlb1_idx].mas3 = 0; 2487 tlb1_write_entry(tlb1_idx); 2488 return; 2489 } 2490 2491 /* Minidumps are based on virtual memory addresses. */ 2492 /* Nothing to do... */ 2493} 2494 2495struct pmap_md * 2496mmu_booke_scan_md(mmu_t mmu, struct pmap_md *prev) 2497{ 2498 static struct pmap_md md; 2499 pte_t *pte; 2500 vm_offset_t va; 2501 2502 if (dumpsys_minidump) { 2503 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */ 2504 if (prev == NULL) { 2505 /* 1st: kernel .data and .bss. */ 2506 md.md_index = 1; 2507 md.md_vaddr = trunc_page((uintptr_t)_etext); 2508 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr; 2509 return (&md); 2510 } 2511 switch (prev->md_index) { 2512 case 1: 2513 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2514 md.md_index = 2; 2515 md.md_vaddr = data_start; 2516 md.md_size = data_end - data_start; 2517 break; 2518 case 2: 2519 /* 3rd: kernel VM. */ 2520 va = prev->md_vaddr + prev->md_size; 2521 /* Find start of next chunk (from va). */ 2522 while (va < virtual_end) { 2523 /* Don't dump the buffer cache. */ 2524 if (va >= kmi.buffer_sva && 2525 va < kmi.buffer_eva) { 2526 va = kmi.buffer_eva; 2527 continue; 2528 } 2529 pte = pte_find(mmu, kernel_pmap, va); 2530 if (pte != NULL && PTE_ISVALID(pte)) 2531 break; 2532 va += PAGE_SIZE; 2533 } 2534 if (va < virtual_end) { 2535 md.md_vaddr = va; 2536 va += PAGE_SIZE; 2537 /* Find last page in chunk. */ 2538 while (va < virtual_end) { 2539 /* Don't run into the buffer cache. */ 2540 if (va == kmi.buffer_sva) 2541 break; 2542 pte = pte_find(mmu, kernel_pmap, va); 2543 if (pte == NULL || !PTE_ISVALID(pte)) 2544 break; 2545 va += PAGE_SIZE; 2546 } 2547 md.md_size = va - md.md_vaddr; 2548 break; 2549 } 2550 md.md_index = 3; 2551 /* FALLTHROUGH */ 2552 default: 2553 return (NULL); 2554 } 2555 } else { /* minidumps */ 2556 mem_regions(&physmem_regions, &physmem_regions_sz, 2557 &availmem_regions, &availmem_regions_sz); 2558 2559 if (prev == NULL) { 2560 /* first physical chunk. */ 2561 md.md_paddr = physmem_regions[0].mr_start; 2562 md.md_size = physmem_regions[0].mr_size; 2563 md.md_vaddr = ~0UL; 2564 md.md_index = 1; 2565 } else if (md.md_index < physmem_regions_sz) { 2566 md.md_paddr = physmem_regions[md.md_index].mr_start; 2567 md.md_size = physmem_regions[md.md_index].mr_size; 2568 md.md_vaddr = ~0UL; 2569 md.md_index++; 2570 } else { 2571 /* There's no next physical chunk. */ 2572 return (NULL); 2573 } 2574 } 2575 2576 return (&md); 2577} 2578 2579/* 2580 * Map a set of physical memory pages into the kernel virtual address space. 2581 * Return a pointer to where it is mapped. This routine is intended to be used 2582 * for mapping device memory, NOT real memory. 2583 */ 2584static void * 2585mmu_booke_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2586{ 2587 void *res; 2588 uintptr_t va; 2589 vm_size_t sz; 2590 2591 va = (pa >= 0x80000000) ? pa : (0xe2000000 + pa); 2592 res = (void *)va; 2593 2594 do { 2595 sz = 1 << (ilog2(size) & ~1); 2596 if (bootverbose) 2597 printf("Wiring VA=%x to PA=%x (size=%x), " 2598 "using TLB1[%d]\n", va, pa, sz, tlb1_idx); 2599 tlb1_set_entry(va, pa, sz, _TLB_ENTRY_IO); 2600 size -= sz; 2601 pa += sz; 2602 va += sz; 2603 } while (size > 0); 2604 2605 return (res); 2606} 2607 2608/* 2609 * 'Unmap' a range mapped by mmu_booke_mapdev(). 2610 */ 2611static void 2612mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2613{ 2614 vm_offset_t base, offset; 2615 2616 /* 2617 * Unmap only if this is inside kernel virtual space. 2618 */ 2619 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2620 base = trunc_page(va); 2621 offset = va & PAGE_MASK; 2622 size = roundup(offset + size, PAGE_SIZE); 2623 kmem_free(kernel_map, base, size); 2624 } 2625} 2626 2627/* 2628 * mmu_booke_object_init_pt preloads the ptes for a given object into the 2629 * specified pmap. This eliminates the blast of soft faults on process startup 2630 * and immediately after an mmap. 2631 */ 2632static void 2633mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2634 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2635{ 2636 2637 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 2638 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2639 ("mmu_booke_object_init_pt: non-device object")); 2640} 2641 2642/* 2643 * Perform the pmap work for mincore. 2644 */ 2645static int 2646mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2647 vm_paddr_t *locked_pa) 2648{ 2649 2650 TODO; 2651 return (0); 2652} 2653 2654/**************************************************************************/ 2655/* TID handling */ 2656/**************************************************************************/ 2657 2658/* 2659 * Allocate a TID. If necessary, steal one from someone else. 2660 * The new TID is flushed from the TLB before returning. 2661 */ 2662static tlbtid_t 2663tid_alloc(pmap_t pmap) 2664{ 2665 tlbtid_t tid; 2666 int thiscpu; 2667 2668 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2669 2670 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 2671 2672 thiscpu = PCPU_GET(cpuid); 2673 2674 tid = PCPU_GET(tid_next); 2675 if (tid > TID_MAX) 2676 tid = TID_MIN; 2677 PCPU_SET(tid_next, tid + 1); 2678 2679 /* If we are stealing TID then clear the relevant pmap's field */ 2680 if (tidbusy[thiscpu][tid] != NULL) { 2681 2682 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 2683 2684 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 2685 2686 /* Flush all entries from TLB0 matching this TID. */ 2687 tid_flush(tid); 2688 } 2689 2690 tidbusy[thiscpu][tid] = pmap; 2691 pmap->pm_tid[thiscpu] = tid; 2692 __asm __volatile("msync; isync"); 2693 2694 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 2695 PCPU_GET(tid_next)); 2696 2697 return (tid); 2698} 2699 2700/**************************************************************************/ 2701/* TLB0 handling */ 2702/**************************************************************************/ 2703 2704static void 2705tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 2706 uint32_t mas7) 2707{ 2708 int as; 2709 char desc[3]; 2710 tlbtid_t tid; 2711 vm_size_t size; 2712 unsigned int tsize; 2713 2714 desc[2] = '\0'; 2715 if (mas1 & MAS1_VALID) 2716 desc[0] = 'V'; 2717 else 2718 desc[0] = ' '; 2719 2720 if (mas1 & MAS1_IPROT) 2721 desc[1] = 'P'; 2722 else 2723 desc[1] = ' '; 2724 2725 as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 2726 tid = MAS1_GETTID(mas1); 2727 2728 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 2729 size = 0; 2730 if (tsize) 2731 size = tsize2size(tsize); 2732 2733 debugf("%3d: (%s) [AS=%d] " 2734 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 2735 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n", 2736 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 2737} 2738 2739/* Convert TLB0 va and way number to tlb0[] table index. */ 2740static inline unsigned int 2741tlb0_tableidx(vm_offset_t va, unsigned int way) 2742{ 2743 unsigned int idx; 2744 2745 idx = (way * TLB0_ENTRIES_PER_WAY); 2746 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 2747 return (idx); 2748} 2749 2750/* 2751 * Invalidate TLB0 entry. 2752 */ 2753static inline void 2754tlb0_flush_entry(vm_offset_t va) 2755{ 2756 2757 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 2758 2759 mtx_assert(&tlbivax_mutex, MA_OWNED); 2760 2761 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 2762 __asm __volatile("isync; msync"); 2763 __asm __volatile("tlbsync; msync"); 2764 2765 CTR1(KTR_PMAP, "%s: e", __func__); 2766} 2767 2768/* Print out contents of the MAS registers for each TLB0 entry */ 2769void 2770tlb0_print_tlbentries(void) 2771{ 2772 uint32_t mas0, mas1, mas2, mas3, mas7; 2773 int entryidx, way, idx; 2774 2775 debugf("TLB0 entries:\n"); 2776 for (way = 0; way < TLB0_WAYS; way ++) 2777 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 2778 2779 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 2780 mtspr(SPR_MAS0, mas0); 2781 __asm __volatile("isync"); 2782 2783 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 2784 mtspr(SPR_MAS2, mas2); 2785 2786 __asm __volatile("isync; tlbre"); 2787 2788 mas1 = mfspr(SPR_MAS1); 2789 mas2 = mfspr(SPR_MAS2); 2790 mas3 = mfspr(SPR_MAS3); 2791 mas7 = mfspr(SPR_MAS7); 2792 2793 idx = tlb0_tableidx(mas2, way); 2794 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 2795 } 2796} 2797 2798/**************************************************************************/ 2799/* TLB1 handling */ 2800/**************************************************************************/ 2801 2802/* 2803 * TLB1 mapping notes: 2804 * 2805 * TLB1[0] CCSRBAR 2806 * TLB1[1] Kernel text and data. 2807 * TLB1[2-15] Additional kernel text and data mappings (if required), PCI 2808 * windows, other devices mappings. 2809 */ 2810 2811/* 2812 * Write given entry to TLB1 hardware. 2813 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 2814 */ 2815static void 2816tlb1_write_entry(unsigned int idx) 2817{ 2818 uint32_t mas0, mas7; 2819 2820 //debugf("tlb1_write_entry: s\n"); 2821 2822 /* Clear high order RPN bits */ 2823 mas7 = 0; 2824 2825 /* Select entry */ 2826 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 2827 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0); 2828 2829 mtspr(SPR_MAS0, mas0); 2830 __asm __volatile("isync"); 2831 mtspr(SPR_MAS1, tlb1[idx].mas1); 2832 __asm __volatile("isync"); 2833 mtspr(SPR_MAS2, tlb1[idx].mas2); 2834 __asm __volatile("isync"); 2835 mtspr(SPR_MAS3, tlb1[idx].mas3); 2836 __asm __volatile("isync"); 2837 mtspr(SPR_MAS7, mas7); 2838 __asm __volatile("isync; tlbwe; isync; msync"); 2839 2840 //debugf("tlb1_write_entry: e\n"); 2841} 2842 2843/* 2844 * Return the largest uint value log such that 2^log <= num. 2845 */ 2846static unsigned int 2847ilog2(unsigned int num) 2848{ 2849 int lz; 2850 2851 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 2852 return (31 - lz); 2853} 2854 2855/* 2856 * Convert TLB TSIZE value to mapped region size. 2857 */ 2858static vm_size_t 2859tsize2size(unsigned int tsize) 2860{ 2861 2862 /* 2863 * size = 4^tsize KB 2864 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 2865 */ 2866 2867 return ((1 << (2 * tsize)) * 1024); 2868} 2869 2870/* 2871 * Convert region size (must be power of 4) to TLB TSIZE value. 2872 */ 2873static unsigned int 2874size2tsize(vm_size_t size) 2875{ 2876 2877 return (ilog2(size) / 2 - 5); 2878} 2879 2880/* 2881 * Register permanent kernel mapping in TLB1. 2882 * 2883 * Entries are created starting from index 0 (current free entry is 2884 * kept in tlb1_idx) and are not supposed to be invalidated. 2885 */ 2886static int 2887tlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size, 2888 uint32_t flags) 2889{ 2890 uint32_t ts, tid; 2891 int tsize; 2892 2893 if (tlb1_idx >= TLB1_ENTRIES) { 2894 printf("tlb1_set_entry: TLB1 full!\n"); 2895 return (-1); 2896 } 2897 2898 /* Convert size to TSIZE */ 2899 tsize = size2tsize(size); 2900 2901 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 2902 /* XXX TS is hard coded to 0 for now as we only use single address space */ 2903 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 2904 2905 /* XXX LOCK tlb1[] */ 2906 2907 tlb1[tlb1_idx].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 2908 tlb1[tlb1_idx].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 2909 tlb1[tlb1_idx].mas2 = (va & MAS2_EPN_MASK) | flags; 2910 2911 /* Set supervisor RWX permission bits */ 2912 tlb1[tlb1_idx].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 2913 2914 tlb1_write_entry(tlb1_idx++); 2915 2916 /* XXX UNLOCK tlb1[] */ 2917 2918 /* 2919 * XXX in general TLB1 updates should be propagated between CPUs, 2920 * since current design assumes to have the same TLB1 set-up on all 2921 * cores. 2922 */ 2923 return (0); 2924} 2925 2926static int 2927tlb1_entry_size_cmp(const void *a, const void *b) 2928{ 2929 const vm_size_t *sza; 2930 const vm_size_t *szb; 2931 2932 sza = a; 2933 szb = b; 2934 if (*sza > *szb) 2935 return (-1); 2936 else if (*sza < *szb) 2937 return (1); 2938 else 2939 return (0); 2940} 2941 2942/* 2943 * Map in contiguous RAM region into the TLB1 using maximum of 2944 * KERNEL_REGION_MAX_TLB_ENTRIES entries. 2945 * 2946 * If necessary round up last entry size and return total size 2947 * used by all allocated entries. 2948 */ 2949vm_size_t 2950tlb1_mapin_region(vm_offset_t va, vm_offset_t pa, vm_size_t size) 2951{ 2952 vm_size_t entry_size[KERNEL_REGION_MAX_TLB_ENTRIES]; 2953 vm_size_t mapped_size, sz, esz; 2954 unsigned int log; 2955 int i; 2956 2957 CTR4(KTR_PMAP, "%s: region size = 0x%08x va = 0x%08x pa = 0x%08x", 2958 __func__, size, va, pa); 2959 2960 mapped_size = 0; 2961 sz = size; 2962 memset(entry_size, 0, sizeof(entry_size)); 2963 2964 /* Calculate entry sizes. */ 2965 for (i = 0; i < KERNEL_REGION_MAX_TLB_ENTRIES && sz > 0; i++) { 2966 2967 /* Largest region that is power of 4 and fits within size */ 2968 log = ilog2(sz) / 2; 2969 esz = 1 << (2 * log); 2970 2971 /* If this is last entry cover remaining size. */ 2972 if (i == KERNEL_REGION_MAX_TLB_ENTRIES - 1) { 2973 while (esz < sz) 2974 esz = esz << 2; 2975 } 2976 2977 entry_size[i] = esz; 2978 mapped_size += esz; 2979 if (esz < sz) 2980 sz -= esz; 2981 else 2982 sz = 0; 2983 } 2984 2985 /* Sort entry sizes, required to get proper entry address alignment. */ 2986 qsort(entry_size, KERNEL_REGION_MAX_TLB_ENTRIES, 2987 sizeof(vm_size_t), tlb1_entry_size_cmp); 2988 2989 /* Load TLB1 entries. */ 2990 for (i = 0; i < KERNEL_REGION_MAX_TLB_ENTRIES; i++) { 2991 esz = entry_size[i]; 2992 if (!esz) 2993 break; 2994 2995 CTR5(KTR_PMAP, "%s: entry %d: sz = 0x%08x (va = 0x%08x " 2996 "pa = 0x%08x)", __func__, tlb1_idx, esz, va, pa); 2997 2998 tlb1_set_entry(va, pa, esz, _TLB_ENTRY_MEM); 2999 3000 va += esz; 3001 pa += esz; 3002 } 3003 3004 CTR3(KTR_PMAP, "%s: mapped size 0x%08x (wasted space 0x%08x)", 3005 __func__, mapped_size, mapped_size - size); 3006 3007 return (mapped_size); 3008} 3009 3010/* 3011 * TLB1 initialization routine, to be called after the very first 3012 * assembler level setup done in locore.S. 3013 */ 3014void 3015tlb1_init(vm_offset_t ccsrbar) 3016{ 3017 uint32_t mas0; 3018 3019 /* TLB1[0] is used to map the kernel. Save that entry. */ 3020 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0); 3021 mtspr(SPR_MAS0, mas0); 3022 __asm __volatile("isync; tlbre"); 3023 3024 tlb1[0].mas1 = mfspr(SPR_MAS1); 3025 tlb1[0].mas2 = mfspr(SPR_MAS2); 3026 tlb1[0].mas3 = mfspr(SPR_MAS3); 3027 3028 /* Map in CCSRBAR in TLB1[1] */ 3029 tlb1_idx = 1; 3030 tlb1_set_entry(CCSRBAR_VA, ccsrbar, CCSRBAR_SIZE, _TLB_ENTRY_IO); 3031 3032 /* Setup TLB miss defaults */ 3033 set_mas4_defaults(); 3034} 3035 3036/* 3037 * Setup MAS4 defaults. 3038 * These values are loaded to MAS0-2 on a TLB miss. 3039 */ 3040static void 3041set_mas4_defaults(void) 3042{ 3043 uint32_t mas4; 3044 3045 /* Defaults: TLB0, PID0, TSIZED=4K */ 3046 mas4 = MAS4_TLBSELD0; 3047 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 3048#ifdef SMP 3049 mas4 |= MAS4_MD; 3050#endif 3051 mtspr(SPR_MAS4, mas4); 3052 __asm __volatile("isync"); 3053} 3054 3055/* 3056 * Print out contents of the MAS registers for each TLB1 entry 3057 */ 3058void 3059tlb1_print_tlbentries(void) 3060{ 3061 uint32_t mas0, mas1, mas2, mas3, mas7; 3062 int i; 3063 3064 debugf("TLB1 entries:\n"); 3065 for (i = 0; i < TLB1_ENTRIES; i++) { 3066 3067 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3068 mtspr(SPR_MAS0, mas0); 3069 3070 __asm __volatile("isync; tlbre"); 3071 3072 mas1 = mfspr(SPR_MAS1); 3073 mas2 = mfspr(SPR_MAS2); 3074 mas3 = mfspr(SPR_MAS3); 3075 mas7 = mfspr(SPR_MAS7); 3076 3077 tlb_print_entry(i, mas1, mas2, mas3, mas7); 3078 } 3079} 3080 3081/* 3082 * Print out contents of the in-ram tlb1 table. 3083 */ 3084void 3085tlb1_print_entries(void) 3086{ 3087 int i; 3088 3089 debugf("tlb1[] table entries:\n"); 3090 for (i = 0; i < TLB1_ENTRIES; i++) 3091 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0); 3092} 3093 3094/* 3095 * Return 0 if the physical IO range is encompassed by one of the 3096 * the TLB1 entries, otherwise return related error code. 3097 */ 3098static int 3099tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 3100{ 3101 uint32_t prot; 3102 vm_paddr_t pa_start; 3103 vm_paddr_t pa_end; 3104 unsigned int entry_tsize; 3105 vm_size_t entry_size; 3106 3107 *va = (vm_offset_t)NULL; 3108 3109 /* Skip invalid entries */ 3110 if (!(tlb1[i].mas1 & MAS1_VALID)) 3111 return (EINVAL); 3112 3113 /* 3114 * The entry must be cache-inhibited, guarded, and r/w 3115 * so it can function as an i/o page 3116 */ 3117 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G); 3118 if (prot != (MAS2_I | MAS2_G)) 3119 return (EPERM); 3120 3121 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW); 3122 if (prot != (MAS3_SR | MAS3_SW)) 3123 return (EPERM); 3124 3125 /* The address should be within the entry range. */ 3126 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3127 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3128 3129 entry_size = tsize2size(entry_tsize); 3130 pa_start = tlb1[i].mas3 & MAS3_RPN; 3131 pa_end = pa_start + entry_size - 1; 3132 3133 if ((pa < pa_start) || ((pa + size) > pa_end)) 3134 return (ERANGE); 3135 3136 /* Return virtual address of this mapping. */ 3137 *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start); 3138 return (0); 3139} 3140