pmap.c revision 222070
1/*- 2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * Some hw specific parts of this pmap were derived or influenced 27 * by NetBSD's ibm4xx pmap module. More generic code is shared with 28 * a few other pmap modules from the FreeBSD tree. 29 */ 30 31 /* 32 * VM layout notes: 33 * 34 * Kernel and user threads run within one common virtual address space 35 * defined by AS=0. 36 * 37 * Virtual address space layout: 38 * ----------------------------- 39 * 0x0000_0000 - 0xafff_ffff : user process 40 * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.) 41 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved 42 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc. 43 * 0xc100_0000 - 0xfeef_ffff : KVA 44 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy 45 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs 46 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0 47 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space 48 * 0xfef0_0000 - 0xffff_ffff : I/O devices region 49 */ 50 51#include <sys/cdefs.h> 52__FBSDID("$FreeBSD: head/sys/powerpc/booke/pmap.c 222070 2011-05-18 16:50:13Z attilio $"); 53 54#include <sys/types.h> 55#include <sys/param.h> 56#include <sys/malloc.h> 57#include <sys/ktr.h> 58#include <sys/proc.h> 59#include <sys/user.h> 60#include <sys/queue.h> 61#include <sys/systm.h> 62#include <sys/kernel.h> 63#include <sys/msgbuf.h> 64#include <sys/lock.h> 65#include <sys/mutex.h> 66#include <sys/smp.h> 67#include <sys/vmmeter.h> 68 69#include <vm/vm.h> 70#include <vm/vm_page.h> 71#include <vm/vm_kern.h> 72#include <vm/vm_pageout.h> 73#include <vm/vm_extern.h> 74#include <vm/vm_object.h> 75#include <vm/vm_param.h> 76#include <vm/vm_map.h> 77#include <vm/vm_pager.h> 78#include <vm/uma.h> 79 80#include <machine/cpu.h> 81#include <machine/pcb.h> 82#include <machine/platform.h> 83 84#include <machine/tlb.h> 85#include <machine/spr.h> 86#include <machine/vmparam.h> 87#include <machine/md_var.h> 88#include <machine/mmuvar.h> 89#include <machine/pmap.h> 90#include <machine/pte.h> 91 92#include "mmu_if.h" 93 94#define DEBUG 95#undef DEBUG 96 97#ifdef DEBUG 98#define debugf(fmt, args...) printf(fmt, ##args) 99#else 100#define debugf(fmt, args...) 101#endif 102 103#define TODO panic("%s: not implemented", __func__); 104 105#include "opt_sched.h" 106#ifndef SCHED_4BSD 107#error "e500 only works with SCHED_4BSD which uses a global scheduler lock." 108#endif 109extern struct mtx sched_lock; 110 111extern int dumpsys_minidump; 112 113extern unsigned char _etext[]; 114extern unsigned char _end[]; 115 116/* Kernel physical load address. */ 117extern uint32_t kernload; 118vm_offset_t kernstart; 119vm_size_t kernsize; 120 121/* Message buffer and tables. */ 122static vm_offset_t data_start; 123static vm_size_t data_end; 124 125/* Phys/avail memory regions. */ 126static struct mem_region *availmem_regions; 127static int availmem_regions_sz; 128static struct mem_region *physmem_regions; 129static int physmem_regions_sz; 130 131/* Reserved KVA space and mutex for mmu_booke_zero_page. */ 132static vm_offset_t zero_page_va; 133static struct mtx zero_page_mutex; 134 135static struct mtx tlbivax_mutex; 136 137/* 138 * Reserved KVA space for mmu_booke_zero_page_idle. This is used 139 * by idle thred only, no lock required. 140 */ 141static vm_offset_t zero_page_idle_va; 142 143/* Reserved KVA space and mutex for mmu_booke_copy_page. */ 144static vm_offset_t copy_page_src_va; 145static vm_offset_t copy_page_dst_va; 146static struct mtx copy_page_mutex; 147 148/**************************************************************************/ 149/* PMAP */ 150/**************************************************************************/ 151 152static void mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t, 153 vm_prot_t, boolean_t); 154 155unsigned int kptbl_min; /* Index of the first kernel ptbl. */ 156unsigned int kernel_ptbls; /* Number of KVA ptbls. */ 157 158/* 159 * If user pmap is processed with mmu_booke_remove and the resident count 160 * drops to 0, there are no more pages to remove, so we need not continue. 161 */ 162#define PMAP_REMOVE_DONE(pmap) \ 163 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0) 164 165extern void tid_flush(tlbtid_t); 166 167/**************************************************************************/ 168/* TLB and TID handling */ 169/**************************************************************************/ 170 171/* Translation ID busy table */ 172static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1]; 173 174/* 175 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500 176 * core revisions and should be read from h/w registers during early config. 177 */ 178uint32_t tlb0_entries; 179uint32_t tlb0_ways; 180uint32_t tlb0_entries_per_way; 181 182#define TLB0_ENTRIES (tlb0_entries) 183#define TLB0_WAYS (tlb0_ways) 184#define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way) 185 186#define TLB1_ENTRIES 16 187 188/* In-ram copy of the TLB1 */ 189static tlb_entry_t tlb1[TLB1_ENTRIES]; 190 191/* Next free entry in the TLB1 */ 192static unsigned int tlb1_idx; 193 194static tlbtid_t tid_alloc(struct pmap *); 195 196static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t); 197 198static int tlb1_set_entry(vm_offset_t, vm_offset_t, vm_size_t, uint32_t); 199static void tlb1_write_entry(unsigned int); 200static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *); 201static vm_size_t tlb1_mapin_region(vm_offset_t, vm_offset_t, vm_size_t); 202 203static vm_size_t tsize2size(unsigned int); 204static unsigned int size2tsize(vm_size_t); 205static unsigned int ilog2(unsigned int); 206 207static void set_mas4_defaults(void); 208 209static inline void tlb0_flush_entry(vm_offset_t); 210static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int); 211 212/**************************************************************************/ 213/* Page table management */ 214/**************************************************************************/ 215 216/* Data for the pv entry allocation mechanism */ 217static uma_zone_t pvzone; 218static struct vm_object pvzone_obj; 219static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 220 221#define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */ 222 223#ifndef PMAP_SHPGPERPROC 224#define PMAP_SHPGPERPROC 200 225#endif 226 227static void ptbl_init(void); 228static struct ptbl_buf *ptbl_buf_alloc(void); 229static void ptbl_buf_free(struct ptbl_buf *); 230static void ptbl_free_pmap_ptbl(pmap_t, pte_t *); 231 232static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int); 233static void ptbl_free(mmu_t, pmap_t, unsigned int); 234static void ptbl_hold(mmu_t, pmap_t, unsigned int); 235static int ptbl_unhold(mmu_t, pmap_t, unsigned int); 236 237static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t); 238static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t); 239static void pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t); 240static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t); 241 242static pv_entry_t pv_alloc(void); 243static void pv_free(pv_entry_t); 244static void pv_insert(pmap_t, vm_offset_t, vm_page_t); 245static void pv_remove(pmap_t, vm_offset_t, vm_page_t); 246 247/* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */ 248#define PTBL_BUFS (128 * 16) 249 250struct ptbl_buf { 251 TAILQ_ENTRY(ptbl_buf) link; /* list link */ 252 vm_offset_t kva; /* va of mapping */ 253}; 254 255/* ptbl free list and a lock used for access synchronization. */ 256static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist; 257static struct mtx ptbl_buf_freelist_lock; 258 259/* Base address of kva space allocated fot ptbl bufs. */ 260static vm_offset_t ptbl_buf_pool_vabase; 261 262/* Pointer to ptbl_buf structures. */ 263static struct ptbl_buf *ptbl_bufs; 264 265void pmap_bootstrap_ap(volatile uint32_t *); 266 267/* 268 * Kernel MMU interface 269 */ 270static void mmu_booke_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t); 271static void mmu_booke_clear_modify(mmu_t, vm_page_t); 272static void mmu_booke_clear_reference(mmu_t, vm_page_t); 273static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t, 274 vm_size_t, vm_offset_t); 275static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t); 276static void mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, 277 vm_prot_t, boolean_t); 278static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 279 vm_page_t, vm_prot_t); 280static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, 281 vm_prot_t); 282static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t); 283static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t, 284 vm_prot_t); 285static void mmu_booke_init(mmu_t); 286static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t); 287static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t); 288static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t); 289static boolean_t mmu_booke_ts_referenced(mmu_t, vm_page_t); 290static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, 291 int); 292static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t, 293 vm_paddr_t *); 294static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t, 295 vm_object_t, vm_pindex_t, vm_size_t); 296static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t); 297static void mmu_booke_page_init(mmu_t, vm_page_t); 298static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t); 299static void mmu_booke_pinit(mmu_t, pmap_t); 300static void mmu_booke_pinit0(mmu_t, pmap_t); 301static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, 302 vm_prot_t); 303static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int); 304static void mmu_booke_qremove(mmu_t, vm_offset_t, int); 305static void mmu_booke_release(mmu_t, pmap_t); 306static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t); 307static void mmu_booke_remove_all(mmu_t, vm_page_t); 308static void mmu_booke_remove_write(mmu_t, vm_page_t); 309static void mmu_booke_zero_page(mmu_t, vm_page_t); 310static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int); 311static void mmu_booke_zero_page_idle(mmu_t, vm_page_t); 312static void mmu_booke_activate(mmu_t, struct thread *); 313static void mmu_booke_deactivate(mmu_t, struct thread *); 314static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t); 315static void *mmu_booke_mapdev(mmu_t, vm_offset_t, vm_size_t); 316static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t); 317static vm_offset_t mmu_booke_kextract(mmu_t, vm_offset_t); 318static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_offset_t); 319static void mmu_booke_kremove(mmu_t, vm_offset_t); 320static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t); 321static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t, 322 vm_size_t); 323static vm_offset_t mmu_booke_dumpsys_map(mmu_t, struct pmap_md *, 324 vm_size_t, vm_size_t *); 325static void mmu_booke_dumpsys_unmap(mmu_t, struct pmap_md *, 326 vm_size_t, vm_offset_t); 327static struct pmap_md *mmu_booke_scan_md(mmu_t, struct pmap_md *); 328 329static mmu_method_t mmu_booke_methods[] = { 330 /* pmap dispatcher interface */ 331 MMUMETHOD(mmu_change_wiring, mmu_booke_change_wiring), 332 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify), 333 MMUMETHOD(mmu_clear_reference, mmu_booke_clear_reference), 334 MMUMETHOD(mmu_copy, mmu_booke_copy), 335 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page), 336 MMUMETHOD(mmu_enter, mmu_booke_enter), 337 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object), 338 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick), 339 MMUMETHOD(mmu_extract, mmu_booke_extract), 340 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold), 341 MMUMETHOD(mmu_init, mmu_booke_init), 342 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified), 343 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable), 344 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced), 345 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced), 346 MMUMETHOD(mmu_map, mmu_booke_map), 347 MMUMETHOD(mmu_mincore, mmu_booke_mincore), 348 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt), 349 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick), 350 MMUMETHOD(mmu_page_init, mmu_booke_page_init), 351 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings), 352 MMUMETHOD(mmu_pinit, mmu_booke_pinit), 353 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0), 354 MMUMETHOD(mmu_protect, mmu_booke_protect), 355 MMUMETHOD(mmu_qenter, mmu_booke_qenter), 356 MMUMETHOD(mmu_qremove, mmu_booke_qremove), 357 MMUMETHOD(mmu_release, mmu_booke_release), 358 MMUMETHOD(mmu_remove, mmu_booke_remove), 359 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all), 360 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write), 361 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache), 362 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page), 363 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area), 364 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle), 365 MMUMETHOD(mmu_activate, mmu_booke_activate), 366 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate), 367 368 /* Internal interfaces */ 369 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap), 370 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped), 371 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev), 372 MMUMETHOD(mmu_kenter, mmu_booke_kenter), 373 MMUMETHOD(mmu_kextract, mmu_booke_kextract), 374/* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */ 375 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev), 376 377 /* dumpsys() support */ 378 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map), 379 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap), 380 MMUMETHOD(mmu_scan_md, mmu_booke_scan_md), 381 382 { 0, 0 } 383}; 384 385MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0); 386 387static inline void 388tlb_miss_lock(void) 389{ 390#ifdef SMP 391 struct pcpu *pc; 392 393 if (!smp_started) 394 return; 395 396 SLIST_FOREACH(pc, &cpuhead, pc_allcpu) { 397 if (pc != pcpup) { 398 399 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, " 400 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock); 401 402 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)), 403 ("tlb_miss_lock: tried to lock self")); 404 405 tlb_lock(pc->pc_booke_tlb_lock); 406 407 CTR1(KTR_PMAP, "%s: locked", __func__); 408 } 409 } 410#endif 411} 412 413static inline void 414tlb_miss_unlock(void) 415{ 416#ifdef SMP 417 struct pcpu *pc; 418 419 if (!smp_started) 420 return; 421 422 SLIST_FOREACH(pc, &cpuhead, pc_allcpu) { 423 if (pc != pcpup) { 424 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d", 425 __func__, pc->pc_cpuid); 426 427 tlb_unlock(pc->pc_booke_tlb_lock); 428 429 CTR1(KTR_PMAP, "%s: unlocked", __func__); 430 } 431 } 432#endif 433} 434 435/* Return number of entries in TLB0. */ 436static __inline void 437tlb0_get_tlbconf(void) 438{ 439 uint32_t tlb0_cfg; 440 441 tlb0_cfg = mfspr(SPR_TLB0CFG); 442 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK; 443 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT; 444 tlb0_entries_per_way = tlb0_entries / tlb0_ways; 445} 446 447/* Initialize pool of kva ptbl buffers. */ 448static void 449ptbl_init(void) 450{ 451 int i; 452 453 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__, 454 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS); 455 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)", 456 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE); 457 458 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF); 459 TAILQ_INIT(&ptbl_buf_freelist); 460 461 for (i = 0; i < PTBL_BUFS; i++) { 462 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE; 463 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link); 464 } 465} 466 467/* Get a ptbl_buf from the freelist. */ 468static struct ptbl_buf * 469ptbl_buf_alloc(void) 470{ 471 struct ptbl_buf *buf; 472 473 mtx_lock(&ptbl_buf_freelist_lock); 474 buf = TAILQ_FIRST(&ptbl_buf_freelist); 475 if (buf != NULL) 476 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link); 477 mtx_unlock(&ptbl_buf_freelist_lock); 478 479 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 480 481 return (buf); 482} 483 484/* Return ptbl buff to free pool. */ 485static void 486ptbl_buf_free(struct ptbl_buf *buf) 487{ 488 489 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf); 490 491 mtx_lock(&ptbl_buf_freelist_lock); 492 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link); 493 mtx_unlock(&ptbl_buf_freelist_lock); 494} 495 496/* 497 * Search the list of allocated ptbl bufs and find on list of allocated ptbls 498 */ 499static void 500ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl) 501{ 502 struct ptbl_buf *pbuf; 503 504 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 505 506 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 507 508 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link) 509 if (pbuf->kva == (vm_offset_t)ptbl) { 510 /* Remove from pmap ptbl buf list. */ 511 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link); 512 513 /* Free corresponding ptbl buf. */ 514 ptbl_buf_free(pbuf); 515 break; 516 } 517} 518 519/* Allocate page table. */ 520static pte_t * 521ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 522{ 523 vm_page_t mtbl[PTBL_PAGES]; 524 vm_page_t m; 525 struct ptbl_buf *pbuf; 526 unsigned int pidx; 527 pte_t *ptbl; 528 int i; 529 530 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 531 (pmap == kernel_pmap), pdir_idx); 532 533 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 534 ("ptbl_alloc: invalid pdir_idx")); 535 KASSERT((pmap->pm_pdir[pdir_idx] == NULL), 536 ("pte_alloc: valid ptbl entry exists!")); 537 538 pbuf = ptbl_buf_alloc(); 539 if (pbuf == NULL) 540 panic("pte_alloc: couldn't alloc kernel virtual memory"); 541 542 ptbl = (pte_t *)pbuf->kva; 543 544 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl); 545 546 /* Allocate ptbl pages, this will sleep! */ 547 for (i = 0; i < PTBL_PAGES; i++) { 548 pidx = (PTBL_PAGES * pdir_idx) + i; 549 while ((m = vm_page_alloc(NULL, pidx, 550 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 551 552 PMAP_UNLOCK(pmap); 553 vm_page_unlock_queues(); 554 VM_WAIT; 555 vm_page_lock_queues(); 556 PMAP_LOCK(pmap); 557 } 558 mtbl[i] = m; 559 } 560 561 /* Map allocated pages into kernel_pmap. */ 562 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES); 563 564 /* Zero whole ptbl. */ 565 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE); 566 567 /* Add pbuf to the pmap ptbl bufs list. */ 568 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link); 569 570 return (ptbl); 571} 572 573/* Free ptbl pages and invalidate pdir entry. */ 574static void 575ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 576{ 577 pte_t *ptbl; 578 vm_paddr_t pa; 579 vm_offset_t va; 580 vm_page_t m; 581 int i; 582 583 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 584 (pmap == kernel_pmap), pdir_idx); 585 586 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 587 ("ptbl_free: invalid pdir_idx")); 588 589 ptbl = pmap->pm_pdir[pdir_idx]; 590 591 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl); 592 593 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl")); 594 595 /* 596 * Invalidate the pdir entry as soon as possible, so that other CPUs 597 * don't attempt to look up the page tables we are releasing. 598 */ 599 mtx_lock_spin(&tlbivax_mutex); 600 tlb_miss_lock(); 601 602 pmap->pm_pdir[pdir_idx] = NULL; 603 604 tlb_miss_unlock(); 605 mtx_unlock_spin(&tlbivax_mutex); 606 607 for (i = 0; i < PTBL_PAGES; i++) { 608 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE)); 609 pa = pte_vatopa(mmu, kernel_pmap, va); 610 m = PHYS_TO_VM_PAGE(pa); 611 vm_page_free_zero(m); 612 atomic_subtract_int(&cnt.v_wire_count, 1); 613 mmu_booke_kremove(mmu, va); 614 } 615 616 ptbl_free_pmap_ptbl(pmap, ptbl); 617} 618 619/* 620 * Decrement ptbl pages hold count and attempt to free ptbl pages. 621 * Called when removing pte entry from ptbl. 622 * 623 * Return 1 if ptbl pages were freed. 624 */ 625static int 626ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 627{ 628 pte_t *ptbl; 629 vm_paddr_t pa; 630 vm_page_t m; 631 int i; 632 633 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap, 634 (pmap == kernel_pmap), pdir_idx); 635 636 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 637 ("ptbl_unhold: invalid pdir_idx")); 638 KASSERT((pmap != kernel_pmap), 639 ("ptbl_unhold: unholding kernel ptbl!")); 640 641 ptbl = pmap->pm_pdir[pdir_idx]; 642 643 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl); 644 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS), 645 ("ptbl_unhold: non kva ptbl")); 646 647 /* decrement hold count */ 648 for (i = 0; i < PTBL_PAGES; i++) { 649 pa = pte_vatopa(mmu, kernel_pmap, 650 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 651 m = PHYS_TO_VM_PAGE(pa); 652 m->wire_count--; 653 } 654 655 /* 656 * Free ptbl pages if there are no pte etries in this ptbl. 657 * wire_count has the same value for all ptbl pages, so check the last 658 * page. 659 */ 660 if (m->wire_count == 0) { 661 ptbl_free(mmu, pmap, pdir_idx); 662 663 //debugf("ptbl_unhold: e (freed ptbl)\n"); 664 return (1); 665 } 666 667 return (0); 668} 669 670/* 671 * Increment hold count for ptbl pages. This routine is used when a new pte 672 * entry is being inserted into the ptbl. 673 */ 674static void 675ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx) 676{ 677 vm_paddr_t pa; 678 pte_t *ptbl; 679 vm_page_t m; 680 int i; 681 682 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap, 683 pdir_idx); 684 685 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)), 686 ("ptbl_hold: invalid pdir_idx")); 687 KASSERT((pmap != kernel_pmap), 688 ("ptbl_hold: holding kernel ptbl!")); 689 690 ptbl = pmap->pm_pdir[pdir_idx]; 691 692 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl")); 693 694 for (i = 0; i < PTBL_PAGES; i++) { 695 pa = pte_vatopa(mmu, kernel_pmap, 696 (vm_offset_t)ptbl + (i * PAGE_SIZE)); 697 m = PHYS_TO_VM_PAGE(pa); 698 m->wire_count++; 699 } 700} 701 702/* Allocate pv_entry structure. */ 703pv_entry_t 704pv_alloc(void) 705{ 706 pv_entry_t pv; 707 708 pv_entry_count++; 709 if (pv_entry_count > pv_entry_high_water) 710 pagedaemon_wakeup(); 711 pv = uma_zalloc(pvzone, M_NOWAIT); 712 713 return (pv); 714} 715 716/* Free pv_entry structure. */ 717static __inline void 718pv_free(pv_entry_t pve) 719{ 720 721 pv_entry_count--; 722 uma_zfree(pvzone, pve); 723} 724 725 726/* Allocate and initialize pv_entry structure. */ 727static void 728pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m) 729{ 730 pv_entry_t pve; 731 732 //int su = (pmap == kernel_pmap); 733 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su, 734 // (u_int32_t)pmap, va, (u_int32_t)m); 735 736 pve = pv_alloc(); 737 if (pve == NULL) 738 panic("pv_insert: no pv entries!"); 739 740 pve->pv_pmap = pmap; 741 pve->pv_va = va; 742 743 /* add to pv_list */ 744 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 745 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 746 747 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link); 748 749 //debugf("pv_insert: e\n"); 750} 751 752/* Destroy pv entry. */ 753static void 754pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m) 755{ 756 pv_entry_t pve; 757 758 //int su = (pmap == kernel_pmap); 759 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va); 760 761 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 762 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 763 764 /* find pv entry */ 765 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) { 766 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) { 767 /* remove from pv_list */ 768 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link); 769 if (TAILQ_EMPTY(&m->md.pv_list)) 770 vm_page_flag_clear(m, PG_WRITEABLE); 771 772 /* free pv entry struct */ 773 pv_free(pve); 774 break; 775 } 776 } 777 778 //debugf("pv_remove: e\n"); 779} 780 781/* 782 * Clean pte entry, try to free page table page if requested. 783 * 784 * Return 1 if ptbl pages were freed, otherwise return 0. 785 */ 786static int 787pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags) 788{ 789 unsigned int pdir_idx = PDIR_IDX(va); 790 unsigned int ptbl_idx = PTBL_IDX(va); 791 vm_page_t m; 792 pte_t *ptbl; 793 pte_t *pte; 794 795 //int su = (pmap == kernel_pmap); 796 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n", 797 // su, (u_int32_t)pmap, va, flags); 798 799 ptbl = pmap->pm_pdir[pdir_idx]; 800 KASSERT(ptbl, ("pte_remove: null ptbl")); 801 802 pte = &ptbl[ptbl_idx]; 803 804 if (pte == NULL || !PTE_ISVALID(pte)) 805 return (0); 806 807 if (PTE_ISWIRED(pte)) 808 pmap->pm_stats.wired_count--; 809 810 /* Handle managed entry. */ 811 if (PTE_ISMANAGED(pte)) { 812 /* Get vm_page_t for mapped pte. */ 813 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 814 815 if (PTE_ISMODIFIED(pte)) 816 vm_page_dirty(m); 817 818 if (PTE_ISREFERENCED(pte)) 819 vm_page_flag_set(m, PG_REFERENCED); 820 821 pv_remove(pmap, va, m); 822 } 823 824 mtx_lock_spin(&tlbivax_mutex); 825 tlb_miss_lock(); 826 827 tlb0_flush_entry(va); 828 pte->flags = 0; 829 pte->rpn = 0; 830 831 tlb_miss_unlock(); 832 mtx_unlock_spin(&tlbivax_mutex); 833 834 pmap->pm_stats.resident_count--; 835 836 if (flags & PTBL_UNHOLD) { 837 //debugf("pte_remove: e (unhold)\n"); 838 return (ptbl_unhold(mmu, pmap, pdir_idx)); 839 } 840 841 //debugf("pte_remove: e\n"); 842 return (0); 843} 844 845/* 846 * Insert PTE for a given page and virtual address. 847 */ 848static void 849pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags) 850{ 851 unsigned int pdir_idx = PDIR_IDX(va); 852 unsigned int ptbl_idx = PTBL_IDX(va); 853 pte_t *ptbl, *pte; 854 855 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__, 856 pmap == kernel_pmap, pmap, va); 857 858 /* Get the page table pointer. */ 859 ptbl = pmap->pm_pdir[pdir_idx]; 860 861 if (ptbl == NULL) { 862 /* Allocate page table pages. */ 863 ptbl = ptbl_alloc(mmu, pmap, pdir_idx); 864 } else { 865 /* 866 * Check if there is valid mapping for requested 867 * va, if there is, remove it. 868 */ 869 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx]; 870 if (PTE_ISVALID(pte)) { 871 pte_remove(mmu, pmap, va, PTBL_HOLD); 872 } else { 873 /* 874 * pte is not used, increment hold count 875 * for ptbl pages. 876 */ 877 if (pmap != kernel_pmap) 878 ptbl_hold(mmu, pmap, pdir_idx); 879 } 880 } 881 882 /* 883 * Insert pv_entry into pv_list for mapped page if part of managed 884 * memory. 885 */ 886 if ((m->flags & PG_FICTITIOUS) == 0) { 887 if ((m->flags & PG_UNMANAGED) == 0) { 888 flags |= PTE_MANAGED; 889 890 /* Create and insert pv entry. */ 891 pv_insert(pmap, va, m); 892 } 893 } 894 895 pmap->pm_stats.resident_count++; 896 897 mtx_lock_spin(&tlbivax_mutex); 898 tlb_miss_lock(); 899 900 tlb0_flush_entry(va); 901 if (pmap->pm_pdir[pdir_idx] == NULL) { 902 /* 903 * If we just allocated a new page table, hook it in 904 * the pdir. 905 */ 906 pmap->pm_pdir[pdir_idx] = ptbl; 907 } 908 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]); 909 pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK; 910 pte->flags |= (PTE_VALID | flags); 911 912 tlb_miss_unlock(); 913 mtx_unlock_spin(&tlbivax_mutex); 914} 915 916/* Return the pa for the given pmap/va. */ 917static vm_paddr_t 918pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va) 919{ 920 vm_paddr_t pa = 0; 921 pte_t *pte; 922 923 pte = pte_find(mmu, pmap, va); 924 if ((pte != NULL) && PTE_ISVALID(pte)) 925 pa = (PTE_PA(pte) | (va & PTE_PA_MASK)); 926 return (pa); 927} 928 929/* Get a pointer to a PTE in a page table. */ 930static pte_t * 931pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va) 932{ 933 unsigned int pdir_idx = PDIR_IDX(va); 934 unsigned int ptbl_idx = PTBL_IDX(va); 935 936 KASSERT((pmap != NULL), ("pte_find: invalid pmap")); 937 938 if (pmap->pm_pdir[pdir_idx]) 939 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx])); 940 941 return (NULL); 942} 943 944/**************************************************************************/ 945/* PMAP related */ 946/**************************************************************************/ 947 948/* 949 * This is called during e500_init, before the system is really initialized. 950 */ 951static void 952mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend) 953{ 954 vm_offset_t phys_kernelend; 955 struct mem_region *mp, *mp1; 956 int cnt, i, j; 957 u_int s, e, sz; 958 u_int phys_avail_count; 959 vm_size_t physsz, hwphyssz, kstack0_sz; 960 vm_offset_t kernel_pdir, kstack0, va; 961 vm_paddr_t kstack0_phys; 962 void *dpcpu; 963 pte_t *pte; 964 965 debugf("mmu_booke_bootstrap: entered\n"); 966 967 /* Initialize invalidation mutex */ 968 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN); 969 970 /* Read TLB0 size and associativity. */ 971 tlb0_get_tlbconf(); 972 973 /* Align kernel start and end address (kernel image). */ 974 kernstart = trunc_page(start); 975 data_start = round_page(kernelend); 976 kernsize = data_start - kernstart; 977 978 data_end = data_start; 979 980 /* Allocate space for the message buffer. */ 981 msgbufp = (struct msgbuf *)data_end; 982 data_end += msgbufsize; 983 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp, 984 data_end); 985 986 data_end = round_page(data_end); 987 988 /* Allocate the dynamic per-cpu area. */ 989 dpcpu = (void *)data_end; 990 data_end += DPCPU_SIZE; 991 dpcpu_init(dpcpu, 0); 992 993 /* Allocate space for ptbl_bufs. */ 994 ptbl_bufs = (struct ptbl_buf *)data_end; 995 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS; 996 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs, 997 data_end); 998 999 data_end = round_page(data_end); 1000 1001 /* Allocate PTE tables for kernel KVA. */ 1002 kernel_pdir = data_end; 1003 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS + 1004 PDIR_SIZE - 1) / PDIR_SIZE; 1005 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE; 1006 debugf(" kernel ptbls: %d\n", kernel_ptbls); 1007 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end); 1008 1009 debugf(" data_end: 0x%08x\n", data_end); 1010 if (data_end - kernstart > 0x1000000) { 1011 data_end = (data_end + 0x3fffff) & ~0x3fffff; 1012 tlb1_mapin_region(kernstart + 0x1000000, 1013 kernload + 0x1000000, data_end - kernstart - 0x1000000); 1014 } else 1015 data_end = (data_end + 0xffffff) & ~0xffffff; 1016 1017 debugf(" updated data_end: 0x%08x\n", data_end); 1018 1019 kernsize += data_end - data_start; 1020 1021 /* 1022 * Clear the structures - note we can only do it safely after the 1023 * possible additional TLB1 translations are in place (above) so that 1024 * all range up to the currently calculated 'data_end' is covered. 1025 */ 1026 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE); 1027 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE); 1028 1029 /*******************************************************/ 1030 /* Set the start and end of kva. */ 1031 /*******************************************************/ 1032 virtual_avail = round_page(data_end); 1033 virtual_end = VM_MAX_KERNEL_ADDRESS; 1034 1035 /* Allocate KVA space for page zero/copy operations. */ 1036 zero_page_va = virtual_avail; 1037 virtual_avail += PAGE_SIZE; 1038 zero_page_idle_va = virtual_avail; 1039 virtual_avail += PAGE_SIZE; 1040 copy_page_src_va = virtual_avail; 1041 virtual_avail += PAGE_SIZE; 1042 copy_page_dst_va = virtual_avail; 1043 virtual_avail += PAGE_SIZE; 1044 debugf("zero_page_va = 0x%08x\n", zero_page_va); 1045 debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va); 1046 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va); 1047 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va); 1048 1049 /* Initialize page zero/copy mutexes. */ 1050 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF); 1051 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF); 1052 1053 /* Allocate KVA space for ptbl bufs. */ 1054 ptbl_buf_pool_vabase = virtual_avail; 1055 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE; 1056 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n", 1057 ptbl_buf_pool_vabase, virtual_avail); 1058 1059 /* Calculate corresponding physical addresses for the kernel region. */ 1060 phys_kernelend = kernload + kernsize; 1061 debugf("kernel image and allocated data:\n"); 1062 debugf(" kernload = 0x%08x\n", kernload); 1063 debugf(" kernstart = 0x%08x\n", kernstart); 1064 debugf(" kernsize = 0x%08x\n", kernsize); 1065 1066 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz) 1067 panic("mmu_booke_bootstrap: phys_avail too small"); 1068 1069 /* 1070 * Remove kernel physical address range from avail regions list. Page 1071 * align all regions. Non-page aligned memory isn't very interesting 1072 * to us. Also, sort the entries for ascending addresses. 1073 */ 1074 1075 /* Retrieve phys/avail mem regions */ 1076 mem_regions(&physmem_regions, &physmem_regions_sz, 1077 &availmem_regions, &availmem_regions_sz); 1078 sz = 0; 1079 cnt = availmem_regions_sz; 1080 debugf("processing avail regions:\n"); 1081 for (mp = availmem_regions; mp->mr_size; mp++) { 1082 s = mp->mr_start; 1083 e = mp->mr_start + mp->mr_size; 1084 debugf(" %08x-%08x -> ", s, e); 1085 /* Check whether this region holds all of the kernel. */ 1086 if (s < kernload && e > phys_kernelend) { 1087 availmem_regions[cnt].mr_start = phys_kernelend; 1088 availmem_regions[cnt++].mr_size = e - phys_kernelend; 1089 e = kernload; 1090 } 1091 /* Look whether this regions starts within the kernel. */ 1092 if (s >= kernload && s < phys_kernelend) { 1093 if (e <= phys_kernelend) 1094 goto empty; 1095 s = phys_kernelend; 1096 } 1097 /* Now look whether this region ends within the kernel. */ 1098 if (e > kernload && e <= phys_kernelend) { 1099 if (s >= kernload) 1100 goto empty; 1101 e = kernload; 1102 } 1103 /* Now page align the start and size of the region. */ 1104 s = round_page(s); 1105 e = trunc_page(e); 1106 if (e < s) 1107 e = s; 1108 sz = e - s; 1109 debugf("%08x-%08x = %x\n", s, e, sz); 1110 1111 /* Check whether some memory is left here. */ 1112 if (sz == 0) { 1113 empty: 1114 memmove(mp, mp + 1, 1115 (cnt - (mp - availmem_regions)) * sizeof(*mp)); 1116 cnt--; 1117 mp--; 1118 continue; 1119 } 1120 1121 /* Do an insertion sort. */ 1122 for (mp1 = availmem_regions; mp1 < mp; mp1++) 1123 if (s < mp1->mr_start) 1124 break; 1125 if (mp1 < mp) { 1126 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1); 1127 mp1->mr_start = s; 1128 mp1->mr_size = sz; 1129 } else { 1130 mp->mr_start = s; 1131 mp->mr_size = sz; 1132 } 1133 } 1134 availmem_regions_sz = cnt; 1135 1136 /*******************************************************/ 1137 /* Steal physical memory for kernel stack from the end */ 1138 /* of the first avail region */ 1139 /*******************************************************/ 1140 kstack0_sz = KSTACK_PAGES * PAGE_SIZE; 1141 kstack0_phys = availmem_regions[0].mr_start + 1142 availmem_regions[0].mr_size; 1143 kstack0_phys -= kstack0_sz; 1144 availmem_regions[0].mr_size -= kstack0_sz; 1145 1146 /*******************************************************/ 1147 /* Fill in phys_avail table, based on availmem_regions */ 1148 /*******************************************************/ 1149 phys_avail_count = 0; 1150 physsz = 0; 1151 hwphyssz = 0; 1152 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz); 1153 1154 debugf("fill in phys_avail:\n"); 1155 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) { 1156 1157 debugf(" region: 0x%08x - 0x%08x (0x%08x)\n", 1158 availmem_regions[i].mr_start, 1159 availmem_regions[i].mr_start + 1160 availmem_regions[i].mr_size, 1161 availmem_regions[i].mr_size); 1162 1163 if (hwphyssz != 0 && 1164 (physsz + availmem_regions[i].mr_size) >= hwphyssz) { 1165 debugf(" hw.physmem adjust\n"); 1166 if (physsz < hwphyssz) { 1167 phys_avail[j] = availmem_regions[i].mr_start; 1168 phys_avail[j + 1] = 1169 availmem_regions[i].mr_start + 1170 hwphyssz - physsz; 1171 physsz = hwphyssz; 1172 phys_avail_count++; 1173 } 1174 break; 1175 } 1176 1177 phys_avail[j] = availmem_regions[i].mr_start; 1178 phys_avail[j + 1] = availmem_regions[i].mr_start + 1179 availmem_regions[i].mr_size; 1180 phys_avail_count++; 1181 physsz += availmem_regions[i].mr_size; 1182 } 1183 physmem = btoc(physsz); 1184 1185 /* Calculate the last available physical address. */ 1186 for (i = 0; phys_avail[i + 2] != 0; i += 2) 1187 ; 1188 Maxmem = powerpc_btop(phys_avail[i + 1]); 1189 1190 debugf("Maxmem = 0x%08lx\n", Maxmem); 1191 debugf("phys_avail_count = %d\n", phys_avail_count); 1192 debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem, 1193 physmem); 1194 1195 /*******************************************************/ 1196 /* Initialize (statically allocated) kernel pmap. */ 1197 /*******************************************************/ 1198 PMAP_LOCK_INIT(kernel_pmap); 1199 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE; 1200 1201 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap); 1202 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls); 1203 debugf("kernel pdir range: 0x%08x - 0x%08x\n", 1204 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1); 1205 1206 /* Initialize kernel pdir */ 1207 for (i = 0; i < kernel_ptbls; i++) 1208 kernel_pmap->pm_pdir[kptbl_min + i] = 1209 (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES)); 1210 1211 for (i = 0; i < MAXCPU; i++) { 1212 kernel_pmap->pm_tid[i] = TID_KERNEL; 1213 1214 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */ 1215 tidbusy[i][0] = kernel_pmap; 1216 } 1217 1218 /* 1219 * Fill in PTEs covering kernel code and data. They are not required 1220 * for address translation, as this area is covered by static TLB1 1221 * entries, but for pte_vatopa() to work correctly with kernel area 1222 * addresses. 1223 */ 1224 for (va = KERNBASE; va < data_end; va += PAGE_SIZE) { 1225 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]); 1226 pte->rpn = kernload + (va - KERNBASE); 1227 pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | 1228 PTE_VALID; 1229 } 1230 /* Mark kernel_pmap active on all CPUs */ 1231 kernel_pmap->pm_active = ~0; 1232 1233 /*******************************************************/ 1234 /* Final setup */ 1235 /*******************************************************/ 1236 1237 /* Enter kstack0 into kernel map, provide guard page */ 1238 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE; 1239 thread0.td_kstack = kstack0; 1240 thread0.td_kstack_pages = KSTACK_PAGES; 1241 1242 debugf("kstack_sz = 0x%08x\n", kstack0_sz); 1243 debugf("kstack0_phys at 0x%08x - 0x%08x\n", 1244 kstack0_phys, kstack0_phys + kstack0_sz); 1245 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz); 1246 1247 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz; 1248 for (i = 0; i < KSTACK_PAGES; i++) { 1249 mmu_booke_kenter(mmu, kstack0, kstack0_phys); 1250 kstack0 += PAGE_SIZE; 1251 kstack0_phys += PAGE_SIZE; 1252 } 1253 1254 debugf("virtual_avail = %08x\n", virtual_avail); 1255 debugf("virtual_end = %08x\n", virtual_end); 1256 1257 debugf("mmu_booke_bootstrap: exit\n"); 1258} 1259 1260void 1261pmap_bootstrap_ap(volatile uint32_t *trcp __unused) 1262{ 1263 int i; 1264 1265 /* 1266 * Finish TLB1 configuration: the BSP already set up its TLB1 and we 1267 * have the snapshot of its contents in the s/w tlb1[] table, so use 1268 * these values directly to (re)program AP's TLB1 hardware. 1269 */ 1270 for (i = 0; i < tlb1_idx; i ++) { 1271 /* Skip invalid entries */ 1272 if (!(tlb1[i].mas1 & MAS1_VALID)) 1273 continue; 1274 1275 tlb1_write_entry(i); 1276 } 1277 1278 set_mas4_defaults(); 1279} 1280 1281/* 1282 * Get the physical page address for the given pmap/virtual address. 1283 */ 1284static vm_paddr_t 1285mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va) 1286{ 1287 vm_paddr_t pa; 1288 1289 PMAP_LOCK(pmap); 1290 pa = pte_vatopa(mmu, pmap, va); 1291 PMAP_UNLOCK(pmap); 1292 1293 return (pa); 1294} 1295 1296/* 1297 * Extract the physical page address associated with the given 1298 * kernel virtual address. 1299 */ 1300static vm_paddr_t 1301mmu_booke_kextract(mmu_t mmu, vm_offset_t va) 1302{ 1303 1304 return (pte_vatopa(mmu, kernel_pmap, va)); 1305} 1306 1307/* 1308 * Initialize the pmap module. 1309 * Called by vm_init, to initialize any structures that the pmap 1310 * system needs to map virtual memory. 1311 */ 1312static void 1313mmu_booke_init(mmu_t mmu) 1314{ 1315 int shpgperproc = PMAP_SHPGPERPROC; 1316 1317 /* 1318 * Initialize the address space (zone) for the pv entries. Set a 1319 * high water mark so that the system can recover from excessive 1320 * numbers of pv entries. 1321 */ 1322 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 1323 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 1324 1325 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 1326 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 1327 1328 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 1329 pv_entry_high_water = 9 * (pv_entry_max / 10); 1330 1331 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 1332 1333 /* Pre-fill pvzone with initial number of pv entries. */ 1334 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN); 1335 1336 /* Initialize ptbl allocation. */ 1337 ptbl_init(); 1338} 1339 1340/* 1341 * Map a list of wired pages into kernel virtual address space. This is 1342 * intended for temporary mappings which do not need page modification or 1343 * references recorded. Existing mappings in the region are overwritten. 1344 */ 1345static void 1346mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count) 1347{ 1348 vm_offset_t va; 1349 1350 va = sva; 1351 while (count-- > 0) { 1352 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m)); 1353 va += PAGE_SIZE; 1354 m++; 1355 } 1356} 1357 1358/* 1359 * Remove page mappings from kernel virtual address space. Intended for 1360 * temporary mappings entered by mmu_booke_qenter. 1361 */ 1362static void 1363mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count) 1364{ 1365 vm_offset_t va; 1366 1367 va = sva; 1368 while (count-- > 0) { 1369 mmu_booke_kremove(mmu, va); 1370 va += PAGE_SIZE; 1371 } 1372} 1373 1374/* 1375 * Map a wired page into kernel virtual address space. 1376 */ 1377static void 1378mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa) 1379{ 1380 unsigned int pdir_idx = PDIR_IDX(va); 1381 unsigned int ptbl_idx = PTBL_IDX(va); 1382 uint32_t flags; 1383 pte_t *pte; 1384 1385 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1386 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va")); 1387 1388 flags = 0; 1389 flags |= (PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID); 1390 flags |= PTE_M; 1391 1392 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1393 1394 mtx_lock_spin(&tlbivax_mutex); 1395 tlb_miss_lock(); 1396 1397 if (PTE_ISVALID(pte)) { 1398 1399 CTR1(KTR_PMAP, "%s: replacing entry!", __func__); 1400 1401 /* Flush entry from TLB0 */ 1402 tlb0_flush_entry(va); 1403 } 1404 1405 pte->rpn = pa & ~PTE_PA_MASK; 1406 pte->flags = flags; 1407 1408 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x " 1409 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n", 1410 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags); 1411 1412 /* Flush the real memory from the instruction cache. */ 1413 if ((flags & (PTE_I | PTE_G)) == 0) { 1414 __syncicache((void *)va, PAGE_SIZE); 1415 } 1416 1417 tlb_miss_unlock(); 1418 mtx_unlock_spin(&tlbivax_mutex); 1419} 1420 1421/* 1422 * Remove a page from kernel page table. 1423 */ 1424static void 1425mmu_booke_kremove(mmu_t mmu, vm_offset_t va) 1426{ 1427 unsigned int pdir_idx = PDIR_IDX(va); 1428 unsigned int ptbl_idx = PTBL_IDX(va); 1429 pte_t *pte; 1430 1431// CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va)); 1432 1433 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) && 1434 (va <= VM_MAX_KERNEL_ADDRESS)), 1435 ("mmu_booke_kremove: invalid va")); 1436 1437 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]); 1438 1439 if (!PTE_ISVALID(pte)) { 1440 1441 CTR1(KTR_PMAP, "%s: invalid pte", __func__); 1442 1443 return; 1444 } 1445 1446 mtx_lock_spin(&tlbivax_mutex); 1447 tlb_miss_lock(); 1448 1449 /* Invalidate entry in TLB0, update PTE. */ 1450 tlb0_flush_entry(va); 1451 pte->flags = 0; 1452 pte->rpn = 0; 1453 1454 tlb_miss_unlock(); 1455 mtx_unlock_spin(&tlbivax_mutex); 1456} 1457 1458/* 1459 * Initialize pmap associated with process 0. 1460 */ 1461static void 1462mmu_booke_pinit0(mmu_t mmu, pmap_t pmap) 1463{ 1464 1465 mmu_booke_pinit(mmu, pmap); 1466 PCPU_SET(curpmap, pmap); 1467} 1468 1469/* 1470 * Initialize a preallocated and zeroed pmap structure, 1471 * such as one in a vmspace structure. 1472 */ 1473static void 1474mmu_booke_pinit(mmu_t mmu, pmap_t pmap) 1475{ 1476 int i; 1477 1478 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap, 1479 curthread->td_proc->p_pid, curthread->td_proc->p_comm); 1480 1481 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap")); 1482 1483 PMAP_LOCK_INIT(pmap); 1484 for (i = 0; i < MAXCPU; i++) 1485 pmap->pm_tid[i] = TID_NONE; 1486 pmap->pm_active = 0; 1487 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1488 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES); 1489 TAILQ_INIT(&pmap->pm_ptbl_list); 1490} 1491 1492/* 1493 * Release any resources held by the given physical map. 1494 * Called when a pmap initialized by mmu_booke_pinit is being released. 1495 * Should only be called if the map contains no valid mappings. 1496 */ 1497static void 1498mmu_booke_release(mmu_t mmu, pmap_t pmap) 1499{ 1500 1501 KASSERT(pmap->pm_stats.resident_count == 0, 1502 ("pmap_release: pmap resident count %ld != 0", 1503 pmap->pm_stats.resident_count)); 1504 1505 PMAP_LOCK_DESTROY(pmap); 1506} 1507 1508/* 1509 * Insert the given physical page at the specified virtual address in the 1510 * target physical map with the protection requested. If specified the page 1511 * will be wired down. 1512 */ 1513static void 1514mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1515 vm_prot_t prot, boolean_t wired) 1516{ 1517 1518 vm_page_lock_queues(); 1519 PMAP_LOCK(pmap); 1520 mmu_booke_enter_locked(mmu, pmap, va, m, prot, wired); 1521 vm_page_unlock_queues(); 1522 PMAP_UNLOCK(pmap); 1523} 1524 1525static void 1526mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1527 vm_prot_t prot, boolean_t wired) 1528{ 1529 pte_t *pte; 1530 vm_paddr_t pa; 1531 uint32_t flags; 1532 int su, sync; 1533 1534 pa = VM_PAGE_TO_PHYS(m); 1535 su = (pmap == kernel_pmap); 1536 sync = 0; 1537 1538 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x " 1539 // "pa=0x%08x prot=0x%08x wired=%d)\n", 1540 // (u_int32_t)pmap, su, pmap->pm_tid, 1541 // (u_int32_t)m, va, pa, prot, wired); 1542 1543 if (su) { 1544 KASSERT(((va >= virtual_avail) && 1545 (va <= VM_MAX_KERNEL_ADDRESS)), 1546 ("mmu_booke_enter_locked: kernel pmap, non kernel va")); 1547 } else { 1548 KASSERT((va <= VM_MAXUSER_ADDRESS), 1549 ("mmu_booke_enter_locked: user pmap, non user va")); 1550 } 1551 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1552 (m->oflags & VPO_BUSY) != 0 || VM_OBJECT_LOCKED(m->object), 1553 ("mmu_booke_enter_locked: page %p is not busy", m)); 1554 1555 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1556 1557 /* 1558 * If there is an existing mapping, and the physical address has not 1559 * changed, must be protection or wiring change. 1560 */ 1561 if (((pte = pte_find(mmu, pmap, va)) != NULL) && 1562 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) { 1563 1564 /* 1565 * Before actually updating pte->flags we calculate and 1566 * prepare its new value in a helper var. 1567 */ 1568 flags = pte->flags; 1569 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED); 1570 1571 /* Wiring change, just update stats. */ 1572 if (wired) { 1573 if (!PTE_ISWIRED(pte)) { 1574 flags |= PTE_WIRED; 1575 pmap->pm_stats.wired_count++; 1576 } 1577 } else { 1578 if (PTE_ISWIRED(pte)) { 1579 flags &= ~PTE_WIRED; 1580 pmap->pm_stats.wired_count--; 1581 } 1582 } 1583 1584 if (prot & VM_PROT_WRITE) { 1585 /* Add write permissions. */ 1586 flags |= PTE_SW; 1587 if (!su) 1588 flags |= PTE_UW; 1589 1590 if ((flags & PTE_MANAGED) != 0) 1591 vm_page_flag_set(m, PG_WRITEABLE); 1592 } else { 1593 /* Handle modified pages, sense modify status. */ 1594 1595 /* 1596 * The PTE_MODIFIED flag could be set by underlying 1597 * TLB misses since we last read it (above), possibly 1598 * other CPUs could update it so we check in the PTE 1599 * directly rather than rely on that saved local flags 1600 * copy. 1601 */ 1602 if (PTE_ISMODIFIED(pte)) 1603 vm_page_dirty(m); 1604 } 1605 1606 if (prot & VM_PROT_EXECUTE) { 1607 flags |= PTE_SX; 1608 if (!su) 1609 flags |= PTE_UX; 1610 1611 /* 1612 * Check existing flags for execute permissions: if we 1613 * are turning execute permissions on, icache should 1614 * be flushed. 1615 */ 1616 if ((pte->flags & (PTE_UX | PTE_SX)) == 0) 1617 sync++; 1618 } 1619 1620 flags &= ~PTE_REFERENCED; 1621 1622 /* 1623 * The new flags value is all calculated -- only now actually 1624 * update the PTE. 1625 */ 1626 mtx_lock_spin(&tlbivax_mutex); 1627 tlb_miss_lock(); 1628 1629 tlb0_flush_entry(va); 1630 pte->flags = flags; 1631 1632 tlb_miss_unlock(); 1633 mtx_unlock_spin(&tlbivax_mutex); 1634 1635 } else { 1636 /* 1637 * If there is an existing mapping, but it's for a different 1638 * physical address, pte_enter() will delete the old mapping. 1639 */ 1640 //if ((pte != NULL) && PTE_ISVALID(pte)) 1641 // debugf("mmu_booke_enter_locked: replace\n"); 1642 //else 1643 // debugf("mmu_booke_enter_locked: new\n"); 1644 1645 /* Now set up the flags and install the new mapping. */ 1646 flags = (PTE_SR | PTE_VALID); 1647 flags |= PTE_M; 1648 1649 if (!su) 1650 flags |= PTE_UR; 1651 1652 if (prot & VM_PROT_WRITE) { 1653 flags |= PTE_SW; 1654 if (!su) 1655 flags |= PTE_UW; 1656 1657 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) 1658 vm_page_flag_set(m, PG_WRITEABLE); 1659 } 1660 1661 if (prot & VM_PROT_EXECUTE) { 1662 flags |= PTE_SX; 1663 if (!su) 1664 flags |= PTE_UX; 1665 } 1666 1667 /* If its wired update stats. */ 1668 if (wired) { 1669 pmap->pm_stats.wired_count++; 1670 flags |= PTE_WIRED; 1671 } 1672 1673 pte_enter(mmu, pmap, m, va, flags); 1674 1675 /* Flush the real memory from the instruction cache. */ 1676 if (prot & VM_PROT_EXECUTE) 1677 sync++; 1678 } 1679 1680 if (sync && (su || pmap == PCPU_GET(curpmap))) { 1681 __syncicache((void *)va, PAGE_SIZE); 1682 sync = 0; 1683 } 1684} 1685 1686/* 1687 * Maps a sequence of resident pages belonging to the same object. 1688 * The sequence begins with the given page m_start. This page is 1689 * mapped at the given virtual address start. Each subsequent page is 1690 * mapped at a virtual address that is offset from start by the same 1691 * amount as the page is offset from m_start within the object. The 1692 * last page in the sequence is the page with the largest offset from 1693 * m_start that can be mapped at a virtual address less than the given 1694 * virtual address end. Not every virtual page between start and end 1695 * is mapped; only those for which a resident page exists with the 1696 * corresponding offset from m_start are mapped. 1697 */ 1698static void 1699mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start, 1700 vm_offset_t end, vm_page_t m_start, vm_prot_t prot) 1701{ 1702 vm_page_t m; 1703 vm_pindex_t diff, psize; 1704 1705 psize = atop(end - start); 1706 m = m_start; 1707 vm_page_lock_queues(); 1708 PMAP_LOCK(pmap); 1709 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 1710 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m, 1711 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1712 m = TAILQ_NEXT(m, listq); 1713 } 1714 vm_page_unlock_queues(); 1715 PMAP_UNLOCK(pmap); 1716} 1717 1718static void 1719mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, 1720 vm_prot_t prot) 1721{ 1722 1723 vm_page_lock_queues(); 1724 PMAP_LOCK(pmap); 1725 mmu_booke_enter_locked(mmu, pmap, va, m, 1726 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE); 1727 vm_page_unlock_queues(); 1728 PMAP_UNLOCK(pmap); 1729} 1730 1731/* 1732 * Remove the given range of addresses from the specified map. 1733 * 1734 * It is assumed that the start and end are properly rounded to the page size. 1735 */ 1736static void 1737mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva) 1738{ 1739 pte_t *pte; 1740 uint8_t hold_flag; 1741 1742 int su = (pmap == kernel_pmap); 1743 1744 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n", 1745 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva); 1746 1747 if (su) { 1748 KASSERT(((va >= virtual_avail) && 1749 (va <= VM_MAX_KERNEL_ADDRESS)), 1750 ("mmu_booke_remove: kernel pmap, non kernel va")); 1751 } else { 1752 KASSERT((va <= VM_MAXUSER_ADDRESS), 1753 ("mmu_booke_remove: user pmap, non user va")); 1754 } 1755 1756 if (PMAP_REMOVE_DONE(pmap)) { 1757 //debugf("mmu_booke_remove: e (empty)\n"); 1758 return; 1759 } 1760 1761 hold_flag = PTBL_HOLD_FLAG(pmap); 1762 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag); 1763 1764 vm_page_lock_queues(); 1765 PMAP_LOCK(pmap); 1766 for (; va < endva; va += PAGE_SIZE) { 1767 pte = pte_find(mmu, pmap, va); 1768 if ((pte != NULL) && PTE_ISVALID(pte)) 1769 pte_remove(mmu, pmap, va, hold_flag); 1770 } 1771 PMAP_UNLOCK(pmap); 1772 vm_page_unlock_queues(); 1773 1774 //debugf("mmu_booke_remove: e\n"); 1775} 1776 1777/* 1778 * Remove physical page from all pmaps in which it resides. 1779 */ 1780static void 1781mmu_booke_remove_all(mmu_t mmu, vm_page_t m) 1782{ 1783 pv_entry_t pv, pvn; 1784 uint8_t hold_flag; 1785 1786 vm_page_lock_queues(); 1787 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) { 1788 pvn = TAILQ_NEXT(pv, pv_link); 1789 1790 PMAP_LOCK(pv->pv_pmap); 1791 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap); 1792 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag); 1793 PMAP_UNLOCK(pv->pv_pmap); 1794 } 1795 vm_page_flag_clear(m, PG_WRITEABLE); 1796 vm_page_unlock_queues(); 1797} 1798 1799/* 1800 * Map a range of physical addresses into kernel virtual address space. 1801 */ 1802static vm_offset_t 1803mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start, 1804 vm_offset_t pa_end, int prot) 1805{ 1806 vm_offset_t sva = *virt; 1807 vm_offset_t va = sva; 1808 1809 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n", 1810 // sva, pa_start, pa_end); 1811 1812 while (pa_start < pa_end) { 1813 mmu_booke_kenter(mmu, va, pa_start); 1814 va += PAGE_SIZE; 1815 pa_start += PAGE_SIZE; 1816 } 1817 *virt = va; 1818 1819 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va); 1820 return (sva); 1821} 1822 1823/* 1824 * The pmap must be activated before it's address space can be accessed in any 1825 * way. 1826 */ 1827static void 1828mmu_booke_activate(mmu_t mmu, struct thread *td) 1829{ 1830 pmap_t pmap; 1831 1832 pmap = &td->td_proc->p_vmspace->vm_pmap; 1833 1834 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)", 1835 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1836 1837 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!")); 1838 1839 mtx_lock_spin(&sched_lock); 1840 1841 atomic_set_int(&pmap->pm_active, PCPU_GET(cpumask)); 1842 PCPU_SET(curpmap, pmap); 1843 1844 if (pmap->pm_tid[PCPU_GET(cpuid)] == TID_NONE) 1845 tid_alloc(pmap); 1846 1847 /* Load PID0 register with pmap tid value. */ 1848 mtspr(SPR_PID0, pmap->pm_tid[PCPU_GET(cpuid)]); 1849 __asm __volatile("isync"); 1850 1851 mtx_unlock_spin(&sched_lock); 1852 1853 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__, 1854 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm); 1855} 1856 1857/* 1858 * Deactivate the specified process's address space. 1859 */ 1860static void 1861mmu_booke_deactivate(mmu_t mmu, struct thread *td) 1862{ 1863 pmap_t pmap; 1864 1865 pmap = &td->td_proc->p_vmspace->vm_pmap; 1866 1867 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x", 1868 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap); 1869 1870 atomic_clear_int(&pmap->pm_active, PCPU_GET(cpumask)); 1871 PCPU_SET(curpmap, NULL); 1872} 1873 1874/* 1875 * Copy the range specified by src_addr/len 1876 * from the source map to the range dst_addr/len 1877 * in the destination map. 1878 * 1879 * This routine is only advisory and need not do anything. 1880 */ 1881static void 1882mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap, 1883 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr) 1884{ 1885 1886} 1887 1888/* 1889 * Set the physical protection on the specified range of this map as requested. 1890 */ 1891static void 1892mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva, 1893 vm_prot_t prot) 1894{ 1895 vm_offset_t va; 1896 vm_page_t m; 1897 pte_t *pte; 1898 1899 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1900 mmu_booke_remove(mmu, pmap, sva, eva); 1901 return; 1902 } 1903 1904 if (prot & VM_PROT_WRITE) 1905 return; 1906 1907 vm_page_lock_queues(); 1908 PMAP_LOCK(pmap); 1909 for (va = sva; va < eva; va += PAGE_SIZE) { 1910 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 1911 if (PTE_ISVALID(pte)) { 1912 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1913 1914 mtx_lock_spin(&tlbivax_mutex); 1915 tlb_miss_lock(); 1916 1917 /* Handle modified pages. */ 1918 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte)) 1919 vm_page_dirty(m); 1920 1921 tlb0_flush_entry(va); 1922 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 1923 1924 tlb_miss_unlock(); 1925 mtx_unlock_spin(&tlbivax_mutex); 1926 } 1927 } 1928 } 1929 PMAP_UNLOCK(pmap); 1930 vm_page_unlock_queues(); 1931} 1932 1933/* 1934 * Clear the write and modified bits in each of the given page's mappings. 1935 */ 1936static void 1937mmu_booke_remove_write(mmu_t mmu, vm_page_t m) 1938{ 1939 pv_entry_t pv; 1940 pte_t *pte; 1941 1942 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 1943 ("mmu_booke_remove_write: page %p is not managed", m)); 1944 1945 /* 1946 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 1947 * another thread while the object is locked. Thus, if PG_WRITEABLE 1948 * is clear, no page table entries need updating. 1949 */ 1950 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 1951 if ((m->oflags & VPO_BUSY) == 0 && 1952 (m->flags & PG_WRITEABLE) == 0) 1953 return; 1954 vm_page_lock_queues(); 1955 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 1956 PMAP_LOCK(pv->pv_pmap); 1957 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) { 1958 if (PTE_ISVALID(pte)) { 1959 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 1960 1961 mtx_lock_spin(&tlbivax_mutex); 1962 tlb_miss_lock(); 1963 1964 /* Handle modified pages. */ 1965 if (PTE_ISMODIFIED(pte)) 1966 vm_page_dirty(m); 1967 1968 /* Flush mapping from TLB0. */ 1969 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED); 1970 1971 tlb_miss_unlock(); 1972 mtx_unlock_spin(&tlbivax_mutex); 1973 } 1974 } 1975 PMAP_UNLOCK(pv->pv_pmap); 1976 } 1977 vm_page_flag_clear(m, PG_WRITEABLE); 1978 vm_page_unlock_queues(); 1979} 1980 1981static void 1982mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz) 1983{ 1984 pte_t *pte; 1985 pmap_t pmap; 1986 vm_page_t m; 1987 vm_offset_t addr; 1988 vm_paddr_t pa; 1989 int active, valid; 1990 1991 va = trunc_page(va); 1992 sz = round_page(sz); 1993 1994 vm_page_lock_queues(); 1995 pmap = PCPU_GET(curpmap); 1996 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0; 1997 while (sz > 0) { 1998 PMAP_LOCK(pm); 1999 pte = pte_find(mmu, pm, va); 2000 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0; 2001 if (valid) 2002 pa = PTE_PA(pte); 2003 PMAP_UNLOCK(pm); 2004 if (valid) { 2005 if (!active) { 2006 /* Create a mapping in the active pmap. */ 2007 addr = 0; 2008 m = PHYS_TO_VM_PAGE(pa); 2009 PMAP_LOCK(pmap); 2010 pte_enter(mmu, pmap, m, addr, 2011 PTE_SR | PTE_VALID | PTE_UR); 2012 __syncicache((void *)addr, PAGE_SIZE); 2013 pte_remove(mmu, pmap, addr, PTBL_UNHOLD); 2014 PMAP_UNLOCK(pmap); 2015 } else 2016 __syncicache((void *)va, PAGE_SIZE); 2017 } 2018 va += PAGE_SIZE; 2019 sz -= PAGE_SIZE; 2020 } 2021 vm_page_unlock_queues(); 2022} 2023 2024/* 2025 * Atomically extract and hold the physical page with the given 2026 * pmap and virtual address pair if that mapping permits the given 2027 * protection. 2028 */ 2029static vm_page_t 2030mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, 2031 vm_prot_t prot) 2032{ 2033 pte_t *pte; 2034 vm_page_t m; 2035 uint32_t pte_wbit; 2036 vm_paddr_t pa; 2037 2038 m = NULL; 2039 pa = 0; 2040 PMAP_LOCK(pmap); 2041retry: 2042 pte = pte_find(mmu, pmap, va); 2043 if ((pte != NULL) && PTE_ISVALID(pte)) { 2044 if (pmap == kernel_pmap) 2045 pte_wbit = PTE_SW; 2046 else 2047 pte_wbit = PTE_UW; 2048 2049 if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) { 2050 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa)) 2051 goto retry; 2052 m = PHYS_TO_VM_PAGE(PTE_PA(pte)); 2053 vm_page_hold(m); 2054 } 2055 } 2056 2057 PA_UNLOCK_COND(pa); 2058 PMAP_UNLOCK(pmap); 2059 return (m); 2060} 2061 2062/* 2063 * Initialize a vm_page's machine-dependent fields. 2064 */ 2065static void 2066mmu_booke_page_init(mmu_t mmu, vm_page_t m) 2067{ 2068 2069 TAILQ_INIT(&m->md.pv_list); 2070} 2071 2072/* 2073 * mmu_booke_zero_page_area zeros the specified hardware page by 2074 * mapping it into virtual memory and using bzero to clear 2075 * its contents. 2076 * 2077 * off and size must reside within a single page. 2078 */ 2079static void 2080mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size) 2081{ 2082 vm_offset_t va; 2083 2084 /* XXX KASSERT off and size are within a single page? */ 2085 2086 mtx_lock(&zero_page_mutex); 2087 va = zero_page_va; 2088 2089 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2090 bzero((caddr_t)va + off, size); 2091 mmu_booke_kremove(mmu, va); 2092 2093 mtx_unlock(&zero_page_mutex); 2094} 2095 2096/* 2097 * mmu_booke_zero_page zeros the specified hardware page. 2098 */ 2099static void 2100mmu_booke_zero_page(mmu_t mmu, vm_page_t m) 2101{ 2102 2103 mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE); 2104} 2105 2106/* 2107 * mmu_booke_copy_page copies the specified (machine independent) page by 2108 * mapping the page into virtual memory and using memcopy to copy the page, 2109 * one machine dependent page at a time. 2110 */ 2111static void 2112mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm) 2113{ 2114 vm_offset_t sva, dva; 2115 2116 sva = copy_page_src_va; 2117 dva = copy_page_dst_va; 2118 2119 mtx_lock(©_page_mutex); 2120 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm)); 2121 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm)); 2122 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE); 2123 mmu_booke_kremove(mmu, dva); 2124 mmu_booke_kremove(mmu, sva); 2125 mtx_unlock(©_page_mutex); 2126} 2127 2128/* 2129 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it 2130 * into virtual memory and using bzero to clear its contents. This is intended 2131 * to be called from the vm_pagezero process only and outside of Giant. No 2132 * lock is required. 2133 */ 2134static void 2135mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m) 2136{ 2137 vm_offset_t va; 2138 2139 va = zero_page_idle_va; 2140 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m)); 2141 bzero((caddr_t)va, PAGE_SIZE); 2142 mmu_booke_kremove(mmu, va); 2143} 2144 2145/* 2146 * Return whether or not the specified physical page was modified 2147 * in any of physical maps. 2148 */ 2149static boolean_t 2150mmu_booke_is_modified(mmu_t mmu, vm_page_t m) 2151{ 2152 pte_t *pte; 2153 pv_entry_t pv; 2154 boolean_t rv; 2155 2156 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2157 ("mmu_booke_is_modified: page %p is not managed", m)); 2158 rv = FALSE; 2159 2160 /* 2161 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 2162 * concurrently set while the object is locked. Thus, if PG_WRITEABLE 2163 * is clear, no PTEs can be modified. 2164 */ 2165 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2166 if ((m->oflags & VPO_BUSY) == 0 && 2167 (m->flags & PG_WRITEABLE) == 0) 2168 return (rv); 2169 vm_page_lock_queues(); 2170 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2171 PMAP_LOCK(pv->pv_pmap); 2172 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2173 PTE_ISVALID(pte)) { 2174 if (PTE_ISMODIFIED(pte)) 2175 rv = TRUE; 2176 } 2177 PMAP_UNLOCK(pv->pv_pmap); 2178 if (rv) 2179 break; 2180 } 2181 vm_page_unlock_queues(); 2182 return (rv); 2183} 2184 2185/* 2186 * Return whether or not the specified virtual address is eligible 2187 * for prefault. 2188 */ 2189static boolean_t 2190mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr) 2191{ 2192 2193 return (FALSE); 2194} 2195 2196/* 2197 * Return whether or not the specified physical page was referenced 2198 * in any physical maps. 2199 */ 2200static boolean_t 2201mmu_booke_is_referenced(mmu_t mmu, vm_page_t m) 2202{ 2203 pte_t *pte; 2204 pv_entry_t pv; 2205 boolean_t rv; 2206 2207 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2208 ("mmu_booke_is_referenced: page %p is not managed", m)); 2209 rv = FALSE; 2210 vm_page_lock_queues(); 2211 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2212 PMAP_LOCK(pv->pv_pmap); 2213 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2214 PTE_ISVALID(pte)) { 2215 if (PTE_ISREFERENCED(pte)) 2216 rv = TRUE; 2217 } 2218 PMAP_UNLOCK(pv->pv_pmap); 2219 if (rv) 2220 break; 2221 } 2222 vm_page_unlock_queues(); 2223 return (rv); 2224} 2225 2226/* 2227 * Clear the modify bits on the specified physical page. 2228 */ 2229static void 2230mmu_booke_clear_modify(mmu_t mmu, vm_page_t m) 2231{ 2232 pte_t *pte; 2233 pv_entry_t pv; 2234 2235 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2236 ("mmu_booke_clear_modify: page %p is not managed", m)); 2237 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2238 KASSERT((m->oflags & VPO_BUSY) == 0, 2239 ("mmu_booke_clear_modify: page %p is busy", m)); 2240 2241 /* 2242 * If the page is not PG_WRITEABLE, then no PTEs can be modified. 2243 * If the object containing the page is locked and the page is not 2244 * VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 2245 */ 2246 if ((m->flags & PG_WRITEABLE) == 0) 2247 return; 2248 vm_page_lock_queues(); 2249 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2250 PMAP_LOCK(pv->pv_pmap); 2251 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2252 PTE_ISVALID(pte)) { 2253 mtx_lock_spin(&tlbivax_mutex); 2254 tlb_miss_lock(); 2255 2256 if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) { 2257 tlb0_flush_entry(pv->pv_va); 2258 pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED | 2259 PTE_REFERENCED); 2260 } 2261 2262 tlb_miss_unlock(); 2263 mtx_unlock_spin(&tlbivax_mutex); 2264 } 2265 PMAP_UNLOCK(pv->pv_pmap); 2266 } 2267 vm_page_unlock_queues(); 2268} 2269 2270/* 2271 * Return a count of reference bits for a page, clearing those bits. 2272 * It is not necessary for every reference bit to be cleared, but it 2273 * is necessary that 0 only be returned when there are truly no 2274 * reference bits set. 2275 * 2276 * XXX: The exact number of bits to check and clear is a matter that 2277 * should be tested and standardized at some point in the future for 2278 * optimal aging of shared pages. 2279 */ 2280static int 2281mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m) 2282{ 2283 pte_t *pte; 2284 pv_entry_t pv; 2285 int count; 2286 2287 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2288 ("mmu_booke_ts_referenced: page %p is not managed", m)); 2289 count = 0; 2290 vm_page_lock_queues(); 2291 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2292 PMAP_LOCK(pv->pv_pmap); 2293 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2294 PTE_ISVALID(pte)) { 2295 if (PTE_ISREFERENCED(pte)) { 2296 mtx_lock_spin(&tlbivax_mutex); 2297 tlb_miss_lock(); 2298 2299 tlb0_flush_entry(pv->pv_va); 2300 pte->flags &= ~PTE_REFERENCED; 2301 2302 tlb_miss_unlock(); 2303 mtx_unlock_spin(&tlbivax_mutex); 2304 2305 if (++count > 4) { 2306 PMAP_UNLOCK(pv->pv_pmap); 2307 break; 2308 } 2309 } 2310 } 2311 PMAP_UNLOCK(pv->pv_pmap); 2312 } 2313 vm_page_unlock_queues(); 2314 return (count); 2315} 2316 2317/* 2318 * Clear the reference bit on the specified physical page. 2319 */ 2320static void 2321mmu_booke_clear_reference(mmu_t mmu, vm_page_t m) 2322{ 2323 pte_t *pte; 2324 pv_entry_t pv; 2325 2326 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2327 ("mmu_booke_clear_reference: page %p is not managed", m)); 2328 vm_page_lock_queues(); 2329 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2330 PMAP_LOCK(pv->pv_pmap); 2331 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL && 2332 PTE_ISVALID(pte)) { 2333 if (PTE_ISREFERENCED(pte)) { 2334 mtx_lock_spin(&tlbivax_mutex); 2335 tlb_miss_lock(); 2336 2337 tlb0_flush_entry(pv->pv_va); 2338 pte->flags &= ~PTE_REFERENCED; 2339 2340 tlb_miss_unlock(); 2341 mtx_unlock_spin(&tlbivax_mutex); 2342 } 2343 } 2344 PMAP_UNLOCK(pv->pv_pmap); 2345 } 2346 vm_page_unlock_queues(); 2347} 2348 2349/* 2350 * Change wiring attribute for a map/virtual-address pair. 2351 */ 2352static void 2353mmu_booke_change_wiring(mmu_t mmu, pmap_t pmap, vm_offset_t va, boolean_t wired) 2354{ 2355 pte_t *pte; 2356 2357 PMAP_LOCK(pmap); 2358 if ((pte = pte_find(mmu, pmap, va)) != NULL) { 2359 if (wired) { 2360 if (!PTE_ISWIRED(pte)) { 2361 pte->flags |= PTE_WIRED; 2362 pmap->pm_stats.wired_count++; 2363 } 2364 } else { 2365 if (PTE_ISWIRED(pte)) { 2366 pte->flags &= ~PTE_WIRED; 2367 pmap->pm_stats.wired_count--; 2368 } 2369 } 2370 } 2371 PMAP_UNLOCK(pmap); 2372} 2373 2374/* 2375 * Return true if the pmap's pv is one of the first 16 pvs linked to from this 2376 * page. This count may be changed upwards or downwards in the future; it is 2377 * only necessary that true be returned for a small subset of pmaps for proper 2378 * page aging. 2379 */ 2380static boolean_t 2381mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m) 2382{ 2383 pv_entry_t pv; 2384 int loops; 2385 boolean_t rv; 2386 2387 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2388 ("mmu_booke_page_exists_quick: page %p is not managed", m)); 2389 loops = 0; 2390 rv = FALSE; 2391 vm_page_lock_queues(); 2392 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2393 if (pv->pv_pmap == pmap) { 2394 rv = TRUE; 2395 break; 2396 } 2397 if (++loops >= 16) 2398 break; 2399 } 2400 vm_page_unlock_queues(); 2401 return (rv); 2402} 2403 2404/* 2405 * Return the number of managed mappings to the given physical page that are 2406 * wired. 2407 */ 2408static int 2409mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m) 2410{ 2411 pv_entry_t pv; 2412 pte_t *pte; 2413 int count = 0; 2414 2415 if ((m->flags & PG_FICTITIOUS) != 0) 2416 return (count); 2417 vm_page_lock_queues(); 2418 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) { 2419 PMAP_LOCK(pv->pv_pmap); 2420 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) 2421 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte)) 2422 count++; 2423 PMAP_UNLOCK(pv->pv_pmap); 2424 } 2425 vm_page_unlock_queues(); 2426 return (count); 2427} 2428 2429static int 2430mmu_booke_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2431{ 2432 int i; 2433 vm_offset_t va; 2434 2435 /* 2436 * This currently does not work for entries that 2437 * overlap TLB1 entries. 2438 */ 2439 for (i = 0; i < tlb1_idx; i ++) { 2440 if (tlb1_iomapped(i, pa, size, &va) == 0) 2441 return (0); 2442 } 2443 2444 return (EFAULT); 2445} 2446 2447vm_offset_t 2448mmu_booke_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2449 vm_size_t *sz) 2450{ 2451 vm_paddr_t pa, ppa; 2452 vm_offset_t va; 2453 vm_size_t gran; 2454 2455 /* Raw physical memory dumps don't have a virtual address. */ 2456 if (md->md_vaddr == ~0UL) { 2457 /* We always map a 256MB page at 256M. */ 2458 gran = 256 * 1024 * 1024; 2459 pa = md->md_paddr + ofs; 2460 ppa = pa & ~(gran - 1); 2461 ofs = pa - ppa; 2462 va = gran; 2463 tlb1_set_entry(va, ppa, gran, _TLB_ENTRY_IO); 2464 if (*sz > (gran - ofs)) 2465 *sz = gran - ofs; 2466 return (va + ofs); 2467 } 2468 2469 /* Minidumps are based on virtual memory addresses. */ 2470 va = md->md_vaddr + ofs; 2471 if (va >= kernstart + kernsize) { 2472 gran = PAGE_SIZE - (va & PAGE_MASK); 2473 if (*sz > gran) 2474 *sz = gran; 2475 } 2476 return (va); 2477} 2478 2479void 2480mmu_booke_dumpsys_unmap(mmu_t mmu, struct pmap_md *md, vm_size_t ofs, 2481 vm_offset_t va) 2482{ 2483 2484 /* Raw physical memory dumps don't have a virtual address. */ 2485 if (md->md_vaddr == ~0UL) { 2486 tlb1_idx--; 2487 tlb1[tlb1_idx].mas1 = 0; 2488 tlb1[tlb1_idx].mas2 = 0; 2489 tlb1[tlb1_idx].mas3 = 0; 2490 tlb1_write_entry(tlb1_idx); 2491 return; 2492 } 2493 2494 /* Minidumps are based on virtual memory addresses. */ 2495 /* Nothing to do... */ 2496} 2497 2498struct pmap_md * 2499mmu_booke_scan_md(mmu_t mmu, struct pmap_md *prev) 2500{ 2501 static struct pmap_md md; 2502 pte_t *pte; 2503 vm_offset_t va; 2504 2505 if (dumpsys_minidump) { 2506 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */ 2507 if (prev == NULL) { 2508 /* 1st: kernel .data and .bss. */ 2509 md.md_index = 1; 2510 md.md_vaddr = trunc_page((uintptr_t)_etext); 2511 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr; 2512 return (&md); 2513 } 2514 switch (prev->md_index) { 2515 case 1: 2516 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */ 2517 md.md_index = 2; 2518 md.md_vaddr = data_start; 2519 md.md_size = data_end - data_start; 2520 break; 2521 case 2: 2522 /* 3rd: kernel VM. */ 2523 va = prev->md_vaddr + prev->md_size; 2524 /* Find start of next chunk (from va). */ 2525 while (va < virtual_end) { 2526 /* Don't dump the buffer cache. */ 2527 if (va >= kmi.buffer_sva && 2528 va < kmi.buffer_eva) { 2529 va = kmi.buffer_eva; 2530 continue; 2531 } 2532 pte = pte_find(mmu, kernel_pmap, va); 2533 if (pte != NULL && PTE_ISVALID(pte)) 2534 break; 2535 va += PAGE_SIZE; 2536 } 2537 if (va < virtual_end) { 2538 md.md_vaddr = va; 2539 va += PAGE_SIZE; 2540 /* Find last page in chunk. */ 2541 while (va < virtual_end) { 2542 /* Don't run into the buffer cache. */ 2543 if (va == kmi.buffer_sva) 2544 break; 2545 pte = pte_find(mmu, kernel_pmap, va); 2546 if (pte == NULL || !PTE_ISVALID(pte)) 2547 break; 2548 va += PAGE_SIZE; 2549 } 2550 md.md_size = va - md.md_vaddr; 2551 break; 2552 } 2553 md.md_index = 3; 2554 /* FALLTHROUGH */ 2555 default: 2556 return (NULL); 2557 } 2558 } else { /* minidumps */ 2559 mem_regions(&physmem_regions, &physmem_regions_sz, 2560 &availmem_regions, &availmem_regions_sz); 2561 2562 if (prev == NULL) { 2563 /* first physical chunk. */ 2564 md.md_paddr = physmem_regions[0].mr_start; 2565 md.md_size = physmem_regions[0].mr_size; 2566 md.md_vaddr = ~0UL; 2567 md.md_index = 1; 2568 } else if (md.md_index < physmem_regions_sz) { 2569 md.md_paddr = physmem_regions[md.md_index].mr_start; 2570 md.md_size = physmem_regions[md.md_index].mr_size; 2571 md.md_vaddr = ~0UL; 2572 md.md_index++; 2573 } else { 2574 /* There's no next physical chunk. */ 2575 return (NULL); 2576 } 2577 } 2578 2579 return (&md); 2580} 2581 2582/* 2583 * Map a set of physical memory pages into the kernel virtual address space. 2584 * Return a pointer to where it is mapped. This routine is intended to be used 2585 * for mapping device memory, NOT real memory. 2586 */ 2587static void * 2588mmu_booke_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size) 2589{ 2590 void *res; 2591 uintptr_t va; 2592 vm_size_t sz; 2593 2594 va = (pa >= 0x80000000) ? pa : (0xe2000000 + pa); 2595 res = (void *)va; 2596 2597 do { 2598 sz = 1 << (ilog2(size) & ~1); 2599 if (bootverbose) 2600 printf("Wiring VA=%x to PA=%x (size=%x), " 2601 "using TLB1[%d]\n", va, pa, sz, tlb1_idx); 2602 tlb1_set_entry(va, pa, sz, _TLB_ENTRY_IO); 2603 size -= sz; 2604 pa += sz; 2605 va += sz; 2606 } while (size > 0); 2607 2608 return (res); 2609} 2610 2611/* 2612 * 'Unmap' a range mapped by mmu_booke_mapdev(). 2613 */ 2614static void 2615mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size) 2616{ 2617 vm_offset_t base, offset; 2618 2619 /* 2620 * Unmap only if this is inside kernel virtual space. 2621 */ 2622 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) { 2623 base = trunc_page(va); 2624 offset = va & PAGE_MASK; 2625 size = roundup(offset + size, PAGE_SIZE); 2626 kmem_free(kernel_map, base, size); 2627 } 2628} 2629 2630/* 2631 * mmu_booke_object_init_pt preloads the ptes for a given object into the 2632 * specified pmap. This eliminates the blast of soft faults on process startup 2633 * and immediately after an mmap. 2634 */ 2635static void 2636mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2637 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2638{ 2639 2640 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 2641 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2642 ("mmu_booke_object_init_pt: non-device object")); 2643} 2644 2645/* 2646 * Perform the pmap work for mincore. 2647 */ 2648static int 2649mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr, 2650 vm_paddr_t *locked_pa) 2651{ 2652 2653 TODO; 2654 return (0); 2655} 2656 2657/**************************************************************************/ 2658/* TID handling */ 2659/**************************************************************************/ 2660 2661/* 2662 * Allocate a TID. If necessary, steal one from someone else. 2663 * The new TID is flushed from the TLB before returning. 2664 */ 2665static tlbtid_t 2666tid_alloc(pmap_t pmap) 2667{ 2668 tlbtid_t tid; 2669 int thiscpu; 2670 2671 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap")); 2672 2673 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap); 2674 2675 thiscpu = PCPU_GET(cpuid); 2676 2677 tid = PCPU_GET(tid_next); 2678 if (tid > TID_MAX) 2679 tid = TID_MIN; 2680 PCPU_SET(tid_next, tid + 1); 2681 2682 /* If we are stealing TID then clear the relevant pmap's field */ 2683 if (tidbusy[thiscpu][tid] != NULL) { 2684 2685 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid); 2686 2687 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE; 2688 2689 /* Flush all entries from TLB0 matching this TID. */ 2690 tid_flush(tid); 2691 } 2692 2693 tidbusy[thiscpu][tid] = pmap; 2694 pmap->pm_tid[thiscpu] = tid; 2695 __asm __volatile("msync; isync"); 2696 2697 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid, 2698 PCPU_GET(tid_next)); 2699 2700 return (tid); 2701} 2702 2703/**************************************************************************/ 2704/* TLB0 handling */ 2705/**************************************************************************/ 2706 2707static void 2708tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3, 2709 uint32_t mas7) 2710{ 2711 int as; 2712 char desc[3]; 2713 tlbtid_t tid; 2714 vm_size_t size; 2715 unsigned int tsize; 2716 2717 desc[2] = '\0'; 2718 if (mas1 & MAS1_VALID) 2719 desc[0] = 'V'; 2720 else 2721 desc[0] = ' '; 2722 2723 if (mas1 & MAS1_IPROT) 2724 desc[1] = 'P'; 2725 else 2726 desc[1] = ' '; 2727 2728 as = (mas1 & MAS1_TS_MASK) ? 1 : 0; 2729 tid = MAS1_GETTID(mas1); 2730 2731 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 2732 size = 0; 2733 if (tsize) 2734 size = tsize2size(tsize); 2735 2736 debugf("%3d: (%s) [AS=%d] " 2737 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x " 2738 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n", 2739 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7); 2740} 2741 2742/* Convert TLB0 va and way number to tlb0[] table index. */ 2743static inline unsigned int 2744tlb0_tableidx(vm_offset_t va, unsigned int way) 2745{ 2746 unsigned int idx; 2747 2748 idx = (way * TLB0_ENTRIES_PER_WAY); 2749 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT; 2750 return (idx); 2751} 2752 2753/* 2754 * Invalidate TLB0 entry. 2755 */ 2756static inline void 2757tlb0_flush_entry(vm_offset_t va) 2758{ 2759 2760 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va); 2761 2762 mtx_assert(&tlbivax_mutex, MA_OWNED); 2763 2764 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK)); 2765 __asm __volatile("isync; msync"); 2766 __asm __volatile("tlbsync; msync"); 2767 2768 CTR1(KTR_PMAP, "%s: e", __func__); 2769} 2770 2771/* Print out contents of the MAS registers for each TLB0 entry */ 2772void 2773tlb0_print_tlbentries(void) 2774{ 2775 uint32_t mas0, mas1, mas2, mas3, mas7; 2776 int entryidx, way, idx; 2777 2778 debugf("TLB0 entries:\n"); 2779 for (way = 0; way < TLB0_WAYS; way ++) 2780 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) { 2781 2782 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way); 2783 mtspr(SPR_MAS0, mas0); 2784 __asm __volatile("isync"); 2785 2786 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT; 2787 mtspr(SPR_MAS2, mas2); 2788 2789 __asm __volatile("isync; tlbre"); 2790 2791 mas1 = mfspr(SPR_MAS1); 2792 mas2 = mfspr(SPR_MAS2); 2793 mas3 = mfspr(SPR_MAS3); 2794 mas7 = mfspr(SPR_MAS7); 2795 2796 idx = tlb0_tableidx(mas2, way); 2797 tlb_print_entry(idx, mas1, mas2, mas3, mas7); 2798 } 2799} 2800 2801/**************************************************************************/ 2802/* TLB1 handling */ 2803/**************************************************************************/ 2804 2805/* 2806 * TLB1 mapping notes: 2807 * 2808 * TLB1[0] CCSRBAR 2809 * TLB1[1] Kernel text and data. 2810 * TLB1[2-15] Additional kernel text and data mappings (if required), PCI 2811 * windows, other devices mappings. 2812 */ 2813 2814/* 2815 * Write given entry to TLB1 hardware. 2816 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7). 2817 */ 2818static void 2819tlb1_write_entry(unsigned int idx) 2820{ 2821 uint32_t mas0, mas7; 2822 2823 //debugf("tlb1_write_entry: s\n"); 2824 2825 /* Clear high order RPN bits */ 2826 mas7 = 0; 2827 2828 /* Select entry */ 2829 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx); 2830 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0); 2831 2832 mtspr(SPR_MAS0, mas0); 2833 __asm __volatile("isync"); 2834 mtspr(SPR_MAS1, tlb1[idx].mas1); 2835 __asm __volatile("isync"); 2836 mtspr(SPR_MAS2, tlb1[idx].mas2); 2837 __asm __volatile("isync"); 2838 mtspr(SPR_MAS3, tlb1[idx].mas3); 2839 __asm __volatile("isync"); 2840 mtspr(SPR_MAS7, mas7); 2841 __asm __volatile("isync; tlbwe; isync; msync"); 2842 2843 //debugf("tlb1_write_entry: e\n"); 2844} 2845 2846/* 2847 * Return the largest uint value log such that 2^log <= num. 2848 */ 2849static unsigned int 2850ilog2(unsigned int num) 2851{ 2852 int lz; 2853 2854 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num)); 2855 return (31 - lz); 2856} 2857 2858/* 2859 * Convert TLB TSIZE value to mapped region size. 2860 */ 2861static vm_size_t 2862tsize2size(unsigned int tsize) 2863{ 2864 2865 /* 2866 * size = 4^tsize KB 2867 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10) 2868 */ 2869 2870 return ((1 << (2 * tsize)) * 1024); 2871} 2872 2873/* 2874 * Convert region size (must be power of 4) to TLB TSIZE value. 2875 */ 2876static unsigned int 2877size2tsize(vm_size_t size) 2878{ 2879 2880 return (ilog2(size) / 2 - 5); 2881} 2882 2883/* 2884 * Register permanent kernel mapping in TLB1. 2885 * 2886 * Entries are created starting from index 0 (current free entry is 2887 * kept in tlb1_idx) and are not supposed to be invalidated. 2888 */ 2889static int 2890tlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size, 2891 uint32_t flags) 2892{ 2893 uint32_t ts, tid; 2894 int tsize; 2895 2896 if (tlb1_idx >= TLB1_ENTRIES) { 2897 printf("tlb1_set_entry: TLB1 full!\n"); 2898 return (-1); 2899 } 2900 2901 /* Convert size to TSIZE */ 2902 tsize = size2tsize(size); 2903 2904 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK; 2905 /* XXX TS is hard coded to 0 for now as we only use single address space */ 2906 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK; 2907 2908 /* XXX LOCK tlb1[] */ 2909 2910 tlb1[tlb1_idx].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid; 2911 tlb1[tlb1_idx].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK); 2912 tlb1[tlb1_idx].mas2 = (va & MAS2_EPN_MASK) | flags; 2913 2914 /* Set supervisor RWX permission bits */ 2915 tlb1[tlb1_idx].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX; 2916 2917 tlb1_write_entry(tlb1_idx++); 2918 2919 /* XXX UNLOCK tlb1[] */ 2920 2921 /* 2922 * XXX in general TLB1 updates should be propagated between CPUs, 2923 * since current design assumes to have the same TLB1 set-up on all 2924 * cores. 2925 */ 2926 return (0); 2927} 2928 2929static int 2930tlb1_entry_size_cmp(const void *a, const void *b) 2931{ 2932 const vm_size_t *sza; 2933 const vm_size_t *szb; 2934 2935 sza = a; 2936 szb = b; 2937 if (*sza > *szb) 2938 return (-1); 2939 else if (*sza < *szb) 2940 return (1); 2941 else 2942 return (0); 2943} 2944 2945/* 2946 * Map in contiguous RAM region into the TLB1 using maximum of 2947 * KERNEL_REGION_MAX_TLB_ENTRIES entries. 2948 * 2949 * If necessary round up last entry size and return total size 2950 * used by all allocated entries. 2951 */ 2952vm_size_t 2953tlb1_mapin_region(vm_offset_t va, vm_offset_t pa, vm_size_t size) 2954{ 2955 vm_size_t entry_size[KERNEL_REGION_MAX_TLB_ENTRIES]; 2956 vm_size_t mapped_size, sz, esz; 2957 unsigned int log; 2958 int i; 2959 2960 CTR4(KTR_PMAP, "%s: region size = 0x%08x va = 0x%08x pa = 0x%08x", 2961 __func__, size, va, pa); 2962 2963 mapped_size = 0; 2964 sz = size; 2965 memset(entry_size, 0, sizeof(entry_size)); 2966 2967 /* Calculate entry sizes. */ 2968 for (i = 0; i < KERNEL_REGION_MAX_TLB_ENTRIES && sz > 0; i++) { 2969 2970 /* Largest region that is power of 4 and fits within size */ 2971 log = ilog2(sz) / 2; 2972 esz = 1 << (2 * log); 2973 2974 /* If this is last entry cover remaining size. */ 2975 if (i == KERNEL_REGION_MAX_TLB_ENTRIES - 1) { 2976 while (esz < sz) 2977 esz = esz << 2; 2978 } 2979 2980 entry_size[i] = esz; 2981 mapped_size += esz; 2982 if (esz < sz) 2983 sz -= esz; 2984 else 2985 sz = 0; 2986 } 2987 2988 /* Sort entry sizes, required to get proper entry address alignment. */ 2989 qsort(entry_size, KERNEL_REGION_MAX_TLB_ENTRIES, 2990 sizeof(vm_size_t), tlb1_entry_size_cmp); 2991 2992 /* Load TLB1 entries. */ 2993 for (i = 0; i < KERNEL_REGION_MAX_TLB_ENTRIES; i++) { 2994 esz = entry_size[i]; 2995 if (!esz) 2996 break; 2997 2998 CTR5(KTR_PMAP, "%s: entry %d: sz = 0x%08x (va = 0x%08x " 2999 "pa = 0x%08x)", __func__, tlb1_idx, esz, va, pa); 3000 3001 tlb1_set_entry(va, pa, esz, _TLB_ENTRY_MEM); 3002 3003 va += esz; 3004 pa += esz; 3005 } 3006 3007 CTR3(KTR_PMAP, "%s: mapped size 0x%08x (wasted space 0x%08x)", 3008 __func__, mapped_size, mapped_size - size); 3009 3010 return (mapped_size); 3011} 3012 3013/* 3014 * TLB1 initialization routine, to be called after the very first 3015 * assembler level setup done in locore.S. 3016 */ 3017void 3018tlb1_init(vm_offset_t ccsrbar) 3019{ 3020 uint32_t mas0; 3021 3022 /* TLB1[1] is used to map the kernel. Save that entry. */ 3023 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(1); 3024 mtspr(SPR_MAS0, mas0); 3025 __asm __volatile("isync; tlbre"); 3026 3027 tlb1[1].mas1 = mfspr(SPR_MAS1); 3028 tlb1[1].mas2 = mfspr(SPR_MAS2); 3029 tlb1[1].mas3 = mfspr(SPR_MAS3); 3030 3031 /* Map in CCSRBAR in TLB1[0] */ 3032 tlb1_idx = 0; 3033 tlb1_set_entry(CCSRBAR_VA, ccsrbar, CCSRBAR_SIZE, _TLB_ENTRY_IO); 3034 /* 3035 * Set the next available TLB1 entry index. Note TLB[1] is reserved 3036 * for initial mapping of kernel text+data, which was set early in 3037 * locore, we need to skip this [busy] entry. 3038 */ 3039 tlb1_idx = 2; 3040 3041 /* Setup TLB miss defaults */ 3042 set_mas4_defaults(); 3043} 3044 3045/* 3046 * Setup MAS4 defaults. 3047 * These values are loaded to MAS0-2 on a TLB miss. 3048 */ 3049static void 3050set_mas4_defaults(void) 3051{ 3052 uint32_t mas4; 3053 3054 /* Defaults: TLB0, PID0, TSIZED=4K */ 3055 mas4 = MAS4_TLBSELD0; 3056 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK; 3057#ifdef SMP 3058 mas4 |= MAS4_MD; 3059#endif 3060 mtspr(SPR_MAS4, mas4); 3061 __asm __volatile("isync"); 3062} 3063 3064/* 3065 * Print out contents of the MAS registers for each TLB1 entry 3066 */ 3067void 3068tlb1_print_tlbentries(void) 3069{ 3070 uint32_t mas0, mas1, mas2, mas3, mas7; 3071 int i; 3072 3073 debugf("TLB1 entries:\n"); 3074 for (i = 0; i < TLB1_ENTRIES; i++) { 3075 3076 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i); 3077 mtspr(SPR_MAS0, mas0); 3078 3079 __asm __volatile("isync; tlbre"); 3080 3081 mas1 = mfspr(SPR_MAS1); 3082 mas2 = mfspr(SPR_MAS2); 3083 mas3 = mfspr(SPR_MAS3); 3084 mas7 = mfspr(SPR_MAS7); 3085 3086 tlb_print_entry(i, mas1, mas2, mas3, mas7); 3087 } 3088} 3089 3090/* 3091 * Print out contents of the in-ram tlb1 table. 3092 */ 3093void 3094tlb1_print_entries(void) 3095{ 3096 int i; 3097 3098 debugf("tlb1[] table entries:\n"); 3099 for (i = 0; i < TLB1_ENTRIES; i++) 3100 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0); 3101} 3102 3103/* 3104 * Return 0 if the physical IO range is encompassed by one of the 3105 * the TLB1 entries, otherwise return related error code. 3106 */ 3107static int 3108tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va) 3109{ 3110 uint32_t prot; 3111 vm_paddr_t pa_start; 3112 vm_paddr_t pa_end; 3113 unsigned int entry_tsize; 3114 vm_size_t entry_size; 3115 3116 *va = (vm_offset_t)NULL; 3117 3118 /* Skip invalid entries */ 3119 if (!(tlb1[i].mas1 & MAS1_VALID)) 3120 return (EINVAL); 3121 3122 /* 3123 * The entry must be cache-inhibited, guarded, and r/w 3124 * so it can function as an i/o page 3125 */ 3126 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G); 3127 if (prot != (MAS2_I | MAS2_G)) 3128 return (EPERM); 3129 3130 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW); 3131 if (prot != (MAS3_SR | MAS3_SW)) 3132 return (EPERM); 3133 3134 /* The address should be within the entry range. */ 3135 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; 3136 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize")); 3137 3138 entry_size = tsize2size(entry_tsize); 3139 pa_start = tlb1[i].mas3 & MAS3_RPN; 3140 pa_end = pa_start + entry_size - 1; 3141 3142 if ((pa < pa_start) || ((pa + size) > pa_end)) 3143 return (ERANGE); 3144 3145 /* Return virtual address of this mapping. */ 3146 *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start); 3147 return (0); 3148} 3149