platform_bare.c revision 212453
1145519Sdarrenr/*- 2145510Sdarrenr * Copyright (c) 2008-2009 Semihalf, Rafal Jaworowski 3170268Sdarrenr * All rights reserved. 4170268Sdarrenr * 5170268Sdarrenr * Redistribution and use in source and binary forms, with or without 6170268Sdarrenr * modification, are permitted provided that the following conditions 7170268Sdarrenr * are met: 8145510Sdarrenr * 9145510Sdarrenr * 1. Redistributions of source code must retain the above copyright 10145510Sdarrenr * notice, this list of conditions and the following disclaimer. 11145510Sdarrenr * 2. Redistributions in binary form must reproduce the above copyright 12145510Sdarrenr * notice, this list of conditions and the following disclaimer in the 13145510Sdarrenr * documentation and/or other materials provided with the distribution. 14145510Sdarrenr * 15145510Sdarrenr * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16145510Sdarrenr * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17145510Sdarrenr * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18145510Sdarrenr * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19145510Sdarrenr * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20145510Sdarrenr * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21145510Sdarrenr * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22145510Sdarrenr * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23145510Sdarrenr * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24145510Sdarrenr * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25145510Sdarrenr */ 26145510Sdarrenr 27145510Sdarrenr#include <sys/cdefs.h> 28145510Sdarrenr__FBSDID("$FreeBSD: head/sys/powerpc/booke/platform_bare.c 212453 2010-09-11 04:45:51Z mav $"); 29145510Sdarrenr 30145510Sdarrenr#include <sys/param.h> 31145510Sdarrenr#include <sys/systm.h> 32145510Sdarrenr#include <sys/kernel.h> 33145510Sdarrenr#include <sys/bus.h> 34145510Sdarrenr#include <sys/pcpu.h> 35145510Sdarrenr#include <sys/proc.h> 36145510Sdarrenr#include <sys/smp.h> 37145510Sdarrenr 38145510Sdarrenr#include <machine/bus.h> 39145510Sdarrenr#include <machine/cpu.h> 40145510Sdarrenr#include <machine/hid.h> 41145510Sdarrenr#include <machine/platform.h> 42145510Sdarrenr#include <machine/platformvar.h> 43145510Sdarrenr#include <machine/smp.h> 44145510Sdarrenr#include <machine/spr.h> 45145510Sdarrenr#include <machine/vmparam.h> 46145510Sdarrenr 47145510Sdarrenr#include <dev/fdt/fdt_common.h> 48145510Sdarrenr#include <dev/ofw/ofw_bus.h> 49145510Sdarrenr#include <dev/ofw/ofw_bus_subr.h> 50145510Sdarrenr#include <dev/ofw/openfirm.h> 51145510Sdarrenr 52145510Sdarrenr#include <powerpc/mpc85xx/mpc85xx.h> 53145510Sdarrenr 54145510Sdarrenr#include "platform_if.h" 55145510Sdarrenr 56145510Sdarrenr#ifdef SMP 57145510Sdarrenrextern void *ap_pcpu; 58145510Sdarrenrextern uint8_t __boot_page[]; /* Boot page body */ 59145510Sdarrenrextern uint32_t kernload; /* Kernel physical load address */ 60145510Sdarrenr#endif 61145510Sdarrenr 62161357Sguidostatic int cpu, maxcpu; 63145510Sdarrenr 64145510Sdarrenrstatic int bare_probe(platform_t); 65145510Sdarrenrstatic void bare_mem_regions(platform_t, struct mem_region **phys, int *physsz, 66145510Sdarrenr struct mem_region **avail, int *availsz); 67145510Sdarrenrstatic u_long bare_timebase_freq(platform_t, struct cpuref *cpuref); 68145510Sdarrenrstatic int bare_smp_first_cpu(platform_t, struct cpuref *cpuref); 69145510Sdarrenrstatic int bare_smp_next_cpu(platform_t, struct cpuref *cpuref); 70145510Sdarrenrstatic int bare_smp_get_bsp(platform_t, struct cpuref *cpuref); 71145510Sdarrenrstatic int bare_smp_start_cpu(platform_t, struct pcpu *cpu); 72145510Sdarrenr 73145510Sdarrenrstatic void e500_reset(platform_t); 74145510Sdarrenr 75145510Sdarrenrstatic platform_method_t bare_methods[] = { 76145510Sdarrenr PLATFORMMETHOD(platform_probe, bare_probe), 77145510Sdarrenr PLATFORMMETHOD(platform_mem_regions, bare_mem_regions), 78145510Sdarrenr PLATFORMMETHOD(platform_timebase_freq, bare_timebase_freq), 79145510Sdarrenr 80145510Sdarrenr PLATFORMMETHOD(platform_smp_first_cpu, bare_smp_first_cpu), 81145510Sdarrenr PLATFORMMETHOD(platform_smp_next_cpu, bare_smp_next_cpu), 82145510Sdarrenr PLATFORMMETHOD(platform_smp_get_bsp, bare_smp_get_bsp), 83145510Sdarrenr PLATFORMMETHOD(platform_smp_start_cpu, bare_smp_start_cpu), 84145510Sdarrenr 85145510Sdarrenr PLATFORMMETHOD(platform_reset, e500_reset), 86145510Sdarrenr 87145510Sdarrenr { 0, 0 } 88145510Sdarrenr}; 89145510Sdarrenr 90145510Sdarrenrstatic platform_def_t bare_platform = { 91145510Sdarrenr "bare metal", 92145510Sdarrenr bare_methods, 93145510Sdarrenr 0 94145510Sdarrenr}; 95145510Sdarrenr 96145510SdarrenrPLATFORM_DEF(bare_platform); 97145510Sdarrenr 98145510Sdarrenrstatic int 99145510Sdarrenrbare_probe(platform_t plat) 100145510Sdarrenr{ 101145510Sdarrenr uint32_t ver, sr; 102145510Sdarrenr int i, law_max, tgt; 103145510Sdarrenr 104145510Sdarrenr ver = SVR_VER(mfspr(SPR_SVR)); 105145510Sdarrenr if (ver == SVR_MPC8572E || ver == SVR_MPC8572) 106145510Sdarrenr maxcpu = 2; 107145510Sdarrenr else 108145510Sdarrenr maxcpu = 1; 109145510Sdarrenr 110145510Sdarrenr /* 111145510Sdarrenr * Clear local access windows. Skip DRAM entries, so we don't shoot 112145510Sdarrenr * ourselves in the foot. 113145510Sdarrenr */ 114145510Sdarrenr law_max = law_getmax(); 115145510Sdarrenr for (i = 0; i < law_max; i++) { 116145510Sdarrenr sr = ccsr_read4(OCP85XX_LAWSR(i)); 117145510Sdarrenr if ((sr & 0x80000000) == 0) 118145510Sdarrenr continue; 119145510Sdarrenr tgt = (sr & 0x01f00000) >> 20; 120145510Sdarrenr if (tgt == OCP85XX_TGTIF_RAM1 || tgt == OCP85XX_TGTIF_RAM2 || 121145510Sdarrenr tgt == OCP85XX_TGTIF_RAM_INTL) 122145510Sdarrenr continue; 123145510Sdarrenr 124145510Sdarrenr ccsr_write4(OCP85XX_LAWSR(i), sr & 0x7fffffff); 125170268Sdarrenr } 126145510Sdarrenr 127145510Sdarrenr return (BUS_PROBE_GENERIC); 128145510Sdarrenr} 129145510Sdarrenr 130145510Sdarrenr#define MEM_REGIONS 8 131145510Sdarrenrstatic struct mem_region avail_regions[MEM_REGIONS]; 132145510Sdarrenr 133145510Sdarrenrvoid 134145510Sdarrenrbare_mem_regions(platform_t plat, struct mem_region **phys, int *physsz, 135145510Sdarrenr struct mem_region **avail, int *availsz) 136145510Sdarrenr{ 137145510Sdarrenr uint32_t memsize; 138145510Sdarrenr int i, rv; 139145510Sdarrenr 140145510Sdarrenr rv = fdt_get_mem_regions(avail_regions, availsz, &memsize); 141145510Sdarrenr 142145510Sdarrenr if (rv != 0) 143145510Sdarrenr return; 144145510Sdarrenr 145145510Sdarrenr for (i = 0; i < *availsz; i++) { 146145510Sdarrenr if (avail_regions[i].mr_start < 1048576) { 147145510Sdarrenr avail_regions[i].mr_size = 148145510Sdarrenr avail_regions[i].mr_size - 149145510Sdarrenr (1048576 - avail_regions[i].mr_start); 150145510Sdarrenr avail_regions[i].mr_start = 1048576; 151145510Sdarrenr } 152145510Sdarrenr } 153145510Sdarrenr *avail = avail_regions; 154145510Sdarrenr 155145510Sdarrenr /* On the bare metal platform phys == avail memory */ 156145510Sdarrenr *physsz = *availsz; 157145510Sdarrenr *phys = *avail; 158145510Sdarrenr} 159145510Sdarrenr 160145510Sdarrenrstatic u_long 161145510Sdarrenrbare_timebase_freq(platform_t plat, struct cpuref *cpuref) 162145510Sdarrenr{ 163145510Sdarrenr u_long ticks = -1; 164145510Sdarrenr phandle_t cpus, child; 165145510Sdarrenr pcell_t freq; 166145510Sdarrenr 167145510Sdarrenr if ((cpus = OF_finddevice("/cpus")) == 0) 168145510Sdarrenr goto out; 169145510Sdarrenr 170145510Sdarrenr if ((child = OF_child(cpus)) == 0) 171145510Sdarrenr goto out; 172145510Sdarrenr 173145510Sdarrenr if (OF_getprop(child, "bus-frequency", (void *)&freq, 174145510Sdarrenr sizeof(freq)) <= 0) 175145510Sdarrenr goto out; 176145510Sdarrenr /* 177145510Sdarrenr * Time Base and Decrementer are updated every 8 CCB bus clocks. 178145510Sdarrenr * HID0[SEL_TBCLK] = 0 179145510Sdarrenr */ 180145510Sdarrenr ticks = freq / 8; 181145510Sdarrenrout: 182161357Sguido if (ticks <= 0) 183161357Sguido panic("Unable to determine timebase frequency!"); 184161357Sguido 185145510Sdarrenr return (ticks); 186145510Sdarrenr} 187145510Sdarrenr 188145510Sdarrenrstatic int 189145510Sdarrenrbare_smp_first_cpu(platform_t plat, struct cpuref *cpuref) 190145510Sdarrenr{ 191145510Sdarrenr 192145510Sdarrenr cpu = 0; 193145510Sdarrenr cpuref->cr_cpuid = cpu; 194145510Sdarrenr cpuref->cr_hwref = cpuref->cr_cpuid; 195145510Sdarrenr if (bootverbose) 196145510Sdarrenr printf("powerpc_smp_first_cpu: cpuid %d\n", cpuref->cr_cpuid); 197145510Sdarrenr cpu++; 198145510Sdarrenr 199161357Sguido return (0); 200161357Sguido} 201161357Sguido 202145510Sdarrenrstatic int 203145510Sdarrenrbare_smp_next_cpu(platform_t plat, struct cpuref *cpuref) 204145510Sdarrenr{ 205145510Sdarrenr 206145510Sdarrenr if (cpu >= maxcpu) 207145510Sdarrenr return (ENOENT); 208145510Sdarrenr 209145510Sdarrenr cpuref->cr_cpuid = cpu++; 210145510Sdarrenr cpuref->cr_hwref = cpuref->cr_cpuid; 211145510Sdarrenr if (bootverbose) 212145510Sdarrenr printf("powerpc_smp_next_cpu: cpuid %d\n", cpuref->cr_cpuid); 213145510Sdarrenr 214145510Sdarrenr return (0); 215145510Sdarrenr} 216145510Sdarrenr 217145510Sdarrenrstatic int 218145510Sdarrenrbare_smp_get_bsp(platform_t plat, struct cpuref *cpuref) 219145510Sdarrenr{ 220145510Sdarrenr 221145510Sdarrenr cpuref->cr_cpuid = mfspr(SPR_PIR); 222145510Sdarrenr cpuref->cr_hwref = cpuref->cr_cpuid; 223145510Sdarrenr 224145510Sdarrenr return (0); 225145510Sdarrenr} 226145510Sdarrenr 227145510Sdarrenrstatic int 228145510Sdarrenrbare_smp_start_cpu(platform_t plat, struct pcpu *pc) 229145510Sdarrenr{ 230145510Sdarrenr#ifdef SMP 231145510Sdarrenr uint32_t bptr, eebpcr; 232145510Sdarrenr int timeout; 233145510Sdarrenr 234145510Sdarrenr eebpcr = ccsr_read4(OCP85XX_EEBPCR); 235145510Sdarrenr if ((eebpcr & (pc->pc_cpumask << 24)) != 0) { 236145510Sdarrenr printf("%s: CPU=%d already out of hold-off state!\n", 237145510Sdarrenr __func__, pc->pc_cpuid); 238145510Sdarrenr return (ENXIO); 239145510Sdarrenr } 240161357Sguido 241145510Sdarrenr ap_pcpu = pc; 242145510Sdarrenr __asm __volatile("msync; isync"); 243145510Sdarrenr 244145510Sdarrenr /* 245145510Sdarrenr * Set BPTR to the physical address of the boot page 246145510Sdarrenr */ 247145510Sdarrenr bptr = ((uint32_t)__boot_page - KERNBASE) + kernload; 248145510Sdarrenr ccsr_write4(OCP85XX_BPTR, (bptr >> 12) | 0x80000000); 249145510Sdarrenr 250161357Sguido /* 251161357Sguido * Release AP from hold-off state 252161357Sguido */ 253145510Sdarrenr eebpcr |= (pc->pc_cpumask << 24); 254145510Sdarrenr ccsr_write4(OCP85XX_EEBPCR, eebpcr); 255145510Sdarrenr __asm __volatile("isync; msync"); 256145510Sdarrenr 257145510Sdarrenr timeout = 500; 258145510Sdarrenr while (!pc->pc_awake && timeout--) 259145510Sdarrenr DELAY(1000); /* wait 1ms */ 260145510Sdarrenr 261145510Sdarrenr return ((pc->pc_awake) ? 0 : EBUSY); 262145510Sdarrenr#else 263145510Sdarrenr /* No SMP support */ 264145510Sdarrenr return (ENXIO); 265145510Sdarrenr#endif 266145510Sdarrenr} 267161357Sguido 268161357Sguidostatic void 269161357Sguidoe500_reset(platform_t plat) 270161357Sguido{ 271161357Sguido uint32_t ver = SVR_VER(mfspr(SPR_SVR)); 272161357Sguido 273161357Sguido if (ver == SVR_MPC8572E || ver == SVR_MPC8572 || 274161357Sguido ver == SVR_MPC8548E || ver == SVR_MPC8548) 275161357Sguido /* Systems with dedicated reset register */ 276161357Sguido ccsr_write4(OCP85XX_RSTCR, 2); 277145510Sdarrenr else { 278145510Sdarrenr /* Clear DBCR0, disables debug interrupts and events. */ 279161357Sguido mtspr(SPR_DBCR0, 0); 280145510Sdarrenr __asm __volatile("isync"); 281145510Sdarrenr 282145510Sdarrenr /* Enable Debug Interrupts in MSR. */ 283145510Sdarrenr mtmsr(mfmsr() | PSL_DE); 284145510Sdarrenr 285145510Sdarrenr /* Enable debug interrupts and issue reset. */ 286145510Sdarrenr mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | 287145510Sdarrenr DBCR0_RST_SYSTEM); 288145510Sdarrenr } 289161357Sguido 290145510Sdarrenr printf("Reset failed...\n"); 291145510Sdarrenr while (1); 292145510Sdarrenr} 293145510Sdarrenr 294145510Sdarrenr