1178628Smarcel/*- 2178628Smarcel * Copyright (c) 2008 Marcel Moolenaar 3178628Smarcel * All rights reserved. 4178628Smarcel * 5178628Smarcel * Redistribution and use in source and binary forms, with or without 6178628Smarcel * modification, are permitted provided that the following conditions 7178628Smarcel * are met: 8178628Smarcel * 9178628Smarcel * 1. Redistributions of source code must retain the above copyright 10178628Smarcel * notice, this list of conditions and the following disclaimer. 11178628Smarcel * 2. Redistributions in binary form must reproduce the above copyright 12178628Smarcel * notice, this list of conditions and the following disclaimer in the 13178628Smarcel * documentation and/or other materials provided with the distribution. 14178628Smarcel * 15178628Smarcel * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16178628Smarcel * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17178628Smarcel * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18178628Smarcel * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19178628Smarcel * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20178628Smarcel * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21178628Smarcel * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22178628Smarcel * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23178628Smarcel * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24178628Smarcel * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25178628Smarcel */ 26178628Smarcel 27178628Smarcel#include <sys/cdefs.h> 28178628Smarcel__FBSDID("$FreeBSD$"); 29178628Smarcel 30178628Smarcel#include <sys/param.h> 31178628Smarcel#include <sys/systm.h> 32178628Smarcel#include <sys/kernel.h> 33178628Smarcel#include <sys/bus.h> 34178628Smarcel#include <sys/pcpu.h> 35178628Smarcel#include <sys/proc.h> 36178628Smarcel#include <sys/smp.h> 37178628Smarcel 38178628Smarcel#include <machine/bus.h> 39178628Smarcel#include <machine/cpu.h> 40178628Smarcel#include <machine/hid.h> 41178628Smarcel#include <machine/intr_machdep.h> 42178628Smarcel#include <machine/pcb.h> 43178628Smarcel#include <machine/psl.h> 44178628Smarcel#include <machine/smp.h> 45178628Smarcel#include <machine/spr.h> 46178628Smarcel#include <machine/trap_aim.h> 47178628Smarcel 48178628Smarcel#include <dev/ofw/openfirm.h> 49178628Smarcel#include <machine/ofw_machdep.h> 50178628Smarcel 51178628Smarcelvoid *ap_pcpu; 52178628Smarcel 53198427Snwhitehornstatic register_t bsp_state[8] __aligned(8); 54198378Snwhitehorn 55198378Snwhitehornstatic void cpudep_save_config(void *dummy); 56198378SnwhitehornSYSINIT(cpu_save_config, SI_SUB_CPU, SI_ORDER_ANY, cpudep_save_config, NULL); 57198378Snwhitehorn 58209975Snwhitehornvoid 59209975Snwhitehorncpudep_ap_early_bootstrap(void) 60209975Snwhitehorn{ 61209975Snwhitehorn register_t reg; 62209975Snwhitehorn 63209975Snwhitehorn __asm __volatile("mtsprg 0, %0" :: "r"(ap_pcpu)); 64209975Snwhitehorn powerpc_sync(); 65209975Snwhitehorn 66209975Snwhitehorn switch (mfpvr() >> 16) { 67209975Snwhitehorn case IBM970: 68209975Snwhitehorn case IBM970FX: 69209975Snwhitehorn case IBM970MP: 70209975Snwhitehorn /* Restore HID4 and HID5, which are necessary for the MMU */ 71209975Snwhitehorn 72209975Snwhitehorn __asm __volatile("ld %0, 16(%2); sync; isync; \ 73209975Snwhitehorn mtspr %1, %0; sync; isync;" 74209975Snwhitehorn : "=r"(reg) : "K"(SPR_HID4), "r"(bsp_state)); 75209975Snwhitehorn __asm __volatile("ld %0, 24(%2); sync; isync; \ 76209975Snwhitehorn mtspr %1, %0; sync; isync;" 77209975Snwhitehorn : "=r"(reg) : "K"(SPR_HID5), "r"(bsp_state)); 78209975Snwhitehorn powerpc_sync(); 79209975Snwhitehorn break; 80209975Snwhitehorn } 81209975Snwhitehorn} 82209975Snwhitehorn 83198378Snwhitehornuintptr_t 84198378Snwhitehorncpudep_ap_bootstrap(void) 85198378Snwhitehorn{ 86198378Snwhitehorn register_t msr, sp; 87198378Snwhitehorn 88198378Snwhitehorn msr = PSL_KERNSET & ~PSL_EE; 89198378Snwhitehorn mtmsr(msr); 90198378Snwhitehorn 91223485Snwhitehorn curthread_reg = pcpup->pc_curthread = pcpup->pc_idlethread; 92198378Snwhitehorn pcpup->pc_curpcb = pcpup->pc_curthread->td_pcb; 93198378Snwhitehorn sp = pcpup->pc_curpcb->pcb_sp; 94198378Snwhitehorn 95198378Snwhitehorn return (sp); 96198378Snwhitehorn} 97198378Snwhitehorn 98183090Smarcelstatic register_t 99209114Snwhitehornmpc74xx_l2_enable(register_t l2cr_config) 100183090Smarcel{ 101209114Snwhitehorn register_t ccr, bit; 102209114Snwhitehorn uint16_t vers; 103183090Smarcel 104209114Snwhitehorn vers = mfpvr() >> 16; 105209114Snwhitehorn switch (vers) { 106209114Snwhitehorn case MPC7400: 107209114Snwhitehorn case MPC7410: 108209114Snwhitehorn bit = L2CR_L2IP; 109209114Snwhitehorn break; 110209114Snwhitehorn default: 111209114Snwhitehorn bit = L2CR_L2I; 112209114Snwhitehorn break; 113209114Snwhitehorn } 114209114Snwhitehorn 115183090Smarcel ccr = mfspr(SPR_L2CR); 116183090Smarcel if (ccr & L2CR_L2E) 117183090Smarcel return (ccr); 118183090Smarcel 119183090Smarcel /* Configure L2 cache. */ 120183090Smarcel ccr = l2cr_config & ~L2CR_L2E; 121183090Smarcel mtspr(SPR_L2CR, ccr | L2CR_L2I); 122183090Smarcel do { 123183090Smarcel ccr = mfspr(SPR_L2CR); 124209114Snwhitehorn } while (ccr & bit); 125183090Smarcel powerpc_sync(); 126183090Smarcel mtspr(SPR_L2CR, l2cr_config); 127183090Smarcel powerpc_sync(); 128183090Smarcel 129183090Smarcel return (l2cr_config); 130183090Smarcel} 131183090Smarcel 132183090Smarcelstatic register_t 133198378Snwhitehornmpc745x_l3_enable(register_t l3cr_config) 134183090Smarcel{ 135183090Smarcel register_t ccr; 136183090Smarcel 137183090Smarcel ccr = mfspr(SPR_L3CR); 138183090Smarcel if (ccr & L3CR_L3E) 139183090Smarcel return (ccr); 140183090Smarcel 141183090Smarcel /* Configure L3 cache. */ 142183090Smarcel ccr = l3cr_config & ~(L3CR_L3E | L3CR_L3I | L3CR_L3PE | L3CR_L3CLKEN); 143183090Smarcel mtspr(SPR_L3CR, ccr); 144183090Smarcel ccr |= 0x4000000; /* Magic, but documented. */ 145183090Smarcel mtspr(SPR_L3CR, ccr); 146183090Smarcel ccr |= L3CR_L3CLKEN; 147183090Smarcel mtspr(SPR_L3CR, ccr); 148183090Smarcel mtspr(SPR_L3CR, ccr | L3CR_L3I); 149183090Smarcel while (mfspr(SPR_L3CR) & L3CR_L3I) 150183090Smarcel ; 151183090Smarcel mtspr(SPR_L3CR, ccr & ~L3CR_L3CLKEN); 152183090Smarcel powerpc_sync(); 153183090Smarcel DELAY(100); 154183090Smarcel mtspr(SPR_L3CR, ccr); 155183090Smarcel powerpc_sync(); 156183090Smarcel DELAY(100); 157183090Smarcel ccr |= L3CR_L3E; 158183090Smarcel mtspr(SPR_L3CR, ccr); 159183090Smarcel powerpc_sync(); 160183090Smarcel 161183090Smarcel return(ccr); 162183090Smarcel} 163183090Smarcel 164183090Smarcelstatic register_t 165209114Snwhitehornmpc74xx_l1d_enable(void) 166183090Smarcel{ 167183090Smarcel register_t hid; 168183090Smarcel 169183090Smarcel hid = mfspr(SPR_HID0); 170183090Smarcel if (hid & HID0_DCE) 171183090Smarcel return (hid); 172183090Smarcel 173183090Smarcel /* Enable L1 D-cache */ 174183090Smarcel hid |= HID0_DCE; 175183090Smarcel powerpc_sync(); 176183090Smarcel mtspr(SPR_HID0, hid | HID0_DCFI); 177183090Smarcel powerpc_sync(); 178183090Smarcel 179183090Smarcel return (hid); 180183090Smarcel} 181183090Smarcel 182183090Smarcelstatic register_t 183209114Snwhitehornmpc74xx_l1i_enable(void) 184183090Smarcel{ 185183090Smarcel register_t hid; 186183090Smarcel 187183090Smarcel hid = mfspr(SPR_HID0); 188183090Smarcel if (hid & HID0_ICE) 189183090Smarcel return (hid); 190183090Smarcel 191183090Smarcel /* Enable L1 I-cache */ 192183090Smarcel hid |= HID0_ICE; 193183090Smarcel isync(); 194183090Smarcel mtspr(SPR_HID0, hid | HID0_ICFI); 195183090Smarcel isync(); 196183090Smarcel 197183090Smarcel return (hid); 198183090Smarcel} 199183090Smarcel 200198378Snwhitehornstatic void 201198378Snwhitehorncpudep_save_config(void *dummy) 202178628Smarcel{ 203198378Snwhitehorn uint16_t vers; 204178628Smarcel 205198378Snwhitehorn vers = mfpvr() >> 16; 206183090Smarcel 207198378Snwhitehorn switch(vers) { 208198378Snwhitehorn case IBM970: 209198378Snwhitehorn case IBM970FX: 210198378Snwhitehorn case IBM970MP: 211209975Snwhitehorn #ifdef __powerpc64__ 212209975Snwhitehorn bsp_state[0] = mfspr(SPR_HID0); 213209975Snwhitehorn bsp_state[1] = mfspr(SPR_HID1); 214209975Snwhitehorn bsp_state[2] = mfspr(SPR_HID4); 215209975Snwhitehorn bsp_state[3] = mfspr(SPR_HID5); 216209975Snwhitehorn #else 217198378Snwhitehorn __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32" 218198378Snwhitehorn : "=r" (bsp_state[0]),"=r" (bsp_state[1]) : "K" (SPR_HID0)); 219198378Snwhitehorn __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32" 220198378Snwhitehorn : "=r" (bsp_state[2]),"=r" (bsp_state[3]) : "K" (SPR_HID1)); 221198378Snwhitehorn __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32" 222198378Snwhitehorn : "=r" (bsp_state[4]),"=r" (bsp_state[5]) : "K" (SPR_HID4)); 223198378Snwhitehorn __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32" 224198378Snwhitehorn : "=r" (bsp_state[6]),"=r" (bsp_state[7]) : "K" (SPR_HID5)); 225209975Snwhitehorn #endif 226178628Smarcel 227198427Snwhitehorn powerpc_sync(); 228198427Snwhitehorn 229198378Snwhitehorn break; 230215182Snwhitehorn case IBMCELLBE: 231215197Snwhitehorn #ifdef NOTYET /* Causes problems if in instruction stream on 970 */ 232215182Snwhitehorn if (mfmsr() & PSL_HV) { 233215182Snwhitehorn bsp_state[0] = mfspr(SPR_HID0); 234215182Snwhitehorn bsp_state[1] = mfspr(SPR_HID1); 235215182Snwhitehorn bsp_state[2] = mfspr(SPR_HID4); 236215182Snwhitehorn bsp_state[3] = mfspr(SPR_HID6); 237215182Snwhitehorn 238215182Snwhitehorn bsp_state[4] = mfspr(SPR_CELL_TSCR); 239215182Snwhitehorn } 240215197Snwhitehorn #endif 241215182Snwhitehorn 242215182Snwhitehorn bsp_state[5] = mfspr(SPR_CELL_TSRL); 243215182Snwhitehorn 244215182Snwhitehorn break; 245198378Snwhitehorn case MPC7450: 246198378Snwhitehorn case MPC7455: 247198378Snwhitehorn case MPC7457: 248198378Snwhitehorn /* Only MPC745x CPUs have an L3 cache. */ 249198378Snwhitehorn bsp_state[3] = mfspr(SPR_L3CR); 250178628Smarcel 251198378Snwhitehorn /* Fallthrough */ 252198378Snwhitehorn case MPC7400: 253198378Snwhitehorn case MPC7410: 254198378Snwhitehorn case MPC7447A: 255198378Snwhitehorn case MPC7448: 256198378Snwhitehorn bsp_state[2] = mfspr(SPR_L2CR); 257198378Snwhitehorn bsp_state[1] = mfspr(SPR_HID1); 258198378Snwhitehorn bsp_state[0] = mfspr(SPR_HID0); 259198378Snwhitehorn break; 260198378Snwhitehorn } 261198378Snwhitehorn} 262178628Smarcel 263198378Snwhitehornvoid 264198378Snwhitehorncpudep_ap_setup() 265198378Snwhitehorn{ 266198378Snwhitehorn register_t reg; 267198378Snwhitehorn uint16_t vers; 268183090Smarcel 269198378Snwhitehorn vers = mfpvr() >> 16; 270178628Smarcel 271198378Snwhitehorn switch(vers) { 272198378Snwhitehorn case IBM970: 273198378Snwhitehorn case IBM970FX: 274198378Snwhitehorn case IBM970MP: 275198378Snwhitehorn /* Set HIOR to 0 */ 276198378Snwhitehorn __asm __volatile("mtspr 311,%0" :: "r"(0)); 277198378Snwhitehorn powerpc_sync(); 278178628Smarcel 279198378Snwhitehorn /* 280198378Snwhitehorn * The 970 has strange rules about how to update HID registers. 281198378Snwhitehorn * See Table 2-3, 970MP manual 282198378Snwhitehorn */ 283198378Snwhitehorn 284198427Snwhitehorn __asm __volatile("mtasr %0; sync" :: "r"(0)); 285198378Snwhitehorn __asm __volatile(" \ 286198378Snwhitehorn ld %0,0(%2); \ 287198427Snwhitehorn sync; isync; \ 288198378Snwhitehorn mtspr %1, %0; \ 289198378Snwhitehorn mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \ 290198427Snwhitehorn mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \ 291198427Snwhitehorn sync; isync" 292198378Snwhitehorn : "=r"(reg) : "K"(SPR_HID0), "r"(bsp_state)); 293198427Snwhitehorn __asm __volatile("ld %0, 8(%2); sync; isync; \ 294198427Snwhitehorn mtspr %1, %0; mtspr %1, %0; sync; isync" 295198427Snwhitehorn : "=r"(reg) : "K"(SPR_HID1), "r"(bsp_state)); 296198427Snwhitehorn __asm __volatile("ld %0, 16(%2); sync; isync; \ 297198427Snwhitehorn mtspr %1, %0; sync; isync;" 298198378Snwhitehorn : "=r"(reg) : "K"(SPR_HID4), "r"(bsp_state)); 299198427Snwhitehorn __asm __volatile("ld %0, 24(%2); sync; isync; \ 300198427Snwhitehorn mtspr %1, %0; sync; isync;" 301198378Snwhitehorn : "=r"(reg) : "K"(SPR_HID5), "r"(bsp_state)); 302198378Snwhitehorn 303198378Snwhitehorn powerpc_sync(); 304198378Snwhitehorn break; 305215182Snwhitehorn case IBMCELLBE: 306215197Snwhitehorn #ifdef NOTYET /* Causes problems if in instruction stream on 970 */ 307215182Snwhitehorn if (mfmsr() & PSL_HV) { 308215182Snwhitehorn mtspr(SPR_HID0, bsp_state[0]); 309215182Snwhitehorn mtspr(SPR_HID1, bsp_state[1]); 310215182Snwhitehorn mtspr(SPR_HID4, bsp_state[2]); 311215182Snwhitehorn mtspr(SPR_HID6, bsp_state[3]); 312215182Snwhitehorn 313215182Snwhitehorn mtspr(SPR_CELL_TSCR, bsp_state[4]); 314215182Snwhitehorn } 315215197Snwhitehorn #endif 316215182Snwhitehorn 317215182Snwhitehorn mtspr(SPR_CELL_TSRL, bsp_state[5]); 318215182Snwhitehorn 319215182Snwhitehorn break; 320198378Snwhitehorn case MPC7450: 321198378Snwhitehorn case MPC7455: 322198378Snwhitehorn case MPC7457: 323198378Snwhitehorn /* Only MPC745x CPUs have an L3 cache. */ 324198378Snwhitehorn reg = mpc745x_l3_enable(bsp_state[3]); 325198378Snwhitehorn 326198378Snwhitehorn /* Fallthrough */ 327198378Snwhitehorn case MPC7400: 328198378Snwhitehorn case MPC7410: 329198378Snwhitehorn case MPC7447A: 330198378Snwhitehorn case MPC7448: 331198378Snwhitehorn /* XXX: Program the CPU ID into PIR */ 332198378Snwhitehorn __asm __volatile("mtspr 1023,%0" :: "r"(PCPU_GET(cpuid))); 333198378Snwhitehorn 334198378Snwhitehorn powerpc_sync(); 335198378Snwhitehorn isync(); 336198378Snwhitehorn 337198378Snwhitehorn mtspr(SPR_HID0, bsp_state[0]); isync(); 338198378Snwhitehorn mtspr(SPR_HID1, bsp_state[1]); isync(); 339198378Snwhitehorn 340209114Snwhitehorn reg = mpc74xx_l2_enable(bsp_state[2]); 341209114Snwhitehorn reg = mpc74xx_l1d_enable(); 342209114Snwhitehorn reg = mpc74xx_l1i_enable(); 343198378Snwhitehorn 344198378Snwhitehorn break; 345198378Snwhitehorn default: 346222618Snwhitehorn#ifdef __powerpc64__ 347222618Snwhitehorn if (!(mfmsr() & PSL_HV)) /* Rely on HV to have set things up */ 348222618Snwhitehorn break; 349222618Snwhitehorn#endif 350198378Snwhitehorn printf("WARNING: Unknown CPU type. Cache performace may be " 351198378Snwhitehorn "suboptimal.\n"); 352198378Snwhitehorn break; 353198378Snwhitehorn } 354178628Smarcel} 355178628Smarcel 356