if_rl.c revision 94883
140516Swpaul/* 240516Swpaul * Copyright (c) 1997, 1998 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_rl.c 94883 2002-04-16 22:03:14Z luigi $ 3340516Swpaul */ 3440516Swpaul 3540516Swpaul/* 3640516Swpaul * RealTek 8129/8139 PCI NIC driver 3740516Swpaul * 3840516Swpaul * Supports several extremely cheap PCI 10/100 adapters based on 3940516Swpaul * the RealTek chipset. Datasheets can be obtained from 4040516Swpaul * www.realtek.com.tw. 4140516Swpaul * 4240516Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4340516Swpaul * Electrical Engineering Department 4440516Swpaul * Columbia University, New York City 4540516Swpaul */ 4640516Swpaul 4740516Swpaul/* 4840516Swpaul * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 4940516Swpaul * probably the worst PCI ethernet controller ever made, with the possible 5040516Swpaul * exception of the FEAST chip made by SMC. The 8139 supports bus-master 5140516Swpaul * DMA, but it has a terrible interface that nullifies any performance 5240516Swpaul * gains that bus-master DMA usually offers. 5340516Swpaul * 5440516Swpaul * For transmission, the chip offers a series of four TX descriptor 5540516Swpaul * registers. Each transmit frame must be in a contiguous buffer, aligned 5641569Swpaul * on a longword (32-bit) boundary. This means we almost always have to 5740516Swpaul * do mbuf copies in order to transmit a frame, except in the unlikely 5840516Swpaul * case where a) the packet fits into a single mbuf, and b) the packet 5940516Swpaul * is 32-bit aligned within the mbuf's data area. The presence of only 6040516Swpaul * four descriptor registers means that we can never have more than four 6140516Swpaul * packets queued for transmission at any one time. 6240516Swpaul * 6340516Swpaul * Reception is not much better. The driver has to allocate a single large 6440516Swpaul * buffer area (up to 64K in size) into which the chip will DMA received 6540516Swpaul * frames. Because we don't know where within this region received packets 6640516Swpaul * will begin or end, we have no choice but to copy data from the buffer 6740516Swpaul * area into mbufs in order to pass the packets up to the higher protocol 6840516Swpaul * levels. 6940516Swpaul * 7040516Swpaul * It's impossible given this rotten design to really achieve decent 7140516Swpaul * performance at 100Mbps, unless you happen to have a 400Mhz PII or 7240516Swpaul * some equally overmuscled CPU to drive it. 7340516Swpaul * 7440516Swpaul * On the bright side, the 8139 does have a built-in PHY, although 7540516Swpaul * rather than using an MDIO serial interface like most other NICs, the 7640516Swpaul * PHY registers are directly accessible through the 8139's register 7740516Swpaul * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 7840516Swpaul * filter. 7940516Swpaul * 8040516Swpaul * The 8129 chip is an older version of the 8139 that uses an external PHY 8140516Swpaul * chip. The 8129 has a serial MDIO interface for accessing the MII where 8240516Swpaul * the 8139 lets you directly access the on-board PHY registers. We need 8340516Swpaul * to select which interface to use depending on the chip type. 8440516Swpaul */ 8540516Swpaul 8640516Swpaul#include <sys/param.h> 8740516Swpaul#include <sys/systm.h> 8840516Swpaul#include <sys/sockio.h> 8940516Swpaul#include <sys/mbuf.h> 9040516Swpaul#include <sys/malloc.h> 9140516Swpaul#include <sys/kernel.h> 9240516Swpaul#include <sys/socket.h> 9340516Swpaul 9440516Swpaul#include <net/if.h> 9540516Swpaul#include <net/if_arp.h> 9640516Swpaul#include <net/ethernet.h> 9740516Swpaul#include <net/if_dl.h> 9840516Swpaul#include <net/if_media.h> 9940516Swpaul 10040516Swpaul#include <net/bpf.h> 10140516Swpaul 10241569Swpaul#include <machine/bus_pio.h> 10341569Swpaul#include <machine/bus_memio.h> 10441569Swpaul#include <machine/bus.h> 10550703Swpaul#include <machine/resource.h> 10650703Swpaul#include <sys/bus.h> 10750703Swpaul#include <sys/rman.h> 10840516Swpaul 10950703Swpaul#include <dev/mii/mii.h> 11050703Swpaul#include <dev/mii/miivar.h> 11150703Swpaul 11240516Swpaul#include <pci/pcireg.h> 11340516Swpaul#include <pci/pcivar.h> 11440516Swpaul 11559758SpeterMODULE_DEPEND(rl, miibus, 1, 1, 1); 11659758Speter 11751089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 11850703Swpaul#include "miibus_if.h" 11950703Swpaul 12040516Swpaul/* 12140516Swpaul * Default to using PIO access for this driver. On SMP systems, 12240516Swpaul * there appear to be problems with memory mapped mode: it looks like 12340516Swpaul * doing too many memory mapped access back to back in rapid succession 12440516Swpaul * can hang the bus. I'm inclined to blame this on crummy design/construction 12540516Swpaul * on the part of RealTek. Memory mapped mode does appear to work on 12640516Swpaul * uniprocessor systems though. 12740516Swpaul */ 12840516Swpaul#define RL_USEIOSPACE 12940516Swpaul 13040516Swpaul#include <pci/if_rlreg.h> 13140516Swpaul 13240516Swpaul#ifndef lint 13341591Sarchiestatic const char rcsid[] = 13450477Speter "$FreeBSD: head/sys/pci/if_rl.c 94883 2002-04-16 22:03:14Z luigi $"; 13540516Swpaul#endif 13640516Swpaul 13740516Swpaul/* 13840516Swpaul * Various supported device vendors/types and their names. 13940516Swpaul */ 14040516Swpaulstatic struct rl_type rl_devs[] = { 14140516Swpaul { RT_VENDORID, RT_DEVICEID_8129, 14240516Swpaul "RealTek 8129 10/100BaseTX" }, 14340516Swpaul { RT_VENDORID, RT_DEVICEID_8139, 14440516Swpaul "RealTek 8139 10/100BaseTX" }, 14567771Swpaul { RT_VENDORID, RT_DEVICEID_8138, 14667771Swpaul "RealTek 8139 10/100BaseTX CardBus" }, 14741243Swpaul { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 14841243Swpaul "Accton MPX 5030/5038 10/100BaseTX" }, 14944238Swpaul { DELTA_VENDORID, DELTA_DEVICEID_8139, 15044238Swpaul "Delta Electronics 8139 10/100BaseTX" }, 15144238Swpaul { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 15244238Swpaul "Addtron Technolgy 8139 10/100BaseTX" }, 15372813Swpaul { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, 15472813Swpaul "D-Link DFE-530TX+ 10/100BaseTX" }, 15594400Swpaul { NORTEL_VENDORID, ACCTON_DEVICEID_5030, 15694400Swpaul "Nortel Networks 10/100BaseTX" }, 15740516Swpaul { 0, 0, NULL } 15840516Swpaul}; 15940516Swpaul 16092739Salfredstatic int rl_probe (device_t); 16192739Salfredstatic int rl_attach (device_t); 16292739Salfredstatic int rl_detach (device_t); 16340516Swpaul 16492739Salfredstatic int rl_encap (struct rl_softc *, struct mbuf * ); 16540516Swpaul 16692739Salfredstatic void rl_rxeof (struct rl_softc *); 16792739Salfredstatic void rl_txeof (struct rl_softc *); 16892739Salfredstatic void rl_intr (void *); 16992739Salfredstatic void rl_tick (void *); 17092739Salfredstatic void rl_start (struct ifnet *); 17192739Salfredstatic int rl_ioctl (struct ifnet *, u_long, caddr_t); 17292739Salfredstatic void rl_init (void *); 17392739Salfredstatic void rl_stop (struct rl_softc *); 17492739Salfredstatic void rl_watchdog (struct ifnet *); 17592739Salfredstatic int rl_suspend (device_t); 17692739Salfredstatic int rl_resume (device_t); 17792739Salfredstatic void rl_shutdown (device_t); 17892739Salfredstatic int rl_ifmedia_upd (struct ifnet *); 17992739Salfredstatic void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 18040516Swpaul 18192739Salfredstatic void rl_eeprom_putbyte (struct rl_softc *, int); 18292739Salfredstatic void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *); 18392739Salfredstatic void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 18492739Salfredstatic void rl_mii_sync (struct rl_softc *); 18592739Salfredstatic void rl_mii_send (struct rl_softc *, u_int32_t, int); 18692739Salfredstatic int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *); 18792739Salfredstatic int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *); 18840516Swpaul 18992739Salfredstatic int rl_miibus_readreg (device_t, int, int); 19092739Salfredstatic int rl_miibus_writereg (device_t, int, int, int); 19192739Salfredstatic void rl_miibus_statchg (device_t); 19240516Swpaul 19392739Salfredstatic u_int8_t rl_calchash (caddr_t); 19492739Salfredstatic void rl_setmulti (struct rl_softc *); 19592739Salfredstatic void rl_reset (struct rl_softc *); 19692739Salfredstatic int rl_list_tx_init (struct rl_softc *); 19740516Swpaul 19892739Salfredstatic void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int); 19992739Salfredstatic void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int); 20081713Swpaul 20150703Swpaul#ifdef RL_USEIOSPACE 20250703Swpaul#define RL_RES SYS_RES_IOPORT 20350703Swpaul#define RL_RID RL_PCI_LOIO 20450703Swpaul#else 20550703Swpaul#define RL_RES SYS_RES_MEMORY 20650703Swpaul#define RL_RID RL_PCI_LOMEM 20750703Swpaul#endif 20850703Swpaul 20950703Swpaulstatic device_method_t rl_methods[] = { 21050703Swpaul /* Device interface */ 21150703Swpaul DEVMETHOD(device_probe, rl_probe), 21250703Swpaul DEVMETHOD(device_attach, rl_attach), 21350703Swpaul DEVMETHOD(device_detach, rl_detach), 21486822Siwasaki DEVMETHOD(device_suspend, rl_suspend), 21586822Siwasaki DEVMETHOD(device_resume, rl_resume), 21650703Swpaul DEVMETHOD(device_shutdown, rl_shutdown), 21750703Swpaul 21850703Swpaul /* bus interface */ 21950703Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 22050703Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 22150703Swpaul 22250703Swpaul /* MII interface */ 22350703Swpaul DEVMETHOD(miibus_readreg, rl_miibus_readreg), 22450703Swpaul DEVMETHOD(miibus_writereg, rl_miibus_writereg), 22550703Swpaul DEVMETHOD(miibus_statchg, rl_miibus_statchg), 22650703Swpaul 22750703Swpaul { 0, 0 } 22850703Swpaul}; 22950703Swpaul 23050703Swpaulstatic driver_t rl_driver = { 23151455Swpaul "rl", 23250703Swpaul rl_methods, 23350703Swpaul sizeof(struct rl_softc) 23450703Swpaul}; 23550703Swpaul 23650703Swpaulstatic devclass_t rl_devclass; 23750703Swpaul 23851533SwpaulDRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 23967931SwpaulDRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0); 24051473SwpaulDRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 24150703Swpaul 24240516Swpaul#define EE_SET(x) \ 24340516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 24440516Swpaul CSR_READ_1(sc, RL_EECMD) | x) 24540516Swpaul 24640516Swpaul#define EE_CLR(x) \ 24740516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 24840516Swpaul CSR_READ_1(sc, RL_EECMD) & ~x) 24940516Swpaul 25081713Swpaulstatic void 25181713Swpaulrl_dma_map_rxbuf(arg, segs, nseg, error) 25281713Swpaul void *arg; 25381713Swpaul bus_dma_segment_t *segs; 25481713Swpaul int nseg, error; 25581713Swpaul{ 25681713Swpaul struct rl_softc *sc; 25781713Swpaul 25881713Swpaul sc = arg; 25981713Swpaul CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 26081713Swpaul 26181713Swpaul return; 26281713Swpaul} 26381713Swpaul 26481713Swpaulstatic void 26581713Swpaulrl_dma_map_txbuf(arg, segs, nseg, error) 26681713Swpaul void *arg; 26781713Swpaul bus_dma_segment_t *segs; 26881713Swpaul int nseg, error; 26981713Swpaul{ 27081713Swpaul struct rl_softc *sc; 27181713Swpaul 27281713Swpaul sc = arg; 27381713Swpaul CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 27481713Swpaul 27581713Swpaul return; 27681713Swpaul} 27781713Swpaul 27840516Swpaul/* 27940516Swpaul * Send a read command and address to the EEPROM, check for ACK. 28040516Swpaul */ 28140516Swpaulstatic void rl_eeprom_putbyte(sc, addr) 28240516Swpaul struct rl_softc *sc; 28341656Swpaul int addr; 28440516Swpaul{ 28540516Swpaul register int d, i; 28640516Swpaul 28767931Swpaul d = addr | sc->rl_eecmd_read; 28840516Swpaul 28940516Swpaul /* 29055170Sbillf * Feed in each bit and strobe the clock. 29140516Swpaul */ 29240516Swpaul for (i = 0x400; i; i >>= 1) { 29340516Swpaul if (d & i) { 29440516Swpaul EE_SET(RL_EE_DATAIN); 29540516Swpaul } else { 29640516Swpaul EE_CLR(RL_EE_DATAIN); 29740516Swpaul } 29840516Swpaul DELAY(100); 29940516Swpaul EE_SET(RL_EE_CLK); 30040516Swpaul DELAY(150); 30140516Swpaul EE_CLR(RL_EE_CLK); 30240516Swpaul DELAY(100); 30340516Swpaul } 30440516Swpaul 30540516Swpaul return; 30640516Swpaul} 30740516Swpaul 30840516Swpaul/* 30940516Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 31040516Swpaul */ 31140516Swpaulstatic void rl_eeprom_getword(sc, addr, dest) 31240516Swpaul struct rl_softc *sc; 31341656Swpaul int addr; 31440516Swpaul u_int16_t *dest; 31540516Swpaul{ 31640516Swpaul register int i; 31740516Swpaul u_int16_t word = 0; 31840516Swpaul 31940516Swpaul /* Enter EEPROM access mode. */ 32040516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 32140516Swpaul 32240516Swpaul /* 32340516Swpaul * Send address of word we want to read. 32440516Swpaul */ 32540516Swpaul rl_eeprom_putbyte(sc, addr); 32640516Swpaul 32740516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 32840516Swpaul 32940516Swpaul /* 33040516Swpaul * Start reading bits from EEPROM. 33140516Swpaul */ 33240516Swpaul for (i = 0x8000; i; i >>= 1) { 33340516Swpaul EE_SET(RL_EE_CLK); 33440516Swpaul DELAY(100); 33540516Swpaul if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 33640516Swpaul word |= i; 33740516Swpaul EE_CLR(RL_EE_CLK); 33840516Swpaul DELAY(100); 33940516Swpaul } 34040516Swpaul 34140516Swpaul /* Turn off EEPROM access mode. */ 34240516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 34340516Swpaul 34440516Swpaul *dest = word; 34540516Swpaul 34640516Swpaul return; 34740516Swpaul} 34840516Swpaul 34940516Swpaul/* 35040516Swpaul * Read a sequence of words from the EEPROM. 35140516Swpaul */ 35240516Swpaulstatic void rl_read_eeprom(sc, dest, off, cnt, swap) 35340516Swpaul struct rl_softc *sc; 35440516Swpaul caddr_t dest; 35540516Swpaul int off; 35640516Swpaul int cnt; 35740516Swpaul int swap; 35840516Swpaul{ 35940516Swpaul int i; 36040516Swpaul u_int16_t word = 0, *ptr; 36140516Swpaul 36240516Swpaul for (i = 0; i < cnt; i++) { 36340516Swpaul rl_eeprom_getword(sc, off + i, &word); 36440516Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 36540516Swpaul if (swap) 36640516Swpaul *ptr = ntohs(word); 36740516Swpaul else 36840516Swpaul *ptr = word; 36940516Swpaul } 37040516Swpaul 37140516Swpaul return; 37240516Swpaul} 37340516Swpaul 37440516Swpaul 37540516Swpaul/* 37640516Swpaul * MII access routines are provided for the 8129, which 37740516Swpaul * doesn't have a built-in PHY. For the 8139, we fake things 37840516Swpaul * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 37940516Swpaul * direct access PHY registers. 38040516Swpaul */ 38140516Swpaul#define MII_SET(x) \ 38240516Swpaul CSR_WRITE_1(sc, RL_MII, \ 38340516Swpaul CSR_READ_1(sc, RL_MII) | x) 38440516Swpaul 38540516Swpaul#define MII_CLR(x) \ 38640516Swpaul CSR_WRITE_1(sc, RL_MII, \ 38740516Swpaul CSR_READ_1(sc, RL_MII) & ~x) 38840516Swpaul 38940516Swpaul/* 39040516Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 39140516Swpaul */ 39240516Swpaulstatic void rl_mii_sync(sc) 39340516Swpaul struct rl_softc *sc; 39440516Swpaul{ 39540516Swpaul register int i; 39640516Swpaul 39740516Swpaul MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 39840516Swpaul 39940516Swpaul for (i = 0; i < 32; i++) { 40040516Swpaul MII_SET(RL_MII_CLK); 40140516Swpaul DELAY(1); 40240516Swpaul MII_CLR(RL_MII_CLK); 40340516Swpaul DELAY(1); 40440516Swpaul } 40540516Swpaul 40640516Swpaul return; 40740516Swpaul} 40840516Swpaul 40940516Swpaul/* 41040516Swpaul * Clock a series of bits through the MII. 41140516Swpaul */ 41240516Swpaulstatic void rl_mii_send(sc, bits, cnt) 41340516Swpaul struct rl_softc *sc; 41440516Swpaul u_int32_t bits; 41540516Swpaul int cnt; 41640516Swpaul{ 41740516Swpaul int i; 41840516Swpaul 41940516Swpaul MII_CLR(RL_MII_CLK); 42040516Swpaul 42140516Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 42240516Swpaul if (bits & i) { 42340516Swpaul MII_SET(RL_MII_DATAOUT); 42440516Swpaul } else { 42540516Swpaul MII_CLR(RL_MII_DATAOUT); 42640516Swpaul } 42740516Swpaul DELAY(1); 42840516Swpaul MII_CLR(RL_MII_CLK); 42940516Swpaul DELAY(1); 43040516Swpaul MII_SET(RL_MII_CLK); 43140516Swpaul } 43240516Swpaul} 43340516Swpaul 43440516Swpaul/* 43540516Swpaul * Read an PHY register through the MII. 43640516Swpaul */ 43740516Swpaulstatic int rl_mii_readreg(sc, frame) 43840516Swpaul struct rl_softc *sc; 43940516Swpaul struct rl_mii_frame *frame; 44040516Swpaul 44140516Swpaul{ 44267087Swpaul int i, ack; 44340516Swpaul 44467087Swpaul RL_LOCK(sc); 44540516Swpaul 44640516Swpaul /* 44740516Swpaul * Set up frame for RX. 44840516Swpaul */ 44940516Swpaul frame->mii_stdelim = RL_MII_STARTDELIM; 45040516Swpaul frame->mii_opcode = RL_MII_READOP; 45140516Swpaul frame->mii_turnaround = 0; 45240516Swpaul frame->mii_data = 0; 45340516Swpaul 45440516Swpaul CSR_WRITE_2(sc, RL_MII, 0); 45540516Swpaul 45640516Swpaul /* 45740516Swpaul * Turn on data xmit. 45840516Swpaul */ 45940516Swpaul MII_SET(RL_MII_DIR); 46040516Swpaul 46140516Swpaul rl_mii_sync(sc); 46240516Swpaul 46340516Swpaul /* 46440516Swpaul * Send command/address info. 46540516Swpaul */ 46640516Swpaul rl_mii_send(sc, frame->mii_stdelim, 2); 46740516Swpaul rl_mii_send(sc, frame->mii_opcode, 2); 46840516Swpaul rl_mii_send(sc, frame->mii_phyaddr, 5); 46940516Swpaul rl_mii_send(sc, frame->mii_regaddr, 5); 47040516Swpaul 47140516Swpaul /* Idle bit */ 47240516Swpaul MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 47340516Swpaul DELAY(1); 47440516Swpaul MII_SET(RL_MII_CLK); 47540516Swpaul DELAY(1); 47640516Swpaul 47740516Swpaul /* Turn off xmit. */ 47840516Swpaul MII_CLR(RL_MII_DIR); 47940516Swpaul 48040516Swpaul /* Check for ack */ 48140516Swpaul MII_CLR(RL_MII_CLK); 48240516Swpaul DELAY(1); 48340516Swpaul MII_SET(RL_MII_CLK); 48440516Swpaul DELAY(1); 48540516Swpaul ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 48640516Swpaul 48740516Swpaul /* 48840516Swpaul * Now try reading data bits. If the ack failed, we still 48940516Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 49040516Swpaul */ 49140516Swpaul if (ack) { 49240516Swpaul for(i = 0; i < 16; i++) { 49340516Swpaul MII_CLR(RL_MII_CLK); 49440516Swpaul DELAY(1); 49540516Swpaul MII_SET(RL_MII_CLK); 49640516Swpaul DELAY(1); 49740516Swpaul } 49840516Swpaul goto fail; 49940516Swpaul } 50040516Swpaul 50140516Swpaul for (i = 0x8000; i; i >>= 1) { 50240516Swpaul MII_CLR(RL_MII_CLK); 50340516Swpaul DELAY(1); 50440516Swpaul if (!ack) { 50540516Swpaul if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 50640516Swpaul frame->mii_data |= i; 50740516Swpaul DELAY(1); 50840516Swpaul } 50940516Swpaul MII_SET(RL_MII_CLK); 51040516Swpaul DELAY(1); 51140516Swpaul } 51240516Swpaul 51340516Swpaulfail: 51440516Swpaul 51540516Swpaul MII_CLR(RL_MII_CLK); 51640516Swpaul DELAY(1); 51740516Swpaul MII_SET(RL_MII_CLK); 51840516Swpaul DELAY(1); 51940516Swpaul 52067087Swpaul RL_UNLOCK(sc); 52140516Swpaul 52240516Swpaul if (ack) 52340516Swpaul return(1); 52440516Swpaul return(0); 52540516Swpaul} 52640516Swpaul 52740516Swpaul/* 52840516Swpaul * Write to a PHY register through the MII. 52940516Swpaul */ 53040516Swpaulstatic int rl_mii_writereg(sc, frame) 53140516Swpaul struct rl_softc *sc; 53240516Swpaul struct rl_mii_frame *frame; 53340516Swpaul 53440516Swpaul{ 53567087Swpaul RL_LOCK(sc); 53640516Swpaul 53740516Swpaul /* 53840516Swpaul * Set up frame for TX. 53940516Swpaul */ 54040516Swpaul 54140516Swpaul frame->mii_stdelim = RL_MII_STARTDELIM; 54240516Swpaul frame->mii_opcode = RL_MII_WRITEOP; 54340516Swpaul frame->mii_turnaround = RL_MII_TURNAROUND; 54440516Swpaul 54540516Swpaul /* 54640516Swpaul * Turn on data output. 54740516Swpaul */ 54840516Swpaul MII_SET(RL_MII_DIR); 54940516Swpaul 55040516Swpaul rl_mii_sync(sc); 55140516Swpaul 55240516Swpaul rl_mii_send(sc, frame->mii_stdelim, 2); 55340516Swpaul rl_mii_send(sc, frame->mii_opcode, 2); 55440516Swpaul rl_mii_send(sc, frame->mii_phyaddr, 5); 55540516Swpaul rl_mii_send(sc, frame->mii_regaddr, 5); 55640516Swpaul rl_mii_send(sc, frame->mii_turnaround, 2); 55740516Swpaul rl_mii_send(sc, frame->mii_data, 16); 55840516Swpaul 55940516Swpaul /* Idle bit. */ 56040516Swpaul MII_SET(RL_MII_CLK); 56140516Swpaul DELAY(1); 56240516Swpaul MII_CLR(RL_MII_CLK); 56340516Swpaul DELAY(1); 56440516Swpaul 56540516Swpaul /* 56640516Swpaul * Turn off xmit. 56740516Swpaul */ 56840516Swpaul MII_CLR(RL_MII_DIR); 56940516Swpaul 57067087Swpaul RL_UNLOCK(sc); 57140516Swpaul 57240516Swpaul return(0); 57340516Swpaul} 57440516Swpaul 57550703Swpaulstatic int rl_miibus_readreg(dev, phy, reg) 57650703Swpaul device_t dev; 57750703Swpaul int phy, reg; 57850703Swpaul{ 57940516Swpaul struct rl_softc *sc; 58040516Swpaul struct rl_mii_frame frame; 58140516Swpaul u_int16_t rval = 0; 58240516Swpaul u_int16_t rl8139_reg = 0; 58340516Swpaul 58450703Swpaul sc = device_get_softc(dev); 58567087Swpaul RL_LOCK(sc); 58650703Swpaul 58740516Swpaul if (sc->rl_type == RL_8139) { 58850703Swpaul /* Pretend the internal PHY is only at address 0 */ 58967087Swpaul if (phy) { 59067087Swpaul RL_UNLOCK(sc); 59150703Swpaul return(0); 59267087Swpaul } 59340516Swpaul switch(reg) { 59450703Swpaul case MII_BMCR: 59540516Swpaul rl8139_reg = RL_BMCR; 59640516Swpaul break; 59750703Swpaul case MII_BMSR: 59840516Swpaul rl8139_reg = RL_BMSR; 59940516Swpaul break; 60050703Swpaul case MII_ANAR: 60140516Swpaul rl8139_reg = RL_ANAR; 60240516Swpaul break; 60350703Swpaul case MII_ANER: 60450703Swpaul rl8139_reg = RL_ANER; 60550703Swpaul break; 60650703Swpaul case MII_ANLPAR: 60740516Swpaul rl8139_reg = RL_LPAR; 60840516Swpaul break; 60950703Swpaul case MII_PHYIDR1: 61050703Swpaul case MII_PHYIDR2: 61167087Swpaul RL_UNLOCK(sc); 61250703Swpaul return(0); 61350703Swpaul break; 61494149Swpaul /* 61594149Swpaul * Allow the rlphy driver to read the media status 61694149Swpaul * register. If we have a link partner which does not 61794149Swpaul * support NWAY, this is the register which will tell 61894149Swpaul * us the results of parallel detection. 61994149Swpaul */ 62094149Swpaul case RL_MEDIASTAT: 62194149Swpaul rval = CSR_READ_1(sc, RL_MEDIASTAT); 62294149Swpaul RL_UNLOCK(sc); 62394149Swpaul return(rval); 62494149Swpaul break; 62540516Swpaul default: 62640516Swpaul printf("rl%d: bad phy register\n", sc->rl_unit); 62767087Swpaul RL_UNLOCK(sc); 62840516Swpaul return(0); 62940516Swpaul } 63040516Swpaul rval = CSR_READ_2(sc, rl8139_reg); 63167087Swpaul RL_UNLOCK(sc); 63240516Swpaul return(rval); 63340516Swpaul } 63440516Swpaul 63540516Swpaul bzero((char *)&frame, sizeof(frame)); 63640516Swpaul 63750703Swpaul frame.mii_phyaddr = phy; 63840516Swpaul frame.mii_regaddr = reg; 63940516Swpaul rl_mii_readreg(sc, &frame); 64067087Swpaul RL_UNLOCK(sc); 64140516Swpaul 64240516Swpaul return(frame.mii_data); 64340516Swpaul} 64440516Swpaul 64550703Swpaulstatic int rl_miibus_writereg(dev, phy, reg, data) 64650703Swpaul device_t dev; 64750703Swpaul int phy, reg, data; 64850703Swpaul{ 64940516Swpaul struct rl_softc *sc; 65040516Swpaul struct rl_mii_frame frame; 65140516Swpaul u_int16_t rl8139_reg = 0; 65240516Swpaul 65350703Swpaul sc = device_get_softc(dev); 65467087Swpaul RL_LOCK(sc); 65550703Swpaul 65640516Swpaul if (sc->rl_type == RL_8139) { 65750703Swpaul /* Pretend the internal PHY is only at address 0 */ 65867087Swpaul if (phy) { 65967087Swpaul RL_UNLOCK(sc); 66050703Swpaul return(0); 66167087Swpaul } 66240516Swpaul switch(reg) { 66350703Swpaul case MII_BMCR: 66440516Swpaul rl8139_reg = RL_BMCR; 66540516Swpaul break; 66650703Swpaul case MII_BMSR: 66740516Swpaul rl8139_reg = RL_BMSR; 66840516Swpaul break; 66950703Swpaul case MII_ANAR: 67040516Swpaul rl8139_reg = RL_ANAR; 67140516Swpaul break; 67250703Swpaul case MII_ANER: 67350703Swpaul rl8139_reg = RL_ANER; 67450703Swpaul break; 67550703Swpaul case MII_ANLPAR: 67640516Swpaul rl8139_reg = RL_LPAR; 67740516Swpaul break; 67850703Swpaul case MII_PHYIDR1: 67950703Swpaul case MII_PHYIDR2: 68067087Swpaul RL_UNLOCK(sc); 68150703Swpaul return(0); 68250703Swpaul break; 68340516Swpaul default: 68440516Swpaul printf("rl%d: bad phy register\n", sc->rl_unit); 68567087Swpaul RL_UNLOCK(sc); 68650703Swpaul return(0); 68740516Swpaul } 68840516Swpaul CSR_WRITE_2(sc, rl8139_reg, data); 68967087Swpaul RL_UNLOCK(sc); 69050703Swpaul return(0); 69140516Swpaul } 69240516Swpaul 69340516Swpaul bzero((char *)&frame, sizeof(frame)); 69440516Swpaul 69550703Swpaul frame.mii_phyaddr = phy; 69640516Swpaul frame.mii_regaddr = reg; 69740516Swpaul frame.mii_data = data; 69840516Swpaul 69940516Swpaul rl_mii_writereg(sc, &frame); 70040516Swpaul 70167087Swpaul RL_UNLOCK(sc); 70250703Swpaul return(0); 70350703Swpaul} 70450703Swpaul 70550703Swpaulstatic void rl_miibus_statchg(dev) 70650703Swpaul device_t dev; 70750703Swpaul{ 70840516Swpaul return; 70940516Swpaul} 71040516Swpaul 71140516Swpaul/* 71243062Swpaul * Calculate CRC of a multicast group address, return the upper 6 bits. 71340516Swpaul */ 71440516Swpaulstatic u_int8_t rl_calchash(addr) 71541656Swpaul caddr_t addr; 71640516Swpaul{ 71740516Swpaul u_int32_t crc, carry; 71840516Swpaul int i, j; 71940516Swpaul u_int8_t c; 72040516Swpaul 72140516Swpaul /* Compute CRC for the address value. */ 72240516Swpaul crc = 0xFFFFFFFF; /* initial value */ 72340516Swpaul 72440516Swpaul for (i = 0; i < 6; i++) { 72540516Swpaul c = *(addr + i); 72640516Swpaul for (j = 0; j < 8; j++) { 72740516Swpaul carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 72840516Swpaul crc <<= 1; 72940516Swpaul c >>= 1; 73040516Swpaul if (carry) 73140516Swpaul crc = (crc ^ 0x04c11db6) | carry; 73240516Swpaul } 73340516Swpaul } 73440516Swpaul 73540516Swpaul /* return the filter bit position */ 73643062Swpaul return(crc >> 26); 73740516Swpaul} 73840516Swpaul 73940516Swpaul/* 74040516Swpaul * Program the 64-bit multicast hash filter. 74140516Swpaul */ 74240516Swpaulstatic void rl_setmulti(sc) 74340516Swpaul struct rl_softc *sc; 74440516Swpaul{ 74540516Swpaul struct ifnet *ifp; 74640516Swpaul int h = 0; 74740516Swpaul u_int32_t hashes[2] = { 0, 0 }; 74840516Swpaul struct ifmultiaddr *ifma; 74940516Swpaul u_int32_t rxfilt; 75040516Swpaul int mcnt = 0; 75140516Swpaul 75240516Swpaul ifp = &sc->arpcom.ac_if; 75340516Swpaul 75440516Swpaul rxfilt = CSR_READ_4(sc, RL_RXCFG); 75540516Swpaul 75643062Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 75740516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 75840516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 75940516Swpaul CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 76040516Swpaul CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 76140516Swpaul return; 76240516Swpaul } 76340516Swpaul 76440516Swpaul /* first, zot all the existing hash bits */ 76540516Swpaul CSR_WRITE_4(sc, RL_MAR0, 0); 76640516Swpaul CSR_WRITE_4(sc, RL_MAR4, 0); 76740516Swpaul 76840516Swpaul /* now program new ones */ 76972084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 77040516Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 77140516Swpaul continue; 77240516Swpaul h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 77340516Swpaul if (h < 32) 77440516Swpaul hashes[0] |= (1 << h); 77540516Swpaul else 77640516Swpaul hashes[1] |= (1 << (h - 32)); 77740516Swpaul mcnt++; 77840516Swpaul } 77940516Swpaul 78040516Swpaul if (mcnt) 78140516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 78240516Swpaul else 78340516Swpaul rxfilt &= ~RL_RXCFG_RX_MULTI; 78440516Swpaul 78540516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 78640516Swpaul CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 78740516Swpaul CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 78840516Swpaul 78940516Swpaul return; 79040516Swpaul} 79140516Swpaul 79240516Swpaulstatic void rl_reset(sc) 79340516Swpaul struct rl_softc *sc; 79440516Swpaul{ 79540516Swpaul register int i; 79640516Swpaul 79740516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 79840516Swpaul 79940516Swpaul for (i = 0; i < RL_TIMEOUT; i++) { 80040516Swpaul DELAY(10); 80140516Swpaul if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 80240516Swpaul break; 80340516Swpaul } 80440516Swpaul if (i == RL_TIMEOUT) 80540516Swpaul printf("rl%d: reset never completed!\n", sc->rl_unit); 80640516Swpaul 80740516Swpaul return; 80840516Swpaul} 80940516Swpaul 81040516Swpaul/* 81140516Swpaul * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 81240516Swpaul * IDs against our list and return a device name if we find a match. 81340516Swpaul */ 81450703Swpaulstatic int rl_probe(dev) 81550703Swpaul device_t dev; 81640516Swpaul{ 81740516Swpaul struct rl_type *t; 81840516Swpaul 81940516Swpaul t = rl_devs; 82040516Swpaul 82140516Swpaul while(t->rl_name != NULL) { 82250703Swpaul if ((pci_get_vendor(dev) == t->rl_vid) && 82350703Swpaul (pci_get_device(dev) == t->rl_did)) { 82450703Swpaul device_set_desc(dev, t->rl_name); 82550703Swpaul return(0); 82640516Swpaul } 82740516Swpaul t++; 82840516Swpaul } 82940516Swpaul 83050703Swpaul return(ENXIO); 83140516Swpaul} 83240516Swpaul 83340516Swpaul/* 83440516Swpaul * Attach the interface. Allocate softc structures, do ifmedia 83540516Swpaul * setup and ethernet/BPF attach. 83640516Swpaul */ 83750703Swpaulstatic int rl_attach(dev) 83850703Swpaul device_t dev; 83940516Swpaul{ 84040516Swpaul u_char eaddr[ETHER_ADDR_LEN]; 84140516Swpaul u_int32_t command; 84240516Swpaul struct rl_softc *sc; 84340516Swpaul struct ifnet *ifp; 84440516Swpaul u_int16_t rl_did = 0; 84550703Swpaul int unit, error = 0, rid; 84640516Swpaul 84750703Swpaul sc = device_get_softc(dev); 84850703Swpaul unit = device_get_unit(dev); 84940516Swpaul bzero(sc, sizeof(struct rl_softc)); 85040516Swpaul 85193818Sjhb mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 85293818Sjhb MTX_DEF | MTX_RECURSE); 85369583Swpaul RL_LOCK(sc); 85469583Swpaul 85540516Swpaul /* 85640516Swpaul * Handle power management nonsense. 85740516Swpaul */ 85840516Swpaul 85970167Swpaul if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 86070167Swpaul u_int32_t iobase, membase, irq; 86140516Swpaul 86270167Swpaul /* Save important PCI config data. */ 86370167Swpaul iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 86470167Swpaul membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 86570167Swpaul irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 86640516Swpaul 86770167Swpaul /* Reset the power state. */ 86870167Swpaul printf("rl%d: chip is is in D%d power mode " 86970167Swpaul "-- setting to D0\n", unit, 87070167Swpaul pci_get_powerstate(dev)); 87140516Swpaul 87270167Swpaul pci_set_powerstate(dev, PCI_POWERSTATE_D0); 87340516Swpaul 87470167Swpaul /* Restore PCI config data. */ 87570167Swpaul pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 87670167Swpaul pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 87770167Swpaul pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 87840516Swpaul } 87940516Swpaul 88040516Swpaul /* 88140516Swpaul * Map control/status registers. 88240516Swpaul */ 88372813Swpaul pci_enable_busmaster(dev); 88479472Swpaul pci_enable_io(dev, SYS_RES_IOPORT); 88579472Swpaul pci_enable_io(dev, SYS_RES_MEMORY); 88661041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 88740516Swpaul 88840516Swpaul#ifdef RL_USEIOSPACE 88940516Swpaul if (!(command & PCIM_CMD_PORTEN)) { 89040516Swpaul printf("rl%d: failed to enable I/O ports!\n", unit); 89150703Swpaul error = ENXIO; 89240516Swpaul goto fail; 89340516Swpaul } 89440516Swpaul#else 89540516Swpaul if (!(command & PCIM_CMD_MEMEN)) { 89640516Swpaul printf("rl%d: failed to enable memory mapping!\n", unit); 89750703Swpaul error = ENXIO; 89840516Swpaul goto fail; 89940516Swpaul } 90050703Swpaul#endif 90140516Swpaul 90250703Swpaul rid = RL_RID; 90350703Swpaul sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 90450703Swpaul 0, ~0, 1, RF_ACTIVE); 90550703Swpaul 90650703Swpaul if (sc->rl_res == NULL) { 90750703Swpaul printf ("rl%d: couldn't map ports/memory\n", unit); 90850703Swpaul error = ENXIO; 90940516Swpaul goto fail; 91040516Swpaul } 91140516Swpaul 91269127Sroger /* Detect the Realtek 8139B. For some reason, this chip is very 91369127Sroger * unstable when left to autoselect the media 91469127Sroger * The best workaround is to set the device to the required 91569127Sroger * media type or to set it to the 10 Meg speed. 91669127Sroger */ 91769127Sroger 91869127Sroger if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { 91969127Sroger printf("rl%d: Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n", unit); 92069127Sroger } 92169127Sroger 92250703Swpaul sc->rl_btag = rman_get_bustag(sc->rl_res); 92350703Swpaul sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 92450703Swpaul 92550703Swpaul rid = 0; 92650703Swpaul sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 92750703Swpaul RF_SHAREABLE | RF_ACTIVE); 92850703Swpaul 92950703Swpaul if (sc->rl_irq == NULL) { 93040516Swpaul printf("rl%d: couldn't map interrupt\n", unit); 93150703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 93250703Swpaul error = ENXIO; 93340516Swpaul goto fail; 93440516Swpaul } 93540516Swpaul 93650703Swpaul error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 93750703Swpaul rl_intr, sc, &sc->rl_intrhand); 93850703Swpaul 93950703Swpaul if (error) { 94068215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 94150703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 94250703Swpaul printf("rl%d: couldn't set up irq\n", unit); 94350703Swpaul goto fail; 94450703Swpaul } 94550703Swpaul 94650703Swpaul callout_handle_init(&sc->rl_stat_ch); 94750703Swpaul 94840516Swpaul /* Reset the adapter. */ 94940516Swpaul rl_reset(sc); 95067931Swpaul sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 95167931Swpaul rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 95268215Swpaul if (rl_did != 0x8129) 95367931Swpaul sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 95440516Swpaul 95540516Swpaul /* 95640516Swpaul * Get station address from the EEPROM. 95740516Swpaul */ 95840516Swpaul rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0); 95940516Swpaul 96040516Swpaul /* 96140516Swpaul * A RealTek chip was detected. Inform the world. 96240516Swpaul */ 96340516Swpaul printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 96440516Swpaul 96540516Swpaul sc->rl_unit = unit; 96640516Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 96740516Swpaul 96840516Swpaul /* 96940516Swpaul * Now read the exact device type from the EEPROM to find 97040516Swpaul * out if it's an 8129 or 8139. 97140516Swpaul */ 97240516Swpaul rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 97340516Swpaul 97444238Swpaul if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 97567771Swpaul rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 97672813Swpaul rl_did == RT_DEVICEID_8138 || rl_did == DLINK_DEVICEID_530TXPLUS) 97740516Swpaul sc->rl_type = RL_8139; 97840516Swpaul else if (rl_did == RT_DEVICEID_8129) 97940516Swpaul sc->rl_type = RL_8129; 98040516Swpaul else { 98140516Swpaul printf("rl%d: unknown device ID: %x\n", unit, rl_did); 98250703Swpaul bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 98368215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 98450703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 98550703Swpaul error = ENXIO; 98640516Swpaul goto fail; 98740516Swpaul } 98840516Swpaul 98981713Swpaul /* 99081713Swpaul * Allocate the parent bus DMA tag appropriate for PCI. 99181713Swpaul */ 99281713Swpaul#define RL_NSEG_NEW 32 99381713Swpaul error = bus_dma_tag_create(NULL, /* parent */ 99481713Swpaul 1, 0, /* alignment, boundary */ 99581713Swpaul BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 99681713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 99781713Swpaul NULL, NULL, /* filter, filterarg */ 99881713Swpaul MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 99981713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 100081713Swpaul BUS_DMA_ALLOCNOW, /* flags */ 100181713Swpaul &sc->rl_parent_tag); 100240516Swpaul 100381713Swpaul /* 100481713Swpaul * Now allocate a tag for the DMA descriptor lists. 100581713Swpaul * All of our lists are allocated as a contiguous block 100681713Swpaul * of memory. 100781713Swpaul */ 100881713Swpaul error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 100981713Swpaul 1, 0, /* alignment, boundary */ 101081713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 101181713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 101281713Swpaul NULL, NULL, /* filter, filterarg */ 101381713Swpaul RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 101481713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 101581713Swpaul 0, /* flags */ 101681713Swpaul &sc->rl_tag); 101781713Swpaul 101881713Swpaul /* 101981713Swpaul * Now allocate a chunk of DMA-able memory based on the 102081713Swpaul * tag we just created. 102181713Swpaul */ 102281713Swpaul error = bus_dmamem_alloc(sc->rl_tag, 102381713Swpaul (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT, 102481713Swpaul &sc->rl_cdata.rl_rx_dmamap); 102581713Swpaul 102640516Swpaul if (sc->rl_cdata.rl_rx_buf == NULL) { 102740516Swpaul printf("rl%d: no memory for list buffers!\n", unit); 102850703Swpaul bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 102968215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 103050703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 103181713Swpaul bus_dma_tag_destroy(sc->rl_tag); 103250703Swpaul error = ENXIO; 103340516Swpaul goto fail; 103440516Swpaul } 103540516Swpaul 103648028Swpaul /* Leave a few bytes before the start of the RX ring buffer. */ 103748028Swpaul sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 103848028Swpaul sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 103948028Swpaul 104050703Swpaul /* Do MII setup */ 104150703Swpaul if (mii_phy_probe(dev, &sc->rl_miibus, 104250703Swpaul rl_ifmedia_upd, rl_ifmedia_sts)) { 104350703Swpaul printf("rl%d: MII without any phy!\n", sc->rl_unit); 104450703Swpaul bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 104568215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 104650703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 104781713Swpaul bus_dmamem_free(sc->rl_tag, 104881713Swpaul sc->rl_cdata.rl_rx_buf, sc->rl_cdata.rl_rx_dmamap); 104981713Swpaul bus_dma_tag_destroy(sc->rl_tag); 105050703Swpaul error = ENXIO; 105150703Swpaul goto fail; 105250703Swpaul } 105350703Swpaul 105440516Swpaul ifp = &sc->arpcom.ac_if; 105540516Swpaul ifp->if_softc = sc; 105640516Swpaul ifp->if_unit = unit; 105740516Swpaul ifp->if_name = "rl"; 105840516Swpaul ifp->if_mtu = ETHERMTU; 105940516Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 106040516Swpaul ifp->if_ioctl = rl_ioctl; 106140516Swpaul ifp->if_output = ether_output; 106240516Swpaul ifp->if_start = rl_start; 106340516Swpaul ifp->if_watchdog = rl_watchdog; 106440516Swpaul ifp->if_init = rl_init; 106540516Swpaul ifp->if_baudrate = 10000000; 106645633Swpaul ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 106740516Swpaul 106840516Swpaul /* 106963090Sarchie * Call MI attach routine. 107040516Swpaul */ 107163090Sarchie ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 107267087Swpaul RL_UNLOCK(sc); 107367087Swpaul return(0); 107440516Swpaul 107540516Swpaulfail: 107667087Swpaul RL_UNLOCK(sc); 107767087Swpaul mtx_destroy(&sc->rl_mtx); 107850703Swpaul return(error); 107940516Swpaul} 108040516Swpaul 108150703Swpaulstatic int rl_detach(dev) 108250703Swpaul device_t dev; 108350703Swpaul{ 108450703Swpaul struct rl_softc *sc; 108550703Swpaul struct ifnet *ifp; 108650703Swpaul 108750703Swpaul sc = device_get_softc(dev); 108867087Swpaul RL_LOCK(sc); 108950703Swpaul ifp = &sc->arpcom.ac_if; 109050703Swpaul 109163090Sarchie ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 109250703Swpaul rl_stop(sc); 109350703Swpaul 109450703Swpaul bus_generic_detach(dev); 109550703Swpaul device_delete_child(dev, sc->rl_miibus); 109650703Swpaul 109750703Swpaul bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 109868215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 109950703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 110050703Swpaul 110181713Swpaul bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 110281713Swpaul bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 110381713Swpaul sc->rl_cdata.rl_rx_dmamap); 110481713Swpaul bus_dma_tag_destroy(sc->rl_tag); 110581713Swpaul bus_dma_tag_destroy(sc->rl_parent_tag); 110650703Swpaul 110767087Swpaul RL_UNLOCK(sc); 110867087Swpaul mtx_destroy(&sc->rl_mtx); 110950703Swpaul 111050703Swpaul return(0); 111150703Swpaul} 111250703Swpaul 111340516Swpaul/* 111440516Swpaul * Initialize the transmit descriptors. 111540516Swpaul */ 111640516Swpaulstatic int rl_list_tx_init(sc) 111740516Swpaul struct rl_softc *sc; 111840516Swpaul{ 111940516Swpaul struct rl_chain_data *cd; 112040516Swpaul int i; 112140516Swpaul 112240516Swpaul cd = &sc->rl_cdata; 112340516Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 112445633Swpaul cd->rl_tx_chain[i] = NULL; 112548028Swpaul CSR_WRITE_4(sc, 112648028Swpaul RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 112740516Swpaul } 112840516Swpaul 112945633Swpaul sc->rl_cdata.cur_tx = 0; 113045633Swpaul sc->rl_cdata.last_tx = 0; 113140516Swpaul 113240516Swpaul return(0); 113340516Swpaul} 113440516Swpaul 113540516Swpaul/* 113640516Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 113740516Swpaul * the higher level protocols. 113840516Swpaul * 113940516Swpaul * You know there's something wrong with a PCI bus-master chip design 114040516Swpaul * when you have to use m_devget(). 114140516Swpaul * 114240516Swpaul * The receive operation is badly documented in the datasheet, so I'll 114340516Swpaul * attempt to document it here. The driver provides a buffer area and 114440516Swpaul * places its base address in the RX buffer start address register. 114540516Swpaul * The chip then begins copying frames into the RX buffer. Each frame 114672645Sasmodai * is preceded by a 32-bit RX status word which specifies the length 114740516Swpaul * of the frame and certain other status bits. Each frame (starting with 114840516Swpaul * the status word) is also 32-bit aligned. The frame length is in the 114940516Swpaul * first 16 bits of the status word; the lower 15 bits correspond with 115040516Swpaul * the 'rx status register' mentioned in the datasheet. 115148028Swpaul * 115248028Swpaul * Note: to make the Alpha happy, the frame payload needs to be aligned 115378508Sbmilekic * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 115478508Sbmilekic * as the offset argument to m_devget(). 115540516Swpaul */ 115640516Swpaulstatic void rl_rxeof(sc) 115740516Swpaul struct rl_softc *sc; 115840516Swpaul{ 115940516Swpaul struct ether_header *eh; 116040516Swpaul struct mbuf *m; 116140516Swpaul struct ifnet *ifp; 116240516Swpaul int total_len = 0; 116340516Swpaul u_int32_t rxstat; 116440516Swpaul caddr_t rxbufpos; 116540516Swpaul int wrap = 0; 116640516Swpaul u_int16_t cur_rx; 116740516Swpaul u_int16_t limit; 116840516Swpaul u_int16_t rx_bytes = 0, max_bytes; 116940516Swpaul 117040516Swpaul ifp = &sc->arpcom.ac_if; 117140516Swpaul 117281713Swpaul bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 117381713Swpaul BUS_DMASYNC_POSTWRITE); 117481713Swpaul 117540516Swpaul cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 117640516Swpaul 117740516Swpaul /* Do not try to read past this point. */ 117840516Swpaul limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 117940516Swpaul 118040516Swpaul if (limit < cur_rx) 118140516Swpaul max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 118240516Swpaul else 118340516Swpaul max_bytes = limit - cur_rx; 118440516Swpaul 118542738Swpaul while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 118694883Sluigi#ifdef DEVICE_POLLING 118794883Sluigi if (ifp->if_ipending & IFF_POLLING) { 118894883Sluigi if (sc->rxcycles <= 0) 118994883Sluigi break; 119094883Sluigi sc->rxcycles--; 119194883Sluigi } 119294883Sluigi#endif /* DEVICE_POLLING */ 119340516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 119440516Swpaul rxstat = *(u_int32_t *)rxbufpos; 119540516Swpaul 119640516Swpaul /* 119740516Swpaul * Here's a totally undocumented fact for you. When the 119840516Swpaul * RealTek chip is in the process of copying a packet into 119940516Swpaul * RAM for you, the length will be 0xfff0. If you spot a 120040516Swpaul * packet header with this value, you need to stop. The 120140516Swpaul * datasheet makes absolutely no mention of this and 120240516Swpaul * RealTek should be shot for this. 120340516Swpaul */ 120440516Swpaul if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 120540516Swpaul break; 120640516Swpaul 120740516Swpaul if (!(rxstat & RL_RXSTAT_RXOK)) { 120840516Swpaul ifp->if_ierrors++; 120950703Swpaul rl_init(sc); 121050703Swpaul return; 121140516Swpaul } 121240516Swpaul 121340516Swpaul /* No errors; receive the packet. */ 121440516Swpaul total_len = rxstat >> 16; 121540516Swpaul rx_bytes += total_len + 4; 121640516Swpaul 121740516Swpaul /* 121842051Swpaul * XXX The RealTek chip includes the CRC with every 121942051Swpaul * received frame, and there's no way to turn this 122042051Swpaul * behavior off (at least, I can't find anything in 122142051Swpaul * the manual that explains how to do it) so we have 122242051Swpaul * to trim off the CRC manually. 122342051Swpaul */ 122442051Swpaul total_len -= ETHER_CRC_LEN; 122542051Swpaul 122642051Swpaul /* 122740516Swpaul * Avoid trying to read more bytes than we know 122840516Swpaul * the chip has prepared for us. 122940516Swpaul */ 123040516Swpaul if (rx_bytes > max_bytes) 123140516Swpaul break; 123240516Swpaul 123340516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + 123440516Swpaul ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 123540516Swpaul 123640516Swpaul if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 123740516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf; 123840516Swpaul 123940516Swpaul wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 124040516Swpaul 124140516Swpaul if (total_len > wrap) { 124278508Sbmilekic m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 124378508Sbmilekic NULL); 124440516Swpaul if (m == NULL) { 124540516Swpaul ifp->if_ierrors++; 124652426Swpaul } else { 124740516Swpaul m_copyback(m, wrap, total_len - wrap, 124840516Swpaul sc->rl_cdata.rl_rx_buf); 124948028Swpaul } 125042051Swpaul cur_rx = (total_len - wrap + ETHER_CRC_LEN); 125140516Swpaul } else { 125278508Sbmilekic m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 125378508Sbmilekic NULL); 125440516Swpaul if (m == NULL) { 125540516Swpaul ifp->if_ierrors++; 125678508Sbmilekic } 125742051Swpaul cur_rx += total_len + 4 + ETHER_CRC_LEN; 125840516Swpaul } 125940516Swpaul 126040516Swpaul /* 126140516Swpaul * Round up to 32-bit boundary. 126240516Swpaul */ 126340516Swpaul cur_rx = (cur_rx + 3) & ~3; 126440516Swpaul CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 126540516Swpaul 126640516Swpaul if (m == NULL) 126740516Swpaul continue; 126840516Swpaul 126940516Swpaul eh = mtod(m, struct ether_header *); 127040516Swpaul ifp->if_ipackets++; 127140516Swpaul 127240516Swpaul /* Remove header from mbuf and pass it on. */ 127340516Swpaul m_adj(m, sizeof(struct ether_header)); 127440516Swpaul ether_input(ifp, eh, m); 127540516Swpaul } 127640516Swpaul 127740516Swpaul return; 127840516Swpaul} 127940516Swpaul 128040516Swpaul/* 128140516Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 128240516Swpaul * the list buffers. 128340516Swpaul */ 128440516Swpaulstatic void rl_txeof(sc) 128540516Swpaul struct rl_softc *sc; 128640516Swpaul{ 128740516Swpaul struct ifnet *ifp; 128840516Swpaul u_int32_t txstat; 128940516Swpaul 129040516Swpaul ifp = &sc->arpcom.ac_if; 129140516Swpaul 129240516Swpaul /* Clear the timeout timer. */ 129340516Swpaul ifp->if_timer = 0; 129440516Swpaul 129540516Swpaul /* 129640516Swpaul * Go through our tx list and free mbufs for those 129740516Swpaul * frames that have been uploaded. 129840516Swpaul */ 129945633Swpaul do { 130045633Swpaul txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 130145633Swpaul if (!(txstat & (RL_TXSTAT_TX_OK| 130245633Swpaul RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 130340516Swpaul break; 130440516Swpaul 130545633Swpaul ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 130640516Swpaul 130745633Swpaul if (RL_LAST_TXMBUF(sc) != NULL) { 130881713Swpaul bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 130981713Swpaul bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 131045633Swpaul m_freem(RL_LAST_TXMBUF(sc)); 131145633Swpaul RL_LAST_TXMBUF(sc) = NULL; 131245633Swpaul } 131345633Swpaul if (txstat & RL_TXSTAT_TX_OK) 131445633Swpaul ifp->if_opackets++; 131545633Swpaul else { 131652426Swpaul int oldthresh; 131745633Swpaul ifp->if_oerrors++; 131845633Swpaul if ((txstat & RL_TXSTAT_TXABRT) || 131945633Swpaul (txstat & RL_TXSTAT_OUTOFWIN)) 132045633Swpaul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 132152426Swpaul oldthresh = sc->rl_txthresh; 132252426Swpaul /* error recovery */ 132352426Swpaul rl_reset(sc); 132452426Swpaul rl_init(sc); 132552426Swpaul /* 132652426Swpaul * If there was a transmit underrun, 132752426Swpaul * bump the TX threshold. 132852426Swpaul */ 132952426Swpaul if (txstat & RL_TXSTAT_TX_UNDERRUN) 133052426Swpaul sc->rl_txthresh = oldthresh + 32; 133152426Swpaul return; 133245633Swpaul } 133345633Swpaul RL_INC(sc->rl_cdata.last_tx); 133445633Swpaul ifp->if_flags &= ~IFF_OACTIVE; 133545633Swpaul } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 133640516Swpaul 133750703Swpaul return; 133850703Swpaul} 133940516Swpaul 134050703Swpaulstatic void rl_tick(xsc) 134150703Swpaul void *xsc; 134250703Swpaul{ 134350703Swpaul struct rl_softc *sc; 134450703Swpaul struct mii_data *mii; 134550703Swpaul 134650703Swpaul sc = xsc; 134767087Swpaul RL_LOCK(sc); 134850703Swpaul mii = device_get_softc(sc->rl_miibus); 134950703Swpaul 135050703Swpaul mii_tick(mii); 135150703Swpaul 135250703Swpaul sc->rl_stat_ch = timeout(rl_tick, sc, hz); 135367087Swpaul RL_UNLOCK(sc); 135450703Swpaul 135540516Swpaul return; 135640516Swpaul} 135740516Swpaul 135894883Sluigi#ifdef DEVICE_POLLING 135994883Sluigistatic void 136094883Sluigirl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 136194883Sluigi{ 136294883Sluigi struct rl_softc *sc = ifp->if_softc; 136394883Sluigi 136494883Sluigi RL_LOCK(sc); 136594883Sluigi if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 136694883Sluigi CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 136794883Sluigi goto done; 136894883Sluigi } 136994883Sluigi 137094883Sluigi sc->rxcycles = count; 137194883Sluigi rl_rxeof(sc); 137294883Sluigi rl_txeof(sc); 137394883Sluigi if (ifp->if_snd.ifq_head != NULL) 137494883Sluigi rl_start(ifp); 137594883Sluigi 137694883Sluigi if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 137794883Sluigi u_int16_t status; 137894883Sluigi 137994883Sluigi status = CSR_READ_2(sc, RL_ISR); 138094883Sluigi if (status) 138194883Sluigi CSR_WRITE_2(sc, RL_ISR, status); 138294883Sluigi 138394883Sluigi /* 138494883Sluigi * XXX check behaviour on receiver stalls. 138594883Sluigi */ 138694883Sluigi 138794883Sluigi if (status & RL_ISR_SYSTEM_ERR) { 138894883Sluigi rl_reset(sc); 138994883Sluigi rl_init(sc); 139094883Sluigi } 139194883Sluigi } 139294883Sluigidone: 139394883Sluigi RL_UNLOCK(sc); 139494883Sluigi} 139594883Sluigi#endif /* DEVICE_POLLING */ 139694883Sluigi 139740516Swpaulstatic void rl_intr(arg) 139840516Swpaul void *arg; 139940516Swpaul{ 140040516Swpaul struct rl_softc *sc; 140140516Swpaul struct ifnet *ifp; 140240516Swpaul u_int16_t status; 140340516Swpaul 140440516Swpaul sc = arg; 140586822Siwasaki 140686822Siwasaki if (sc->suspended) { 140786822Siwasaki return; 140886822Siwasaki } 140986822Siwasaki 141067087Swpaul RL_LOCK(sc); 141140516Swpaul ifp = &sc->arpcom.ac_if; 141240516Swpaul 141394883Sluigi#ifdef DEVICE_POLLING 141494883Sluigi if (ifp->if_ipending & IFF_POLLING) 141594883Sluigi goto done; 141694883Sluigi if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */ 141794883Sluigi CSR_WRITE_2(sc, RL_IMR, 0x0000); 141894883Sluigi rl_poll(ifp, 0, 1); 141994883Sluigi goto done; 142094883Sluigi } 142194883Sluigi#endif /* DEVICE_POLLING */ 142240516Swpaul 142340516Swpaul for (;;) { 142440516Swpaul 142540516Swpaul status = CSR_READ_2(sc, RL_ISR); 142640516Swpaul if (status) 142740516Swpaul CSR_WRITE_2(sc, RL_ISR, status); 142840516Swpaul 142940516Swpaul if ((status & RL_INTRS) == 0) 143040516Swpaul break; 143140516Swpaul 143240516Swpaul if (status & RL_ISR_RX_OK) 143340516Swpaul rl_rxeof(sc); 143440516Swpaul 143540516Swpaul if (status & RL_ISR_RX_ERR) 143640516Swpaul rl_rxeof(sc); 143740516Swpaul 143845633Swpaul if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 143940516Swpaul rl_txeof(sc); 144040516Swpaul 144140516Swpaul if (status & RL_ISR_SYSTEM_ERR) { 144240516Swpaul rl_reset(sc); 144340516Swpaul rl_init(sc); 144440516Swpaul } 144540516Swpaul 144640516Swpaul } 144740516Swpaul 144852426Swpaul if (ifp->if_snd.ifq_head != NULL) 144940516Swpaul rl_start(ifp); 145040516Swpaul 145194883Sluigi#ifdef DEVICE_POLLING 145294883Sluigidone: 145394883Sluigi#endif 145467087Swpaul RL_UNLOCK(sc); 145567087Swpaul 145640516Swpaul return; 145740516Swpaul} 145840516Swpaul 145940516Swpaul/* 146040516Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 146140516Swpaul * pointers to the fragment pointers. 146240516Swpaul */ 146345633Swpaulstatic int rl_encap(sc, m_head) 146440516Swpaul struct rl_softc *sc; 146540516Swpaul struct mbuf *m_head; 146640516Swpaul{ 146741243Swpaul struct mbuf *m_new = NULL; 146840516Swpaul 146940516Swpaul /* 147045633Swpaul * The RealTek is brain damaged and wants longword-aligned 147145633Swpaul * TX buffers, plus we can only have one fragment buffer 147245633Swpaul * per packet. We have to copy pretty much all the time. 147340516Swpaul */ 147440516Swpaul 147541243Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 147687846Sluigi if (m_new == NULL) 147741243Swpaul return(1); 147841243Swpaul if (m_head->m_pkthdr.len > MHLEN) { 147941243Swpaul MCLGET(m_new, M_DONTWAIT); 148041243Swpaul if (!(m_new->m_flags & M_EXT)) { 148141243Swpaul m_freem(m_new); 148240516Swpaul return(1); 148340516Swpaul } 148440516Swpaul } 148552426Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 148641243Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 148741243Swpaul m_freem(m_head); 148841243Swpaul m_head = m_new; 148940516Swpaul 149040516Swpaul /* Pad frames to at least 60 bytes. */ 149141243Swpaul if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 149255058Swpaul /* 149355058Swpaul * Make security concious people happy: zero out the 149455058Swpaul * bytes in the pad area, since we don't know what 149555058Swpaul * this mbuf cluster buffer's previous user might 149655058Swpaul * have left in it. 149755058Swpaul */ 149855058Swpaul bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 149955058Swpaul RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 150040516Swpaul m_head->m_pkthdr.len += 150152426Swpaul (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 150241243Swpaul m_head->m_len = m_head->m_pkthdr.len; 150341243Swpaul } 150440516Swpaul 150545633Swpaul RL_CUR_TXMBUF(sc) = m_head; 150640516Swpaul 150740516Swpaul return(0); 150840516Swpaul} 150940516Swpaul 151040516Swpaul/* 151140516Swpaul * Main transmit routine. 151240516Swpaul */ 151340516Swpaul 151440516Swpaulstatic void rl_start(ifp) 151540516Swpaul struct ifnet *ifp; 151640516Swpaul{ 151740516Swpaul struct rl_softc *sc; 151840516Swpaul struct mbuf *m_head = NULL; 151940516Swpaul 152040516Swpaul sc = ifp->if_softc; 152167087Swpaul RL_LOCK(sc); 152240516Swpaul 152345633Swpaul while(RL_CUR_TXMBUF(sc) == NULL) { 152440516Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 152540516Swpaul if (m_head == NULL) 152640516Swpaul break; 152740516Swpaul 152858801Swpaul if (rl_encap(sc, m_head)) { 152958801Swpaul IF_PREPEND(&ifp->if_snd, m_head); 153058801Swpaul ifp->if_flags |= IFF_OACTIVE; 153158801Swpaul break; 153258801Swpaul } 153340516Swpaul 153440516Swpaul /* 153540516Swpaul * If there's a BPF listener, bounce a copy of this frame 153640516Swpaul * to him. 153740516Swpaul */ 153840516Swpaul if (ifp->if_bpf) 153945633Swpaul bpf_mtap(ifp, RL_CUR_TXMBUF(sc)); 154051583Swpaul 154140516Swpaul /* 154240516Swpaul * Transmit the frame. 154340516Swpaul */ 154481713Swpaul bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 154581713Swpaul bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 154681713Swpaul mtod(RL_CUR_TXMBUF(sc), void *), 154781713Swpaul RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 154881713Swpaul bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 154981713Swpaul BUS_DMASYNC_PREREAD); 155045633Swpaul CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 155152426Swpaul RL_TXTHRESH(sc->rl_txthresh) | 155252426Swpaul RL_CUR_TXMBUF(sc)->m_pkthdr.len); 155345633Swpaul 155445633Swpaul RL_INC(sc->rl_cdata.cur_tx); 155540516Swpaul } 155640516Swpaul 155740516Swpaul /* 155845633Swpaul * We broke out of the loop because all our TX slots are 155945633Swpaul * full. Mark the NIC as busy until it drains some of the 156045633Swpaul * packets from the queue. 156145633Swpaul */ 156245633Swpaul if (RL_CUR_TXMBUF(sc) != NULL) 156345633Swpaul ifp->if_flags |= IFF_OACTIVE; 156445633Swpaul 156545633Swpaul /* 156640516Swpaul * Set a timeout in case the chip goes out to lunch. 156740516Swpaul */ 156840516Swpaul ifp->if_timer = 5; 156967087Swpaul RL_UNLOCK(sc); 157040516Swpaul 157140516Swpaul return; 157240516Swpaul} 157340516Swpaul 157440516Swpaulstatic void rl_init(xsc) 157540516Swpaul void *xsc; 157640516Swpaul{ 157740516Swpaul struct rl_softc *sc = xsc; 157840516Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 157950703Swpaul struct mii_data *mii; 158067087Swpaul int i; 158140516Swpaul u_int32_t rxcfg = 0; 158240516Swpaul 158367087Swpaul RL_LOCK(sc); 158450703Swpaul mii = device_get_softc(sc->rl_miibus); 158540516Swpaul 158640516Swpaul /* 158740516Swpaul * Cancel pending I/O and free all RX/TX buffers. 158840516Swpaul */ 158940516Swpaul rl_stop(sc); 159040516Swpaul 159140516Swpaul /* Init our MAC address */ 159240516Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) { 159340516Swpaul CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 159440516Swpaul } 159540516Swpaul 159640516Swpaul /* Init the RX buffer pointer register. */ 159781713Swpaul bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 159881713Swpaul sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 159981713Swpaul bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 160081713Swpaul BUS_DMASYNC_PREWRITE); 160140516Swpaul 160240516Swpaul /* Init TX descriptors. */ 160340516Swpaul rl_list_tx_init(sc); 160440516Swpaul 160540516Swpaul /* 160640516Swpaul * Enable transmit and receive. 160740516Swpaul */ 160840516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 160940516Swpaul 161040516Swpaul /* 161145633Swpaul * Set the initial TX and RX configuration. 161240516Swpaul */ 161345633Swpaul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 161440516Swpaul CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 161540516Swpaul 161640516Swpaul /* Set the individual bit to receive frames for this host only. */ 161740516Swpaul rxcfg = CSR_READ_4(sc, RL_RXCFG); 161840516Swpaul rxcfg |= RL_RXCFG_RX_INDIV; 161940516Swpaul 162040516Swpaul /* If we want promiscuous mode, set the allframes bit. */ 162140516Swpaul if (ifp->if_flags & IFF_PROMISC) { 162240516Swpaul rxcfg |= RL_RXCFG_RX_ALLPHYS; 162340516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 162440516Swpaul } else { 162540516Swpaul rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 162640516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 162740516Swpaul } 162840516Swpaul 162940516Swpaul /* 163040516Swpaul * Set capture broadcast bit to capture broadcast frames. 163140516Swpaul */ 163240516Swpaul if (ifp->if_flags & IFF_BROADCAST) { 163340516Swpaul rxcfg |= RL_RXCFG_RX_BROAD; 163440516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 163540516Swpaul } else { 163640516Swpaul rxcfg &= ~RL_RXCFG_RX_BROAD; 163740516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 163840516Swpaul } 163940516Swpaul 164040516Swpaul /* 164140516Swpaul * Program the multicast filter, if necessary. 164240516Swpaul */ 164340516Swpaul rl_setmulti(sc); 164440516Swpaul 164594883Sluigi#ifdef DEVICE_POLLING 164640516Swpaul /* 164794883Sluigi * Disable interrupts if we are polling. 164894883Sluigi */ 164994883Sluigi if (ifp->if_ipending & IFF_POLLING) 165094883Sluigi CSR_WRITE_2(sc, RL_IMR, 0); 165194883Sluigi else /* otherwise ... */ 165294883Sluigi#endif /* DEVICE_POLLING */ 165394883Sluigi /* 165440516Swpaul * Enable interrupts. 165540516Swpaul */ 165640516Swpaul CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 165740516Swpaul 165852426Swpaul /* Set initial TX threshold */ 165952426Swpaul sc->rl_txthresh = RL_TX_THRESH_INIT; 166052426Swpaul 166140516Swpaul /* Start RX/TX process. */ 166240516Swpaul CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 166340516Swpaul 166440516Swpaul /* Enable receiver and transmitter. */ 166540516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 166640516Swpaul 166750703Swpaul mii_mediachg(mii); 166840516Swpaul 166940516Swpaul CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 167040516Swpaul 167140516Swpaul ifp->if_flags |= IFF_RUNNING; 167240516Swpaul ifp->if_flags &= ~IFF_OACTIVE; 167340516Swpaul 167450703Swpaul sc->rl_stat_ch = timeout(rl_tick, sc, hz); 167567087Swpaul RL_UNLOCK(sc); 167650703Swpaul 167740516Swpaul return; 167840516Swpaul} 167940516Swpaul 168040516Swpaul/* 168140516Swpaul * Set media options. 168240516Swpaul */ 168340516Swpaulstatic int rl_ifmedia_upd(ifp) 168440516Swpaul struct ifnet *ifp; 168540516Swpaul{ 168640516Swpaul struct rl_softc *sc; 168750703Swpaul struct mii_data *mii; 168840516Swpaul 168940516Swpaul sc = ifp->if_softc; 169050703Swpaul mii = device_get_softc(sc->rl_miibus); 169150703Swpaul mii_mediachg(mii); 169240516Swpaul 169340516Swpaul return(0); 169440516Swpaul} 169540516Swpaul 169640516Swpaul/* 169740516Swpaul * Report current media status. 169840516Swpaul */ 169940516Swpaulstatic void rl_ifmedia_sts(ifp, ifmr) 170040516Swpaul struct ifnet *ifp; 170140516Swpaul struct ifmediareq *ifmr; 170240516Swpaul{ 170340516Swpaul struct rl_softc *sc; 170450703Swpaul struct mii_data *mii; 170540516Swpaul 170640516Swpaul sc = ifp->if_softc; 170750703Swpaul mii = device_get_softc(sc->rl_miibus); 170840516Swpaul 170950703Swpaul mii_pollstat(mii); 171050703Swpaul ifmr->ifm_active = mii->mii_media_active; 171150703Swpaul ifmr->ifm_status = mii->mii_media_status; 171240516Swpaul 171340516Swpaul return; 171440516Swpaul} 171540516Swpaul 171640516Swpaulstatic int rl_ioctl(ifp, command, data) 171740516Swpaul struct ifnet *ifp; 171840516Swpaul u_long command; 171940516Swpaul caddr_t data; 172040516Swpaul{ 172140516Swpaul struct rl_softc *sc = ifp->if_softc; 172240516Swpaul struct ifreq *ifr = (struct ifreq *) data; 172350703Swpaul struct mii_data *mii; 172467087Swpaul int error = 0; 172540516Swpaul 172667087Swpaul RL_LOCK(sc); 172740516Swpaul 172840516Swpaul switch(command) { 172940516Swpaul case SIOCSIFADDR: 173040516Swpaul case SIOCGIFADDR: 173140516Swpaul case SIOCSIFMTU: 173240516Swpaul error = ether_ioctl(ifp, command, data); 173340516Swpaul break; 173440516Swpaul case SIOCSIFFLAGS: 173540516Swpaul if (ifp->if_flags & IFF_UP) { 173640516Swpaul rl_init(sc); 173740516Swpaul } else { 173840516Swpaul if (ifp->if_flags & IFF_RUNNING) 173940516Swpaul rl_stop(sc); 174040516Swpaul } 174140516Swpaul error = 0; 174240516Swpaul break; 174340516Swpaul case SIOCADDMULTI: 174440516Swpaul case SIOCDELMULTI: 174540516Swpaul rl_setmulti(sc); 174640516Swpaul error = 0; 174740516Swpaul break; 174840516Swpaul case SIOCGIFMEDIA: 174940516Swpaul case SIOCSIFMEDIA: 175050703Swpaul mii = device_get_softc(sc->rl_miibus); 175150703Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 175240516Swpaul break; 175340516Swpaul default: 175440516Swpaul error = EINVAL; 175540516Swpaul break; 175640516Swpaul } 175740516Swpaul 175867087Swpaul RL_UNLOCK(sc); 175940516Swpaul 176040516Swpaul return(error); 176140516Swpaul} 176240516Swpaul 176340516Swpaulstatic void rl_watchdog(ifp) 176440516Swpaul struct ifnet *ifp; 176540516Swpaul{ 176640516Swpaul struct rl_softc *sc; 176740516Swpaul 176840516Swpaul sc = ifp->if_softc; 176967087Swpaul RL_LOCK(sc); 177040516Swpaul printf("rl%d: watchdog timeout\n", sc->rl_unit); 177140516Swpaul ifp->if_oerrors++; 177250703Swpaul 177340516Swpaul rl_txeof(sc); 177440516Swpaul rl_rxeof(sc); 177540516Swpaul rl_init(sc); 177667087Swpaul RL_UNLOCK(sc); 177740516Swpaul 177840516Swpaul return; 177940516Swpaul} 178040516Swpaul 178140516Swpaul/* 178240516Swpaul * Stop the adapter and free any mbufs allocated to the 178340516Swpaul * RX and TX lists. 178440516Swpaul */ 178540516Swpaulstatic void rl_stop(sc) 178640516Swpaul struct rl_softc *sc; 178740516Swpaul{ 178840516Swpaul register int i; 178940516Swpaul struct ifnet *ifp; 179040516Swpaul 179167087Swpaul RL_LOCK(sc); 179240516Swpaul ifp = &sc->arpcom.ac_if; 179340516Swpaul ifp->if_timer = 0; 179440516Swpaul 179550703Swpaul untimeout(rl_tick, sc, sc->rl_stat_ch); 179694883Sluigi ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 179794883Sluigi#ifdef DEVICE_POLLING 179894883Sluigi ether_poll_deregister(ifp); 179994883Sluigi#endif /* DEVICE_POLLING */ 180050703Swpaul 180140516Swpaul CSR_WRITE_1(sc, RL_COMMAND, 0x00); 180240516Swpaul CSR_WRITE_2(sc, RL_IMR, 0x0000); 180381713Swpaul bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 180440516Swpaul 180540516Swpaul /* 180640516Swpaul * Free the TX list buffers. 180740516Swpaul */ 180840516Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 180945633Swpaul if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 181081713Swpaul bus_dmamap_unload(sc->rl_tag, 181181713Swpaul sc->rl_cdata.rl_tx_dmamap[i]); 181281713Swpaul bus_dmamap_destroy(sc->rl_tag, 181381713Swpaul sc->rl_cdata.rl_tx_dmamap[i]); 181445633Swpaul m_freem(sc->rl_cdata.rl_tx_chain[i]); 181545633Swpaul sc->rl_cdata.rl_tx_chain[i] = NULL; 181645633Swpaul CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 181740516Swpaul } 181840516Swpaul } 181940516Swpaul 182067087Swpaul RL_UNLOCK(sc); 182140516Swpaul return; 182240516Swpaul} 182340516Swpaul 182440516Swpaul/* 182586822Siwasaki * Device suspend routine. Stop the interface and save some PCI 182686822Siwasaki * settings in case the BIOS doesn't restore them properly on 182786822Siwasaki * resume. 182886822Siwasaki */ 182986822Siwasakistatic int rl_suspend(dev) 183086822Siwasaki device_t dev; 183186822Siwasaki{ 183286822Siwasaki register int i; 183386822Siwasaki struct rl_softc *sc; 183486822Siwasaki 183586822Siwasaki sc = device_get_softc(dev); 183686822Siwasaki 183786822Siwasaki rl_stop(sc); 183886822Siwasaki 183986822Siwasaki for (i = 0; i < 5; i++) 184086822Siwasaki sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 184186822Siwasaki sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 184286822Siwasaki sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 184386822Siwasaki sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 184486822Siwasaki sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 184586822Siwasaki 184686822Siwasaki sc->suspended = 1; 184786822Siwasaki 184886822Siwasaki return (0); 184986822Siwasaki} 185086822Siwasaki 185186822Siwasaki/* 185286822Siwasaki * Device resume routine. Restore some PCI settings in case the BIOS 185386822Siwasaki * doesn't, re-enable busmastering, and restart the interface if 185486822Siwasaki * appropriate. 185586822Siwasaki */ 185686822Siwasakistatic int rl_resume(dev) 185786822Siwasaki device_t dev; 185886822Siwasaki{ 185986822Siwasaki register int i; 186086822Siwasaki struct rl_softc *sc; 186186822Siwasaki struct ifnet *ifp; 186286822Siwasaki 186386822Siwasaki sc = device_get_softc(dev); 186486822Siwasaki ifp = &sc->arpcom.ac_if; 186586822Siwasaki 186686822Siwasaki /* better way to do this? */ 186786822Siwasaki for (i = 0; i < 5; i++) 186886822Siwasaki pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 186986822Siwasaki pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 187086822Siwasaki pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 187186822Siwasaki pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 187286822Siwasaki pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 187386822Siwasaki 187486822Siwasaki /* reenable busmastering */ 187586822Siwasaki pci_enable_busmaster(dev); 187686822Siwasaki pci_enable_io(dev, RL_RES); 187786822Siwasaki 187886822Siwasaki /* reinitialize interface if necessary */ 187986822Siwasaki if (ifp->if_flags & IFF_UP) 188086822Siwasaki rl_init(sc); 188186822Siwasaki 188286822Siwasaki sc->suspended = 0; 188386822Siwasaki 188486822Siwasaki return (0); 188586822Siwasaki} 188686822Siwasaki 188786822Siwasaki/* 188840516Swpaul * Stop all chip I/O so that the kernel's probe routines don't 188940516Swpaul * get confused by errant DMAs when rebooting. 189040516Swpaul */ 189150703Swpaulstatic void rl_shutdown(dev) 189250703Swpaul device_t dev; 189340516Swpaul{ 189450703Swpaul struct rl_softc *sc; 189540516Swpaul 189650703Swpaul sc = device_get_softc(dev); 189750703Swpaul 189840516Swpaul rl_stop(sc); 189940516Swpaul 190040516Swpaul return; 190140516Swpaul} 1902