if_rl.c revision 93818
140516Swpaul/* 240516Swpaul * Copyright (c) 1997, 1998 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_rl.c 93818 2002-04-04 21:03:38Z jhb $ 3340516Swpaul */ 3440516Swpaul 3540516Swpaul/* 3640516Swpaul * RealTek 8129/8139 PCI NIC driver 3740516Swpaul * 3840516Swpaul * Supports several extremely cheap PCI 10/100 adapters based on 3940516Swpaul * the RealTek chipset. Datasheets can be obtained from 4040516Swpaul * www.realtek.com.tw. 4140516Swpaul * 4240516Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4340516Swpaul * Electrical Engineering Department 4440516Swpaul * Columbia University, New York City 4540516Swpaul */ 4640516Swpaul 4740516Swpaul/* 4840516Swpaul * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 4940516Swpaul * probably the worst PCI ethernet controller ever made, with the possible 5040516Swpaul * exception of the FEAST chip made by SMC. The 8139 supports bus-master 5140516Swpaul * DMA, but it has a terrible interface that nullifies any performance 5240516Swpaul * gains that bus-master DMA usually offers. 5340516Swpaul * 5440516Swpaul * For transmission, the chip offers a series of four TX descriptor 5540516Swpaul * registers. Each transmit frame must be in a contiguous buffer, aligned 5641569Swpaul * on a longword (32-bit) boundary. This means we almost always have to 5740516Swpaul * do mbuf copies in order to transmit a frame, except in the unlikely 5840516Swpaul * case where a) the packet fits into a single mbuf, and b) the packet 5940516Swpaul * is 32-bit aligned within the mbuf's data area. The presence of only 6040516Swpaul * four descriptor registers means that we can never have more than four 6140516Swpaul * packets queued for transmission at any one time. 6240516Swpaul * 6340516Swpaul * Reception is not much better. The driver has to allocate a single large 6440516Swpaul * buffer area (up to 64K in size) into which the chip will DMA received 6540516Swpaul * frames. Because we don't know where within this region received packets 6640516Swpaul * will begin or end, we have no choice but to copy data from the buffer 6740516Swpaul * area into mbufs in order to pass the packets up to the higher protocol 6840516Swpaul * levels. 6940516Swpaul * 7040516Swpaul * It's impossible given this rotten design to really achieve decent 7140516Swpaul * performance at 100Mbps, unless you happen to have a 400Mhz PII or 7240516Swpaul * some equally overmuscled CPU to drive it. 7340516Swpaul * 7440516Swpaul * On the bright side, the 8139 does have a built-in PHY, although 7540516Swpaul * rather than using an MDIO serial interface like most other NICs, the 7640516Swpaul * PHY registers are directly accessible through the 8139's register 7740516Swpaul * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 7840516Swpaul * filter. 7940516Swpaul * 8040516Swpaul * The 8129 chip is an older version of the 8139 that uses an external PHY 8140516Swpaul * chip. The 8129 has a serial MDIO interface for accessing the MII where 8240516Swpaul * the 8139 lets you directly access the on-board PHY registers. We need 8340516Swpaul * to select which interface to use depending on the chip type. 8440516Swpaul */ 8540516Swpaul 8640516Swpaul#include <sys/param.h> 8740516Swpaul#include <sys/systm.h> 8840516Swpaul#include <sys/sockio.h> 8940516Swpaul#include <sys/mbuf.h> 9040516Swpaul#include <sys/malloc.h> 9140516Swpaul#include <sys/kernel.h> 9240516Swpaul#include <sys/socket.h> 9340516Swpaul 9440516Swpaul#include <net/if.h> 9540516Swpaul#include <net/if_arp.h> 9640516Swpaul#include <net/ethernet.h> 9740516Swpaul#include <net/if_dl.h> 9840516Swpaul#include <net/if_media.h> 9940516Swpaul 10040516Swpaul#include <net/bpf.h> 10140516Swpaul 10241569Swpaul#include <machine/bus_pio.h> 10341569Swpaul#include <machine/bus_memio.h> 10441569Swpaul#include <machine/bus.h> 10550703Swpaul#include <machine/resource.h> 10650703Swpaul#include <sys/bus.h> 10750703Swpaul#include <sys/rman.h> 10840516Swpaul 10950703Swpaul#include <dev/mii/mii.h> 11050703Swpaul#include <dev/mii/miivar.h> 11150703Swpaul 11240516Swpaul#include <pci/pcireg.h> 11340516Swpaul#include <pci/pcivar.h> 11440516Swpaul 11559758SpeterMODULE_DEPEND(rl, miibus, 1, 1, 1); 11659758Speter 11751089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 11850703Swpaul#include "miibus_if.h" 11950703Swpaul 12040516Swpaul/* 12140516Swpaul * Default to using PIO access for this driver. On SMP systems, 12240516Swpaul * there appear to be problems with memory mapped mode: it looks like 12340516Swpaul * doing too many memory mapped access back to back in rapid succession 12440516Swpaul * can hang the bus. I'm inclined to blame this on crummy design/construction 12540516Swpaul * on the part of RealTek. Memory mapped mode does appear to work on 12640516Swpaul * uniprocessor systems though. 12740516Swpaul */ 12840516Swpaul#define RL_USEIOSPACE 12940516Swpaul 13040516Swpaul#include <pci/if_rlreg.h> 13140516Swpaul 13240516Swpaul#ifndef lint 13341591Sarchiestatic const char rcsid[] = 13450477Speter "$FreeBSD: head/sys/pci/if_rl.c 93818 2002-04-04 21:03:38Z jhb $"; 13540516Swpaul#endif 13640516Swpaul 13740516Swpaul/* 13840516Swpaul * Various supported device vendors/types and their names. 13940516Swpaul */ 14040516Swpaulstatic struct rl_type rl_devs[] = { 14140516Swpaul { RT_VENDORID, RT_DEVICEID_8129, 14240516Swpaul "RealTek 8129 10/100BaseTX" }, 14340516Swpaul { RT_VENDORID, RT_DEVICEID_8139, 14440516Swpaul "RealTek 8139 10/100BaseTX" }, 14567771Swpaul { RT_VENDORID, RT_DEVICEID_8138, 14667771Swpaul "RealTek 8139 10/100BaseTX CardBus" }, 14741243Swpaul { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 14841243Swpaul "Accton MPX 5030/5038 10/100BaseTX" }, 14944238Swpaul { DELTA_VENDORID, DELTA_DEVICEID_8139, 15044238Swpaul "Delta Electronics 8139 10/100BaseTX" }, 15144238Swpaul { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 15244238Swpaul "Addtron Technolgy 8139 10/100BaseTX" }, 15372813Swpaul { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, 15472813Swpaul "D-Link DFE-530TX+ 10/100BaseTX" }, 15540516Swpaul { 0, 0, NULL } 15640516Swpaul}; 15740516Swpaul 15892739Salfredstatic int rl_probe (device_t); 15992739Salfredstatic int rl_attach (device_t); 16092739Salfredstatic int rl_detach (device_t); 16140516Swpaul 16292739Salfredstatic int rl_encap (struct rl_softc *, struct mbuf * ); 16340516Swpaul 16492739Salfredstatic void rl_rxeof (struct rl_softc *); 16592739Salfredstatic void rl_txeof (struct rl_softc *); 16692739Salfredstatic void rl_intr (void *); 16792739Salfredstatic void rl_tick (void *); 16892739Salfredstatic void rl_start (struct ifnet *); 16992739Salfredstatic int rl_ioctl (struct ifnet *, u_long, caddr_t); 17092739Salfredstatic void rl_init (void *); 17192739Salfredstatic void rl_stop (struct rl_softc *); 17292739Salfredstatic void rl_watchdog (struct ifnet *); 17392739Salfredstatic int rl_suspend (device_t); 17492739Salfredstatic int rl_resume (device_t); 17592739Salfredstatic void rl_shutdown (device_t); 17692739Salfredstatic int rl_ifmedia_upd (struct ifnet *); 17792739Salfredstatic void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 17840516Swpaul 17992739Salfredstatic void rl_eeprom_putbyte (struct rl_softc *, int); 18092739Salfredstatic void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *); 18192739Salfredstatic void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 18292739Salfredstatic void rl_mii_sync (struct rl_softc *); 18392739Salfredstatic void rl_mii_send (struct rl_softc *, u_int32_t, int); 18492739Salfredstatic int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *); 18592739Salfredstatic int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *); 18640516Swpaul 18792739Salfredstatic int rl_miibus_readreg (device_t, int, int); 18892739Salfredstatic int rl_miibus_writereg (device_t, int, int, int); 18992739Salfredstatic void rl_miibus_statchg (device_t); 19040516Swpaul 19192739Salfredstatic u_int8_t rl_calchash (caddr_t); 19292739Salfredstatic void rl_setmulti (struct rl_softc *); 19392739Salfredstatic void rl_reset (struct rl_softc *); 19492739Salfredstatic int rl_list_tx_init (struct rl_softc *); 19540516Swpaul 19692739Salfredstatic void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int); 19792739Salfredstatic void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int); 19881713Swpaul 19950703Swpaul#ifdef RL_USEIOSPACE 20050703Swpaul#define RL_RES SYS_RES_IOPORT 20150703Swpaul#define RL_RID RL_PCI_LOIO 20250703Swpaul#else 20350703Swpaul#define RL_RES SYS_RES_MEMORY 20450703Swpaul#define RL_RID RL_PCI_LOMEM 20550703Swpaul#endif 20650703Swpaul 20750703Swpaulstatic device_method_t rl_methods[] = { 20850703Swpaul /* Device interface */ 20950703Swpaul DEVMETHOD(device_probe, rl_probe), 21050703Swpaul DEVMETHOD(device_attach, rl_attach), 21150703Swpaul DEVMETHOD(device_detach, rl_detach), 21286822Siwasaki DEVMETHOD(device_suspend, rl_suspend), 21386822Siwasaki DEVMETHOD(device_resume, rl_resume), 21450703Swpaul DEVMETHOD(device_shutdown, rl_shutdown), 21550703Swpaul 21650703Swpaul /* bus interface */ 21750703Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 21850703Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 21950703Swpaul 22050703Swpaul /* MII interface */ 22150703Swpaul DEVMETHOD(miibus_readreg, rl_miibus_readreg), 22250703Swpaul DEVMETHOD(miibus_writereg, rl_miibus_writereg), 22350703Swpaul DEVMETHOD(miibus_statchg, rl_miibus_statchg), 22450703Swpaul 22550703Swpaul { 0, 0 } 22650703Swpaul}; 22750703Swpaul 22850703Swpaulstatic driver_t rl_driver = { 22951455Swpaul "rl", 23050703Swpaul rl_methods, 23150703Swpaul sizeof(struct rl_softc) 23250703Swpaul}; 23350703Swpaul 23450703Swpaulstatic devclass_t rl_devclass; 23550703Swpaul 23651533SwpaulDRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 23767931SwpaulDRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0); 23851473SwpaulDRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 23950703Swpaul 24040516Swpaul#define EE_SET(x) \ 24140516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 24240516Swpaul CSR_READ_1(sc, RL_EECMD) | x) 24340516Swpaul 24440516Swpaul#define EE_CLR(x) \ 24540516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 24640516Swpaul CSR_READ_1(sc, RL_EECMD) & ~x) 24740516Swpaul 24881713Swpaulstatic void 24981713Swpaulrl_dma_map_rxbuf(arg, segs, nseg, error) 25081713Swpaul void *arg; 25181713Swpaul bus_dma_segment_t *segs; 25281713Swpaul int nseg, error; 25381713Swpaul{ 25481713Swpaul struct rl_softc *sc; 25581713Swpaul 25681713Swpaul sc = arg; 25781713Swpaul CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 25881713Swpaul 25981713Swpaul return; 26081713Swpaul} 26181713Swpaul 26281713Swpaulstatic void 26381713Swpaulrl_dma_map_txbuf(arg, segs, nseg, error) 26481713Swpaul void *arg; 26581713Swpaul bus_dma_segment_t *segs; 26681713Swpaul int nseg, error; 26781713Swpaul{ 26881713Swpaul struct rl_softc *sc; 26981713Swpaul 27081713Swpaul sc = arg; 27181713Swpaul CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 27281713Swpaul 27381713Swpaul return; 27481713Swpaul} 27581713Swpaul 27640516Swpaul/* 27740516Swpaul * Send a read command and address to the EEPROM, check for ACK. 27840516Swpaul */ 27940516Swpaulstatic void rl_eeprom_putbyte(sc, addr) 28040516Swpaul struct rl_softc *sc; 28141656Swpaul int addr; 28240516Swpaul{ 28340516Swpaul register int d, i; 28440516Swpaul 28567931Swpaul d = addr | sc->rl_eecmd_read; 28640516Swpaul 28740516Swpaul /* 28855170Sbillf * Feed in each bit and strobe the clock. 28940516Swpaul */ 29040516Swpaul for (i = 0x400; i; i >>= 1) { 29140516Swpaul if (d & i) { 29240516Swpaul EE_SET(RL_EE_DATAIN); 29340516Swpaul } else { 29440516Swpaul EE_CLR(RL_EE_DATAIN); 29540516Swpaul } 29640516Swpaul DELAY(100); 29740516Swpaul EE_SET(RL_EE_CLK); 29840516Swpaul DELAY(150); 29940516Swpaul EE_CLR(RL_EE_CLK); 30040516Swpaul DELAY(100); 30140516Swpaul } 30240516Swpaul 30340516Swpaul return; 30440516Swpaul} 30540516Swpaul 30640516Swpaul/* 30740516Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 30840516Swpaul */ 30940516Swpaulstatic void rl_eeprom_getword(sc, addr, dest) 31040516Swpaul struct rl_softc *sc; 31141656Swpaul int addr; 31240516Swpaul u_int16_t *dest; 31340516Swpaul{ 31440516Swpaul register int i; 31540516Swpaul u_int16_t word = 0; 31640516Swpaul 31740516Swpaul /* Enter EEPROM access mode. */ 31840516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 31940516Swpaul 32040516Swpaul /* 32140516Swpaul * Send address of word we want to read. 32240516Swpaul */ 32340516Swpaul rl_eeprom_putbyte(sc, addr); 32440516Swpaul 32540516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 32640516Swpaul 32740516Swpaul /* 32840516Swpaul * Start reading bits from EEPROM. 32940516Swpaul */ 33040516Swpaul for (i = 0x8000; i; i >>= 1) { 33140516Swpaul EE_SET(RL_EE_CLK); 33240516Swpaul DELAY(100); 33340516Swpaul if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 33440516Swpaul word |= i; 33540516Swpaul EE_CLR(RL_EE_CLK); 33640516Swpaul DELAY(100); 33740516Swpaul } 33840516Swpaul 33940516Swpaul /* Turn off EEPROM access mode. */ 34040516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 34140516Swpaul 34240516Swpaul *dest = word; 34340516Swpaul 34440516Swpaul return; 34540516Swpaul} 34640516Swpaul 34740516Swpaul/* 34840516Swpaul * Read a sequence of words from the EEPROM. 34940516Swpaul */ 35040516Swpaulstatic void rl_read_eeprom(sc, dest, off, cnt, swap) 35140516Swpaul struct rl_softc *sc; 35240516Swpaul caddr_t dest; 35340516Swpaul int off; 35440516Swpaul int cnt; 35540516Swpaul int swap; 35640516Swpaul{ 35740516Swpaul int i; 35840516Swpaul u_int16_t word = 0, *ptr; 35940516Swpaul 36040516Swpaul for (i = 0; i < cnt; i++) { 36140516Swpaul rl_eeprom_getword(sc, off + i, &word); 36240516Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 36340516Swpaul if (swap) 36440516Swpaul *ptr = ntohs(word); 36540516Swpaul else 36640516Swpaul *ptr = word; 36740516Swpaul } 36840516Swpaul 36940516Swpaul return; 37040516Swpaul} 37140516Swpaul 37240516Swpaul 37340516Swpaul/* 37440516Swpaul * MII access routines are provided for the 8129, which 37540516Swpaul * doesn't have a built-in PHY. For the 8139, we fake things 37640516Swpaul * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 37740516Swpaul * direct access PHY registers. 37840516Swpaul */ 37940516Swpaul#define MII_SET(x) \ 38040516Swpaul CSR_WRITE_1(sc, RL_MII, \ 38140516Swpaul CSR_READ_1(sc, RL_MII) | x) 38240516Swpaul 38340516Swpaul#define MII_CLR(x) \ 38440516Swpaul CSR_WRITE_1(sc, RL_MII, \ 38540516Swpaul CSR_READ_1(sc, RL_MII) & ~x) 38640516Swpaul 38740516Swpaul/* 38840516Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 38940516Swpaul */ 39040516Swpaulstatic void rl_mii_sync(sc) 39140516Swpaul struct rl_softc *sc; 39240516Swpaul{ 39340516Swpaul register int i; 39440516Swpaul 39540516Swpaul MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 39640516Swpaul 39740516Swpaul for (i = 0; i < 32; i++) { 39840516Swpaul MII_SET(RL_MII_CLK); 39940516Swpaul DELAY(1); 40040516Swpaul MII_CLR(RL_MII_CLK); 40140516Swpaul DELAY(1); 40240516Swpaul } 40340516Swpaul 40440516Swpaul return; 40540516Swpaul} 40640516Swpaul 40740516Swpaul/* 40840516Swpaul * Clock a series of bits through the MII. 40940516Swpaul */ 41040516Swpaulstatic void rl_mii_send(sc, bits, cnt) 41140516Swpaul struct rl_softc *sc; 41240516Swpaul u_int32_t bits; 41340516Swpaul int cnt; 41440516Swpaul{ 41540516Swpaul int i; 41640516Swpaul 41740516Swpaul MII_CLR(RL_MII_CLK); 41840516Swpaul 41940516Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 42040516Swpaul if (bits & i) { 42140516Swpaul MII_SET(RL_MII_DATAOUT); 42240516Swpaul } else { 42340516Swpaul MII_CLR(RL_MII_DATAOUT); 42440516Swpaul } 42540516Swpaul DELAY(1); 42640516Swpaul MII_CLR(RL_MII_CLK); 42740516Swpaul DELAY(1); 42840516Swpaul MII_SET(RL_MII_CLK); 42940516Swpaul } 43040516Swpaul} 43140516Swpaul 43240516Swpaul/* 43340516Swpaul * Read an PHY register through the MII. 43440516Swpaul */ 43540516Swpaulstatic int rl_mii_readreg(sc, frame) 43640516Swpaul struct rl_softc *sc; 43740516Swpaul struct rl_mii_frame *frame; 43840516Swpaul 43940516Swpaul{ 44067087Swpaul int i, ack; 44140516Swpaul 44267087Swpaul RL_LOCK(sc); 44340516Swpaul 44440516Swpaul /* 44540516Swpaul * Set up frame for RX. 44640516Swpaul */ 44740516Swpaul frame->mii_stdelim = RL_MII_STARTDELIM; 44840516Swpaul frame->mii_opcode = RL_MII_READOP; 44940516Swpaul frame->mii_turnaround = 0; 45040516Swpaul frame->mii_data = 0; 45140516Swpaul 45240516Swpaul CSR_WRITE_2(sc, RL_MII, 0); 45340516Swpaul 45440516Swpaul /* 45540516Swpaul * Turn on data xmit. 45640516Swpaul */ 45740516Swpaul MII_SET(RL_MII_DIR); 45840516Swpaul 45940516Swpaul rl_mii_sync(sc); 46040516Swpaul 46140516Swpaul /* 46240516Swpaul * Send command/address info. 46340516Swpaul */ 46440516Swpaul rl_mii_send(sc, frame->mii_stdelim, 2); 46540516Swpaul rl_mii_send(sc, frame->mii_opcode, 2); 46640516Swpaul rl_mii_send(sc, frame->mii_phyaddr, 5); 46740516Swpaul rl_mii_send(sc, frame->mii_regaddr, 5); 46840516Swpaul 46940516Swpaul /* Idle bit */ 47040516Swpaul MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 47140516Swpaul DELAY(1); 47240516Swpaul MII_SET(RL_MII_CLK); 47340516Swpaul DELAY(1); 47440516Swpaul 47540516Swpaul /* Turn off xmit. */ 47640516Swpaul MII_CLR(RL_MII_DIR); 47740516Swpaul 47840516Swpaul /* Check for ack */ 47940516Swpaul MII_CLR(RL_MII_CLK); 48040516Swpaul DELAY(1); 48140516Swpaul MII_SET(RL_MII_CLK); 48240516Swpaul DELAY(1); 48340516Swpaul ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 48440516Swpaul 48540516Swpaul /* 48640516Swpaul * Now try reading data bits. If the ack failed, we still 48740516Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 48840516Swpaul */ 48940516Swpaul if (ack) { 49040516Swpaul for(i = 0; i < 16; i++) { 49140516Swpaul MII_CLR(RL_MII_CLK); 49240516Swpaul DELAY(1); 49340516Swpaul MII_SET(RL_MII_CLK); 49440516Swpaul DELAY(1); 49540516Swpaul } 49640516Swpaul goto fail; 49740516Swpaul } 49840516Swpaul 49940516Swpaul for (i = 0x8000; i; i >>= 1) { 50040516Swpaul MII_CLR(RL_MII_CLK); 50140516Swpaul DELAY(1); 50240516Swpaul if (!ack) { 50340516Swpaul if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 50440516Swpaul frame->mii_data |= i; 50540516Swpaul DELAY(1); 50640516Swpaul } 50740516Swpaul MII_SET(RL_MII_CLK); 50840516Swpaul DELAY(1); 50940516Swpaul } 51040516Swpaul 51140516Swpaulfail: 51240516Swpaul 51340516Swpaul MII_CLR(RL_MII_CLK); 51440516Swpaul DELAY(1); 51540516Swpaul MII_SET(RL_MII_CLK); 51640516Swpaul DELAY(1); 51740516Swpaul 51867087Swpaul RL_UNLOCK(sc); 51940516Swpaul 52040516Swpaul if (ack) 52140516Swpaul return(1); 52240516Swpaul return(0); 52340516Swpaul} 52440516Swpaul 52540516Swpaul/* 52640516Swpaul * Write to a PHY register through the MII. 52740516Swpaul */ 52840516Swpaulstatic int rl_mii_writereg(sc, frame) 52940516Swpaul struct rl_softc *sc; 53040516Swpaul struct rl_mii_frame *frame; 53140516Swpaul 53240516Swpaul{ 53367087Swpaul RL_LOCK(sc); 53440516Swpaul 53540516Swpaul /* 53640516Swpaul * Set up frame for TX. 53740516Swpaul */ 53840516Swpaul 53940516Swpaul frame->mii_stdelim = RL_MII_STARTDELIM; 54040516Swpaul frame->mii_opcode = RL_MII_WRITEOP; 54140516Swpaul frame->mii_turnaround = RL_MII_TURNAROUND; 54240516Swpaul 54340516Swpaul /* 54440516Swpaul * Turn on data output. 54540516Swpaul */ 54640516Swpaul MII_SET(RL_MII_DIR); 54740516Swpaul 54840516Swpaul rl_mii_sync(sc); 54940516Swpaul 55040516Swpaul rl_mii_send(sc, frame->mii_stdelim, 2); 55140516Swpaul rl_mii_send(sc, frame->mii_opcode, 2); 55240516Swpaul rl_mii_send(sc, frame->mii_phyaddr, 5); 55340516Swpaul rl_mii_send(sc, frame->mii_regaddr, 5); 55440516Swpaul rl_mii_send(sc, frame->mii_turnaround, 2); 55540516Swpaul rl_mii_send(sc, frame->mii_data, 16); 55640516Swpaul 55740516Swpaul /* Idle bit. */ 55840516Swpaul MII_SET(RL_MII_CLK); 55940516Swpaul DELAY(1); 56040516Swpaul MII_CLR(RL_MII_CLK); 56140516Swpaul DELAY(1); 56240516Swpaul 56340516Swpaul /* 56440516Swpaul * Turn off xmit. 56540516Swpaul */ 56640516Swpaul MII_CLR(RL_MII_DIR); 56740516Swpaul 56867087Swpaul RL_UNLOCK(sc); 56940516Swpaul 57040516Swpaul return(0); 57140516Swpaul} 57240516Swpaul 57350703Swpaulstatic int rl_miibus_readreg(dev, phy, reg) 57450703Swpaul device_t dev; 57550703Swpaul int phy, reg; 57650703Swpaul{ 57740516Swpaul struct rl_softc *sc; 57840516Swpaul struct rl_mii_frame frame; 57940516Swpaul u_int16_t rval = 0; 58040516Swpaul u_int16_t rl8139_reg = 0; 58140516Swpaul 58250703Swpaul sc = device_get_softc(dev); 58367087Swpaul RL_LOCK(sc); 58450703Swpaul 58540516Swpaul if (sc->rl_type == RL_8139) { 58650703Swpaul /* Pretend the internal PHY is only at address 0 */ 58767087Swpaul if (phy) { 58867087Swpaul RL_UNLOCK(sc); 58950703Swpaul return(0); 59067087Swpaul } 59140516Swpaul switch(reg) { 59250703Swpaul case MII_BMCR: 59340516Swpaul rl8139_reg = RL_BMCR; 59440516Swpaul break; 59550703Swpaul case MII_BMSR: 59640516Swpaul rl8139_reg = RL_BMSR; 59740516Swpaul break; 59850703Swpaul case MII_ANAR: 59940516Swpaul rl8139_reg = RL_ANAR; 60040516Swpaul break; 60150703Swpaul case MII_ANER: 60250703Swpaul rl8139_reg = RL_ANER; 60350703Swpaul break; 60450703Swpaul case MII_ANLPAR: 60540516Swpaul rl8139_reg = RL_LPAR; 60640516Swpaul break; 60750703Swpaul case MII_PHYIDR1: 60850703Swpaul case MII_PHYIDR2: 60967087Swpaul RL_UNLOCK(sc); 61050703Swpaul return(0); 61150703Swpaul break; 61240516Swpaul default: 61340516Swpaul printf("rl%d: bad phy register\n", sc->rl_unit); 61467087Swpaul RL_UNLOCK(sc); 61540516Swpaul return(0); 61640516Swpaul } 61740516Swpaul rval = CSR_READ_2(sc, rl8139_reg); 61867087Swpaul RL_UNLOCK(sc); 61940516Swpaul return(rval); 62040516Swpaul } 62140516Swpaul 62240516Swpaul bzero((char *)&frame, sizeof(frame)); 62340516Swpaul 62450703Swpaul frame.mii_phyaddr = phy; 62540516Swpaul frame.mii_regaddr = reg; 62640516Swpaul rl_mii_readreg(sc, &frame); 62767087Swpaul RL_UNLOCK(sc); 62840516Swpaul 62940516Swpaul return(frame.mii_data); 63040516Swpaul} 63140516Swpaul 63250703Swpaulstatic int rl_miibus_writereg(dev, phy, reg, data) 63350703Swpaul device_t dev; 63450703Swpaul int phy, reg, data; 63550703Swpaul{ 63640516Swpaul struct rl_softc *sc; 63740516Swpaul struct rl_mii_frame frame; 63840516Swpaul u_int16_t rl8139_reg = 0; 63940516Swpaul 64050703Swpaul sc = device_get_softc(dev); 64167087Swpaul RL_LOCK(sc); 64250703Swpaul 64340516Swpaul if (sc->rl_type == RL_8139) { 64450703Swpaul /* Pretend the internal PHY is only at address 0 */ 64567087Swpaul if (phy) { 64667087Swpaul RL_UNLOCK(sc); 64750703Swpaul return(0); 64867087Swpaul } 64940516Swpaul switch(reg) { 65050703Swpaul case MII_BMCR: 65140516Swpaul rl8139_reg = RL_BMCR; 65240516Swpaul break; 65350703Swpaul case MII_BMSR: 65440516Swpaul rl8139_reg = RL_BMSR; 65540516Swpaul break; 65650703Swpaul case MII_ANAR: 65740516Swpaul rl8139_reg = RL_ANAR; 65840516Swpaul break; 65950703Swpaul case MII_ANER: 66050703Swpaul rl8139_reg = RL_ANER; 66150703Swpaul break; 66250703Swpaul case MII_ANLPAR: 66340516Swpaul rl8139_reg = RL_LPAR; 66440516Swpaul break; 66550703Swpaul case MII_PHYIDR1: 66650703Swpaul case MII_PHYIDR2: 66767087Swpaul RL_UNLOCK(sc); 66850703Swpaul return(0); 66950703Swpaul break; 67040516Swpaul default: 67140516Swpaul printf("rl%d: bad phy register\n", sc->rl_unit); 67267087Swpaul RL_UNLOCK(sc); 67350703Swpaul return(0); 67440516Swpaul } 67540516Swpaul CSR_WRITE_2(sc, rl8139_reg, data); 67667087Swpaul RL_UNLOCK(sc); 67750703Swpaul return(0); 67840516Swpaul } 67940516Swpaul 68040516Swpaul bzero((char *)&frame, sizeof(frame)); 68140516Swpaul 68250703Swpaul frame.mii_phyaddr = phy; 68340516Swpaul frame.mii_regaddr = reg; 68440516Swpaul frame.mii_data = data; 68540516Swpaul 68640516Swpaul rl_mii_writereg(sc, &frame); 68740516Swpaul 68867087Swpaul RL_UNLOCK(sc); 68950703Swpaul return(0); 69050703Swpaul} 69150703Swpaul 69250703Swpaulstatic void rl_miibus_statchg(dev) 69350703Swpaul device_t dev; 69450703Swpaul{ 69540516Swpaul return; 69640516Swpaul} 69740516Swpaul 69840516Swpaul/* 69943062Swpaul * Calculate CRC of a multicast group address, return the upper 6 bits. 70040516Swpaul */ 70140516Swpaulstatic u_int8_t rl_calchash(addr) 70241656Swpaul caddr_t addr; 70340516Swpaul{ 70440516Swpaul u_int32_t crc, carry; 70540516Swpaul int i, j; 70640516Swpaul u_int8_t c; 70740516Swpaul 70840516Swpaul /* Compute CRC for the address value. */ 70940516Swpaul crc = 0xFFFFFFFF; /* initial value */ 71040516Swpaul 71140516Swpaul for (i = 0; i < 6; i++) { 71240516Swpaul c = *(addr + i); 71340516Swpaul for (j = 0; j < 8; j++) { 71440516Swpaul carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 71540516Swpaul crc <<= 1; 71640516Swpaul c >>= 1; 71740516Swpaul if (carry) 71840516Swpaul crc = (crc ^ 0x04c11db6) | carry; 71940516Swpaul } 72040516Swpaul } 72140516Swpaul 72240516Swpaul /* return the filter bit position */ 72343062Swpaul return(crc >> 26); 72440516Swpaul} 72540516Swpaul 72640516Swpaul/* 72740516Swpaul * Program the 64-bit multicast hash filter. 72840516Swpaul */ 72940516Swpaulstatic void rl_setmulti(sc) 73040516Swpaul struct rl_softc *sc; 73140516Swpaul{ 73240516Swpaul struct ifnet *ifp; 73340516Swpaul int h = 0; 73440516Swpaul u_int32_t hashes[2] = { 0, 0 }; 73540516Swpaul struct ifmultiaddr *ifma; 73640516Swpaul u_int32_t rxfilt; 73740516Swpaul int mcnt = 0; 73840516Swpaul 73940516Swpaul ifp = &sc->arpcom.ac_if; 74040516Swpaul 74140516Swpaul rxfilt = CSR_READ_4(sc, RL_RXCFG); 74240516Swpaul 74343062Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 74440516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 74540516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 74640516Swpaul CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 74740516Swpaul CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 74840516Swpaul return; 74940516Swpaul } 75040516Swpaul 75140516Swpaul /* first, zot all the existing hash bits */ 75240516Swpaul CSR_WRITE_4(sc, RL_MAR0, 0); 75340516Swpaul CSR_WRITE_4(sc, RL_MAR4, 0); 75440516Swpaul 75540516Swpaul /* now program new ones */ 75672084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 75740516Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 75840516Swpaul continue; 75940516Swpaul h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 76040516Swpaul if (h < 32) 76140516Swpaul hashes[0] |= (1 << h); 76240516Swpaul else 76340516Swpaul hashes[1] |= (1 << (h - 32)); 76440516Swpaul mcnt++; 76540516Swpaul } 76640516Swpaul 76740516Swpaul if (mcnt) 76840516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 76940516Swpaul else 77040516Swpaul rxfilt &= ~RL_RXCFG_RX_MULTI; 77140516Swpaul 77240516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 77340516Swpaul CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 77440516Swpaul CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 77540516Swpaul 77640516Swpaul return; 77740516Swpaul} 77840516Swpaul 77940516Swpaulstatic void rl_reset(sc) 78040516Swpaul struct rl_softc *sc; 78140516Swpaul{ 78240516Swpaul register int i; 78340516Swpaul 78440516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 78540516Swpaul 78640516Swpaul for (i = 0; i < RL_TIMEOUT; i++) { 78740516Swpaul DELAY(10); 78840516Swpaul if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 78940516Swpaul break; 79040516Swpaul } 79140516Swpaul if (i == RL_TIMEOUT) 79240516Swpaul printf("rl%d: reset never completed!\n", sc->rl_unit); 79340516Swpaul 79440516Swpaul return; 79540516Swpaul} 79640516Swpaul 79740516Swpaul/* 79840516Swpaul * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 79940516Swpaul * IDs against our list and return a device name if we find a match. 80040516Swpaul */ 80150703Swpaulstatic int rl_probe(dev) 80250703Swpaul device_t dev; 80340516Swpaul{ 80440516Swpaul struct rl_type *t; 80540516Swpaul 80640516Swpaul t = rl_devs; 80740516Swpaul 80840516Swpaul while(t->rl_name != NULL) { 80950703Swpaul if ((pci_get_vendor(dev) == t->rl_vid) && 81050703Swpaul (pci_get_device(dev) == t->rl_did)) { 81150703Swpaul device_set_desc(dev, t->rl_name); 81250703Swpaul return(0); 81340516Swpaul } 81440516Swpaul t++; 81540516Swpaul } 81640516Swpaul 81750703Swpaul return(ENXIO); 81840516Swpaul} 81940516Swpaul 82040516Swpaul/* 82140516Swpaul * Attach the interface. Allocate softc structures, do ifmedia 82240516Swpaul * setup and ethernet/BPF attach. 82340516Swpaul */ 82450703Swpaulstatic int rl_attach(dev) 82550703Swpaul device_t dev; 82640516Swpaul{ 82740516Swpaul u_char eaddr[ETHER_ADDR_LEN]; 82840516Swpaul u_int32_t command; 82940516Swpaul struct rl_softc *sc; 83040516Swpaul struct ifnet *ifp; 83140516Swpaul u_int16_t rl_did = 0; 83250703Swpaul int unit, error = 0, rid; 83340516Swpaul 83450703Swpaul sc = device_get_softc(dev); 83550703Swpaul unit = device_get_unit(dev); 83640516Swpaul bzero(sc, sizeof(struct rl_softc)); 83740516Swpaul 83893818Sjhb mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 83993818Sjhb MTX_DEF | MTX_RECURSE); 84069583Swpaul RL_LOCK(sc); 84169583Swpaul 84240516Swpaul /* 84340516Swpaul * Handle power management nonsense. 84440516Swpaul */ 84540516Swpaul 84670167Swpaul if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 84770167Swpaul u_int32_t iobase, membase, irq; 84840516Swpaul 84970167Swpaul /* Save important PCI config data. */ 85070167Swpaul iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 85170167Swpaul membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 85270167Swpaul irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 85340516Swpaul 85470167Swpaul /* Reset the power state. */ 85570167Swpaul printf("rl%d: chip is is in D%d power mode " 85670167Swpaul "-- setting to D0\n", unit, 85770167Swpaul pci_get_powerstate(dev)); 85840516Swpaul 85970167Swpaul pci_set_powerstate(dev, PCI_POWERSTATE_D0); 86040516Swpaul 86170167Swpaul /* Restore PCI config data. */ 86270167Swpaul pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 86370167Swpaul pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 86470167Swpaul pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 86540516Swpaul } 86640516Swpaul 86740516Swpaul /* 86840516Swpaul * Map control/status registers. 86940516Swpaul */ 87072813Swpaul pci_enable_busmaster(dev); 87179472Swpaul pci_enable_io(dev, SYS_RES_IOPORT); 87279472Swpaul pci_enable_io(dev, SYS_RES_MEMORY); 87361041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 87440516Swpaul 87540516Swpaul#ifdef RL_USEIOSPACE 87640516Swpaul if (!(command & PCIM_CMD_PORTEN)) { 87740516Swpaul printf("rl%d: failed to enable I/O ports!\n", unit); 87850703Swpaul error = ENXIO; 87940516Swpaul goto fail; 88040516Swpaul } 88140516Swpaul#else 88240516Swpaul if (!(command & PCIM_CMD_MEMEN)) { 88340516Swpaul printf("rl%d: failed to enable memory mapping!\n", unit); 88450703Swpaul error = ENXIO; 88540516Swpaul goto fail; 88640516Swpaul } 88750703Swpaul#endif 88840516Swpaul 88950703Swpaul rid = RL_RID; 89050703Swpaul sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 89150703Swpaul 0, ~0, 1, RF_ACTIVE); 89250703Swpaul 89350703Swpaul if (sc->rl_res == NULL) { 89450703Swpaul printf ("rl%d: couldn't map ports/memory\n", unit); 89550703Swpaul error = ENXIO; 89640516Swpaul goto fail; 89740516Swpaul } 89840516Swpaul 89969127Sroger /* Detect the Realtek 8139B. For some reason, this chip is very 90069127Sroger * unstable when left to autoselect the media 90169127Sroger * The best workaround is to set the device to the required 90269127Sroger * media type or to set it to the 10 Meg speed. 90369127Sroger */ 90469127Sroger 90569127Sroger if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { 90669127Sroger printf("rl%d: Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n", unit); 90769127Sroger } 90869127Sroger 90950703Swpaul sc->rl_btag = rman_get_bustag(sc->rl_res); 91050703Swpaul sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 91150703Swpaul 91250703Swpaul rid = 0; 91350703Swpaul sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 91450703Swpaul RF_SHAREABLE | RF_ACTIVE); 91550703Swpaul 91650703Swpaul if (sc->rl_irq == NULL) { 91740516Swpaul printf("rl%d: couldn't map interrupt\n", unit); 91850703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 91950703Swpaul error = ENXIO; 92040516Swpaul goto fail; 92140516Swpaul } 92240516Swpaul 92350703Swpaul error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 92450703Swpaul rl_intr, sc, &sc->rl_intrhand); 92550703Swpaul 92650703Swpaul if (error) { 92768215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 92850703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 92950703Swpaul printf("rl%d: couldn't set up irq\n", unit); 93050703Swpaul goto fail; 93150703Swpaul } 93250703Swpaul 93350703Swpaul callout_handle_init(&sc->rl_stat_ch); 93450703Swpaul 93540516Swpaul /* Reset the adapter. */ 93640516Swpaul rl_reset(sc); 93767931Swpaul sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 93867931Swpaul rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 93968215Swpaul if (rl_did != 0x8129) 94067931Swpaul sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 94140516Swpaul 94240516Swpaul /* 94340516Swpaul * Get station address from the EEPROM. 94440516Swpaul */ 94540516Swpaul rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0); 94640516Swpaul 94740516Swpaul /* 94840516Swpaul * A RealTek chip was detected. Inform the world. 94940516Swpaul */ 95040516Swpaul printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 95140516Swpaul 95240516Swpaul sc->rl_unit = unit; 95340516Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 95440516Swpaul 95540516Swpaul /* 95640516Swpaul * Now read the exact device type from the EEPROM to find 95740516Swpaul * out if it's an 8129 or 8139. 95840516Swpaul */ 95940516Swpaul rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 96040516Swpaul 96144238Swpaul if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 96267771Swpaul rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 96372813Swpaul rl_did == RT_DEVICEID_8138 || rl_did == DLINK_DEVICEID_530TXPLUS) 96440516Swpaul sc->rl_type = RL_8139; 96540516Swpaul else if (rl_did == RT_DEVICEID_8129) 96640516Swpaul sc->rl_type = RL_8129; 96740516Swpaul else { 96840516Swpaul printf("rl%d: unknown device ID: %x\n", unit, rl_did); 96950703Swpaul bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 97068215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 97150703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 97250703Swpaul error = ENXIO; 97340516Swpaul goto fail; 97440516Swpaul } 97540516Swpaul 97681713Swpaul /* 97781713Swpaul * Allocate the parent bus DMA tag appropriate for PCI. 97881713Swpaul */ 97981713Swpaul#define RL_NSEG_NEW 32 98081713Swpaul error = bus_dma_tag_create(NULL, /* parent */ 98181713Swpaul 1, 0, /* alignment, boundary */ 98281713Swpaul BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 98381713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 98481713Swpaul NULL, NULL, /* filter, filterarg */ 98581713Swpaul MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 98681713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 98781713Swpaul BUS_DMA_ALLOCNOW, /* flags */ 98881713Swpaul &sc->rl_parent_tag); 98940516Swpaul 99081713Swpaul /* 99181713Swpaul * Now allocate a tag for the DMA descriptor lists. 99281713Swpaul * All of our lists are allocated as a contiguous block 99381713Swpaul * of memory. 99481713Swpaul */ 99581713Swpaul error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 99681713Swpaul 1, 0, /* alignment, boundary */ 99781713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 99881713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 99981713Swpaul NULL, NULL, /* filter, filterarg */ 100081713Swpaul RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 100181713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 100281713Swpaul 0, /* flags */ 100381713Swpaul &sc->rl_tag); 100481713Swpaul 100581713Swpaul /* 100681713Swpaul * Now allocate a chunk of DMA-able memory based on the 100781713Swpaul * tag we just created. 100881713Swpaul */ 100981713Swpaul error = bus_dmamem_alloc(sc->rl_tag, 101081713Swpaul (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT, 101181713Swpaul &sc->rl_cdata.rl_rx_dmamap); 101281713Swpaul 101340516Swpaul if (sc->rl_cdata.rl_rx_buf == NULL) { 101440516Swpaul printf("rl%d: no memory for list buffers!\n", unit); 101550703Swpaul bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 101668215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 101750703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 101881713Swpaul bus_dma_tag_destroy(sc->rl_tag); 101950703Swpaul error = ENXIO; 102040516Swpaul goto fail; 102140516Swpaul } 102240516Swpaul 102348028Swpaul /* Leave a few bytes before the start of the RX ring buffer. */ 102448028Swpaul sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 102548028Swpaul sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 102648028Swpaul 102750703Swpaul /* Do MII setup */ 102850703Swpaul if (mii_phy_probe(dev, &sc->rl_miibus, 102950703Swpaul rl_ifmedia_upd, rl_ifmedia_sts)) { 103050703Swpaul printf("rl%d: MII without any phy!\n", sc->rl_unit); 103150703Swpaul bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 103268215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 103350703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 103481713Swpaul bus_dmamem_free(sc->rl_tag, 103581713Swpaul sc->rl_cdata.rl_rx_buf, sc->rl_cdata.rl_rx_dmamap); 103681713Swpaul bus_dma_tag_destroy(sc->rl_tag); 103750703Swpaul error = ENXIO; 103850703Swpaul goto fail; 103950703Swpaul } 104050703Swpaul 104140516Swpaul ifp = &sc->arpcom.ac_if; 104240516Swpaul ifp->if_softc = sc; 104340516Swpaul ifp->if_unit = unit; 104440516Swpaul ifp->if_name = "rl"; 104540516Swpaul ifp->if_mtu = ETHERMTU; 104640516Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 104740516Swpaul ifp->if_ioctl = rl_ioctl; 104840516Swpaul ifp->if_output = ether_output; 104940516Swpaul ifp->if_start = rl_start; 105040516Swpaul ifp->if_watchdog = rl_watchdog; 105140516Swpaul ifp->if_init = rl_init; 105240516Swpaul ifp->if_baudrate = 10000000; 105345633Swpaul ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 105440516Swpaul 105540516Swpaul /* 105663090Sarchie * Call MI attach routine. 105740516Swpaul */ 105863090Sarchie ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 105967087Swpaul RL_UNLOCK(sc); 106067087Swpaul return(0); 106140516Swpaul 106240516Swpaulfail: 106367087Swpaul RL_UNLOCK(sc); 106467087Swpaul mtx_destroy(&sc->rl_mtx); 106550703Swpaul return(error); 106640516Swpaul} 106740516Swpaul 106850703Swpaulstatic int rl_detach(dev) 106950703Swpaul device_t dev; 107050703Swpaul{ 107150703Swpaul struct rl_softc *sc; 107250703Swpaul struct ifnet *ifp; 107350703Swpaul 107450703Swpaul sc = device_get_softc(dev); 107567087Swpaul RL_LOCK(sc); 107650703Swpaul ifp = &sc->arpcom.ac_if; 107750703Swpaul 107863090Sarchie ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 107950703Swpaul rl_stop(sc); 108050703Swpaul 108150703Swpaul bus_generic_detach(dev); 108250703Swpaul device_delete_child(dev, sc->rl_miibus); 108350703Swpaul 108450703Swpaul bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 108568215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 108650703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 108750703Swpaul 108881713Swpaul bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 108981713Swpaul bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 109081713Swpaul sc->rl_cdata.rl_rx_dmamap); 109181713Swpaul bus_dma_tag_destroy(sc->rl_tag); 109281713Swpaul bus_dma_tag_destroy(sc->rl_parent_tag); 109350703Swpaul 109467087Swpaul RL_UNLOCK(sc); 109567087Swpaul mtx_destroy(&sc->rl_mtx); 109650703Swpaul 109750703Swpaul return(0); 109850703Swpaul} 109950703Swpaul 110040516Swpaul/* 110140516Swpaul * Initialize the transmit descriptors. 110240516Swpaul */ 110340516Swpaulstatic int rl_list_tx_init(sc) 110440516Swpaul struct rl_softc *sc; 110540516Swpaul{ 110640516Swpaul struct rl_chain_data *cd; 110740516Swpaul int i; 110840516Swpaul 110940516Swpaul cd = &sc->rl_cdata; 111040516Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 111145633Swpaul cd->rl_tx_chain[i] = NULL; 111248028Swpaul CSR_WRITE_4(sc, 111348028Swpaul RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 111440516Swpaul } 111540516Swpaul 111645633Swpaul sc->rl_cdata.cur_tx = 0; 111745633Swpaul sc->rl_cdata.last_tx = 0; 111840516Swpaul 111940516Swpaul return(0); 112040516Swpaul} 112140516Swpaul 112240516Swpaul/* 112340516Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 112440516Swpaul * the higher level protocols. 112540516Swpaul * 112640516Swpaul * You know there's something wrong with a PCI bus-master chip design 112740516Swpaul * when you have to use m_devget(). 112840516Swpaul * 112940516Swpaul * The receive operation is badly documented in the datasheet, so I'll 113040516Swpaul * attempt to document it here. The driver provides a buffer area and 113140516Swpaul * places its base address in the RX buffer start address register. 113240516Swpaul * The chip then begins copying frames into the RX buffer. Each frame 113372645Sasmodai * is preceded by a 32-bit RX status word which specifies the length 113440516Swpaul * of the frame and certain other status bits. Each frame (starting with 113540516Swpaul * the status word) is also 32-bit aligned. The frame length is in the 113640516Swpaul * first 16 bits of the status word; the lower 15 bits correspond with 113740516Swpaul * the 'rx status register' mentioned in the datasheet. 113848028Swpaul * 113948028Swpaul * Note: to make the Alpha happy, the frame payload needs to be aligned 114078508Sbmilekic * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 114178508Sbmilekic * as the offset argument to m_devget(). 114240516Swpaul */ 114340516Swpaulstatic void rl_rxeof(sc) 114440516Swpaul struct rl_softc *sc; 114540516Swpaul{ 114640516Swpaul struct ether_header *eh; 114740516Swpaul struct mbuf *m; 114840516Swpaul struct ifnet *ifp; 114940516Swpaul int total_len = 0; 115040516Swpaul u_int32_t rxstat; 115140516Swpaul caddr_t rxbufpos; 115240516Swpaul int wrap = 0; 115340516Swpaul u_int16_t cur_rx; 115440516Swpaul u_int16_t limit; 115540516Swpaul u_int16_t rx_bytes = 0, max_bytes; 115640516Swpaul 115740516Swpaul ifp = &sc->arpcom.ac_if; 115840516Swpaul 115981713Swpaul bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 116081713Swpaul BUS_DMASYNC_POSTWRITE); 116181713Swpaul 116240516Swpaul cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 116340516Swpaul 116440516Swpaul /* Do not try to read past this point. */ 116540516Swpaul limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 116640516Swpaul 116740516Swpaul if (limit < cur_rx) 116840516Swpaul max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 116940516Swpaul else 117040516Swpaul max_bytes = limit - cur_rx; 117140516Swpaul 117242738Swpaul while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 117340516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 117440516Swpaul rxstat = *(u_int32_t *)rxbufpos; 117540516Swpaul 117640516Swpaul /* 117740516Swpaul * Here's a totally undocumented fact for you. When the 117840516Swpaul * RealTek chip is in the process of copying a packet into 117940516Swpaul * RAM for you, the length will be 0xfff0. If you spot a 118040516Swpaul * packet header with this value, you need to stop. The 118140516Swpaul * datasheet makes absolutely no mention of this and 118240516Swpaul * RealTek should be shot for this. 118340516Swpaul */ 118440516Swpaul if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 118540516Swpaul break; 118640516Swpaul 118740516Swpaul if (!(rxstat & RL_RXSTAT_RXOK)) { 118840516Swpaul ifp->if_ierrors++; 118950703Swpaul rl_init(sc); 119050703Swpaul return; 119140516Swpaul } 119240516Swpaul 119340516Swpaul /* No errors; receive the packet. */ 119440516Swpaul total_len = rxstat >> 16; 119540516Swpaul rx_bytes += total_len + 4; 119640516Swpaul 119740516Swpaul /* 119842051Swpaul * XXX The RealTek chip includes the CRC with every 119942051Swpaul * received frame, and there's no way to turn this 120042051Swpaul * behavior off (at least, I can't find anything in 120142051Swpaul * the manual that explains how to do it) so we have 120242051Swpaul * to trim off the CRC manually. 120342051Swpaul */ 120442051Swpaul total_len -= ETHER_CRC_LEN; 120542051Swpaul 120642051Swpaul /* 120740516Swpaul * Avoid trying to read more bytes than we know 120840516Swpaul * the chip has prepared for us. 120940516Swpaul */ 121040516Swpaul if (rx_bytes > max_bytes) 121140516Swpaul break; 121240516Swpaul 121340516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + 121440516Swpaul ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 121540516Swpaul 121640516Swpaul if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 121740516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf; 121840516Swpaul 121940516Swpaul wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 122040516Swpaul 122140516Swpaul if (total_len > wrap) { 122278508Sbmilekic m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 122378508Sbmilekic NULL); 122440516Swpaul if (m == NULL) { 122540516Swpaul ifp->if_ierrors++; 122652426Swpaul } else { 122740516Swpaul m_copyback(m, wrap, total_len - wrap, 122840516Swpaul sc->rl_cdata.rl_rx_buf); 122948028Swpaul } 123042051Swpaul cur_rx = (total_len - wrap + ETHER_CRC_LEN); 123140516Swpaul } else { 123278508Sbmilekic m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 123378508Sbmilekic NULL); 123440516Swpaul if (m == NULL) { 123540516Swpaul ifp->if_ierrors++; 123678508Sbmilekic } 123742051Swpaul cur_rx += total_len + 4 + ETHER_CRC_LEN; 123840516Swpaul } 123940516Swpaul 124040516Swpaul /* 124140516Swpaul * Round up to 32-bit boundary. 124240516Swpaul */ 124340516Swpaul cur_rx = (cur_rx + 3) & ~3; 124440516Swpaul CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 124540516Swpaul 124640516Swpaul if (m == NULL) 124740516Swpaul continue; 124840516Swpaul 124940516Swpaul eh = mtod(m, struct ether_header *); 125040516Swpaul ifp->if_ipackets++; 125140516Swpaul 125240516Swpaul /* Remove header from mbuf and pass it on. */ 125340516Swpaul m_adj(m, sizeof(struct ether_header)); 125440516Swpaul ether_input(ifp, eh, m); 125540516Swpaul } 125640516Swpaul 125740516Swpaul return; 125840516Swpaul} 125940516Swpaul 126040516Swpaul/* 126140516Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 126240516Swpaul * the list buffers. 126340516Swpaul */ 126440516Swpaulstatic void rl_txeof(sc) 126540516Swpaul struct rl_softc *sc; 126640516Swpaul{ 126740516Swpaul struct ifnet *ifp; 126840516Swpaul u_int32_t txstat; 126940516Swpaul 127040516Swpaul ifp = &sc->arpcom.ac_if; 127140516Swpaul 127240516Swpaul /* Clear the timeout timer. */ 127340516Swpaul ifp->if_timer = 0; 127440516Swpaul 127540516Swpaul /* 127640516Swpaul * Go through our tx list and free mbufs for those 127740516Swpaul * frames that have been uploaded. 127840516Swpaul */ 127945633Swpaul do { 128045633Swpaul txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 128145633Swpaul if (!(txstat & (RL_TXSTAT_TX_OK| 128245633Swpaul RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 128340516Swpaul break; 128440516Swpaul 128545633Swpaul ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 128640516Swpaul 128745633Swpaul if (RL_LAST_TXMBUF(sc) != NULL) { 128881713Swpaul bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 128981713Swpaul bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 129045633Swpaul m_freem(RL_LAST_TXMBUF(sc)); 129145633Swpaul RL_LAST_TXMBUF(sc) = NULL; 129245633Swpaul } 129345633Swpaul if (txstat & RL_TXSTAT_TX_OK) 129445633Swpaul ifp->if_opackets++; 129545633Swpaul else { 129652426Swpaul int oldthresh; 129745633Swpaul ifp->if_oerrors++; 129845633Swpaul if ((txstat & RL_TXSTAT_TXABRT) || 129945633Swpaul (txstat & RL_TXSTAT_OUTOFWIN)) 130045633Swpaul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 130152426Swpaul oldthresh = sc->rl_txthresh; 130252426Swpaul /* error recovery */ 130352426Swpaul rl_reset(sc); 130452426Swpaul rl_init(sc); 130552426Swpaul /* 130652426Swpaul * If there was a transmit underrun, 130752426Swpaul * bump the TX threshold. 130852426Swpaul */ 130952426Swpaul if (txstat & RL_TXSTAT_TX_UNDERRUN) 131052426Swpaul sc->rl_txthresh = oldthresh + 32; 131152426Swpaul return; 131245633Swpaul } 131345633Swpaul RL_INC(sc->rl_cdata.last_tx); 131445633Swpaul ifp->if_flags &= ~IFF_OACTIVE; 131545633Swpaul } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 131640516Swpaul 131750703Swpaul return; 131850703Swpaul} 131940516Swpaul 132050703Swpaulstatic void rl_tick(xsc) 132150703Swpaul void *xsc; 132250703Swpaul{ 132350703Swpaul struct rl_softc *sc; 132450703Swpaul struct mii_data *mii; 132550703Swpaul 132650703Swpaul sc = xsc; 132767087Swpaul RL_LOCK(sc); 132850703Swpaul mii = device_get_softc(sc->rl_miibus); 132950703Swpaul 133050703Swpaul mii_tick(mii); 133150703Swpaul 133250703Swpaul sc->rl_stat_ch = timeout(rl_tick, sc, hz); 133367087Swpaul RL_UNLOCK(sc); 133450703Swpaul 133540516Swpaul return; 133640516Swpaul} 133740516Swpaul 133840516Swpaulstatic void rl_intr(arg) 133940516Swpaul void *arg; 134040516Swpaul{ 134140516Swpaul struct rl_softc *sc; 134240516Swpaul struct ifnet *ifp; 134340516Swpaul u_int16_t status; 134440516Swpaul 134540516Swpaul sc = arg; 134686822Siwasaki 134786822Siwasaki if (sc->suspended) { 134886822Siwasaki return; 134986822Siwasaki } 135086822Siwasaki 135167087Swpaul RL_LOCK(sc); 135240516Swpaul ifp = &sc->arpcom.ac_if; 135340516Swpaul 135440516Swpaul /* Disable interrupts. */ 135540516Swpaul CSR_WRITE_2(sc, RL_IMR, 0x0000); 135640516Swpaul 135740516Swpaul for (;;) { 135840516Swpaul 135940516Swpaul status = CSR_READ_2(sc, RL_ISR); 136040516Swpaul if (status) 136140516Swpaul CSR_WRITE_2(sc, RL_ISR, status); 136240516Swpaul 136340516Swpaul if ((status & RL_INTRS) == 0) 136440516Swpaul break; 136540516Swpaul 136640516Swpaul if (status & RL_ISR_RX_OK) 136740516Swpaul rl_rxeof(sc); 136840516Swpaul 136940516Swpaul if (status & RL_ISR_RX_ERR) 137040516Swpaul rl_rxeof(sc); 137140516Swpaul 137245633Swpaul if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 137340516Swpaul rl_txeof(sc); 137440516Swpaul 137540516Swpaul if (status & RL_ISR_SYSTEM_ERR) { 137640516Swpaul rl_reset(sc); 137740516Swpaul rl_init(sc); 137840516Swpaul } 137940516Swpaul 138040516Swpaul } 138140516Swpaul 138240516Swpaul /* Re-enable interrupts. */ 138340516Swpaul CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 138440516Swpaul 138552426Swpaul if (ifp->if_snd.ifq_head != NULL) 138640516Swpaul rl_start(ifp); 138740516Swpaul 138867087Swpaul RL_UNLOCK(sc); 138967087Swpaul 139040516Swpaul return; 139140516Swpaul} 139240516Swpaul 139340516Swpaul/* 139440516Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 139540516Swpaul * pointers to the fragment pointers. 139640516Swpaul */ 139745633Swpaulstatic int rl_encap(sc, m_head) 139840516Swpaul struct rl_softc *sc; 139940516Swpaul struct mbuf *m_head; 140040516Swpaul{ 140141243Swpaul struct mbuf *m_new = NULL; 140240516Swpaul 140340516Swpaul /* 140445633Swpaul * The RealTek is brain damaged and wants longword-aligned 140545633Swpaul * TX buffers, plus we can only have one fragment buffer 140645633Swpaul * per packet. We have to copy pretty much all the time. 140740516Swpaul */ 140840516Swpaul 140941243Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 141087846Sluigi if (m_new == NULL) 141141243Swpaul return(1); 141241243Swpaul if (m_head->m_pkthdr.len > MHLEN) { 141341243Swpaul MCLGET(m_new, M_DONTWAIT); 141441243Swpaul if (!(m_new->m_flags & M_EXT)) { 141541243Swpaul m_freem(m_new); 141640516Swpaul return(1); 141740516Swpaul } 141840516Swpaul } 141952426Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 142041243Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 142141243Swpaul m_freem(m_head); 142241243Swpaul m_head = m_new; 142340516Swpaul 142440516Swpaul /* Pad frames to at least 60 bytes. */ 142541243Swpaul if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 142655058Swpaul /* 142755058Swpaul * Make security concious people happy: zero out the 142855058Swpaul * bytes in the pad area, since we don't know what 142955058Swpaul * this mbuf cluster buffer's previous user might 143055058Swpaul * have left in it. 143155058Swpaul */ 143255058Swpaul bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 143355058Swpaul RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 143440516Swpaul m_head->m_pkthdr.len += 143552426Swpaul (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 143641243Swpaul m_head->m_len = m_head->m_pkthdr.len; 143741243Swpaul } 143840516Swpaul 143945633Swpaul RL_CUR_TXMBUF(sc) = m_head; 144040516Swpaul 144140516Swpaul return(0); 144240516Swpaul} 144340516Swpaul 144440516Swpaul/* 144540516Swpaul * Main transmit routine. 144640516Swpaul */ 144740516Swpaul 144840516Swpaulstatic void rl_start(ifp) 144940516Swpaul struct ifnet *ifp; 145040516Swpaul{ 145140516Swpaul struct rl_softc *sc; 145240516Swpaul struct mbuf *m_head = NULL; 145340516Swpaul 145440516Swpaul sc = ifp->if_softc; 145567087Swpaul RL_LOCK(sc); 145640516Swpaul 145745633Swpaul while(RL_CUR_TXMBUF(sc) == NULL) { 145840516Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 145940516Swpaul if (m_head == NULL) 146040516Swpaul break; 146140516Swpaul 146258801Swpaul if (rl_encap(sc, m_head)) { 146358801Swpaul IF_PREPEND(&ifp->if_snd, m_head); 146458801Swpaul ifp->if_flags |= IFF_OACTIVE; 146558801Swpaul break; 146658801Swpaul } 146740516Swpaul 146840516Swpaul /* 146940516Swpaul * If there's a BPF listener, bounce a copy of this frame 147040516Swpaul * to him. 147140516Swpaul */ 147240516Swpaul if (ifp->if_bpf) 147345633Swpaul bpf_mtap(ifp, RL_CUR_TXMBUF(sc)); 147451583Swpaul 147540516Swpaul /* 147640516Swpaul * Transmit the frame. 147740516Swpaul */ 147881713Swpaul bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 147981713Swpaul bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 148081713Swpaul mtod(RL_CUR_TXMBUF(sc), void *), 148181713Swpaul RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 148281713Swpaul bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 148381713Swpaul BUS_DMASYNC_PREREAD); 148445633Swpaul CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 148552426Swpaul RL_TXTHRESH(sc->rl_txthresh) | 148652426Swpaul RL_CUR_TXMBUF(sc)->m_pkthdr.len); 148745633Swpaul 148845633Swpaul RL_INC(sc->rl_cdata.cur_tx); 148940516Swpaul } 149040516Swpaul 149140516Swpaul /* 149245633Swpaul * We broke out of the loop because all our TX slots are 149345633Swpaul * full. Mark the NIC as busy until it drains some of the 149445633Swpaul * packets from the queue. 149545633Swpaul */ 149645633Swpaul if (RL_CUR_TXMBUF(sc) != NULL) 149745633Swpaul ifp->if_flags |= IFF_OACTIVE; 149845633Swpaul 149945633Swpaul /* 150040516Swpaul * Set a timeout in case the chip goes out to lunch. 150140516Swpaul */ 150240516Swpaul ifp->if_timer = 5; 150367087Swpaul RL_UNLOCK(sc); 150440516Swpaul 150540516Swpaul return; 150640516Swpaul} 150740516Swpaul 150840516Swpaulstatic void rl_init(xsc) 150940516Swpaul void *xsc; 151040516Swpaul{ 151140516Swpaul struct rl_softc *sc = xsc; 151240516Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 151350703Swpaul struct mii_data *mii; 151467087Swpaul int i; 151540516Swpaul u_int32_t rxcfg = 0; 151640516Swpaul 151767087Swpaul RL_LOCK(sc); 151850703Swpaul mii = device_get_softc(sc->rl_miibus); 151940516Swpaul 152040516Swpaul /* 152140516Swpaul * Cancel pending I/O and free all RX/TX buffers. 152240516Swpaul */ 152340516Swpaul rl_stop(sc); 152440516Swpaul 152540516Swpaul /* Init our MAC address */ 152640516Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) { 152740516Swpaul CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 152840516Swpaul } 152940516Swpaul 153040516Swpaul /* Init the RX buffer pointer register. */ 153181713Swpaul bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 153281713Swpaul sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 153381713Swpaul bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 153481713Swpaul BUS_DMASYNC_PREWRITE); 153540516Swpaul 153640516Swpaul /* Init TX descriptors. */ 153740516Swpaul rl_list_tx_init(sc); 153840516Swpaul 153940516Swpaul /* 154040516Swpaul * Enable transmit and receive. 154140516Swpaul */ 154240516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 154340516Swpaul 154440516Swpaul /* 154545633Swpaul * Set the initial TX and RX configuration. 154640516Swpaul */ 154745633Swpaul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 154840516Swpaul CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 154940516Swpaul 155040516Swpaul /* Set the individual bit to receive frames for this host only. */ 155140516Swpaul rxcfg = CSR_READ_4(sc, RL_RXCFG); 155240516Swpaul rxcfg |= RL_RXCFG_RX_INDIV; 155340516Swpaul 155440516Swpaul /* If we want promiscuous mode, set the allframes bit. */ 155540516Swpaul if (ifp->if_flags & IFF_PROMISC) { 155640516Swpaul rxcfg |= RL_RXCFG_RX_ALLPHYS; 155740516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 155840516Swpaul } else { 155940516Swpaul rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 156040516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 156140516Swpaul } 156240516Swpaul 156340516Swpaul /* 156440516Swpaul * Set capture broadcast bit to capture broadcast frames. 156540516Swpaul */ 156640516Swpaul if (ifp->if_flags & IFF_BROADCAST) { 156740516Swpaul rxcfg |= RL_RXCFG_RX_BROAD; 156840516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 156940516Swpaul } else { 157040516Swpaul rxcfg &= ~RL_RXCFG_RX_BROAD; 157140516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 157240516Swpaul } 157340516Swpaul 157440516Swpaul /* 157540516Swpaul * Program the multicast filter, if necessary. 157640516Swpaul */ 157740516Swpaul rl_setmulti(sc); 157840516Swpaul 157940516Swpaul /* 158040516Swpaul * Enable interrupts. 158140516Swpaul */ 158240516Swpaul CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 158340516Swpaul 158452426Swpaul /* Set initial TX threshold */ 158552426Swpaul sc->rl_txthresh = RL_TX_THRESH_INIT; 158652426Swpaul 158740516Swpaul /* Start RX/TX process. */ 158840516Swpaul CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 158940516Swpaul 159040516Swpaul /* Enable receiver and transmitter. */ 159140516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 159240516Swpaul 159350703Swpaul mii_mediachg(mii); 159440516Swpaul 159540516Swpaul CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 159640516Swpaul 159740516Swpaul ifp->if_flags |= IFF_RUNNING; 159840516Swpaul ifp->if_flags &= ~IFF_OACTIVE; 159940516Swpaul 160050703Swpaul sc->rl_stat_ch = timeout(rl_tick, sc, hz); 160167087Swpaul RL_UNLOCK(sc); 160250703Swpaul 160340516Swpaul return; 160440516Swpaul} 160540516Swpaul 160640516Swpaul/* 160740516Swpaul * Set media options. 160840516Swpaul */ 160940516Swpaulstatic int rl_ifmedia_upd(ifp) 161040516Swpaul struct ifnet *ifp; 161140516Swpaul{ 161240516Swpaul struct rl_softc *sc; 161350703Swpaul struct mii_data *mii; 161440516Swpaul 161540516Swpaul sc = ifp->if_softc; 161650703Swpaul mii = device_get_softc(sc->rl_miibus); 161750703Swpaul mii_mediachg(mii); 161840516Swpaul 161940516Swpaul return(0); 162040516Swpaul} 162140516Swpaul 162240516Swpaul/* 162340516Swpaul * Report current media status. 162440516Swpaul */ 162540516Swpaulstatic void rl_ifmedia_sts(ifp, ifmr) 162640516Swpaul struct ifnet *ifp; 162740516Swpaul struct ifmediareq *ifmr; 162840516Swpaul{ 162940516Swpaul struct rl_softc *sc; 163050703Swpaul struct mii_data *mii; 163140516Swpaul 163240516Swpaul sc = ifp->if_softc; 163350703Swpaul mii = device_get_softc(sc->rl_miibus); 163440516Swpaul 163550703Swpaul mii_pollstat(mii); 163650703Swpaul ifmr->ifm_active = mii->mii_media_active; 163750703Swpaul ifmr->ifm_status = mii->mii_media_status; 163840516Swpaul 163940516Swpaul return; 164040516Swpaul} 164140516Swpaul 164240516Swpaulstatic int rl_ioctl(ifp, command, data) 164340516Swpaul struct ifnet *ifp; 164440516Swpaul u_long command; 164540516Swpaul caddr_t data; 164640516Swpaul{ 164740516Swpaul struct rl_softc *sc = ifp->if_softc; 164840516Swpaul struct ifreq *ifr = (struct ifreq *) data; 164950703Swpaul struct mii_data *mii; 165067087Swpaul int error = 0; 165140516Swpaul 165267087Swpaul RL_LOCK(sc); 165340516Swpaul 165440516Swpaul switch(command) { 165540516Swpaul case SIOCSIFADDR: 165640516Swpaul case SIOCGIFADDR: 165740516Swpaul case SIOCSIFMTU: 165840516Swpaul error = ether_ioctl(ifp, command, data); 165940516Swpaul break; 166040516Swpaul case SIOCSIFFLAGS: 166140516Swpaul if (ifp->if_flags & IFF_UP) { 166240516Swpaul rl_init(sc); 166340516Swpaul } else { 166440516Swpaul if (ifp->if_flags & IFF_RUNNING) 166540516Swpaul rl_stop(sc); 166640516Swpaul } 166740516Swpaul error = 0; 166840516Swpaul break; 166940516Swpaul case SIOCADDMULTI: 167040516Swpaul case SIOCDELMULTI: 167140516Swpaul rl_setmulti(sc); 167240516Swpaul error = 0; 167340516Swpaul break; 167440516Swpaul case SIOCGIFMEDIA: 167540516Swpaul case SIOCSIFMEDIA: 167650703Swpaul mii = device_get_softc(sc->rl_miibus); 167750703Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 167840516Swpaul break; 167940516Swpaul default: 168040516Swpaul error = EINVAL; 168140516Swpaul break; 168240516Swpaul } 168340516Swpaul 168467087Swpaul RL_UNLOCK(sc); 168540516Swpaul 168640516Swpaul return(error); 168740516Swpaul} 168840516Swpaul 168940516Swpaulstatic void rl_watchdog(ifp) 169040516Swpaul struct ifnet *ifp; 169140516Swpaul{ 169240516Swpaul struct rl_softc *sc; 169340516Swpaul 169440516Swpaul sc = ifp->if_softc; 169567087Swpaul RL_LOCK(sc); 169640516Swpaul printf("rl%d: watchdog timeout\n", sc->rl_unit); 169740516Swpaul ifp->if_oerrors++; 169850703Swpaul 169940516Swpaul rl_txeof(sc); 170040516Swpaul rl_rxeof(sc); 170140516Swpaul rl_init(sc); 170267087Swpaul RL_UNLOCK(sc); 170340516Swpaul 170440516Swpaul return; 170540516Swpaul} 170640516Swpaul 170740516Swpaul/* 170840516Swpaul * Stop the adapter and free any mbufs allocated to the 170940516Swpaul * RX and TX lists. 171040516Swpaul */ 171140516Swpaulstatic void rl_stop(sc) 171240516Swpaul struct rl_softc *sc; 171340516Swpaul{ 171440516Swpaul register int i; 171540516Swpaul struct ifnet *ifp; 171640516Swpaul 171767087Swpaul RL_LOCK(sc); 171840516Swpaul ifp = &sc->arpcom.ac_if; 171940516Swpaul ifp->if_timer = 0; 172040516Swpaul 172150703Swpaul untimeout(rl_tick, sc, sc->rl_stat_ch); 172250703Swpaul 172340516Swpaul CSR_WRITE_1(sc, RL_COMMAND, 0x00); 172440516Swpaul CSR_WRITE_2(sc, RL_IMR, 0x0000); 172581713Swpaul bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 172640516Swpaul 172740516Swpaul /* 172840516Swpaul * Free the TX list buffers. 172940516Swpaul */ 173040516Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 173145633Swpaul if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 173281713Swpaul bus_dmamap_unload(sc->rl_tag, 173381713Swpaul sc->rl_cdata.rl_tx_dmamap[i]); 173481713Swpaul bus_dmamap_destroy(sc->rl_tag, 173581713Swpaul sc->rl_cdata.rl_tx_dmamap[i]); 173645633Swpaul m_freem(sc->rl_cdata.rl_tx_chain[i]); 173745633Swpaul sc->rl_cdata.rl_tx_chain[i] = NULL; 173845633Swpaul CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 173940516Swpaul } 174040516Swpaul } 174140516Swpaul 174240516Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 174367087Swpaul RL_UNLOCK(sc); 174440516Swpaul return; 174540516Swpaul} 174640516Swpaul 174740516Swpaul/* 174886822Siwasaki * Device suspend routine. Stop the interface and save some PCI 174986822Siwasaki * settings in case the BIOS doesn't restore them properly on 175086822Siwasaki * resume. 175186822Siwasaki */ 175286822Siwasakistatic int rl_suspend(dev) 175386822Siwasaki device_t dev; 175486822Siwasaki{ 175586822Siwasaki register int i; 175686822Siwasaki struct rl_softc *sc; 175786822Siwasaki 175886822Siwasaki sc = device_get_softc(dev); 175986822Siwasaki 176086822Siwasaki rl_stop(sc); 176186822Siwasaki 176286822Siwasaki for (i = 0; i < 5; i++) 176386822Siwasaki sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 176486822Siwasaki sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 176586822Siwasaki sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 176686822Siwasaki sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 176786822Siwasaki sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 176886822Siwasaki 176986822Siwasaki sc->suspended = 1; 177086822Siwasaki 177186822Siwasaki return (0); 177286822Siwasaki} 177386822Siwasaki 177486822Siwasaki/* 177586822Siwasaki * Device resume routine. Restore some PCI settings in case the BIOS 177686822Siwasaki * doesn't, re-enable busmastering, and restart the interface if 177786822Siwasaki * appropriate. 177886822Siwasaki */ 177986822Siwasakistatic int rl_resume(dev) 178086822Siwasaki device_t dev; 178186822Siwasaki{ 178286822Siwasaki register int i; 178386822Siwasaki struct rl_softc *sc; 178486822Siwasaki struct ifnet *ifp; 178586822Siwasaki 178686822Siwasaki sc = device_get_softc(dev); 178786822Siwasaki ifp = &sc->arpcom.ac_if; 178886822Siwasaki 178986822Siwasaki /* better way to do this? */ 179086822Siwasaki for (i = 0; i < 5; i++) 179186822Siwasaki pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 179286822Siwasaki pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 179386822Siwasaki pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 179486822Siwasaki pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 179586822Siwasaki pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 179686822Siwasaki 179786822Siwasaki /* reenable busmastering */ 179886822Siwasaki pci_enable_busmaster(dev); 179986822Siwasaki pci_enable_io(dev, RL_RES); 180086822Siwasaki 180186822Siwasaki /* reinitialize interface if necessary */ 180286822Siwasaki if (ifp->if_flags & IFF_UP) 180386822Siwasaki rl_init(sc); 180486822Siwasaki 180586822Siwasaki sc->suspended = 0; 180686822Siwasaki 180786822Siwasaki return (0); 180886822Siwasaki} 180986822Siwasaki 181086822Siwasaki/* 181140516Swpaul * Stop all chip I/O so that the kernel's probe routines don't 181240516Swpaul * get confused by errant DMAs when rebooting. 181340516Swpaul */ 181450703Swpaulstatic void rl_shutdown(dev) 181550703Swpaul device_t dev; 181640516Swpaul{ 181750703Swpaul struct rl_softc *sc; 181840516Swpaul 181950703Swpaul sc = device_get_softc(dev); 182050703Swpaul 182140516Swpaul rl_stop(sc); 182240516Swpaul 182340516Swpaul return; 182440516Swpaul} 1825