if_rl.c revision 68215
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_rl.c 68215 2000-11-01 23:56:46Z wpaul $ 33 */ 34 35/* 36 * RealTek 8129/8139 PCI NIC driver 37 * 38 * Supports several extremely cheap PCI 10/100 adapters based on 39 * the RealTek chipset. Datasheets can be obtained from 40 * www.realtek.com.tw. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 49 * probably the worst PCI ethernet controller ever made, with the possible 50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 51 * DMA, but it has a terrible interface that nullifies any performance 52 * gains that bus-master DMA usually offers. 53 * 54 * For transmission, the chip offers a series of four TX descriptor 55 * registers. Each transmit frame must be in a contiguous buffer, aligned 56 * on a longword (32-bit) boundary. This means we almost always have to 57 * do mbuf copies in order to transmit a frame, except in the unlikely 58 * case where a) the packet fits into a single mbuf, and b) the packet 59 * is 32-bit aligned within the mbuf's data area. The presence of only 60 * four descriptor registers means that we can never have more than four 61 * packets queued for transmission at any one time. 62 * 63 * Reception is not much better. The driver has to allocate a single large 64 * buffer area (up to 64K in size) into which the chip will DMA received 65 * frames. Because we don't know where within this region received packets 66 * will begin or end, we have no choice but to copy data from the buffer 67 * area into mbufs in order to pass the packets up to the higher protocol 68 * levels. 69 * 70 * It's impossible given this rotten design to really achieve decent 71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 72 * some equally overmuscled CPU to drive it. 73 * 74 * On the bright side, the 8139 does have a built-in PHY, although 75 * rather than using an MDIO serial interface like most other NICs, the 76 * PHY registers are directly accessible through the 8139's register 77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 78 * filter. 79 * 80 * The 8129 chip is an older version of the 8139 that uses an external PHY 81 * chip. The 8129 has a serial MDIO interface for accessing the MII where 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86#include <sys/param.h> 87#include <sys/systm.h> 88#include <sys/sockio.h> 89#include <sys/mbuf.h> 90#include <sys/malloc.h> 91#include <sys/kernel.h> 92#include <sys/socket.h> 93 94#include <net/if.h> 95#include <net/if_arp.h> 96#include <net/ethernet.h> 97#include <net/if_dl.h> 98#include <net/if_media.h> 99 100#include <net/bpf.h> 101 102#include <vm/vm.h> /* for vtophys */ 103#include <vm/pmap.h> /* for vtophys */ 104#include <machine/bus_pio.h> 105#include <machine/bus_memio.h> 106#include <machine/bus.h> 107#include <machine/resource.h> 108#include <sys/bus.h> 109#include <sys/rman.h> 110 111#include <dev/mii/mii.h> 112#include <dev/mii/miivar.h> 113 114#include <pci/pcireg.h> 115#include <pci/pcivar.h> 116 117MODULE_DEPEND(rl, miibus, 1, 1, 1); 118 119/* "controller miibus0" required. See GENERIC if you get errors here. */ 120#include "miibus_if.h" 121 122/* 123 * Default to using PIO access for this driver. On SMP systems, 124 * there appear to be problems with memory mapped mode: it looks like 125 * doing too many memory mapped access back to back in rapid succession 126 * can hang the bus. I'm inclined to blame this on crummy design/construction 127 * on the part of RealTek. Memory mapped mode does appear to work on 128 * uniprocessor systems though. 129 */ 130#define RL_USEIOSPACE 131 132#include <pci/if_rlreg.h> 133 134#ifndef lint 135static const char rcsid[] = 136 "$FreeBSD: head/sys/pci/if_rl.c 68215 2000-11-01 23:56:46Z wpaul $"; 137#endif 138 139/* 140 * Various supported device vendors/types and their names. 141 */ 142static struct rl_type rl_devs[] = { 143 { RT_VENDORID, RT_DEVICEID_8129, 144 "RealTek 8129 10/100BaseTX" }, 145 { RT_VENDORID, RT_DEVICEID_8139, 146 "RealTek 8139 10/100BaseTX" }, 147 { RT_VENDORID, RT_DEVICEID_8138, 148 "RealTek 8139 10/100BaseTX CardBus" }, 149 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 150 "Accton MPX 5030/5038 10/100BaseTX" }, 151 { DELTA_VENDORID, DELTA_DEVICEID_8139, 152 "Delta Electronics 8139 10/100BaseTX" }, 153 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 154 "Addtron Technolgy 8139 10/100BaseTX" }, 155 { 0, 0, NULL } 156}; 157 158static int rl_probe __P((device_t)); 159static int rl_attach __P((device_t)); 160static int rl_detach __P((device_t)); 161 162static int rl_encap __P((struct rl_softc *, struct mbuf * )); 163 164static void rl_rxeof __P((struct rl_softc *)); 165static void rl_txeof __P((struct rl_softc *)); 166static void rl_intr __P((void *)); 167static void rl_tick __P((void *)); 168static void rl_start __P((struct ifnet *)); 169static int rl_ioctl __P((struct ifnet *, u_long, caddr_t)); 170static void rl_init __P((void *)); 171static void rl_stop __P((struct rl_softc *)); 172static void rl_watchdog __P((struct ifnet *)); 173static void rl_shutdown __P((device_t)); 174static int rl_ifmedia_upd __P((struct ifnet *)); 175static void rl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 176 177static void rl_eeprom_putbyte __P((struct rl_softc *, int)); 178static void rl_eeprom_getword __P((struct rl_softc *, int, u_int16_t *)); 179static void rl_read_eeprom __P((struct rl_softc *, caddr_t, 180 int, int, int)); 181static void rl_mii_sync __P((struct rl_softc *)); 182static void rl_mii_send __P((struct rl_softc *, u_int32_t, int)); 183static int rl_mii_readreg __P((struct rl_softc *, struct rl_mii_frame *)); 184static int rl_mii_writereg __P((struct rl_softc *, struct rl_mii_frame *)); 185 186static int rl_miibus_readreg __P((device_t, int, int)); 187static int rl_miibus_writereg __P((device_t, int, int, int)); 188static void rl_miibus_statchg __P((device_t)); 189 190static u_int8_t rl_calchash __P((caddr_t)); 191static void rl_setmulti __P((struct rl_softc *)); 192static void rl_reset __P((struct rl_softc *)); 193static int rl_list_tx_init __P((struct rl_softc *)); 194 195#ifdef RL_USEIOSPACE 196#define RL_RES SYS_RES_IOPORT 197#define RL_RID RL_PCI_LOIO 198#else 199#define RL_RES SYS_RES_MEMORY 200#define RL_RID RL_PCI_LOMEM 201#endif 202 203static device_method_t rl_methods[] = { 204 /* Device interface */ 205 DEVMETHOD(device_probe, rl_probe), 206 DEVMETHOD(device_attach, rl_attach), 207 DEVMETHOD(device_detach, rl_detach), 208 DEVMETHOD(device_shutdown, rl_shutdown), 209 210 /* bus interface */ 211 DEVMETHOD(bus_print_child, bus_generic_print_child), 212 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 213 214 /* MII interface */ 215 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 216 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 217 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 218 219 { 0, 0 } 220}; 221 222static driver_t rl_driver = { 223 "rl", 224 rl_methods, 225 sizeof(struct rl_softc) 226}; 227 228static devclass_t rl_devclass; 229 230DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 231DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0); 232DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 233 234#define EE_SET(x) \ 235 CSR_WRITE_1(sc, RL_EECMD, \ 236 CSR_READ_1(sc, RL_EECMD) | x) 237 238#define EE_CLR(x) \ 239 CSR_WRITE_1(sc, RL_EECMD, \ 240 CSR_READ_1(sc, RL_EECMD) & ~x) 241 242/* 243 * Send a read command and address to the EEPROM, check for ACK. 244 */ 245static void rl_eeprom_putbyte(sc, addr) 246 struct rl_softc *sc; 247 int addr; 248{ 249 register int d, i; 250 251 d = addr | sc->rl_eecmd_read; 252 253 /* 254 * Feed in each bit and strobe the clock. 255 */ 256 for (i = 0x400; i; i >>= 1) { 257 if (d & i) { 258 EE_SET(RL_EE_DATAIN); 259 } else { 260 EE_CLR(RL_EE_DATAIN); 261 } 262 DELAY(100); 263 EE_SET(RL_EE_CLK); 264 DELAY(150); 265 EE_CLR(RL_EE_CLK); 266 DELAY(100); 267 } 268 269 return; 270} 271 272/* 273 * Read a word of data stored in the EEPROM at address 'addr.' 274 */ 275static void rl_eeprom_getword(sc, addr, dest) 276 struct rl_softc *sc; 277 int addr; 278 u_int16_t *dest; 279{ 280 register int i; 281 u_int16_t word = 0; 282 283 /* Enter EEPROM access mode. */ 284 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 285 286 /* 287 * Send address of word we want to read. 288 */ 289 rl_eeprom_putbyte(sc, addr); 290 291 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 292 293 /* 294 * Start reading bits from EEPROM. 295 */ 296 for (i = 0x8000; i; i >>= 1) { 297 EE_SET(RL_EE_CLK); 298 DELAY(100); 299 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 300 word |= i; 301 EE_CLR(RL_EE_CLK); 302 DELAY(100); 303 } 304 305 /* Turn off EEPROM access mode. */ 306 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 307 308 *dest = word; 309 310 return; 311} 312 313/* 314 * Read a sequence of words from the EEPROM. 315 */ 316static void rl_read_eeprom(sc, dest, off, cnt, swap) 317 struct rl_softc *sc; 318 caddr_t dest; 319 int off; 320 int cnt; 321 int swap; 322{ 323 int i; 324 u_int16_t word = 0, *ptr; 325 326 for (i = 0; i < cnt; i++) { 327 rl_eeprom_getword(sc, off + i, &word); 328 ptr = (u_int16_t *)(dest + (i * 2)); 329 if (swap) 330 *ptr = ntohs(word); 331 else 332 *ptr = word; 333 } 334 335 return; 336} 337 338 339/* 340 * MII access routines are provided for the 8129, which 341 * doesn't have a built-in PHY. For the 8139, we fake things 342 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 343 * direct access PHY registers. 344 */ 345#define MII_SET(x) \ 346 CSR_WRITE_1(sc, RL_MII, \ 347 CSR_READ_1(sc, RL_MII) | x) 348 349#define MII_CLR(x) \ 350 CSR_WRITE_1(sc, RL_MII, \ 351 CSR_READ_1(sc, RL_MII) & ~x) 352 353/* 354 * Sync the PHYs by setting data bit and strobing the clock 32 times. 355 */ 356static void rl_mii_sync(sc) 357 struct rl_softc *sc; 358{ 359 register int i; 360 361 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 362 363 for (i = 0; i < 32; i++) { 364 MII_SET(RL_MII_CLK); 365 DELAY(1); 366 MII_CLR(RL_MII_CLK); 367 DELAY(1); 368 } 369 370 return; 371} 372 373/* 374 * Clock a series of bits through the MII. 375 */ 376static void rl_mii_send(sc, bits, cnt) 377 struct rl_softc *sc; 378 u_int32_t bits; 379 int cnt; 380{ 381 int i; 382 383 MII_CLR(RL_MII_CLK); 384 385 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 386 if (bits & i) { 387 MII_SET(RL_MII_DATAOUT); 388 } else { 389 MII_CLR(RL_MII_DATAOUT); 390 } 391 DELAY(1); 392 MII_CLR(RL_MII_CLK); 393 DELAY(1); 394 MII_SET(RL_MII_CLK); 395 } 396} 397 398/* 399 * Read an PHY register through the MII. 400 */ 401static int rl_mii_readreg(sc, frame) 402 struct rl_softc *sc; 403 struct rl_mii_frame *frame; 404 405{ 406 int i, ack; 407 408 RL_LOCK(sc); 409 410 /* 411 * Set up frame for RX. 412 */ 413 frame->mii_stdelim = RL_MII_STARTDELIM; 414 frame->mii_opcode = RL_MII_READOP; 415 frame->mii_turnaround = 0; 416 frame->mii_data = 0; 417 418 CSR_WRITE_2(sc, RL_MII, 0); 419 420 /* 421 * Turn on data xmit. 422 */ 423 MII_SET(RL_MII_DIR); 424 425 rl_mii_sync(sc); 426 427 /* 428 * Send command/address info. 429 */ 430 rl_mii_send(sc, frame->mii_stdelim, 2); 431 rl_mii_send(sc, frame->mii_opcode, 2); 432 rl_mii_send(sc, frame->mii_phyaddr, 5); 433 rl_mii_send(sc, frame->mii_regaddr, 5); 434 435 /* Idle bit */ 436 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 437 DELAY(1); 438 MII_SET(RL_MII_CLK); 439 DELAY(1); 440 441 /* Turn off xmit. */ 442 MII_CLR(RL_MII_DIR); 443 444 /* Check for ack */ 445 MII_CLR(RL_MII_CLK); 446 DELAY(1); 447 MII_SET(RL_MII_CLK); 448 DELAY(1); 449 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 450 451 /* 452 * Now try reading data bits. If the ack failed, we still 453 * need to clock through 16 cycles to keep the PHY(s) in sync. 454 */ 455 if (ack) { 456 for(i = 0; i < 16; i++) { 457 MII_CLR(RL_MII_CLK); 458 DELAY(1); 459 MII_SET(RL_MII_CLK); 460 DELAY(1); 461 } 462 goto fail; 463 } 464 465 for (i = 0x8000; i; i >>= 1) { 466 MII_CLR(RL_MII_CLK); 467 DELAY(1); 468 if (!ack) { 469 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 470 frame->mii_data |= i; 471 DELAY(1); 472 } 473 MII_SET(RL_MII_CLK); 474 DELAY(1); 475 } 476 477fail: 478 479 MII_CLR(RL_MII_CLK); 480 DELAY(1); 481 MII_SET(RL_MII_CLK); 482 DELAY(1); 483 484 RL_UNLOCK(sc); 485 486 if (ack) 487 return(1); 488 return(0); 489} 490 491/* 492 * Write to a PHY register through the MII. 493 */ 494static int rl_mii_writereg(sc, frame) 495 struct rl_softc *sc; 496 struct rl_mii_frame *frame; 497 498{ 499 RL_LOCK(sc); 500 501 /* 502 * Set up frame for TX. 503 */ 504 505 frame->mii_stdelim = RL_MII_STARTDELIM; 506 frame->mii_opcode = RL_MII_WRITEOP; 507 frame->mii_turnaround = RL_MII_TURNAROUND; 508 509 /* 510 * Turn on data output. 511 */ 512 MII_SET(RL_MII_DIR); 513 514 rl_mii_sync(sc); 515 516 rl_mii_send(sc, frame->mii_stdelim, 2); 517 rl_mii_send(sc, frame->mii_opcode, 2); 518 rl_mii_send(sc, frame->mii_phyaddr, 5); 519 rl_mii_send(sc, frame->mii_regaddr, 5); 520 rl_mii_send(sc, frame->mii_turnaround, 2); 521 rl_mii_send(sc, frame->mii_data, 16); 522 523 /* Idle bit. */ 524 MII_SET(RL_MII_CLK); 525 DELAY(1); 526 MII_CLR(RL_MII_CLK); 527 DELAY(1); 528 529 /* 530 * Turn off xmit. 531 */ 532 MII_CLR(RL_MII_DIR); 533 534 RL_UNLOCK(sc); 535 536 return(0); 537} 538 539static int rl_miibus_readreg(dev, phy, reg) 540 device_t dev; 541 int phy, reg; 542{ 543 struct rl_softc *sc; 544 struct rl_mii_frame frame; 545 u_int16_t rval = 0; 546 u_int16_t rl8139_reg = 0; 547 548 sc = device_get_softc(dev); 549 RL_LOCK(sc); 550 551 if (sc->rl_type == RL_8139) { 552 /* Pretend the internal PHY is only at address 0 */ 553 if (phy) { 554 RL_UNLOCK(sc); 555 return(0); 556 } 557 switch(reg) { 558 case MII_BMCR: 559 rl8139_reg = RL_BMCR; 560 break; 561 case MII_BMSR: 562 rl8139_reg = RL_BMSR; 563 break; 564 case MII_ANAR: 565 rl8139_reg = RL_ANAR; 566 break; 567 case MII_ANER: 568 rl8139_reg = RL_ANER; 569 break; 570 case MII_ANLPAR: 571 rl8139_reg = RL_LPAR; 572 break; 573 case MII_PHYIDR1: 574 case MII_PHYIDR2: 575 RL_UNLOCK(sc); 576 return(0); 577 break; 578 default: 579 printf("rl%d: bad phy register\n", sc->rl_unit); 580 RL_UNLOCK(sc); 581 return(0); 582 } 583 rval = CSR_READ_2(sc, rl8139_reg); 584 RL_UNLOCK(sc); 585 return(rval); 586 } 587 588 bzero((char *)&frame, sizeof(frame)); 589 590 frame.mii_phyaddr = phy; 591 frame.mii_regaddr = reg; 592 rl_mii_readreg(sc, &frame); 593 RL_UNLOCK(sc); 594 595 return(frame.mii_data); 596} 597 598static int rl_miibus_writereg(dev, phy, reg, data) 599 device_t dev; 600 int phy, reg, data; 601{ 602 struct rl_softc *sc; 603 struct rl_mii_frame frame; 604 u_int16_t rl8139_reg = 0; 605 606 sc = device_get_softc(dev); 607 RL_LOCK(sc); 608 609 if (sc->rl_type == RL_8139) { 610 /* Pretend the internal PHY is only at address 0 */ 611 if (phy) { 612 RL_UNLOCK(sc); 613 return(0); 614 } 615 switch(reg) { 616 case MII_BMCR: 617 rl8139_reg = RL_BMCR; 618 break; 619 case MII_BMSR: 620 rl8139_reg = RL_BMSR; 621 break; 622 case MII_ANAR: 623 rl8139_reg = RL_ANAR; 624 break; 625 case MII_ANER: 626 rl8139_reg = RL_ANER; 627 break; 628 case MII_ANLPAR: 629 rl8139_reg = RL_LPAR; 630 break; 631 case MII_PHYIDR1: 632 case MII_PHYIDR2: 633 RL_UNLOCK(sc); 634 return(0); 635 break; 636 default: 637 printf("rl%d: bad phy register\n", sc->rl_unit); 638 RL_UNLOCK(sc); 639 return(0); 640 } 641 CSR_WRITE_2(sc, rl8139_reg, data); 642 RL_UNLOCK(sc); 643 return(0); 644 } 645 646 bzero((char *)&frame, sizeof(frame)); 647 648 frame.mii_phyaddr = phy; 649 frame.mii_regaddr = reg; 650 frame.mii_data = data; 651 652 rl_mii_writereg(sc, &frame); 653 654 RL_UNLOCK(sc); 655 return(0); 656} 657 658static void rl_miibus_statchg(dev) 659 device_t dev; 660{ 661 return; 662} 663 664/* 665 * Calculate CRC of a multicast group address, return the upper 6 bits. 666 */ 667static u_int8_t rl_calchash(addr) 668 caddr_t addr; 669{ 670 u_int32_t crc, carry; 671 int i, j; 672 u_int8_t c; 673 674 /* Compute CRC for the address value. */ 675 crc = 0xFFFFFFFF; /* initial value */ 676 677 for (i = 0; i < 6; i++) { 678 c = *(addr + i); 679 for (j = 0; j < 8; j++) { 680 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 681 crc <<= 1; 682 c >>= 1; 683 if (carry) 684 crc = (crc ^ 0x04c11db6) | carry; 685 } 686 } 687 688 /* return the filter bit position */ 689 return(crc >> 26); 690} 691 692/* 693 * Program the 64-bit multicast hash filter. 694 */ 695static void rl_setmulti(sc) 696 struct rl_softc *sc; 697{ 698 struct ifnet *ifp; 699 int h = 0; 700 u_int32_t hashes[2] = { 0, 0 }; 701 struct ifmultiaddr *ifma; 702 u_int32_t rxfilt; 703 int mcnt = 0; 704 705 ifp = &sc->arpcom.ac_if; 706 707 rxfilt = CSR_READ_4(sc, RL_RXCFG); 708 709 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 710 rxfilt |= RL_RXCFG_RX_MULTI; 711 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 712 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 713 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 714 return; 715 } 716 717 /* first, zot all the existing hash bits */ 718 CSR_WRITE_4(sc, RL_MAR0, 0); 719 CSR_WRITE_4(sc, RL_MAR4, 0); 720 721 /* now program new ones */ 722 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 723 ifma = ifma->ifma_link.le_next) { 724 if (ifma->ifma_addr->sa_family != AF_LINK) 725 continue; 726 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 727 if (h < 32) 728 hashes[0] |= (1 << h); 729 else 730 hashes[1] |= (1 << (h - 32)); 731 mcnt++; 732 } 733 734 if (mcnt) 735 rxfilt |= RL_RXCFG_RX_MULTI; 736 else 737 rxfilt &= ~RL_RXCFG_RX_MULTI; 738 739 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 740 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 741 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 742 743 return; 744} 745 746static void rl_reset(sc) 747 struct rl_softc *sc; 748{ 749 register int i; 750 751 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 752 753 for (i = 0; i < RL_TIMEOUT; i++) { 754 DELAY(10); 755 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 756 break; 757 } 758 if (i == RL_TIMEOUT) 759 printf("rl%d: reset never completed!\n", sc->rl_unit); 760 761 return; 762} 763 764/* 765 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 766 * IDs against our list and return a device name if we find a match. 767 */ 768static int rl_probe(dev) 769 device_t dev; 770{ 771 struct rl_type *t; 772 773 t = rl_devs; 774 775 while(t->rl_name != NULL) { 776 if ((pci_get_vendor(dev) == t->rl_vid) && 777 (pci_get_device(dev) == t->rl_did)) { 778 device_set_desc(dev, t->rl_name); 779 return(0); 780 } 781 t++; 782 } 783 784 return(ENXIO); 785} 786 787/* 788 * Attach the interface. Allocate softc structures, do ifmedia 789 * setup and ethernet/BPF attach. 790 */ 791static int rl_attach(dev) 792 device_t dev; 793{ 794 u_char eaddr[ETHER_ADDR_LEN]; 795 u_int32_t command; 796 struct rl_softc *sc; 797 struct ifnet *ifp; 798 u_int16_t rl_did = 0; 799 int unit, error = 0, rid; 800 801 sc = device_get_softc(dev); 802 unit = device_get_unit(dev); 803 bzero(sc, sizeof(struct rl_softc)); 804 805 /* 806 * Handle power management nonsense. 807 */ 808 809 command = pci_read_config(dev, RL_PCI_CAPID, 4) & 0x000000FF; 810 if (command == 0x01) { 811 812 command = pci_read_config(dev, RL_PCI_PWRMGMTCTRL, 4); 813 if (command & RL_PSTATE_MASK) { 814 u_int32_t iobase, membase, irq; 815 816 /* Save important PCI config data. */ 817 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 818 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 819 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 820 821 /* Reset the power state. */ 822 printf("rl%d: chip is is in D%d power mode " 823 "-- setting to D0\n", unit, command & RL_PSTATE_MASK); 824 command &= 0xFFFFFFFC; 825 pci_write_config(dev, RL_PCI_PWRMGMTCTRL, command, 4); 826 827 /* Restore PCI config data. */ 828 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 829 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 830 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 831 } 832 } 833 834 /* 835 * Map control/status registers. 836 */ 837 command = pci_read_config(dev, PCIR_COMMAND, 4); 838 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 839 pci_write_config(dev, PCIR_COMMAND, command, 4); 840 command = pci_read_config(dev, PCIR_COMMAND, 4); 841 842#ifdef RL_USEIOSPACE 843 if (!(command & PCIM_CMD_PORTEN)) { 844 printf("rl%d: failed to enable I/O ports!\n", unit); 845 error = ENXIO; 846 goto fail; 847 } 848#else 849 if (!(command & PCIM_CMD_MEMEN)) { 850 printf("rl%d: failed to enable memory mapping!\n", unit); 851 error = ENXIO; 852 goto fail; 853 } 854#endif 855 856 rid = RL_RID; 857 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 858 0, ~0, 1, RF_ACTIVE); 859 860 if (sc->rl_res == NULL) { 861 printf ("rl%d: couldn't map ports/memory\n", unit); 862 error = ENXIO; 863 goto fail; 864 } 865 866 sc->rl_btag = rman_get_bustag(sc->rl_res); 867 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 868 869 rid = 0; 870 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 871 RF_SHAREABLE | RF_ACTIVE); 872 873 if (sc->rl_irq == NULL) { 874 printf("rl%d: couldn't map interrupt\n", unit); 875 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 876 error = ENXIO; 877 goto fail; 878 } 879 880 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 881 rl_intr, sc, &sc->rl_intrhand); 882 883 if (error) { 884 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 885 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 886 printf("rl%d: couldn't set up irq\n", unit); 887 goto fail; 888 } 889 890 callout_handle_init(&sc->rl_stat_ch); 891 892 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_DEF); 893 RL_LOCK(sc); 894 895 /* Reset the adapter. */ 896 rl_reset(sc); 897 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 898 rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 899 if (rl_did != 0x8129) 900 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 901 902 /* 903 * Get station address from the EEPROM. 904 */ 905 rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0); 906 907 /* 908 * A RealTek chip was detected. Inform the world. 909 */ 910 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 911 912 sc->rl_unit = unit; 913 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 914 915 /* 916 * Now read the exact device type from the EEPROM to find 917 * out if it's an 8129 or 8139. 918 */ 919 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 920 921 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 922 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 923 rl_did == RT_DEVICEID_8138) 924 sc->rl_type = RL_8139; 925 else if (rl_did == RT_DEVICEID_8129) 926 sc->rl_type = RL_8129; 927 else { 928 printf("rl%d: unknown device ID: %x\n", unit, rl_did); 929 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 930 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 931 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 932 error = ENXIO; 933 goto fail; 934 } 935 936 sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 1518, M_DEVBUF, 937 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 938 939 if (sc->rl_cdata.rl_rx_buf == NULL) { 940 printf("rl%d: no memory for list buffers!\n", unit); 941 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 942 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 943 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 944 error = ENXIO; 945 goto fail; 946 } 947 948 /* Leave a few bytes before the start of the RX ring buffer. */ 949 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 950 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 951 952 /* Do MII setup */ 953 if (mii_phy_probe(dev, &sc->rl_miibus, 954 rl_ifmedia_upd, rl_ifmedia_sts)) { 955 printf("rl%d: MII without any phy!\n", sc->rl_unit); 956 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 957 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 958 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 959 free(sc->rl_cdata.rl_rx_buf, M_DEVBUF); 960 error = ENXIO; 961 goto fail; 962 } 963 964 ifp = &sc->arpcom.ac_if; 965 ifp->if_softc = sc; 966 ifp->if_unit = unit; 967 ifp->if_name = "rl"; 968 ifp->if_mtu = ETHERMTU; 969 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 970 ifp->if_ioctl = rl_ioctl; 971 ifp->if_output = ether_output; 972 ifp->if_start = rl_start; 973 ifp->if_watchdog = rl_watchdog; 974 ifp->if_init = rl_init; 975 ifp->if_baudrate = 10000000; 976 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 977 978 /* 979 * Call MI attach routine. 980 */ 981 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 982 RL_UNLOCK(sc); 983 return(0); 984 985fail: 986 RL_UNLOCK(sc); 987 mtx_destroy(&sc->rl_mtx); 988 return(error); 989} 990 991static int rl_detach(dev) 992 device_t dev; 993{ 994 struct rl_softc *sc; 995 struct ifnet *ifp; 996 997 sc = device_get_softc(dev); 998 RL_LOCK(sc); 999 ifp = &sc->arpcom.ac_if; 1000 1001 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1002 rl_stop(sc); 1003 1004 bus_generic_detach(dev); 1005 device_delete_child(dev, sc->rl_miibus); 1006 1007 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1008 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1009 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1010 1011 contigfree(sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN + 32, M_DEVBUF); 1012 1013 RL_UNLOCK(sc); 1014 mtx_destroy(&sc->rl_mtx); 1015 1016 return(0); 1017} 1018 1019/* 1020 * Initialize the transmit descriptors. 1021 */ 1022static int rl_list_tx_init(sc) 1023 struct rl_softc *sc; 1024{ 1025 struct rl_chain_data *cd; 1026 int i; 1027 1028 cd = &sc->rl_cdata; 1029 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1030 cd->rl_tx_chain[i] = NULL; 1031 CSR_WRITE_4(sc, 1032 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 1033 } 1034 1035 sc->rl_cdata.cur_tx = 0; 1036 sc->rl_cdata.last_tx = 0; 1037 1038 return(0); 1039} 1040 1041/* 1042 * A frame has been uploaded: pass the resulting mbuf chain up to 1043 * the higher level protocols. 1044 * 1045 * You know there's something wrong with a PCI bus-master chip design 1046 * when you have to use m_devget(). 1047 * 1048 * The receive operation is badly documented in the datasheet, so I'll 1049 * attempt to document it here. The driver provides a buffer area and 1050 * places its base address in the RX buffer start address register. 1051 * The chip then begins copying frames into the RX buffer. Each frame 1052 * is preceeded by a 32-bit RX status word which specifies the length 1053 * of the frame and certain other status bits. Each frame (starting with 1054 * the status word) is also 32-bit aligned. The frame length is in the 1055 * first 16 bits of the status word; the lower 15 bits correspond with 1056 * the 'rx status register' mentioned in the datasheet. 1057 * 1058 * Note: to make the Alpha happy, the frame payload needs to be aligned 1059 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from 1060 * the ring buffer starting at an address two bytes before the actual 1061 * data location. We can then shave off the first two bytes using m_adj(). 1062 * The reason we do this is because m_devget() doesn't let us specify an 1063 * offset into the mbuf storage space, so we have to artificially create 1064 * one. The ring is allocated in such a way that there are a few unused 1065 * bytes of space preceecing it so that it will be safe for us to do the 1066 * 2-byte backstep even if reading from the ring at offset 0. 1067 */ 1068static void rl_rxeof(sc) 1069 struct rl_softc *sc; 1070{ 1071 struct ether_header *eh; 1072 struct mbuf *m; 1073 struct ifnet *ifp; 1074 int total_len = 0; 1075 u_int32_t rxstat; 1076 caddr_t rxbufpos; 1077 int wrap = 0; 1078 u_int16_t cur_rx; 1079 u_int16_t limit; 1080 u_int16_t rx_bytes = 0, max_bytes; 1081 1082 ifp = &sc->arpcom.ac_if; 1083 1084 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1085 1086 /* Do not try to read past this point. */ 1087 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1088 1089 if (limit < cur_rx) 1090 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1091 else 1092 max_bytes = limit - cur_rx; 1093 1094 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1095 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1096 rxstat = *(u_int32_t *)rxbufpos; 1097 1098 /* 1099 * Here's a totally undocumented fact for you. When the 1100 * RealTek chip is in the process of copying a packet into 1101 * RAM for you, the length will be 0xfff0. If you spot a 1102 * packet header with this value, you need to stop. The 1103 * datasheet makes absolutely no mention of this and 1104 * RealTek should be shot for this. 1105 */ 1106 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1107 break; 1108 1109 if (!(rxstat & RL_RXSTAT_RXOK)) { 1110 ifp->if_ierrors++; 1111 rl_init(sc); 1112 return; 1113 } 1114 1115 /* No errors; receive the packet. */ 1116 total_len = rxstat >> 16; 1117 rx_bytes += total_len + 4; 1118 1119 /* 1120 * XXX The RealTek chip includes the CRC with every 1121 * received frame, and there's no way to turn this 1122 * behavior off (at least, I can't find anything in 1123 * the manual that explains how to do it) so we have 1124 * to trim off the CRC manually. 1125 */ 1126 total_len -= ETHER_CRC_LEN; 1127 1128 /* 1129 * Avoid trying to read more bytes than we know 1130 * the chip has prepared for us. 1131 */ 1132 if (rx_bytes > max_bytes) 1133 break; 1134 1135 rxbufpos = sc->rl_cdata.rl_rx_buf + 1136 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 1137 1138 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1139 rxbufpos = sc->rl_cdata.rl_rx_buf; 1140 1141 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1142 1143 if (total_len > wrap) { 1144 /* 1145 * Fool m_devget() into thinking we want to copy 1146 * the whole buffer so we don't end up fragmenting 1147 * the data. 1148 */ 1149 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1150 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 1151 if (m == NULL) { 1152 ifp->if_ierrors++; 1153 printf("rl%d: out of mbufs, tried to " 1154 "copy %d bytes\n", sc->rl_unit, wrap); 1155 } else { 1156 m_adj(m, RL_ETHER_ALIGN); 1157 m_copyback(m, wrap, total_len - wrap, 1158 sc->rl_cdata.rl_rx_buf); 1159 } 1160 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1161 } else { 1162 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1163 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 1164 if (m == NULL) { 1165 ifp->if_ierrors++; 1166 printf("rl%d: out of mbufs, tried to " 1167 "copy %d bytes\n", sc->rl_unit, total_len); 1168 } else 1169 m_adj(m, RL_ETHER_ALIGN); 1170 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1171 } 1172 1173 /* 1174 * Round up to 32-bit boundary. 1175 */ 1176 cur_rx = (cur_rx + 3) & ~3; 1177 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1178 1179 if (m == NULL) 1180 continue; 1181 1182 eh = mtod(m, struct ether_header *); 1183 ifp->if_ipackets++; 1184 1185 /* Remove header from mbuf and pass it on. */ 1186 m_adj(m, sizeof(struct ether_header)); 1187 ether_input(ifp, eh, m); 1188 } 1189 1190 return; 1191} 1192 1193/* 1194 * A frame was downloaded to the chip. It's safe for us to clean up 1195 * the list buffers. 1196 */ 1197static void rl_txeof(sc) 1198 struct rl_softc *sc; 1199{ 1200 struct ifnet *ifp; 1201 u_int32_t txstat; 1202 1203 ifp = &sc->arpcom.ac_if; 1204 1205 /* Clear the timeout timer. */ 1206 ifp->if_timer = 0; 1207 1208 /* 1209 * Go through our tx list and free mbufs for those 1210 * frames that have been uploaded. 1211 */ 1212 do { 1213 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1214 if (!(txstat & (RL_TXSTAT_TX_OK| 1215 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1216 break; 1217 1218 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1219 1220 if (RL_LAST_TXMBUF(sc) != NULL) { 1221 m_freem(RL_LAST_TXMBUF(sc)); 1222 RL_LAST_TXMBUF(sc) = NULL; 1223 } 1224 if (txstat & RL_TXSTAT_TX_OK) 1225 ifp->if_opackets++; 1226 else { 1227 int oldthresh; 1228 ifp->if_oerrors++; 1229 if ((txstat & RL_TXSTAT_TXABRT) || 1230 (txstat & RL_TXSTAT_OUTOFWIN)) 1231 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1232 oldthresh = sc->rl_txthresh; 1233 /* error recovery */ 1234 rl_reset(sc); 1235 rl_init(sc); 1236 /* 1237 * If there was a transmit underrun, 1238 * bump the TX threshold. 1239 */ 1240 if (txstat & RL_TXSTAT_TX_UNDERRUN) 1241 sc->rl_txthresh = oldthresh + 32; 1242 return; 1243 } 1244 RL_INC(sc->rl_cdata.last_tx); 1245 ifp->if_flags &= ~IFF_OACTIVE; 1246 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1247 1248 return; 1249} 1250 1251static void rl_tick(xsc) 1252 void *xsc; 1253{ 1254 struct rl_softc *sc; 1255 struct mii_data *mii; 1256 1257 sc = xsc; 1258 RL_LOCK(sc); 1259 mii = device_get_softc(sc->rl_miibus); 1260 1261 mii_tick(mii); 1262 1263 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1264 RL_UNLOCK(sc); 1265 1266 return; 1267} 1268 1269static void rl_intr(arg) 1270 void *arg; 1271{ 1272 struct rl_softc *sc; 1273 struct ifnet *ifp; 1274 u_int16_t status; 1275 1276 sc = arg; 1277 RL_LOCK(sc); 1278 ifp = &sc->arpcom.ac_if; 1279 1280 /* Disable interrupts. */ 1281 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1282 1283 for (;;) { 1284 1285 status = CSR_READ_2(sc, RL_ISR); 1286 if (status) 1287 CSR_WRITE_2(sc, RL_ISR, status); 1288 1289 if ((status & RL_INTRS) == 0) 1290 break; 1291 1292 if (status & RL_ISR_RX_OK) 1293 rl_rxeof(sc); 1294 1295 if (status & RL_ISR_RX_ERR) 1296 rl_rxeof(sc); 1297 1298 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1299 rl_txeof(sc); 1300 1301 if (status & RL_ISR_SYSTEM_ERR) { 1302 rl_reset(sc); 1303 rl_init(sc); 1304 } 1305 1306 } 1307 1308 /* Re-enable interrupts. */ 1309 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1310 1311 if (ifp->if_snd.ifq_head != NULL) 1312 rl_start(ifp); 1313 1314 RL_UNLOCK(sc); 1315 1316 return; 1317} 1318 1319/* 1320 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1321 * pointers to the fragment pointers. 1322 */ 1323static int rl_encap(sc, m_head) 1324 struct rl_softc *sc; 1325 struct mbuf *m_head; 1326{ 1327 struct mbuf *m_new = NULL; 1328 1329 /* 1330 * The RealTek is brain damaged and wants longword-aligned 1331 * TX buffers, plus we can only have one fragment buffer 1332 * per packet. We have to copy pretty much all the time. 1333 */ 1334 1335 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1336 if (m_new == NULL) { 1337 printf("rl%d: no memory for tx list", sc->rl_unit); 1338 return(1); 1339 } 1340 if (m_head->m_pkthdr.len > MHLEN) { 1341 MCLGET(m_new, M_DONTWAIT); 1342 if (!(m_new->m_flags & M_EXT)) { 1343 m_freem(m_new); 1344 printf("rl%d: no memory for tx list", 1345 sc->rl_unit); 1346 return(1); 1347 } 1348 } 1349 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1350 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1351 m_freem(m_head); 1352 m_head = m_new; 1353 1354 /* Pad frames to at least 60 bytes. */ 1355 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1356 /* 1357 * Make security concious people happy: zero out the 1358 * bytes in the pad area, since we don't know what 1359 * this mbuf cluster buffer's previous user might 1360 * have left in it. 1361 */ 1362 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1363 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1364 m_head->m_pkthdr.len += 1365 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1366 m_head->m_len = m_head->m_pkthdr.len; 1367 } 1368 1369 RL_CUR_TXMBUF(sc) = m_head; 1370 1371 return(0); 1372} 1373 1374/* 1375 * Main transmit routine. 1376 */ 1377 1378static void rl_start(ifp) 1379 struct ifnet *ifp; 1380{ 1381 struct rl_softc *sc; 1382 struct mbuf *m_head = NULL; 1383 1384 sc = ifp->if_softc; 1385 RL_LOCK(sc); 1386 1387 while(RL_CUR_TXMBUF(sc) == NULL) { 1388 IF_DEQUEUE(&ifp->if_snd, m_head); 1389 if (m_head == NULL) 1390 break; 1391 1392 if (rl_encap(sc, m_head)) { 1393 IF_PREPEND(&ifp->if_snd, m_head); 1394 ifp->if_flags |= IFF_OACTIVE; 1395 break; 1396 } 1397 1398 /* 1399 * If there's a BPF listener, bounce a copy of this frame 1400 * to him. 1401 */ 1402 if (ifp->if_bpf) 1403 bpf_mtap(ifp, RL_CUR_TXMBUF(sc)); 1404 1405 /* 1406 * Transmit the frame. 1407 */ 1408 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), 1409 vtophys(mtod(RL_CUR_TXMBUF(sc), caddr_t))); 1410 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1411 RL_TXTHRESH(sc->rl_txthresh) | 1412 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1413 1414 RL_INC(sc->rl_cdata.cur_tx); 1415 } 1416 1417 /* 1418 * We broke out of the loop because all our TX slots are 1419 * full. Mark the NIC as busy until it drains some of the 1420 * packets from the queue. 1421 */ 1422 if (RL_CUR_TXMBUF(sc) != NULL) 1423 ifp->if_flags |= IFF_OACTIVE; 1424 1425 /* 1426 * Set a timeout in case the chip goes out to lunch. 1427 */ 1428 ifp->if_timer = 5; 1429 RL_UNLOCK(sc); 1430 1431 return; 1432} 1433 1434static void rl_init(xsc) 1435 void *xsc; 1436{ 1437 struct rl_softc *sc = xsc; 1438 struct ifnet *ifp = &sc->arpcom.ac_if; 1439 struct mii_data *mii; 1440 int i; 1441 u_int32_t rxcfg = 0; 1442 1443 RL_LOCK(sc); 1444 mii = device_get_softc(sc->rl_miibus); 1445 1446 /* 1447 * Cancel pending I/O and free all RX/TX buffers. 1448 */ 1449 rl_stop(sc); 1450 1451 /* Init our MAC address */ 1452 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1453 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 1454 } 1455 1456 /* Init the RX buffer pointer register. */ 1457 CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf)); 1458 1459 /* Init TX descriptors. */ 1460 rl_list_tx_init(sc); 1461 1462 /* 1463 * Enable transmit and receive. 1464 */ 1465 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1466 1467 /* 1468 * Set the initial TX and RX configuration. 1469 */ 1470 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1471 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1472 1473 /* Set the individual bit to receive frames for this host only. */ 1474 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1475 rxcfg |= RL_RXCFG_RX_INDIV; 1476 1477 /* If we want promiscuous mode, set the allframes bit. */ 1478 if (ifp->if_flags & IFF_PROMISC) { 1479 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1480 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1481 } else { 1482 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1483 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1484 } 1485 1486 /* 1487 * Set capture broadcast bit to capture broadcast frames. 1488 */ 1489 if (ifp->if_flags & IFF_BROADCAST) { 1490 rxcfg |= RL_RXCFG_RX_BROAD; 1491 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1492 } else { 1493 rxcfg &= ~RL_RXCFG_RX_BROAD; 1494 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1495 } 1496 1497 /* 1498 * Program the multicast filter, if necessary. 1499 */ 1500 rl_setmulti(sc); 1501 1502 /* 1503 * Enable interrupts. 1504 */ 1505 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1506 1507 /* Set initial TX threshold */ 1508 sc->rl_txthresh = RL_TX_THRESH_INIT; 1509 1510 /* Start RX/TX process. */ 1511 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1512 1513 /* Enable receiver and transmitter. */ 1514 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1515 1516 mii_mediachg(mii); 1517 1518 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1519 1520 ifp->if_flags |= IFF_RUNNING; 1521 ifp->if_flags &= ~IFF_OACTIVE; 1522 1523 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1524 RL_UNLOCK(sc); 1525 1526 return; 1527} 1528 1529/* 1530 * Set media options. 1531 */ 1532static int rl_ifmedia_upd(ifp) 1533 struct ifnet *ifp; 1534{ 1535 struct rl_softc *sc; 1536 struct mii_data *mii; 1537 1538 sc = ifp->if_softc; 1539 mii = device_get_softc(sc->rl_miibus); 1540 mii_mediachg(mii); 1541 1542 return(0); 1543} 1544 1545/* 1546 * Report current media status. 1547 */ 1548static void rl_ifmedia_sts(ifp, ifmr) 1549 struct ifnet *ifp; 1550 struct ifmediareq *ifmr; 1551{ 1552 struct rl_softc *sc; 1553 struct mii_data *mii; 1554 1555 sc = ifp->if_softc; 1556 mii = device_get_softc(sc->rl_miibus); 1557 1558 mii_pollstat(mii); 1559 ifmr->ifm_active = mii->mii_media_active; 1560 ifmr->ifm_status = mii->mii_media_status; 1561 1562 return; 1563} 1564 1565static int rl_ioctl(ifp, command, data) 1566 struct ifnet *ifp; 1567 u_long command; 1568 caddr_t data; 1569{ 1570 struct rl_softc *sc = ifp->if_softc; 1571 struct ifreq *ifr = (struct ifreq *) data; 1572 struct mii_data *mii; 1573 int error = 0; 1574 1575 RL_LOCK(sc); 1576 1577 switch(command) { 1578 case SIOCSIFADDR: 1579 case SIOCGIFADDR: 1580 case SIOCSIFMTU: 1581 error = ether_ioctl(ifp, command, data); 1582 break; 1583 case SIOCSIFFLAGS: 1584 if (ifp->if_flags & IFF_UP) { 1585 rl_init(sc); 1586 } else { 1587 if (ifp->if_flags & IFF_RUNNING) 1588 rl_stop(sc); 1589 } 1590 error = 0; 1591 break; 1592 case SIOCADDMULTI: 1593 case SIOCDELMULTI: 1594 rl_setmulti(sc); 1595 error = 0; 1596 break; 1597 case SIOCGIFMEDIA: 1598 case SIOCSIFMEDIA: 1599 mii = device_get_softc(sc->rl_miibus); 1600 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1601 break; 1602 default: 1603 error = EINVAL; 1604 break; 1605 } 1606 1607 RL_UNLOCK(sc); 1608 1609 return(error); 1610} 1611 1612static void rl_watchdog(ifp) 1613 struct ifnet *ifp; 1614{ 1615 struct rl_softc *sc; 1616 1617 sc = ifp->if_softc; 1618 RL_LOCK(sc); 1619 printf("rl%d: watchdog timeout\n", sc->rl_unit); 1620 ifp->if_oerrors++; 1621 1622 rl_txeof(sc); 1623 rl_rxeof(sc); 1624 rl_init(sc); 1625 RL_UNLOCK(sc); 1626 1627 return; 1628} 1629 1630/* 1631 * Stop the adapter and free any mbufs allocated to the 1632 * RX and TX lists. 1633 */ 1634static void rl_stop(sc) 1635 struct rl_softc *sc; 1636{ 1637 register int i; 1638 struct ifnet *ifp; 1639 1640 RL_LOCK(sc); 1641 ifp = &sc->arpcom.ac_if; 1642 ifp->if_timer = 0; 1643 1644 untimeout(rl_tick, sc, sc->rl_stat_ch); 1645 1646 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1647 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1648 1649 /* 1650 * Free the TX list buffers. 1651 */ 1652 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1653 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1654 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1655 sc->rl_cdata.rl_tx_chain[i] = NULL; 1656 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 1657 } 1658 } 1659 1660 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1661 RL_UNLOCK(sc); 1662 return; 1663} 1664 1665/* 1666 * Stop all chip I/O so that the kernel's probe routines don't 1667 * get confused by errant DMAs when rebooting. 1668 */ 1669static void rl_shutdown(dev) 1670 device_t dev; 1671{ 1672 struct rl_softc *sc; 1673 1674 sc = device_get_softc(dev); 1675 1676 rl_stop(sc); 1677 1678 return; 1679} 1680