if_rl.c revision 58801
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_rl.c 58801 2000-03-29 20:06:15Z wpaul $ 33 */ 34 35/* 36 * RealTek 8129/8139 PCI NIC driver 37 * 38 * Supports several extremely cheap PCI 10/100 adapters based on 39 * the RealTek chipset. Datasheets can be obtained from 40 * www.realtek.com.tw. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 49 * probably the worst PCI ethernet controller ever made, with the possible 50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 51 * DMA, but it has a terrible interface that nullifies any performance 52 * gains that bus-master DMA usually offers. 53 * 54 * For transmission, the chip offers a series of four TX descriptor 55 * registers. Each transmit frame must be in a contiguous buffer, aligned 56 * on a longword (32-bit) boundary. This means we almost always have to 57 * do mbuf copies in order to transmit a frame, except in the unlikely 58 * case where a) the packet fits into a single mbuf, and b) the packet 59 * is 32-bit aligned within the mbuf's data area. The presence of only 60 * four descriptor registers means that we can never have more than four 61 * packets queued for transmission at any one time. 62 * 63 * Reception is not much better. The driver has to allocate a single large 64 * buffer area (up to 64K in size) into which the chip will DMA received 65 * frames. Because we don't know where within this region received packets 66 * will begin or end, we have no choice but to copy data from the buffer 67 * area into mbufs in order to pass the packets up to the higher protocol 68 * levels. 69 * 70 * It's impossible given this rotten design to really achieve decent 71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 72 * some equally overmuscled CPU to drive it. 73 * 74 * On the bright side, the 8139 does have a built-in PHY, although 75 * rather than using an MDIO serial interface like most other NICs, the 76 * PHY registers are directly accessible through the 8139's register 77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 78 * filter. 79 * 80 * The 8129 chip is an older version of the 8139 that uses an external PHY 81 * chip. The 8129 has a serial MDIO interface for accessing the MII where 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86#include <sys/param.h> 87#include <sys/systm.h> 88#include <sys/sockio.h> 89#include <sys/mbuf.h> 90#include <sys/malloc.h> 91#include <sys/kernel.h> 92#include <sys/socket.h> 93 94#include <net/if.h> 95#include <net/if_arp.h> 96#include <net/ethernet.h> 97#include <net/if_dl.h> 98#include <net/if_media.h> 99 100#include <net/bpf.h> 101 102#include <vm/vm.h> /* for vtophys */ 103#include <vm/pmap.h> /* for vtophys */ 104#include <machine/clock.h> /* for DELAY */ 105#include <machine/bus_pio.h> 106#include <machine/bus_memio.h> 107#include <machine/bus.h> 108#include <machine/resource.h> 109#include <sys/bus.h> 110#include <sys/rman.h> 111 112#include <dev/mii/mii.h> 113#include <dev/mii/miivar.h> 114 115#include <pci/pcireg.h> 116#include <pci/pcivar.h> 117 118/* "controller miibus0" required. See GENERIC if you get errors here. */ 119#include "miibus_if.h" 120 121/* 122 * Default to using PIO access for this driver. On SMP systems, 123 * there appear to be problems with memory mapped mode: it looks like 124 * doing too many memory mapped access back to back in rapid succession 125 * can hang the bus. I'm inclined to blame this on crummy design/construction 126 * on the part of RealTek. Memory mapped mode does appear to work on 127 * uniprocessor systems though. 128 */ 129#define RL_USEIOSPACE 130 131#include <pci/if_rlreg.h> 132 133#ifndef lint 134static const char rcsid[] = 135 "$FreeBSD: head/sys/pci/if_rl.c 58801 2000-03-29 20:06:15Z wpaul $"; 136#endif 137 138/* 139 * Various supported device vendors/types and their names. 140 */ 141static struct rl_type rl_devs[] = { 142 { RT_VENDORID, RT_DEVICEID_8129, 143 "RealTek 8129 10/100BaseTX" }, 144 { RT_VENDORID, RT_DEVICEID_8139, 145 "RealTek 8139 10/100BaseTX" }, 146 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 147 "Accton MPX 5030/5038 10/100BaseTX" }, 148 { DELTA_VENDORID, DELTA_DEVICEID_8139, 149 "Delta Electronics 8139 10/100BaseTX" }, 150 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 151 "Addtron Technolgy 8139 10/100BaseTX" }, 152 { 0, 0, NULL } 153}; 154 155static int rl_probe __P((device_t)); 156static int rl_attach __P((device_t)); 157static int rl_detach __P((device_t)); 158 159static int rl_encap __P((struct rl_softc *, struct mbuf * )); 160 161static void rl_rxeof __P((struct rl_softc *)); 162static void rl_txeof __P((struct rl_softc *)); 163static void rl_intr __P((void *)); 164static void rl_tick __P((void *)); 165static void rl_start __P((struct ifnet *)); 166static int rl_ioctl __P((struct ifnet *, u_long, caddr_t)); 167static void rl_init __P((void *)); 168static void rl_stop __P((struct rl_softc *)); 169static void rl_watchdog __P((struct ifnet *)); 170static void rl_shutdown __P((device_t)); 171static int rl_ifmedia_upd __P((struct ifnet *)); 172static void rl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 173 174static void rl_eeprom_putbyte __P((struct rl_softc *, int)); 175static void rl_eeprom_getword __P((struct rl_softc *, int, u_int16_t *)); 176static void rl_read_eeprom __P((struct rl_softc *, caddr_t, 177 int, int, int)); 178static void rl_mii_sync __P((struct rl_softc *)); 179static void rl_mii_send __P((struct rl_softc *, u_int32_t, int)); 180static int rl_mii_readreg __P((struct rl_softc *, struct rl_mii_frame *)); 181static int rl_mii_writereg __P((struct rl_softc *, struct rl_mii_frame *)); 182 183static int rl_miibus_readreg __P((device_t, int, int)); 184static int rl_miibus_writereg __P((device_t, int, int, int)); 185static void rl_miibus_statchg __P((device_t)); 186 187static u_int8_t rl_calchash __P((caddr_t)); 188static void rl_setmulti __P((struct rl_softc *)); 189static void rl_reset __P((struct rl_softc *)); 190static int rl_list_tx_init __P((struct rl_softc *)); 191 192#ifdef RL_USEIOSPACE 193#define RL_RES SYS_RES_IOPORT 194#define RL_RID RL_PCI_LOIO 195#else 196#define RL_RES SYS_RES_MEMORY 197#define RL_RID RL_PCI_LOMEM 198#endif 199 200static device_method_t rl_methods[] = { 201 /* Device interface */ 202 DEVMETHOD(device_probe, rl_probe), 203 DEVMETHOD(device_attach, rl_attach), 204 DEVMETHOD(device_detach, rl_detach), 205 DEVMETHOD(device_shutdown, rl_shutdown), 206 207 /* bus interface */ 208 DEVMETHOD(bus_print_child, bus_generic_print_child), 209 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 210 211 /* MII interface */ 212 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 213 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 214 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 215 216 { 0, 0 } 217}; 218 219static driver_t rl_driver = { 220 "rl", 221 rl_methods, 222 sizeof(struct rl_softc) 223}; 224 225static devclass_t rl_devclass; 226 227DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 228DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 229 230#define EE_SET(x) \ 231 CSR_WRITE_1(sc, RL_EECMD, \ 232 CSR_READ_1(sc, RL_EECMD) | x) 233 234#define EE_CLR(x) \ 235 CSR_WRITE_1(sc, RL_EECMD, \ 236 CSR_READ_1(sc, RL_EECMD) & ~x) 237 238/* 239 * Send a read command and address to the EEPROM, check for ACK. 240 */ 241static void rl_eeprom_putbyte(sc, addr) 242 struct rl_softc *sc; 243 int addr; 244{ 245 register int d, i; 246 247 d = addr | RL_EECMD_READ; 248 249 /* 250 * Feed in each bit and strobe the clock. 251 */ 252 for (i = 0x400; i; i >>= 1) { 253 if (d & i) { 254 EE_SET(RL_EE_DATAIN); 255 } else { 256 EE_CLR(RL_EE_DATAIN); 257 } 258 DELAY(100); 259 EE_SET(RL_EE_CLK); 260 DELAY(150); 261 EE_CLR(RL_EE_CLK); 262 DELAY(100); 263 } 264 265 return; 266} 267 268/* 269 * Read a word of data stored in the EEPROM at address 'addr.' 270 */ 271static void rl_eeprom_getword(sc, addr, dest) 272 struct rl_softc *sc; 273 int addr; 274 u_int16_t *dest; 275{ 276 register int i; 277 u_int16_t word = 0; 278 279 /* Enter EEPROM access mode. */ 280 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 281 282 /* 283 * Send address of word we want to read. 284 */ 285 rl_eeprom_putbyte(sc, addr); 286 287 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 288 289 /* 290 * Start reading bits from EEPROM. 291 */ 292 for (i = 0x8000; i; i >>= 1) { 293 EE_SET(RL_EE_CLK); 294 DELAY(100); 295 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 296 word |= i; 297 EE_CLR(RL_EE_CLK); 298 DELAY(100); 299 } 300 301 /* Turn off EEPROM access mode. */ 302 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 303 304 *dest = word; 305 306 return; 307} 308 309/* 310 * Read a sequence of words from the EEPROM. 311 */ 312static void rl_read_eeprom(sc, dest, off, cnt, swap) 313 struct rl_softc *sc; 314 caddr_t dest; 315 int off; 316 int cnt; 317 int swap; 318{ 319 int i; 320 u_int16_t word = 0, *ptr; 321 322 for (i = 0; i < cnt; i++) { 323 rl_eeprom_getword(sc, off + i, &word); 324 ptr = (u_int16_t *)(dest + (i * 2)); 325 if (swap) 326 *ptr = ntohs(word); 327 else 328 *ptr = word; 329 } 330 331 return; 332} 333 334 335/* 336 * MII access routines are provided for the 8129, which 337 * doesn't have a built-in PHY. For the 8139, we fake things 338 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 339 * direct access PHY registers. 340 */ 341#define MII_SET(x) \ 342 CSR_WRITE_1(sc, RL_MII, \ 343 CSR_READ_1(sc, RL_MII) | x) 344 345#define MII_CLR(x) \ 346 CSR_WRITE_1(sc, RL_MII, \ 347 CSR_READ_1(sc, RL_MII) & ~x) 348 349/* 350 * Sync the PHYs by setting data bit and strobing the clock 32 times. 351 */ 352static void rl_mii_sync(sc) 353 struct rl_softc *sc; 354{ 355 register int i; 356 357 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 358 359 for (i = 0; i < 32; i++) { 360 MII_SET(RL_MII_CLK); 361 DELAY(1); 362 MII_CLR(RL_MII_CLK); 363 DELAY(1); 364 } 365 366 return; 367} 368 369/* 370 * Clock a series of bits through the MII. 371 */ 372static void rl_mii_send(sc, bits, cnt) 373 struct rl_softc *sc; 374 u_int32_t bits; 375 int cnt; 376{ 377 int i; 378 379 MII_CLR(RL_MII_CLK); 380 381 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 382 if (bits & i) { 383 MII_SET(RL_MII_DATAOUT); 384 } else { 385 MII_CLR(RL_MII_DATAOUT); 386 } 387 DELAY(1); 388 MII_CLR(RL_MII_CLK); 389 DELAY(1); 390 MII_SET(RL_MII_CLK); 391 } 392} 393 394/* 395 * Read an PHY register through the MII. 396 */ 397static int rl_mii_readreg(sc, frame) 398 struct rl_softc *sc; 399 struct rl_mii_frame *frame; 400 401{ 402 int i, ack, s; 403 404 s = splimp(); 405 406 /* 407 * Set up frame for RX. 408 */ 409 frame->mii_stdelim = RL_MII_STARTDELIM; 410 frame->mii_opcode = RL_MII_READOP; 411 frame->mii_turnaround = 0; 412 frame->mii_data = 0; 413 414 CSR_WRITE_2(sc, RL_MII, 0); 415 416 /* 417 * Turn on data xmit. 418 */ 419 MII_SET(RL_MII_DIR); 420 421 rl_mii_sync(sc); 422 423 /* 424 * Send command/address info. 425 */ 426 rl_mii_send(sc, frame->mii_stdelim, 2); 427 rl_mii_send(sc, frame->mii_opcode, 2); 428 rl_mii_send(sc, frame->mii_phyaddr, 5); 429 rl_mii_send(sc, frame->mii_regaddr, 5); 430 431 /* Idle bit */ 432 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 433 DELAY(1); 434 MII_SET(RL_MII_CLK); 435 DELAY(1); 436 437 /* Turn off xmit. */ 438 MII_CLR(RL_MII_DIR); 439 440 /* Check for ack */ 441 MII_CLR(RL_MII_CLK); 442 DELAY(1); 443 MII_SET(RL_MII_CLK); 444 DELAY(1); 445 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 446 447 /* 448 * Now try reading data bits. If the ack failed, we still 449 * need to clock through 16 cycles to keep the PHY(s) in sync. 450 */ 451 if (ack) { 452 for(i = 0; i < 16; i++) { 453 MII_CLR(RL_MII_CLK); 454 DELAY(1); 455 MII_SET(RL_MII_CLK); 456 DELAY(1); 457 } 458 goto fail; 459 } 460 461 for (i = 0x8000; i; i >>= 1) { 462 MII_CLR(RL_MII_CLK); 463 DELAY(1); 464 if (!ack) { 465 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 466 frame->mii_data |= i; 467 DELAY(1); 468 } 469 MII_SET(RL_MII_CLK); 470 DELAY(1); 471 } 472 473fail: 474 475 MII_CLR(RL_MII_CLK); 476 DELAY(1); 477 MII_SET(RL_MII_CLK); 478 DELAY(1); 479 480 splx(s); 481 482 if (ack) 483 return(1); 484 return(0); 485} 486 487/* 488 * Write to a PHY register through the MII. 489 */ 490static int rl_mii_writereg(sc, frame) 491 struct rl_softc *sc; 492 struct rl_mii_frame *frame; 493 494{ 495 int s; 496 497 s = splimp(); 498 /* 499 * Set up frame for TX. 500 */ 501 502 frame->mii_stdelim = RL_MII_STARTDELIM; 503 frame->mii_opcode = RL_MII_WRITEOP; 504 frame->mii_turnaround = RL_MII_TURNAROUND; 505 506 /* 507 * Turn on data output. 508 */ 509 MII_SET(RL_MII_DIR); 510 511 rl_mii_sync(sc); 512 513 rl_mii_send(sc, frame->mii_stdelim, 2); 514 rl_mii_send(sc, frame->mii_opcode, 2); 515 rl_mii_send(sc, frame->mii_phyaddr, 5); 516 rl_mii_send(sc, frame->mii_regaddr, 5); 517 rl_mii_send(sc, frame->mii_turnaround, 2); 518 rl_mii_send(sc, frame->mii_data, 16); 519 520 /* Idle bit. */ 521 MII_SET(RL_MII_CLK); 522 DELAY(1); 523 MII_CLR(RL_MII_CLK); 524 DELAY(1); 525 526 /* 527 * Turn off xmit. 528 */ 529 MII_CLR(RL_MII_DIR); 530 531 splx(s); 532 533 return(0); 534} 535 536static int rl_miibus_readreg(dev, phy, reg) 537 device_t dev; 538 int phy, reg; 539{ 540 struct rl_softc *sc; 541 struct rl_mii_frame frame; 542 u_int16_t rval = 0; 543 u_int16_t rl8139_reg = 0; 544 545 sc = device_get_softc(dev); 546 547 if (sc->rl_type == RL_8139) { 548 /* Pretend the internal PHY is only at address 0 */ 549 if (phy) 550 return(0); 551 switch(reg) { 552 case MII_BMCR: 553 rl8139_reg = RL_BMCR; 554 break; 555 case MII_BMSR: 556 rl8139_reg = RL_BMSR; 557 break; 558 case MII_ANAR: 559 rl8139_reg = RL_ANAR; 560 break; 561 case MII_ANER: 562 rl8139_reg = RL_ANER; 563 break; 564 case MII_ANLPAR: 565 rl8139_reg = RL_LPAR; 566 break; 567 case MII_PHYIDR1: 568 case MII_PHYIDR2: 569 return(0); 570 break; 571 default: 572 printf("rl%d: bad phy register\n", sc->rl_unit); 573 return(0); 574 } 575 rval = CSR_READ_2(sc, rl8139_reg); 576 return(rval); 577 } 578 579 bzero((char *)&frame, sizeof(frame)); 580 581 frame.mii_phyaddr = phy; 582 frame.mii_regaddr = reg; 583 rl_mii_readreg(sc, &frame); 584 585 return(frame.mii_data); 586} 587 588static int rl_miibus_writereg(dev, phy, reg, data) 589 device_t dev; 590 int phy, reg, data; 591{ 592 struct rl_softc *sc; 593 struct rl_mii_frame frame; 594 u_int16_t rl8139_reg = 0; 595 596 sc = device_get_softc(dev); 597 598 if (sc->rl_type == RL_8139) { 599 /* Pretend the internal PHY is only at address 0 */ 600 if (phy) 601 return(0); 602 switch(reg) { 603 case MII_BMCR: 604 rl8139_reg = RL_BMCR; 605 break; 606 case MII_BMSR: 607 rl8139_reg = RL_BMSR; 608 break; 609 case MII_ANAR: 610 rl8139_reg = RL_ANAR; 611 break; 612 case MII_ANER: 613 rl8139_reg = RL_ANER; 614 break; 615 case MII_ANLPAR: 616 rl8139_reg = RL_LPAR; 617 break; 618 case MII_PHYIDR1: 619 case MII_PHYIDR2: 620 return(0); 621 break; 622 default: 623 printf("rl%d: bad phy register\n", sc->rl_unit); 624 return(0); 625 } 626 CSR_WRITE_2(sc, rl8139_reg, data); 627 return(0); 628 } 629 630 bzero((char *)&frame, sizeof(frame)); 631 632 frame.mii_phyaddr = phy; 633 frame.mii_regaddr = reg; 634 frame.mii_data = data; 635 636 rl_mii_writereg(sc, &frame); 637 638 return(0); 639} 640 641static void rl_miibus_statchg(dev) 642 device_t dev; 643{ 644 return; 645} 646 647/* 648 * Calculate CRC of a multicast group address, return the upper 6 bits. 649 */ 650static u_int8_t rl_calchash(addr) 651 caddr_t addr; 652{ 653 u_int32_t crc, carry; 654 int i, j; 655 u_int8_t c; 656 657 /* Compute CRC for the address value. */ 658 crc = 0xFFFFFFFF; /* initial value */ 659 660 for (i = 0; i < 6; i++) { 661 c = *(addr + i); 662 for (j = 0; j < 8; j++) { 663 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 664 crc <<= 1; 665 c >>= 1; 666 if (carry) 667 crc = (crc ^ 0x04c11db6) | carry; 668 } 669 } 670 671 /* return the filter bit position */ 672 return(crc >> 26); 673} 674 675/* 676 * Program the 64-bit multicast hash filter. 677 */ 678static void rl_setmulti(sc) 679 struct rl_softc *sc; 680{ 681 struct ifnet *ifp; 682 int h = 0; 683 u_int32_t hashes[2] = { 0, 0 }; 684 struct ifmultiaddr *ifma; 685 u_int32_t rxfilt; 686 int mcnt = 0; 687 688 ifp = &sc->arpcom.ac_if; 689 690 rxfilt = CSR_READ_4(sc, RL_RXCFG); 691 692 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 693 rxfilt |= RL_RXCFG_RX_MULTI; 694 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 695 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 696 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 697 return; 698 } 699 700 /* first, zot all the existing hash bits */ 701 CSR_WRITE_4(sc, RL_MAR0, 0); 702 CSR_WRITE_4(sc, RL_MAR4, 0); 703 704 /* now program new ones */ 705 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 706 ifma = ifma->ifma_link.le_next) { 707 if (ifma->ifma_addr->sa_family != AF_LINK) 708 continue; 709 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 710 if (h < 32) 711 hashes[0] |= (1 << h); 712 else 713 hashes[1] |= (1 << (h - 32)); 714 mcnt++; 715 } 716 717 if (mcnt) 718 rxfilt |= RL_RXCFG_RX_MULTI; 719 else 720 rxfilt &= ~RL_RXCFG_RX_MULTI; 721 722 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 723 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 724 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 725 726 return; 727} 728 729static void rl_reset(sc) 730 struct rl_softc *sc; 731{ 732 register int i; 733 734 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 735 736 for (i = 0; i < RL_TIMEOUT; i++) { 737 DELAY(10); 738 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 739 break; 740 } 741 if (i == RL_TIMEOUT) 742 printf("rl%d: reset never completed!\n", sc->rl_unit); 743 744 return; 745} 746 747/* 748 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 749 * IDs against our list and return a device name if we find a match. 750 */ 751static int rl_probe(dev) 752 device_t dev; 753{ 754 struct rl_type *t; 755 756 t = rl_devs; 757 758 while(t->rl_name != NULL) { 759 if ((pci_get_vendor(dev) == t->rl_vid) && 760 (pci_get_device(dev) == t->rl_did)) { 761 device_set_desc(dev, t->rl_name); 762 return(0); 763 } 764 t++; 765 } 766 767 return(ENXIO); 768} 769 770/* 771 * Attach the interface. Allocate softc structures, do ifmedia 772 * setup and ethernet/BPF attach. 773 */ 774static int rl_attach(dev) 775 device_t dev; 776{ 777 int s; 778 u_char eaddr[ETHER_ADDR_LEN]; 779 u_int32_t command; 780 struct rl_softc *sc; 781 struct ifnet *ifp; 782 u_int16_t rl_did = 0; 783 int unit, error = 0, rid; 784 785 s = splimp(); 786 787 sc = device_get_softc(dev); 788 unit = device_get_unit(dev); 789 bzero(sc, sizeof(struct rl_softc)); 790 791 /* 792 * Handle power management nonsense. 793 */ 794 795 command = pci_read_config(dev, RL_PCI_CAPID, 4) & 0x000000FF; 796 if (command == 0x01) { 797 798 command = pci_read_config(dev, RL_PCI_PWRMGMTCTRL, 4); 799 if (command & RL_PSTATE_MASK) { 800 u_int32_t iobase, membase, irq; 801 802 /* Save important PCI config data. */ 803 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 804 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 805 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 806 807 /* Reset the power state. */ 808 printf("rl%d: chip is is in D%d power mode " 809 "-- setting to D0\n", unit, command & RL_PSTATE_MASK); 810 command &= 0xFFFFFFFC; 811 pci_write_config(dev, RL_PCI_PWRMGMTCTRL, command, 4); 812 813 /* Restore PCI config data. */ 814 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 815 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 816 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 817 } 818 } 819 820 /* 821 * Map control/status registers. 822 */ 823 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 824 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 825 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 826 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 827 828#ifdef RL_USEIOSPACE 829 if (!(command & PCIM_CMD_PORTEN)) { 830 printf("rl%d: failed to enable I/O ports!\n", unit); 831 error = ENXIO; 832 goto fail; 833 } 834#else 835 if (!(command & PCIM_CMD_MEMEN)) { 836 printf("rl%d: failed to enable memory mapping!\n", unit); 837 error = ENXIO; 838 goto fail; 839 } 840#endif 841 842 rid = RL_RID; 843 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 844 0, ~0, 1, RF_ACTIVE); 845 846 if (sc->rl_res == NULL) { 847 printf ("rl%d: couldn't map ports/memory\n", unit); 848 error = ENXIO; 849 goto fail; 850 } 851 852 sc->rl_btag = rman_get_bustag(sc->rl_res); 853 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 854 855 rid = 0; 856 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 857 RF_SHAREABLE | RF_ACTIVE); 858 859 if (sc->rl_irq == NULL) { 860 printf("rl%d: couldn't map interrupt\n", unit); 861 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 862 error = ENXIO; 863 goto fail; 864 } 865 866 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 867 rl_intr, sc, &sc->rl_intrhand); 868 869 if (error) { 870 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res); 871 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 872 printf("rl%d: couldn't set up irq\n", unit); 873 goto fail; 874 } 875 876 callout_handle_init(&sc->rl_stat_ch); 877 878 /* Reset the adapter. */ 879 rl_reset(sc); 880 881 /* 882 * Get station address from the EEPROM. 883 */ 884 rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0); 885 886 /* 887 * A RealTek chip was detected. Inform the world. 888 */ 889 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 890 891 sc->rl_unit = unit; 892 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 893 894 /* 895 * Now read the exact device type from the EEPROM to find 896 * out if it's an 8129 or 8139. 897 */ 898 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 899 900 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 901 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139) 902 sc->rl_type = RL_8139; 903 else if (rl_did == RT_DEVICEID_8129) 904 sc->rl_type = RL_8129; 905 else { 906 printf("rl%d: unknown device ID: %x\n", unit, rl_did); 907 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 908 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res); 909 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 910 error = ENXIO; 911 goto fail; 912 } 913 914 sc->rl_cdata.rl_rx_buf = contigmalloc(RL_RXBUFLEN + 32, M_DEVBUF, 915 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 916 917 if (sc->rl_cdata.rl_rx_buf == NULL) { 918 printf("rl%d: no memory for list buffers!\n", unit); 919 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 920 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res); 921 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 922 error = ENXIO; 923 goto fail; 924 } 925 926 /* Leave a few bytes before the start of the RX ring buffer. */ 927 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 928 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 929 930 /* Do MII setup */ 931 if (mii_phy_probe(dev, &sc->rl_miibus, 932 rl_ifmedia_upd, rl_ifmedia_sts)) { 933 printf("rl%d: MII without any phy!\n", sc->rl_unit); 934 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 935 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res); 936 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 937 free(sc->rl_cdata.rl_rx_buf, M_DEVBUF); 938 error = ENXIO; 939 goto fail; 940 } 941 942 ifp = &sc->arpcom.ac_if; 943 ifp->if_softc = sc; 944 ifp->if_unit = unit; 945 ifp->if_name = "rl"; 946 ifp->if_mtu = ETHERMTU; 947 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 948 ifp->if_ioctl = rl_ioctl; 949 ifp->if_output = ether_output; 950 ifp->if_start = rl_start; 951 ifp->if_watchdog = rl_watchdog; 952 ifp->if_init = rl_init; 953 ifp->if_baudrate = 10000000; 954 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 955 956 /* 957 * Call MI attach routines. 958 */ 959 if_attach(ifp); 960 ether_ifattach(ifp); 961 962 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 963 964fail: 965 splx(s); 966 return(error); 967} 968 969static int rl_detach(dev) 970 device_t dev; 971{ 972 struct rl_softc *sc; 973 struct ifnet *ifp; 974 int s; 975 976 s = splimp(); 977 978 sc = device_get_softc(dev); 979 ifp = &sc->arpcom.ac_if; 980 981 if_detach(ifp); 982 rl_stop(sc); 983 984 bus_generic_detach(dev); 985 device_delete_child(dev, sc->rl_miibus); 986 987 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 988 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_res); 989 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 990 991 contigfree(sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN + 32, M_DEVBUF); 992 993 splx(s); 994 995 return(0); 996} 997 998/* 999 * Initialize the transmit descriptors. 1000 */ 1001static int rl_list_tx_init(sc) 1002 struct rl_softc *sc; 1003{ 1004 struct rl_chain_data *cd; 1005 int i; 1006 1007 cd = &sc->rl_cdata; 1008 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1009 cd->rl_tx_chain[i] = NULL; 1010 CSR_WRITE_4(sc, 1011 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 1012 } 1013 1014 sc->rl_cdata.cur_tx = 0; 1015 sc->rl_cdata.last_tx = 0; 1016 1017 return(0); 1018} 1019 1020/* 1021 * A frame has been uploaded: pass the resulting mbuf chain up to 1022 * the higher level protocols. 1023 * 1024 * You know there's something wrong with a PCI bus-master chip design 1025 * when you have to use m_devget(). 1026 * 1027 * The receive operation is badly documented in the datasheet, so I'll 1028 * attempt to document it here. The driver provides a buffer area and 1029 * places its base address in the RX buffer start address register. 1030 * The chip then begins copying frames into the RX buffer. Each frame 1031 * is preceeded by a 32-bit RX status word which specifies the length 1032 * of the frame and certain other status bits. Each frame (starting with 1033 * the status word) is also 32-bit aligned. The frame length is in the 1034 * first 16 bits of the status word; the lower 15 bits correspond with 1035 * the 'rx status register' mentioned in the datasheet. 1036 * 1037 * Note: to make the Alpha happy, the frame payload needs to be aligned 1038 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from 1039 * the ring buffer starting at an address two bytes before the actual 1040 * data location. We can then shave off the first two bytes using m_adj(). 1041 * The reason we do this is because m_devget() doesn't let us specify an 1042 * offset into the mbuf storage space, so we have to artificially create 1043 * one. The ring is allocated in such a way that there are a few unused 1044 * bytes of space preceecing it so that it will be safe for us to do the 1045 * 2-byte backstep even if reading from the ring at offset 0. 1046 */ 1047static void rl_rxeof(sc) 1048 struct rl_softc *sc; 1049{ 1050 struct ether_header *eh; 1051 struct mbuf *m; 1052 struct ifnet *ifp; 1053 int total_len = 0; 1054 u_int32_t rxstat; 1055 caddr_t rxbufpos; 1056 int wrap = 0; 1057 u_int16_t cur_rx; 1058 u_int16_t limit; 1059 u_int16_t rx_bytes = 0, max_bytes; 1060 1061 ifp = &sc->arpcom.ac_if; 1062 1063 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1064 1065 /* Do not try to read past this point. */ 1066 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1067 1068 if (limit < cur_rx) 1069 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1070 else 1071 max_bytes = limit - cur_rx; 1072 1073 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1074 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1075 rxstat = *(u_int32_t *)rxbufpos; 1076 1077 /* 1078 * Here's a totally undocumented fact for you. When the 1079 * RealTek chip is in the process of copying a packet into 1080 * RAM for you, the length will be 0xfff0. If you spot a 1081 * packet header with this value, you need to stop. The 1082 * datasheet makes absolutely no mention of this and 1083 * RealTek should be shot for this. 1084 */ 1085 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1086 break; 1087 1088 if (!(rxstat & RL_RXSTAT_RXOK)) { 1089 ifp->if_ierrors++; 1090 rl_init(sc); 1091 return; 1092 } 1093 1094 /* No errors; receive the packet. */ 1095 total_len = rxstat >> 16; 1096 rx_bytes += total_len + 4; 1097 1098 /* 1099 * XXX The RealTek chip includes the CRC with every 1100 * received frame, and there's no way to turn this 1101 * behavior off (at least, I can't find anything in 1102 * the manual that explains how to do it) so we have 1103 * to trim off the CRC manually. 1104 */ 1105 total_len -= ETHER_CRC_LEN; 1106 1107 /* 1108 * Avoid trying to read more bytes than we know 1109 * the chip has prepared for us. 1110 */ 1111 if (rx_bytes > max_bytes) 1112 break; 1113 1114 rxbufpos = sc->rl_cdata.rl_rx_buf + 1115 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 1116 1117 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1118 rxbufpos = sc->rl_cdata.rl_rx_buf; 1119 1120 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1121 1122 if (total_len > wrap) { 1123 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1124 wrap + RL_ETHER_ALIGN, 0, ifp, NULL); 1125 if (m == NULL) { 1126 ifp->if_ierrors++; 1127 printf("rl%d: out of mbufs, tried to " 1128 "copy %d bytes\n", sc->rl_unit, wrap); 1129 } else { 1130 m_adj(m, RL_ETHER_ALIGN); 1131 m_copyback(m, wrap, total_len - wrap, 1132 sc->rl_cdata.rl_rx_buf); 1133 if (m->m_len < sizeof(struct ether_header)) 1134 m = m_pullup(m, 1135 sizeof(struct ether_header)); 1136 if (m == NULL) { 1137 printf("rl%d: m_pullup failed", 1138 sc->rl_unit); 1139 ifp->if_ierrors++; 1140 } 1141 } 1142 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1143 } else { 1144 m = m_devget(rxbufpos - RL_ETHER_ALIGN, 1145 total_len + RL_ETHER_ALIGN, 0, ifp, NULL); 1146 if (m == NULL) { 1147 ifp->if_ierrors++; 1148 printf("rl%d: out of mbufs, tried to " 1149 "copy %d bytes\n", sc->rl_unit, total_len); 1150 } else 1151 m_adj(m, RL_ETHER_ALIGN); 1152 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1153 } 1154 1155 /* 1156 * Round up to 32-bit boundary. 1157 */ 1158 cur_rx = (cur_rx + 3) & ~3; 1159 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1160 1161 if (m == NULL) 1162 continue; 1163 1164 eh = mtod(m, struct ether_header *); 1165 ifp->if_ipackets++; 1166 1167 /* 1168 * Handle BPF listeners. Let the BPF user see the packet, but 1169 * don't pass it up to the ether_input() layer unless it's 1170 * a broadcast packet, multicast packet, matches our ethernet 1171 * address or the interface is in promiscuous mode. 1172 */ 1173 if (ifp->if_bpf) { 1174 bpf_mtap(ifp, m); 1175 if (ifp->if_flags & IFF_PROMISC && 1176 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1177 ETHER_ADDR_LEN) && 1178 (eh->ether_dhost[0] & 1) == 0)) { 1179 m_freem(m); 1180 continue; 1181 } 1182 } 1183 1184 /* Remove header from mbuf and pass it on. */ 1185 m_adj(m, sizeof(struct ether_header)); 1186 ether_input(ifp, eh, m); 1187 } 1188 1189 return; 1190} 1191 1192/* 1193 * A frame was downloaded to the chip. It's safe for us to clean up 1194 * the list buffers. 1195 */ 1196static void rl_txeof(sc) 1197 struct rl_softc *sc; 1198{ 1199 struct ifnet *ifp; 1200 u_int32_t txstat; 1201 1202 ifp = &sc->arpcom.ac_if; 1203 1204 /* Clear the timeout timer. */ 1205 ifp->if_timer = 0; 1206 1207 /* 1208 * Go through our tx list and free mbufs for those 1209 * frames that have been uploaded. 1210 */ 1211 do { 1212 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1213 if (!(txstat & (RL_TXSTAT_TX_OK| 1214 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1215 break; 1216 1217 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1218 1219 if (RL_LAST_TXMBUF(sc) != NULL) { 1220 m_freem(RL_LAST_TXMBUF(sc)); 1221 RL_LAST_TXMBUF(sc) = NULL; 1222 } 1223 if (txstat & RL_TXSTAT_TX_OK) 1224 ifp->if_opackets++; 1225 else { 1226 int oldthresh; 1227 ifp->if_oerrors++; 1228 if ((txstat & RL_TXSTAT_TXABRT) || 1229 (txstat & RL_TXSTAT_OUTOFWIN)) 1230 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1231 oldthresh = sc->rl_txthresh; 1232 /* error recovery */ 1233 rl_reset(sc); 1234 rl_init(sc); 1235 /* 1236 * If there was a transmit underrun, 1237 * bump the TX threshold. 1238 */ 1239 if (txstat & RL_TXSTAT_TX_UNDERRUN) 1240 sc->rl_txthresh = oldthresh + 32; 1241 return; 1242 } 1243 RL_INC(sc->rl_cdata.last_tx); 1244 ifp->if_flags &= ~IFF_OACTIVE; 1245 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1246 1247 return; 1248} 1249 1250static void rl_tick(xsc) 1251 void *xsc; 1252{ 1253 struct rl_softc *sc; 1254 struct mii_data *mii; 1255 int s; 1256 1257 s = splimp(); 1258 1259 sc = xsc; 1260 mii = device_get_softc(sc->rl_miibus); 1261 1262 mii_tick(mii); 1263 1264 splx(s); 1265 1266 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1267 1268 return; 1269} 1270 1271static void rl_intr(arg) 1272 void *arg; 1273{ 1274 struct rl_softc *sc; 1275 struct ifnet *ifp; 1276 u_int16_t status; 1277 1278 sc = arg; 1279 ifp = &sc->arpcom.ac_if; 1280 1281 /* Disable interrupts. */ 1282 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1283 1284 for (;;) { 1285 1286 status = CSR_READ_2(sc, RL_ISR); 1287 if (status) 1288 CSR_WRITE_2(sc, RL_ISR, status); 1289 1290 if ((status & RL_INTRS) == 0) 1291 break; 1292 1293 if (status & RL_ISR_RX_OK) 1294 rl_rxeof(sc); 1295 1296 if (status & RL_ISR_RX_ERR) 1297 rl_rxeof(sc); 1298 1299 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1300 rl_txeof(sc); 1301 1302 if (status & RL_ISR_SYSTEM_ERR) { 1303 rl_reset(sc); 1304 rl_init(sc); 1305 } 1306 1307 } 1308 1309 /* Re-enable interrupts. */ 1310 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1311 1312 if (ifp->if_snd.ifq_head != NULL) 1313 rl_start(ifp); 1314 1315 return; 1316} 1317 1318/* 1319 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1320 * pointers to the fragment pointers. 1321 */ 1322static int rl_encap(sc, m_head) 1323 struct rl_softc *sc; 1324 struct mbuf *m_head; 1325{ 1326 struct mbuf *m_new = NULL; 1327 1328 /* 1329 * The RealTek is brain damaged and wants longword-aligned 1330 * TX buffers, plus we can only have one fragment buffer 1331 * per packet. We have to copy pretty much all the time. 1332 */ 1333 1334 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1335 if (m_new == NULL) { 1336 printf("rl%d: no memory for tx list", sc->rl_unit); 1337 return(1); 1338 } 1339 if (m_head->m_pkthdr.len > MHLEN) { 1340 MCLGET(m_new, M_DONTWAIT); 1341 if (!(m_new->m_flags & M_EXT)) { 1342 m_freem(m_new); 1343 printf("rl%d: no memory for tx list", 1344 sc->rl_unit); 1345 return(1); 1346 } 1347 } 1348 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1349 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1350 m_freem(m_head); 1351 m_head = m_new; 1352 1353 /* Pad frames to at least 60 bytes. */ 1354 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1355 /* 1356 * Make security concious people happy: zero out the 1357 * bytes in the pad area, since we don't know what 1358 * this mbuf cluster buffer's previous user might 1359 * have left in it. 1360 */ 1361 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1362 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1363 m_head->m_pkthdr.len += 1364 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1365 m_head->m_len = m_head->m_pkthdr.len; 1366 } 1367 1368 RL_CUR_TXMBUF(sc) = m_head; 1369 1370 return(0); 1371} 1372 1373/* 1374 * Main transmit routine. 1375 */ 1376 1377static void rl_start(ifp) 1378 struct ifnet *ifp; 1379{ 1380 struct rl_softc *sc; 1381 struct mbuf *m_head = NULL; 1382 1383 sc = ifp->if_softc; 1384 1385 while(RL_CUR_TXMBUF(sc) == NULL) { 1386 IF_DEQUEUE(&ifp->if_snd, m_head); 1387 if (m_head == NULL) 1388 break; 1389 1390 if (rl_encap(sc, m_head)) { 1391 IF_PREPEND(&ifp->if_snd, m_head); 1392 ifp->if_flags |= IFF_OACTIVE; 1393 break; 1394 } 1395 1396 /* 1397 * If there's a BPF listener, bounce a copy of this frame 1398 * to him. 1399 */ 1400 if (ifp->if_bpf) 1401 bpf_mtap(ifp, RL_CUR_TXMBUF(sc)); 1402 1403 /* 1404 * Transmit the frame. 1405 */ 1406 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), 1407 vtophys(mtod(RL_CUR_TXMBUF(sc), caddr_t))); 1408 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1409 RL_TXTHRESH(sc->rl_txthresh) | 1410 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1411 1412 RL_INC(sc->rl_cdata.cur_tx); 1413 } 1414 1415 /* 1416 * We broke out of the loop because all our TX slots are 1417 * full. Mark the NIC as busy until it drains some of the 1418 * packets from the queue. 1419 */ 1420 if (RL_CUR_TXMBUF(sc) != NULL) 1421 ifp->if_flags |= IFF_OACTIVE; 1422 1423 /* 1424 * Set a timeout in case the chip goes out to lunch. 1425 */ 1426 ifp->if_timer = 5; 1427 1428 return; 1429} 1430 1431static void rl_init(xsc) 1432 void *xsc; 1433{ 1434 struct rl_softc *sc = xsc; 1435 struct ifnet *ifp = &sc->arpcom.ac_if; 1436 struct mii_data *mii; 1437 int s, i; 1438 u_int32_t rxcfg = 0; 1439 1440 s = splimp(); 1441 1442 mii = device_get_softc(sc->rl_miibus); 1443 1444 /* 1445 * Cancel pending I/O and free all RX/TX buffers. 1446 */ 1447 rl_stop(sc); 1448 1449 /* Init our MAC address */ 1450 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1451 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 1452 } 1453 1454 /* Init the RX buffer pointer register. */ 1455 CSR_WRITE_4(sc, RL_RXADDR, vtophys(sc->rl_cdata.rl_rx_buf)); 1456 1457 /* Init TX descriptors. */ 1458 rl_list_tx_init(sc); 1459 1460 /* 1461 * Enable transmit and receive. 1462 */ 1463 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1464 1465 /* 1466 * Set the initial TX and RX configuration. 1467 */ 1468 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1469 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1470 1471 /* Set the individual bit to receive frames for this host only. */ 1472 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1473 rxcfg |= RL_RXCFG_RX_INDIV; 1474 1475 /* If we want promiscuous mode, set the allframes bit. */ 1476 if (ifp->if_flags & IFF_PROMISC) { 1477 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1478 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1479 } else { 1480 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1481 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1482 } 1483 1484 /* 1485 * Set capture broadcast bit to capture broadcast frames. 1486 */ 1487 if (ifp->if_flags & IFF_BROADCAST) { 1488 rxcfg |= RL_RXCFG_RX_BROAD; 1489 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1490 } else { 1491 rxcfg &= ~RL_RXCFG_RX_BROAD; 1492 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1493 } 1494 1495 /* 1496 * Program the multicast filter, if necessary. 1497 */ 1498 rl_setmulti(sc); 1499 1500 /* 1501 * Enable interrupts. 1502 */ 1503 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1504 1505 /* Set initial TX threshold */ 1506 sc->rl_txthresh = RL_TX_THRESH_INIT; 1507 1508 /* Start RX/TX process. */ 1509 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1510 1511 /* Enable receiver and transmitter. */ 1512 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1513 1514 mii_mediachg(mii); 1515 1516 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1517 1518 ifp->if_flags |= IFF_RUNNING; 1519 ifp->if_flags &= ~IFF_OACTIVE; 1520 1521 (void)splx(s); 1522 1523 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1524 1525 return; 1526} 1527 1528/* 1529 * Set media options. 1530 */ 1531static int rl_ifmedia_upd(ifp) 1532 struct ifnet *ifp; 1533{ 1534 struct rl_softc *sc; 1535 struct mii_data *mii; 1536 1537 sc = ifp->if_softc; 1538 mii = device_get_softc(sc->rl_miibus); 1539 mii_mediachg(mii); 1540 1541 return(0); 1542} 1543 1544/* 1545 * Report current media status. 1546 */ 1547static void rl_ifmedia_sts(ifp, ifmr) 1548 struct ifnet *ifp; 1549 struct ifmediareq *ifmr; 1550{ 1551 struct rl_softc *sc; 1552 struct mii_data *mii; 1553 1554 sc = ifp->if_softc; 1555 mii = device_get_softc(sc->rl_miibus); 1556 1557 mii_pollstat(mii); 1558 ifmr->ifm_active = mii->mii_media_active; 1559 ifmr->ifm_status = mii->mii_media_status; 1560 1561 return; 1562} 1563 1564static int rl_ioctl(ifp, command, data) 1565 struct ifnet *ifp; 1566 u_long command; 1567 caddr_t data; 1568{ 1569 struct rl_softc *sc = ifp->if_softc; 1570 struct ifreq *ifr = (struct ifreq *) data; 1571 struct mii_data *mii; 1572 int s, error = 0; 1573 1574 s = splimp(); 1575 1576 switch(command) { 1577 case SIOCSIFADDR: 1578 case SIOCGIFADDR: 1579 case SIOCSIFMTU: 1580 error = ether_ioctl(ifp, command, data); 1581 break; 1582 case SIOCSIFFLAGS: 1583 if (ifp->if_flags & IFF_UP) { 1584 rl_init(sc); 1585 } else { 1586 if (ifp->if_flags & IFF_RUNNING) 1587 rl_stop(sc); 1588 } 1589 error = 0; 1590 break; 1591 case SIOCADDMULTI: 1592 case SIOCDELMULTI: 1593 rl_setmulti(sc); 1594 error = 0; 1595 break; 1596 case SIOCGIFMEDIA: 1597 case SIOCSIFMEDIA: 1598 mii = device_get_softc(sc->rl_miibus); 1599 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1600 break; 1601 default: 1602 error = EINVAL; 1603 break; 1604 } 1605 1606 (void)splx(s); 1607 1608 return(error); 1609} 1610 1611static void rl_watchdog(ifp) 1612 struct ifnet *ifp; 1613{ 1614 struct rl_softc *sc; 1615 1616 sc = ifp->if_softc; 1617 1618 printf("rl%d: watchdog timeout\n", sc->rl_unit); 1619 ifp->if_oerrors++; 1620 1621 rl_txeof(sc); 1622 rl_rxeof(sc); 1623 rl_init(sc); 1624 1625 return; 1626} 1627 1628/* 1629 * Stop the adapter and free any mbufs allocated to the 1630 * RX and TX lists. 1631 */ 1632static void rl_stop(sc) 1633 struct rl_softc *sc; 1634{ 1635 register int i; 1636 struct ifnet *ifp; 1637 1638 ifp = &sc->arpcom.ac_if; 1639 ifp->if_timer = 0; 1640 1641 untimeout(rl_tick, sc, sc->rl_stat_ch); 1642 1643 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1644 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1645 1646 /* 1647 * Free the TX list buffers. 1648 */ 1649 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1650 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1651 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1652 sc->rl_cdata.rl_tx_chain[i] = NULL; 1653 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 1654 } 1655 } 1656 1657 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1658 1659 return; 1660} 1661 1662/* 1663 * Stop all chip I/O so that the kernel's probe routines don't 1664 * get confused by errant DMAs when rebooting. 1665 */ 1666static void rl_shutdown(dev) 1667 device_t dev; 1668{ 1669 struct rl_softc *sc; 1670 1671 sc = device_get_softc(dev); 1672 1673 rl_stop(sc); 1674 1675 return; 1676} 1677