if_rl.c revision 108729
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_rl.c 108729 2003-01-05 21:36:59Z jake $ 33 */ 34 35/* 36 * RealTek 8129/8139 PCI NIC driver 37 * 38 * Supports several extremely cheap PCI 10/100 adapters based on 39 * the RealTek chipset. Datasheets can be obtained from 40 * www.realtek.com.tw. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 49 * probably the worst PCI ethernet controller ever made, with the possible 50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 51 * DMA, but it has a terrible interface that nullifies any performance 52 * gains that bus-master DMA usually offers. 53 * 54 * For transmission, the chip offers a series of four TX descriptor 55 * registers. Each transmit frame must be in a contiguous buffer, aligned 56 * on a longword (32-bit) boundary. This means we almost always have to 57 * do mbuf copies in order to transmit a frame, except in the unlikely 58 * case where a) the packet fits into a single mbuf, and b) the packet 59 * is 32-bit aligned within the mbuf's data area. The presence of only 60 * four descriptor registers means that we can never have more than four 61 * packets queued for transmission at any one time. 62 * 63 * Reception is not much better. The driver has to allocate a single large 64 * buffer area (up to 64K in size) into which the chip will DMA received 65 * frames. Because we don't know where within this region received packets 66 * will begin or end, we have no choice but to copy data from the buffer 67 * area into mbufs in order to pass the packets up to the higher protocol 68 * levels. 69 * 70 * It's impossible given this rotten design to really achieve decent 71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 72 * some equally overmuscled CPU to drive it. 73 * 74 * On the bright side, the 8139 does have a built-in PHY, although 75 * rather than using an MDIO serial interface like most other NICs, the 76 * PHY registers are directly accessible through the 8139's register 77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 78 * filter. 79 * 80 * The 8129 chip is an older version of the 8139 that uses an external PHY 81 * chip. The 8129 has a serial MDIO interface for accessing the MII where 82 * the 8139 lets you directly access the on-board PHY registers. We need 83 * to select which interface to use depending on the chip type. 84 */ 85 86#include <sys/param.h> 87#include <sys/endian.h> 88#include <sys/systm.h> 89#include <sys/sockio.h> 90#include <sys/mbuf.h> 91#include <sys/malloc.h> 92#include <sys/kernel.h> 93#include <sys/socket.h> 94 95#include <net/if.h> 96#include <net/if_arp.h> 97#include <net/ethernet.h> 98#include <net/if_dl.h> 99#include <net/if_media.h> 100 101#include <net/bpf.h> 102 103#include <machine/bus_pio.h> 104#include <machine/bus_memio.h> 105#include <machine/bus.h> 106#include <machine/resource.h> 107#include <sys/bus.h> 108#include <sys/rman.h> 109 110#include <dev/mii/mii.h> 111#include <dev/mii/miivar.h> 112 113#include <pci/pcireg.h> 114#include <pci/pcivar.h> 115 116MODULE_DEPEND(rl, miibus, 1, 1, 1); 117 118/* "controller miibus0" required. See GENERIC if you get errors here. */ 119#include "miibus_if.h" 120 121/* 122 * Default to using PIO access for this driver. On SMP systems, 123 * there appear to be problems with memory mapped mode: it looks like 124 * doing too many memory mapped access back to back in rapid succession 125 * can hang the bus. I'm inclined to blame this on crummy design/construction 126 * on the part of RealTek. Memory mapped mode does appear to work on 127 * uniprocessor systems though. 128 */ 129#define RL_USEIOSPACE 130 131#include <pci/if_rlreg.h> 132 133#ifndef lint 134static const char rcsid[] = 135 "$FreeBSD: head/sys/pci/if_rl.c 108729 2003-01-05 21:36:59Z jake $"; 136#endif 137 138/* 139 * Various supported device vendors/types and their names. 140 */ 141static struct rl_type rl_devs[] = { 142 { RT_VENDORID, RT_DEVICEID_8129, 143 "RealTek 8129 10/100BaseTX" }, 144 { RT_VENDORID, RT_DEVICEID_8139, 145 "RealTek 8139 10/100BaseTX" }, 146 { RT_VENDORID, RT_DEVICEID_8138, 147 "RealTek 8139 10/100BaseTX CardBus" }, 148 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 149 "Accton MPX 5030/5038 10/100BaseTX" }, 150 { DELTA_VENDORID, DELTA_DEVICEID_8139, 151 "Delta Electronics 8139 10/100BaseTX" }, 152 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 153 "Addtron Technolgy 8139 10/100BaseTX" }, 154 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, 155 "D-Link DFE-530TX+ 10/100BaseTX" }, 156 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, 157 "D-Link DFE-690TXD 10/100BaseTX" }, 158 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, 159 "Nortel Networks 10/100BaseTX" }, 160 { COREGA_VENDORID, COREGA_DEVICEID_CBTXD, 161 "Corega FEther CB-TXD" }, 162 { 0, 0, NULL } 163}; 164 165static int rl_probe (device_t); 166static int rl_attach (device_t); 167static int rl_detach (device_t); 168 169static int rl_encap (struct rl_softc *, struct mbuf * ); 170 171static void rl_rxeof (struct rl_softc *); 172static void rl_txeof (struct rl_softc *); 173static void rl_intr (void *); 174static void rl_tick (void *); 175static void rl_start (struct ifnet *); 176static int rl_ioctl (struct ifnet *, u_long, caddr_t); 177static void rl_init (void *); 178static void rl_stop (struct rl_softc *); 179static void rl_watchdog (struct ifnet *); 180static int rl_suspend (device_t); 181static int rl_resume (device_t); 182static void rl_shutdown (device_t); 183static int rl_ifmedia_upd (struct ifnet *); 184static void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 185 186static void rl_eeprom_putbyte (struct rl_softc *, int); 187static void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *); 188static void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 189static void rl_mii_sync (struct rl_softc *); 190static void rl_mii_send (struct rl_softc *, u_int32_t, int); 191static int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *); 192static int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *); 193 194static int rl_miibus_readreg (device_t, int, int); 195static int rl_miibus_writereg (device_t, int, int, int); 196static void rl_miibus_statchg (device_t); 197 198static u_int8_t rl_calchash (caddr_t); 199static void rl_setmulti (struct rl_softc *); 200static void rl_reset (struct rl_softc *); 201static int rl_list_tx_init (struct rl_softc *); 202 203static void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int); 204static void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int); 205 206#ifdef RL_USEIOSPACE 207#define RL_RES SYS_RES_IOPORT 208#define RL_RID RL_PCI_LOIO 209#else 210#define RL_RES SYS_RES_MEMORY 211#define RL_RID RL_PCI_LOMEM 212#endif 213 214static device_method_t rl_methods[] = { 215 /* Device interface */ 216 DEVMETHOD(device_probe, rl_probe), 217 DEVMETHOD(device_attach, rl_attach), 218 DEVMETHOD(device_detach, rl_detach), 219 DEVMETHOD(device_suspend, rl_suspend), 220 DEVMETHOD(device_resume, rl_resume), 221 DEVMETHOD(device_shutdown, rl_shutdown), 222 223 /* bus interface */ 224 DEVMETHOD(bus_print_child, bus_generic_print_child), 225 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 226 227 /* MII interface */ 228 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 229 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 230 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 231 232 { 0, 0 } 233}; 234 235static driver_t rl_driver = { 236 "rl", 237 rl_methods, 238 sizeof(struct rl_softc) 239}; 240 241static devclass_t rl_devclass; 242 243DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 244DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0); 245DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 246 247#define EE_SET(x) \ 248 CSR_WRITE_1(sc, RL_EECMD, \ 249 CSR_READ_1(sc, RL_EECMD) | x) 250 251#define EE_CLR(x) \ 252 CSR_WRITE_1(sc, RL_EECMD, \ 253 CSR_READ_1(sc, RL_EECMD) & ~x) 254 255static void 256rl_dma_map_rxbuf(arg, segs, nseg, error) 257 void *arg; 258 bus_dma_segment_t *segs; 259 int nseg, error; 260{ 261 struct rl_softc *sc; 262 263 sc = arg; 264 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 265 266 return; 267} 268 269static void 270rl_dma_map_txbuf(arg, segs, nseg, error) 271 void *arg; 272 bus_dma_segment_t *segs; 273 int nseg, error; 274{ 275 struct rl_softc *sc; 276 277 sc = arg; 278 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 279 280 return; 281} 282 283/* 284 * Send a read command and address to the EEPROM, check for ACK. 285 */ 286static void 287rl_eeprom_putbyte(sc, addr) 288 struct rl_softc *sc; 289 int addr; 290{ 291 register int d, i; 292 293 d = addr | sc->rl_eecmd_read; 294 295 /* 296 * Feed in each bit and strobe the clock. 297 */ 298 for (i = 0x400; i; i >>= 1) { 299 if (d & i) { 300 EE_SET(RL_EE_DATAIN); 301 } else { 302 EE_CLR(RL_EE_DATAIN); 303 } 304 DELAY(100); 305 EE_SET(RL_EE_CLK); 306 DELAY(150); 307 EE_CLR(RL_EE_CLK); 308 DELAY(100); 309 } 310 311 return; 312} 313 314/* 315 * Read a word of data stored in the EEPROM at address 'addr.' 316 */ 317static void 318rl_eeprom_getword(sc, addr, dest) 319 struct rl_softc *sc; 320 int addr; 321 u_int16_t *dest; 322{ 323 register int i; 324 u_int16_t word = 0; 325 326 /* Enter EEPROM access mode. */ 327 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 328 329 /* 330 * Send address of word we want to read. 331 */ 332 rl_eeprom_putbyte(sc, addr); 333 334 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 335 336 /* 337 * Start reading bits from EEPROM. 338 */ 339 for (i = 0x8000; i; i >>= 1) { 340 EE_SET(RL_EE_CLK); 341 DELAY(100); 342 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 343 word |= i; 344 EE_CLR(RL_EE_CLK); 345 DELAY(100); 346 } 347 348 /* Turn off EEPROM access mode. */ 349 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 350 351 *dest = word; 352 353 return; 354} 355 356/* 357 * Read a sequence of words from the EEPROM. 358 */ 359static void 360rl_read_eeprom(sc, dest, off, cnt, swap) 361 struct rl_softc *sc; 362 caddr_t dest; 363 int off; 364 int cnt; 365 int swap; 366{ 367 int i; 368 u_int16_t word = 0, *ptr; 369 370 for (i = 0; i < cnt; i++) { 371 rl_eeprom_getword(sc, off + i, &word); 372 ptr = (u_int16_t *)(dest + (i * 2)); 373 if (swap) 374 *ptr = ntohs(word); 375 else 376 *ptr = word; 377 } 378 379 return; 380} 381 382 383/* 384 * MII access routines are provided for the 8129, which 385 * doesn't have a built-in PHY. For the 8139, we fake things 386 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 387 * direct access PHY registers. 388 */ 389#define MII_SET(x) \ 390 CSR_WRITE_1(sc, RL_MII, \ 391 CSR_READ_1(sc, RL_MII) | (x)) 392 393#define MII_CLR(x) \ 394 CSR_WRITE_1(sc, RL_MII, \ 395 CSR_READ_1(sc, RL_MII) & ~(x)) 396 397/* 398 * Sync the PHYs by setting data bit and strobing the clock 32 times. 399 */ 400static void 401rl_mii_sync(sc) 402 struct rl_softc *sc; 403{ 404 register int i; 405 406 MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 407 408 for (i = 0; i < 32; i++) { 409 MII_SET(RL_MII_CLK); 410 DELAY(1); 411 MII_CLR(RL_MII_CLK); 412 DELAY(1); 413 } 414 415 return; 416} 417 418/* 419 * Clock a series of bits through the MII. 420 */ 421static void 422rl_mii_send(sc, bits, cnt) 423 struct rl_softc *sc; 424 u_int32_t bits; 425 int cnt; 426{ 427 int i; 428 429 MII_CLR(RL_MII_CLK); 430 431 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 432 if (bits & i) { 433 MII_SET(RL_MII_DATAOUT); 434 } else { 435 MII_CLR(RL_MII_DATAOUT); 436 } 437 DELAY(1); 438 MII_CLR(RL_MII_CLK); 439 DELAY(1); 440 MII_SET(RL_MII_CLK); 441 } 442} 443 444/* 445 * Read an PHY register through the MII. 446 */ 447static int 448rl_mii_readreg(sc, frame) 449 struct rl_softc *sc; 450 struct rl_mii_frame *frame; 451 452{ 453 int i, ack; 454 455 RL_LOCK(sc); 456 457 /* 458 * Set up frame for RX. 459 */ 460 frame->mii_stdelim = RL_MII_STARTDELIM; 461 frame->mii_opcode = RL_MII_READOP; 462 frame->mii_turnaround = 0; 463 frame->mii_data = 0; 464 465 CSR_WRITE_2(sc, RL_MII, 0); 466 467 /* 468 * Turn on data xmit. 469 */ 470 MII_SET(RL_MII_DIR); 471 472 rl_mii_sync(sc); 473 474 /* 475 * Send command/address info. 476 */ 477 rl_mii_send(sc, frame->mii_stdelim, 2); 478 rl_mii_send(sc, frame->mii_opcode, 2); 479 rl_mii_send(sc, frame->mii_phyaddr, 5); 480 rl_mii_send(sc, frame->mii_regaddr, 5); 481 482 /* Idle bit */ 483 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 484 DELAY(1); 485 MII_SET(RL_MII_CLK); 486 DELAY(1); 487 488 /* Turn off xmit. */ 489 MII_CLR(RL_MII_DIR); 490 491 /* Check for ack */ 492 MII_CLR(RL_MII_CLK); 493 DELAY(1); 494 MII_SET(RL_MII_CLK); 495 DELAY(1); 496 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 497 498 /* 499 * Now try reading data bits. If the ack failed, we still 500 * need to clock through 16 cycles to keep the PHY(s) in sync. 501 */ 502 if (ack) { 503 for(i = 0; i < 16; i++) { 504 MII_CLR(RL_MII_CLK); 505 DELAY(1); 506 MII_SET(RL_MII_CLK); 507 DELAY(1); 508 } 509 goto fail; 510 } 511 512 for (i = 0x8000; i; i >>= 1) { 513 MII_CLR(RL_MII_CLK); 514 DELAY(1); 515 if (!ack) { 516 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 517 frame->mii_data |= i; 518 DELAY(1); 519 } 520 MII_SET(RL_MII_CLK); 521 DELAY(1); 522 } 523 524fail: 525 526 MII_CLR(RL_MII_CLK); 527 DELAY(1); 528 MII_SET(RL_MII_CLK); 529 DELAY(1); 530 531 RL_UNLOCK(sc); 532 533 if (ack) 534 return(1); 535 return(0); 536} 537 538/* 539 * Write to a PHY register through the MII. 540 */ 541static int 542rl_mii_writereg(sc, frame) 543 struct rl_softc *sc; 544 struct rl_mii_frame *frame; 545 546{ 547 RL_LOCK(sc); 548 549 /* 550 * Set up frame for TX. 551 */ 552 553 frame->mii_stdelim = RL_MII_STARTDELIM; 554 frame->mii_opcode = RL_MII_WRITEOP; 555 frame->mii_turnaround = RL_MII_TURNAROUND; 556 557 /* 558 * Turn on data output. 559 */ 560 MII_SET(RL_MII_DIR); 561 562 rl_mii_sync(sc); 563 564 rl_mii_send(sc, frame->mii_stdelim, 2); 565 rl_mii_send(sc, frame->mii_opcode, 2); 566 rl_mii_send(sc, frame->mii_phyaddr, 5); 567 rl_mii_send(sc, frame->mii_regaddr, 5); 568 rl_mii_send(sc, frame->mii_turnaround, 2); 569 rl_mii_send(sc, frame->mii_data, 16); 570 571 /* Idle bit. */ 572 MII_SET(RL_MII_CLK); 573 DELAY(1); 574 MII_CLR(RL_MII_CLK); 575 DELAY(1); 576 577 /* 578 * Turn off xmit. 579 */ 580 MII_CLR(RL_MII_DIR); 581 582 RL_UNLOCK(sc); 583 584 return(0); 585} 586 587static int 588rl_miibus_readreg(dev, phy, reg) 589 device_t dev; 590 int phy, reg; 591{ 592 struct rl_softc *sc; 593 struct rl_mii_frame frame; 594 u_int16_t rval = 0; 595 u_int16_t rl8139_reg = 0; 596 597 sc = device_get_softc(dev); 598 RL_LOCK(sc); 599 600 if (sc->rl_type == RL_8139) { 601 /* Pretend the internal PHY is only at address 0 */ 602 if (phy) { 603 RL_UNLOCK(sc); 604 return(0); 605 } 606 switch(reg) { 607 case MII_BMCR: 608 rl8139_reg = RL_BMCR; 609 break; 610 case MII_BMSR: 611 rl8139_reg = RL_BMSR; 612 break; 613 case MII_ANAR: 614 rl8139_reg = RL_ANAR; 615 break; 616 case MII_ANER: 617 rl8139_reg = RL_ANER; 618 break; 619 case MII_ANLPAR: 620 rl8139_reg = RL_LPAR; 621 break; 622 case MII_PHYIDR1: 623 case MII_PHYIDR2: 624 RL_UNLOCK(sc); 625 return(0); 626 break; 627 /* 628 * Allow the rlphy driver to read the media status 629 * register. If we have a link partner which does not 630 * support NWAY, this is the register which will tell 631 * us the results of parallel detection. 632 */ 633 case RL_MEDIASTAT: 634 rval = CSR_READ_1(sc, RL_MEDIASTAT); 635 RL_UNLOCK(sc); 636 return(rval); 637 break; 638 default: 639 printf("rl%d: bad phy register\n", sc->rl_unit); 640 RL_UNLOCK(sc); 641 return(0); 642 } 643 rval = CSR_READ_2(sc, rl8139_reg); 644 RL_UNLOCK(sc); 645 return(rval); 646 } 647 648 bzero((char *)&frame, sizeof(frame)); 649 650 frame.mii_phyaddr = phy; 651 frame.mii_regaddr = reg; 652 rl_mii_readreg(sc, &frame); 653 RL_UNLOCK(sc); 654 655 return(frame.mii_data); 656} 657 658static int 659rl_miibus_writereg(dev, phy, reg, data) 660 device_t dev; 661 int phy, reg, data; 662{ 663 struct rl_softc *sc; 664 struct rl_mii_frame frame; 665 u_int16_t rl8139_reg = 0; 666 667 sc = device_get_softc(dev); 668 RL_LOCK(sc); 669 670 if (sc->rl_type == RL_8139) { 671 /* Pretend the internal PHY is only at address 0 */ 672 if (phy) { 673 RL_UNLOCK(sc); 674 return(0); 675 } 676 switch(reg) { 677 case MII_BMCR: 678 rl8139_reg = RL_BMCR; 679 break; 680 case MII_BMSR: 681 rl8139_reg = RL_BMSR; 682 break; 683 case MII_ANAR: 684 rl8139_reg = RL_ANAR; 685 break; 686 case MII_ANER: 687 rl8139_reg = RL_ANER; 688 break; 689 case MII_ANLPAR: 690 rl8139_reg = RL_LPAR; 691 break; 692 case MII_PHYIDR1: 693 case MII_PHYIDR2: 694 RL_UNLOCK(sc); 695 return(0); 696 break; 697 default: 698 printf("rl%d: bad phy register\n", sc->rl_unit); 699 RL_UNLOCK(sc); 700 return(0); 701 } 702 CSR_WRITE_2(sc, rl8139_reg, data); 703 RL_UNLOCK(sc); 704 return(0); 705 } 706 707 bzero((char *)&frame, sizeof(frame)); 708 709 frame.mii_phyaddr = phy; 710 frame.mii_regaddr = reg; 711 frame.mii_data = data; 712 713 rl_mii_writereg(sc, &frame); 714 715 RL_UNLOCK(sc); 716 return(0); 717} 718 719static void 720rl_miibus_statchg(dev) 721 device_t dev; 722{ 723 return; 724} 725 726/* 727 * Calculate CRC of a multicast group address, return the upper 6 bits. 728 */ 729static u_int8_t 730rl_calchash(addr) 731 caddr_t addr; 732{ 733 u_int32_t crc, carry; 734 int i, j; 735 u_int8_t c; 736 737 /* Compute CRC for the address value. */ 738 crc = 0xFFFFFFFF; /* initial value */ 739 740 for (i = 0; i < 6; i++) { 741 c = *(addr + i); 742 for (j = 0; j < 8; j++) { 743 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 744 crc <<= 1; 745 c >>= 1; 746 if (carry) 747 crc = (crc ^ 0x04c11db6) | carry; 748 } 749 } 750 751 /* return the filter bit position */ 752 return(crc >> 26); 753} 754 755/* 756 * Program the 64-bit multicast hash filter. 757 */ 758static void 759rl_setmulti(sc) 760 struct rl_softc *sc; 761{ 762 struct ifnet *ifp; 763 int h = 0; 764 u_int32_t hashes[2] = { 0, 0 }; 765 struct ifmultiaddr *ifma; 766 u_int32_t rxfilt; 767 int mcnt = 0; 768 769 ifp = &sc->arpcom.ac_if; 770 771 rxfilt = CSR_READ_4(sc, RL_RXCFG); 772 773 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 774 rxfilt |= RL_RXCFG_RX_MULTI; 775 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 776 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 777 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 778 return; 779 } 780 781 /* first, zot all the existing hash bits */ 782 CSR_WRITE_4(sc, RL_MAR0, 0); 783 CSR_WRITE_4(sc, RL_MAR4, 0); 784 785 /* now program new ones */ 786 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 787 if (ifma->ifma_addr->sa_family != AF_LINK) 788 continue; 789 h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 790 if (h < 32) 791 hashes[0] |= (1 << h); 792 else 793 hashes[1] |= (1 << (h - 32)); 794 mcnt++; 795 } 796 797 if (mcnt) 798 rxfilt |= RL_RXCFG_RX_MULTI; 799 else 800 rxfilt &= ~RL_RXCFG_RX_MULTI; 801 802 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 803 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 804 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 805 806 return; 807} 808 809static void 810rl_reset(sc) 811 struct rl_softc *sc; 812{ 813 register int i; 814 815 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 816 817 for (i = 0; i < RL_TIMEOUT; i++) { 818 DELAY(10); 819 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 820 break; 821 } 822 if (i == RL_TIMEOUT) 823 printf("rl%d: reset never completed!\n", sc->rl_unit); 824 825 return; 826} 827 828/* 829 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 830 * IDs against our list and return a device name if we find a match. 831 */ 832static int 833rl_probe(dev) 834 device_t dev; 835{ 836 struct rl_type *t; 837 838 t = rl_devs; 839 840 while(t->rl_name != NULL) { 841 if ((pci_get_vendor(dev) == t->rl_vid) && 842 (pci_get_device(dev) == t->rl_did)) { 843 device_set_desc(dev, t->rl_name); 844 return(0); 845 } 846 t++; 847 } 848 849 return(ENXIO); 850} 851 852/* 853 * Attach the interface. Allocate softc structures, do ifmedia 854 * setup and ethernet/BPF attach. 855 */ 856static int 857rl_attach(dev) 858 device_t dev; 859{ 860 u_char eaddr[ETHER_ADDR_LEN]; 861 u_int32_t command; 862 u_int16_t as[3]; 863 struct rl_softc *sc; 864 struct ifnet *ifp; 865 u_int16_t rl_did = 0; 866 int unit, error = 0, rid, i; 867 868 sc = device_get_softc(dev); 869 unit = device_get_unit(dev); 870 bzero(sc, sizeof(struct rl_softc)); 871 872 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 873 MTX_DEF | MTX_RECURSE); 874 875 /* 876 * Handle power management nonsense. 877 */ 878 879 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 880 u_int32_t iobase, membase, irq; 881 882 /* Save important PCI config data. */ 883 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 884 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 885 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 886 887 /* Reset the power state. */ 888 printf("rl%d: chip is is in D%d power mode " 889 "-- setting to D0\n", unit, 890 pci_get_powerstate(dev)); 891 892 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 893 894 /* Restore PCI config data. */ 895 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 896 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 897 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 898 } 899 900 /* 901 * Map control/status registers. 902 */ 903 pci_enable_busmaster(dev); 904 pci_enable_io(dev, SYS_RES_IOPORT); 905 pci_enable_io(dev, SYS_RES_MEMORY); 906 command = pci_read_config(dev, PCIR_COMMAND, 4); 907 908#ifdef RL_USEIOSPACE 909 if (!(command & PCIM_CMD_PORTEN)) { 910 printf("rl%d: failed to enable I/O ports!\n", unit); 911 error = ENXIO; 912 goto fail; 913 } 914#else 915 if (!(command & PCIM_CMD_MEMEN)) { 916 printf("rl%d: failed to enable memory mapping!\n", unit); 917 error = ENXIO; 918 goto fail; 919 } 920#endif 921 922 rid = RL_RID; 923 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 924 0, ~0, 1, RF_ACTIVE); 925 926 if (sc->rl_res == NULL) { 927 printf ("rl%d: couldn't map ports/memory\n", unit); 928 error = ENXIO; 929 goto fail; 930 } 931 932 /* Detect the Realtek 8139B. For some reason, this chip is very 933 * unstable when left to autoselect the media 934 * The best workaround is to set the device to the required 935 * media type or to set it to the 10 Meg speed. 936 */ 937 938 if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { 939 printf("rl%d: Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n", unit); 940 } 941 942 sc->rl_btag = rman_get_bustag(sc->rl_res); 943 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 944 945 rid = 0; 946 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 947 RF_SHAREABLE | RF_ACTIVE); 948 949 if (sc->rl_irq == NULL) { 950 printf("rl%d: couldn't map interrupt\n", unit); 951 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 952 error = ENXIO; 953 goto fail; 954 } 955 956 /* Reset the adapter. */ 957 rl_reset(sc); 958 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 959 rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 960 if (rl_did != 0x8129) 961 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 962 963 /* 964 * Get station address from the EEPROM. 965 */ 966 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 967 for (i = 0; i < 3; i++) { 968 eaddr[(i * 2) + 0] = as[i] & 0xff; 969 eaddr[(i * 2) + 1] = as[i] >> 8; 970 } 971 972 /* 973 * A RealTek chip was detected. Inform the world. 974 */ 975 printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 976 977 sc->rl_unit = unit; 978 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 979 980 /* 981 * Now read the exact device type from the EEPROM to find 982 * out if it's an 8129 or 8139. 983 */ 984 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 985 986 if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 987 rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 988 rl_did == RT_DEVICEID_8138 || rl_did == DLINK_DEVICEID_530TXPLUS || 989 rl_did == DLINK_DEVICEID_690TXD || rl_did == COREGA_DEVICEID_CBTXD) 990 sc->rl_type = RL_8139; 991 else if (rl_did == RT_DEVICEID_8129) 992 sc->rl_type = RL_8129; 993 else { 994 printf("rl%d: unknown device ID: %x\n", unit, rl_did); 995 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 996 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 997 error = ENXIO; 998 goto fail; 999 } 1000 1001 /* 1002 * Allocate the parent bus DMA tag appropriate for PCI. 1003 */ 1004#define RL_NSEG_NEW 32 1005 error = bus_dma_tag_create(NULL, /* parent */ 1006 1, 0, /* alignment, boundary */ 1007 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1008 BUS_SPACE_MAXADDR, /* highaddr */ 1009 NULL, NULL, /* filter, filterarg */ 1010 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1011 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1012 BUS_DMA_ALLOCNOW, /* flags */ 1013 &sc->rl_parent_tag); 1014 1015 /* 1016 * Now allocate a tag for the DMA descriptor lists. 1017 * All of our lists are allocated as a contiguous block 1018 * of memory. 1019 */ 1020 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 1021 1, 0, /* alignment, boundary */ 1022 BUS_SPACE_MAXADDR, /* lowaddr */ 1023 BUS_SPACE_MAXADDR, /* highaddr */ 1024 NULL, NULL, /* filter, filterarg */ 1025 RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 1026 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1027 0, /* flags */ 1028 &sc->rl_tag); 1029 1030 /* 1031 * Now allocate a chunk of DMA-able memory based on the 1032 * tag we just created. 1033 */ 1034 error = bus_dmamem_alloc(sc->rl_tag, 1035 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT, 1036 &sc->rl_cdata.rl_rx_dmamap); 1037 1038 if (sc->rl_cdata.rl_rx_buf == NULL) { 1039 printf("rl%d: no memory for list buffers!\n", unit); 1040 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1041 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1042 bus_dma_tag_destroy(sc->rl_tag); 1043 error = ENXIO; 1044 goto fail; 1045 } 1046 1047 /* Leave a few bytes before the start of the RX ring buffer. */ 1048 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 1049 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 1050 1051 /* Do MII setup */ 1052 if (mii_phy_probe(dev, &sc->rl_miibus, 1053 rl_ifmedia_upd, rl_ifmedia_sts)) { 1054 printf("rl%d: MII without any phy!\n", sc->rl_unit); 1055 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1056 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1057 bus_dmamem_free(sc->rl_tag, 1058 sc->rl_cdata.rl_rx_buf, sc->rl_cdata.rl_rx_dmamap); 1059 bus_dma_tag_destroy(sc->rl_tag); 1060 error = ENXIO; 1061 goto fail; 1062 } 1063 1064 ifp = &sc->arpcom.ac_if; 1065 ifp->if_softc = sc; 1066 ifp->if_unit = unit; 1067 ifp->if_name = "rl"; 1068 ifp->if_mtu = ETHERMTU; 1069 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1070 ifp->if_ioctl = rl_ioctl; 1071 ifp->if_output = ether_output; 1072 ifp->if_start = rl_start; 1073 ifp->if_watchdog = rl_watchdog; 1074 ifp->if_init = rl_init; 1075 ifp->if_baudrate = 10000000; 1076 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1077 1078 /* 1079 * Call MI attach routine. 1080 */ 1081 ether_ifattach(ifp, eaddr); 1082 1083 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 1084 rl_intr, sc, &sc->rl_intrhand); 1085 1086 if (error) { 1087 printf("rl%d: couldn't set up irq\n", unit); 1088 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1089 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1090 bus_dmamem_free(sc->rl_tag, 1091 sc->rl_cdata.rl_rx_buf, sc->rl_cdata.rl_rx_dmamap); 1092 bus_dma_tag_destroy(sc->rl_tag); 1093 goto fail; 1094 } 1095 1096 callout_handle_init(&sc->rl_stat_ch); 1097 return(0); 1098fail: 1099 mtx_destroy(&sc->rl_mtx); 1100 return(error); 1101} 1102 1103static int 1104rl_detach(dev) 1105 device_t dev; 1106{ 1107 struct rl_softc *sc; 1108 struct ifnet *ifp; 1109 1110 sc = device_get_softc(dev); 1111 RL_LOCK(sc); 1112 ifp = &sc->arpcom.ac_if; 1113 1114 ether_ifdetach(ifp); 1115 rl_stop(sc); 1116 1117 bus_generic_detach(dev); 1118 device_delete_child(dev, sc->rl_miibus); 1119 1120 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1121 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1122 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1123 1124 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1125 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 1126 sc->rl_cdata.rl_rx_dmamap); 1127 bus_dma_tag_destroy(sc->rl_tag); 1128 bus_dma_tag_destroy(sc->rl_parent_tag); 1129 1130 RL_UNLOCK(sc); 1131 mtx_destroy(&sc->rl_mtx); 1132 1133 return(0); 1134} 1135 1136/* 1137 * Initialize the transmit descriptors. 1138 */ 1139static int 1140rl_list_tx_init(sc) 1141 struct rl_softc *sc; 1142{ 1143 struct rl_chain_data *cd; 1144 int i; 1145 1146 cd = &sc->rl_cdata; 1147 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1148 cd->rl_tx_chain[i] = NULL; 1149 CSR_WRITE_4(sc, 1150 RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 1151 } 1152 1153 sc->rl_cdata.cur_tx = 0; 1154 sc->rl_cdata.last_tx = 0; 1155 1156 return(0); 1157} 1158 1159/* 1160 * A frame has been uploaded: pass the resulting mbuf chain up to 1161 * the higher level protocols. 1162 * 1163 * You know there's something wrong with a PCI bus-master chip design 1164 * when you have to use m_devget(). 1165 * 1166 * The receive operation is badly documented in the datasheet, so I'll 1167 * attempt to document it here. The driver provides a buffer area and 1168 * places its base address in the RX buffer start address register. 1169 * The chip then begins copying frames into the RX buffer. Each frame 1170 * is preceded by a 32-bit RX status word which specifies the length 1171 * of the frame and certain other status bits. Each frame (starting with 1172 * the status word) is also 32-bit aligned. The frame length is in the 1173 * first 16 bits of the status word; the lower 15 bits correspond with 1174 * the 'rx status register' mentioned in the datasheet. 1175 * 1176 * Note: to make the Alpha happy, the frame payload needs to be aligned 1177 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1178 * as the offset argument to m_devget(). 1179 */ 1180static void 1181rl_rxeof(sc) 1182 struct rl_softc *sc; 1183{ 1184 struct mbuf *m; 1185 struct ifnet *ifp; 1186 int total_len = 0; 1187 u_int32_t rxstat; 1188 caddr_t rxbufpos; 1189 int wrap = 0; 1190 u_int16_t cur_rx; 1191 u_int16_t limit; 1192 u_int16_t rx_bytes = 0, max_bytes; 1193 1194 ifp = &sc->arpcom.ac_if; 1195 1196 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1197 BUS_DMASYNC_POSTREAD); 1198 1199 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1200 1201 /* Do not try to read past this point. */ 1202 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1203 1204 if (limit < cur_rx) 1205 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1206 else 1207 max_bytes = limit - cur_rx; 1208 1209 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1210#ifdef DEVICE_POLLING 1211 if (ifp->if_flags & IFF_POLLING) { 1212 if (sc->rxcycles <= 0) 1213 break; 1214 sc->rxcycles--; 1215 } 1216#endif /* DEVICE_POLLING */ 1217 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1218 rxstat = le32toh(*(u_int32_t *)rxbufpos); 1219 1220 /* 1221 * Here's a totally undocumented fact for you. When the 1222 * RealTek chip is in the process of copying a packet into 1223 * RAM for you, the length will be 0xfff0. If you spot a 1224 * packet header with this value, you need to stop. The 1225 * datasheet makes absolutely no mention of this and 1226 * RealTek should be shot for this. 1227 */ 1228 if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 1229 break; 1230 1231 if (!(rxstat & RL_RXSTAT_RXOK)) { 1232 ifp->if_ierrors++; 1233 rl_init(sc); 1234 return; 1235 } 1236 1237 /* No errors; receive the packet. */ 1238 total_len = rxstat >> 16; 1239 rx_bytes += total_len + 4; 1240 1241 /* 1242 * XXX The RealTek chip includes the CRC with every 1243 * received frame, and there's no way to turn this 1244 * behavior off (at least, I can't find anything in 1245 * the manual that explains how to do it) so we have 1246 * to trim off the CRC manually. 1247 */ 1248 total_len -= ETHER_CRC_LEN; 1249 1250 /* 1251 * Avoid trying to read more bytes than we know 1252 * the chip has prepared for us. 1253 */ 1254 if (rx_bytes > max_bytes) 1255 break; 1256 1257 rxbufpos = sc->rl_cdata.rl_rx_buf + 1258 ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 1259 1260 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1261 rxbufpos = sc->rl_cdata.rl_rx_buf; 1262 1263 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1264 1265 if (total_len > wrap) { 1266 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1267 NULL); 1268 if (m == NULL) { 1269 ifp->if_ierrors++; 1270 } else { 1271 m_copyback(m, wrap, total_len - wrap, 1272 sc->rl_cdata.rl_rx_buf); 1273 } 1274 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1275 } else { 1276 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1277 NULL); 1278 if (m == NULL) { 1279 ifp->if_ierrors++; 1280 } 1281 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1282 } 1283 1284 /* 1285 * Round up to 32-bit boundary. 1286 */ 1287 cur_rx = (cur_rx + 3) & ~3; 1288 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1289 1290 if (m == NULL) 1291 continue; 1292 1293 ifp->if_ipackets++; 1294 (*ifp->if_input)(ifp, m); 1295 } 1296 1297 return; 1298} 1299 1300/* 1301 * A frame was downloaded to the chip. It's safe for us to clean up 1302 * the list buffers. 1303 */ 1304static void 1305rl_txeof(sc) 1306 struct rl_softc *sc; 1307{ 1308 struct ifnet *ifp; 1309 u_int32_t txstat; 1310 1311 ifp = &sc->arpcom.ac_if; 1312 1313 /* 1314 * Go through our tx list and free mbufs for those 1315 * frames that have been uploaded. 1316 */ 1317 do { 1318 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1319 if (!(txstat & (RL_TXSTAT_TX_OK| 1320 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1321 break; 1322 1323 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 1324 1325 if (RL_LAST_TXMBUF(sc) != NULL) { 1326 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1327 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 1328 m_freem(RL_LAST_TXMBUF(sc)); 1329 RL_LAST_TXMBUF(sc) = NULL; 1330 } 1331 if (txstat & RL_TXSTAT_TX_OK) 1332 ifp->if_opackets++; 1333 else { 1334 int oldthresh; 1335 ifp->if_oerrors++; 1336 if ((txstat & RL_TXSTAT_TXABRT) || 1337 (txstat & RL_TXSTAT_OUTOFWIN)) 1338 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1339 oldthresh = sc->rl_txthresh; 1340 /* error recovery */ 1341 rl_reset(sc); 1342 rl_init(sc); 1343 /* 1344 * If there was a transmit underrun, 1345 * bump the TX threshold. 1346 */ 1347 if (txstat & RL_TXSTAT_TX_UNDERRUN) 1348 sc->rl_txthresh = oldthresh + 32; 1349 return; 1350 } 1351 RL_INC(sc->rl_cdata.last_tx); 1352 ifp->if_flags &= ~IFF_OACTIVE; 1353 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1354 1355 ifp->if_timer = 1356 (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) ? 0 : 5; 1357 1358 return; 1359} 1360 1361static void 1362rl_tick(xsc) 1363 void *xsc; 1364{ 1365 struct rl_softc *sc; 1366 struct mii_data *mii; 1367 1368 sc = xsc; 1369 RL_LOCK(sc); 1370 mii = device_get_softc(sc->rl_miibus); 1371 1372 mii_tick(mii); 1373 1374 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1375 RL_UNLOCK(sc); 1376 1377 return; 1378} 1379 1380#ifdef DEVICE_POLLING 1381static void 1382rl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1383{ 1384 struct rl_softc *sc = ifp->if_softc; 1385 1386 RL_LOCK(sc); 1387 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1388 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1389 goto done; 1390 } 1391 1392 sc->rxcycles = count; 1393 rl_rxeof(sc); 1394 rl_txeof(sc); 1395 if (ifp->if_snd.ifq_head != NULL) 1396 rl_start(ifp); 1397 1398 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1399 u_int16_t status; 1400 1401 status = CSR_READ_2(sc, RL_ISR); 1402 if (status == 0xffff) 1403 goto done; 1404 if (status) 1405 CSR_WRITE_2(sc, RL_ISR, status); 1406 1407 /* 1408 * XXX check behaviour on receiver stalls. 1409 */ 1410 1411 if (status & RL_ISR_SYSTEM_ERR) { 1412 rl_reset(sc); 1413 rl_init(sc); 1414 } 1415 } 1416done: 1417 RL_UNLOCK(sc); 1418} 1419#endif /* DEVICE_POLLING */ 1420 1421static void 1422rl_intr(arg) 1423 void *arg; 1424{ 1425 struct rl_softc *sc; 1426 struct ifnet *ifp; 1427 u_int16_t status; 1428 1429 sc = arg; 1430 1431 if (sc->suspended) { 1432 return; 1433 } 1434 1435 RL_LOCK(sc); 1436 ifp = &sc->arpcom.ac_if; 1437 1438#ifdef DEVICE_POLLING 1439 if (ifp->if_flags & IFF_POLLING) 1440 goto done; 1441 if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */ 1442 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1443 rl_poll(ifp, 0, 1); 1444 goto done; 1445 } 1446#endif /* DEVICE_POLLING */ 1447 1448 for (;;) { 1449 1450 status = CSR_READ_2(sc, RL_ISR); 1451 /* If the card has gone away the read returns 0xffff. */ 1452 if (status == 0xffff) 1453 break; 1454 if (status) 1455 CSR_WRITE_2(sc, RL_ISR, status); 1456 1457 if ((status & RL_INTRS) == 0) 1458 break; 1459 1460 if (status & RL_ISR_RX_OK) 1461 rl_rxeof(sc); 1462 1463 if (status & RL_ISR_RX_ERR) 1464 rl_rxeof(sc); 1465 1466 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 1467 rl_txeof(sc); 1468 1469 if (status & RL_ISR_SYSTEM_ERR) { 1470 rl_reset(sc); 1471 rl_init(sc); 1472 } 1473 1474 } 1475 1476 if (ifp->if_snd.ifq_head != NULL) 1477 rl_start(ifp); 1478 1479#ifdef DEVICE_POLLING 1480done: 1481#endif 1482 RL_UNLOCK(sc); 1483 1484 return; 1485} 1486 1487/* 1488 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1489 * pointers to the fragment pointers. 1490 */ 1491static int 1492rl_encap(sc, m_head) 1493 struct rl_softc *sc; 1494 struct mbuf *m_head; 1495{ 1496 struct mbuf *m_new = NULL; 1497 1498 /* 1499 * The RealTek is brain damaged and wants longword-aligned 1500 * TX buffers, plus we can only have one fragment buffer 1501 * per packet. We have to copy pretty much all the time. 1502 */ 1503 1504 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1505 if (m_new == NULL) 1506 return(1); 1507 if (m_head->m_pkthdr.len > MHLEN) { 1508 MCLGET(m_new, M_DONTWAIT); 1509 if (!(m_new->m_flags & M_EXT)) { 1510 m_freem(m_new); 1511 return(1); 1512 } 1513 } 1514 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1515 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1516 m_freem(m_head); 1517 m_head = m_new; 1518 1519 /* Pad frames to at least 60 bytes. */ 1520 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 1521 /* 1522 * Make security concious people happy: zero out the 1523 * bytes in the pad area, since we don't know what 1524 * this mbuf cluster buffer's previous user might 1525 * have left in it. 1526 */ 1527 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 1528 RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1529 m_head->m_pkthdr.len += 1530 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 1531 m_head->m_len = m_head->m_pkthdr.len; 1532 } 1533 1534 RL_CUR_TXMBUF(sc) = m_head; 1535 1536 return(0); 1537} 1538 1539/* 1540 * Main transmit routine. 1541 */ 1542 1543static void 1544rl_start(ifp) 1545 struct ifnet *ifp; 1546{ 1547 struct rl_softc *sc; 1548 struct mbuf *m_head = NULL; 1549 1550 sc = ifp->if_softc; 1551 RL_LOCK(sc); 1552 1553 while(RL_CUR_TXMBUF(sc) == NULL) { 1554 IF_DEQUEUE(&ifp->if_snd, m_head); 1555 if (m_head == NULL) 1556 break; 1557 1558 if (rl_encap(sc, m_head)) { 1559 IF_PREPEND(&ifp->if_snd, m_head); 1560 ifp->if_flags |= IFF_OACTIVE; 1561 break; 1562 } 1563 1564 /* 1565 * If there's a BPF listener, bounce a copy of this frame 1566 * to him. 1567 */ 1568 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 1569 1570 /* 1571 * Transmit the frame. 1572 */ 1573 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 1574 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 1575 mtod(RL_CUR_TXMBUF(sc), void *), 1576 RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 1577 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 1578 BUS_DMASYNC_PREREAD); 1579 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1580 RL_TXTHRESH(sc->rl_txthresh) | 1581 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1582 1583 RL_INC(sc->rl_cdata.cur_tx); 1584 } 1585 1586 /* 1587 * We broke out of the loop because all our TX slots are 1588 * full. Mark the NIC as busy until it drains some of the 1589 * packets from the queue. 1590 */ 1591 if (RL_CUR_TXMBUF(sc) != NULL) 1592 ifp->if_flags |= IFF_OACTIVE; 1593 1594 /* 1595 * Set a timeout in case the chip goes out to lunch. 1596 */ 1597 ifp->if_timer = 5; 1598 RL_UNLOCK(sc); 1599 1600 return; 1601} 1602 1603static void 1604rl_init(xsc) 1605 void *xsc; 1606{ 1607 struct rl_softc *sc = xsc; 1608 struct ifnet *ifp = &sc->arpcom.ac_if; 1609 struct mii_data *mii; 1610 int i; 1611 u_int32_t rxcfg = 0; 1612 1613 RL_LOCK(sc); 1614 mii = device_get_softc(sc->rl_miibus); 1615 1616 /* 1617 * Cancel pending I/O and free all RX/TX buffers. 1618 */ 1619 rl_stop(sc); 1620 1621 /* Init our MAC address */ 1622 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1623 CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 1624 } 1625 1626 /* Init the RX buffer pointer register. */ 1627 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1628 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 1629 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 1630 BUS_DMASYNC_PREWRITE); 1631 1632 /* Init TX descriptors. */ 1633 rl_list_tx_init(sc); 1634 1635 /* 1636 * Enable transmit and receive. 1637 */ 1638 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1639 1640 /* 1641 * Set the initial TX and RX configuration. 1642 */ 1643 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1644 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1645 1646 /* Set the individual bit to receive frames for this host only. */ 1647 rxcfg = CSR_READ_4(sc, RL_RXCFG); 1648 rxcfg |= RL_RXCFG_RX_INDIV; 1649 1650 /* If we want promiscuous mode, set the allframes bit. */ 1651 if (ifp->if_flags & IFF_PROMISC) { 1652 rxcfg |= RL_RXCFG_RX_ALLPHYS; 1653 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1654 } else { 1655 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 1656 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1657 } 1658 1659 /* 1660 * Set capture broadcast bit to capture broadcast frames. 1661 */ 1662 if (ifp->if_flags & IFF_BROADCAST) { 1663 rxcfg |= RL_RXCFG_RX_BROAD; 1664 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1665 } else { 1666 rxcfg &= ~RL_RXCFG_RX_BROAD; 1667 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 1668 } 1669 1670 /* 1671 * Program the multicast filter, if necessary. 1672 */ 1673 rl_setmulti(sc); 1674 1675#ifdef DEVICE_POLLING 1676 /* 1677 * Disable interrupts if we are polling. 1678 */ 1679 if (ifp->if_flags & IFF_POLLING) 1680 CSR_WRITE_2(sc, RL_IMR, 0); 1681 else /* otherwise ... */ 1682#endif /* DEVICE_POLLING */ 1683 /* 1684 * Enable interrupts. 1685 */ 1686 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1687 1688 /* Set initial TX threshold */ 1689 sc->rl_txthresh = RL_TX_THRESH_INIT; 1690 1691 /* Start RX/TX process. */ 1692 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1693 1694 /* Enable receiver and transmitter. */ 1695 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1696 1697 mii_mediachg(mii); 1698 1699 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1700 1701 ifp->if_flags |= IFF_RUNNING; 1702 ifp->if_flags &= ~IFF_OACTIVE; 1703 1704 sc->rl_stat_ch = timeout(rl_tick, sc, hz); 1705 RL_UNLOCK(sc); 1706 1707 return; 1708} 1709 1710/* 1711 * Set media options. 1712 */ 1713static int 1714rl_ifmedia_upd(ifp) 1715 struct ifnet *ifp; 1716{ 1717 struct rl_softc *sc; 1718 struct mii_data *mii; 1719 1720 sc = ifp->if_softc; 1721 mii = device_get_softc(sc->rl_miibus); 1722 mii_mediachg(mii); 1723 1724 return(0); 1725} 1726 1727/* 1728 * Report current media status. 1729 */ 1730static void 1731rl_ifmedia_sts(ifp, ifmr) 1732 struct ifnet *ifp; 1733 struct ifmediareq *ifmr; 1734{ 1735 struct rl_softc *sc; 1736 struct mii_data *mii; 1737 1738 sc = ifp->if_softc; 1739 mii = device_get_softc(sc->rl_miibus); 1740 1741 mii_pollstat(mii); 1742 ifmr->ifm_active = mii->mii_media_active; 1743 ifmr->ifm_status = mii->mii_media_status; 1744 1745 return; 1746} 1747 1748static int 1749rl_ioctl(ifp, command, data) 1750 struct ifnet *ifp; 1751 u_long command; 1752 caddr_t data; 1753{ 1754 struct rl_softc *sc = ifp->if_softc; 1755 struct ifreq *ifr = (struct ifreq *) data; 1756 struct mii_data *mii; 1757 int error = 0; 1758 1759 RL_LOCK(sc); 1760 1761 switch(command) { 1762 case SIOCSIFFLAGS: 1763 if (ifp->if_flags & IFF_UP) { 1764 rl_init(sc); 1765 } else { 1766 if (ifp->if_flags & IFF_RUNNING) 1767 rl_stop(sc); 1768 } 1769 error = 0; 1770 break; 1771 case SIOCADDMULTI: 1772 case SIOCDELMULTI: 1773 rl_setmulti(sc); 1774 error = 0; 1775 break; 1776 case SIOCGIFMEDIA: 1777 case SIOCSIFMEDIA: 1778 mii = device_get_softc(sc->rl_miibus); 1779 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1780 break; 1781 default: 1782 error = ether_ioctl(ifp, command, data); 1783 break; 1784 } 1785 1786 RL_UNLOCK(sc); 1787 1788 return(error); 1789} 1790 1791static void 1792rl_watchdog(ifp) 1793 struct ifnet *ifp; 1794{ 1795 struct rl_softc *sc; 1796 1797 sc = ifp->if_softc; 1798 RL_LOCK(sc); 1799 printf("rl%d: watchdog timeout\n", sc->rl_unit); 1800 ifp->if_oerrors++; 1801 1802 rl_txeof(sc); 1803 rl_rxeof(sc); 1804 rl_init(sc); 1805 RL_UNLOCK(sc); 1806 1807 return; 1808} 1809 1810/* 1811 * Stop the adapter and free any mbufs allocated to the 1812 * RX and TX lists. 1813 */ 1814static void 1815rl_stop(sc) 1816 struct rl_softc *sc; 1817{ 1818 register int i; 1819 struct ifnet *ifp; 1820 1821 RL_LOCK(sc); 1822 ifp = &sc->arpcom.ac_if; 1823 ifp->if_timer = 0; 1824 1825 untimeout(rl_tick, sc, sc->rl_stat_ch); 1826 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1827#ifdef DEVICE_POLLING 1828 ether_poll_deregister(ifp); 1829#endif /* DEVICE_POLLING */ 1830 1831 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1832 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1833 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 1834 1835 /* 1836 * Free the TX list buffers. 1837 */ 1838 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1839 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1840 bus_dmamap_unload(sc->rl_tag, 1841 sc->rl_cdata.rl_tx_dmamap[i]); 1842 bus_dmamap_destroy(sc->rl_tag, 1843 sc->rl_cdata.rl_tx_dmamap[i]); 1844 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1845 sc->rl_cdata.rl_tx_chain[i] = NULL; 1846 CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 1847 } 1848 } 1849 1850 RL_UNLOCK(sc); 1851 return; 1852} 1853 1854/* 1855 * Device suspend routine. Stop the interface and save some PCI 1856 * settings in case the BIOS doesn't restore them properly on 1857 * resume. 1858 */ 1859static int 1860rl_suspend(dev) 1861 device_t dev; 1862{ 1863 register int i; 1864 struct rl_softc *sc; 1865 1866 sc = device_get_softc(dev); 1867 1868 rl_stop(sc); 1869 1870 for (i = 0; i < 5; i++) 1871 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 1872 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 1873 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 1874 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 1875 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 1876 1877 sc->suspended = 1; 1878 1879 return (0); 1880} 1881 1882/* 1883 * Device resume routine. Restore some PCI settings in case the BIOS 1884 * doesn't, re-enable busmastering, and restart the interface if 1885 * appropriate. 1886 */ 1887static int 1888rl_resume(dev) 1889 device_t dev; 1890{ 1891 register int i; 1892 struct rl_softc *sc; 1893 struct ifnet *ifp; 1894 1895 sc = device_get_softc(dev); 1896 ifp = &sc->arpcom.ac_if; 1897 1898 /* better way to do this? */ 1899 for (i = 0; i < 5; i++) 1900 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 1901 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 1902 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 1903 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 1904 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 1905 1906 /* reenable busmastering */ 1907 pci_enable_busmaster(dev); 1908 pci_enable_io(dev, RL_RES); 1909 1910 /* reinitialize interface if necessary */ 1911 if (ifp->if_flags & IFF_UP) 1912 rl_init(sc); 1913 1914 sc->suspended = 0; 1915 1916 return (0); 1917} 1918 1919/* 1920 * Stop all chip I/O so that the kernel's probe routines don't 1921 * get confused by errant DMAs when rebooting. 1922 */ 1923static void 1924rl_shutdown(dev) 1925 device_t dev; 1926{ 1927 struct rl_softc *sc; 1928 1929 sc = device_get_softc(dev); 1930 1931 rl_stop(sc); 1932 1933 return; 1934} 1935