if_rl.c revision 106936
140516Swpaul/* 240516Swpaul * Copyright (c) 1997, 1998 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_rl.c 106936 2002-11-14 23:49:09Z sam $ 3340516Swpaul */ 3440516Swpaul 3540516Swpaul/* 3640516Swpaul * RealTek 8129/8139 PCI NIC driver 3740516Swpaul * 3840516Swpaul * Supports several extremely cheap PCI 10/100 adapters based on 3940516Swpaul * the RealTek chipset. Datasheets can be obtained from 4040516Swpaul * www.realtek.com.tw. 4140516Swpaul * 4240516Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4340516Swpaul * Electrical Engineering Department 4440516Swpaul * Columbia University, New York City 4540516Swpaul */ 4640516Swpaul 4740516Swpaul/* 4840516Swpaul * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 4940516Swpaul * probably the worst PCI ethernet controller ever made, with the possible 5040516Swpaul * exception of the FEAST chip made by SMC. The 8139 supports bus-master 5140516Swpaul * DMA, but it has a terrible interface that nullifies any performance 5240516Swpaul * gains that bus-master DMA usually offers. 5340516Swpaul * 5440516Swpaul * For transmission, the chip offers a series of four TX descriptor 5540516Swpaul * registers. Each transmit frame must be in a contiguous buffer, aligned 5641569Swpaul * on a longword (32-bit) boundary. This means we almost always have to 5740516Swpaul * do mbuf copies in order to transmit a frame, except in the unlikely 5840516Swpaul * case where a) the packet fits into a single mbuf, and b) the packet 5940516Swpaul * is 32-bit aligned within the mbuf's data area. The presence of only 6040516Swpaul * four descriptor registers means that we can never have more than four 6140516Swpaul * packets queued for transmission at any one time. 6240516Swpaul * 6340516Swpaul * Reception is not much better. The driver has to allocate a single large 6440516Swpaul * buffer area (up to 64K in size) into which the chip will DMA received 6540516Swpaul * frames. Because we don't know where within this region received packets 6640516Swpaul * will begin or end, we have no choice but to copy data from the buffer 6740516Swpaul * area into mbufs in order to pass the packets up to the higher protocol 6840516Swpaul * levels. 6940516Swpaul * 7040516Swpaul * It's impossible given this rotten design to really achieve decent 7140516Swpaul * performance at 100Mbps, unless you happen to have a 400Mhz PII or 7240516Swpaul * some equally overmuscled CPU to drive it. 7340516Swpaul * 7440516Swpaul * On the bright side, the 8139 does have a built-in PHY, although 7540516Swpaul * rather than using an MDIO serial interface like most other NICs, the 7640516Swpaul * PHY registers are directly accessible through the 8139's register 7740516Swpaul * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 7840516Swpaul * filter. 7940516Swpaul * 8040516Swpaul * The 8129 chip is an older version of the 8139 that uses an external PHY 8140516Swpaul * chip. The 8129 has a serial MDIO interface for accessing the MII where 8240516Swpaul * the 8139 lets you directly access the on-board PHY registers. We need 8340516Swpaul * to select which interface to use depending on the chip type. 8440516Swpaul */ 8540516Swpaul 8640516Swpaul#include <sys/param.h> 8740516Swpaul#include <sys/systm.h> 8840516Swpaul#include <sys/sockio.h> 8940516Swpaul#include <sys/mbuf.h> 9040516Swpaul#include <sys/malloc.h> 9140516Swpaul#include <sys/kernel.h> 9240516Swpaul#include <sys/socket.h> 9340516Swpaul 9440516Swpaul#include <net/if.h> 9540516Swpaul#include <net/if_arp.h> 9640516Swpaul#include <net/ethernet.h> 9740516Swpaul#include <net/if_dl.h> 9840516Swpaul#include <net/if_media.h> 9940516Swpaul 10040516Swpaul#include <net/bpf.h> 10140516Swpaul 10241569Swpaul#include <machine/bus_pio.h> 10341569Swpaul#include <machine/bus_memio.h> 10441569Swpaul#include <machine/bus.h> 10550703Swpaul#include <machine/resource.h> 10650703Swpaul#include <sys/bus.h> 10750703Swpaul#include <sys/rman.h> 10840516Swpaul 10950703Swpaul#include <dev/mii/mii.h> 11050703Swpaul#include <dev/mii/miivar.h> 11150703Swpaul 11240516Swpaul#include <pci/pcireg.h> 11340516Swpaul#include <pci/pcivar.h> 11440516Swpaul 11559758SpeterMODULE_DEPEND(rl, miibus, 1, 1, 1); 11659758Speter 11751089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 11850703Swpaul#include "miibus_if.h" 11950703Swpaul 12040516Swpaul/* 12140516Swpaul * Default to using PIO access for this driver. On SMP systems, 12240516Swpaul * there appear to be problems with memory mapped mode: it looks like 12340516Swpaul * doing too many memory mapped access back to back in rapid succession 12440516Swpaul * can hang the bus. I'm inclined to blame this on crummy design/construction 12540516Swpaul * on the part of RealTek. Memory mapped mode does appear to work on 12640516Swpaul * uniprocessor systems though. 12740516Swpaul */ 12840516Swpaul#define RL_USEIOSPACE 12940516Swpaul 13040516Swpaul#include <pci/if_rlreg.h> 13140516Swpaul 13240516Swpaul#ifndef lint 13341591Sarchiestatic const char rcsid[] = 13450477Speter "$FreeBSD: head/sys/pci/if_rl.c 106936 2002-11-14 23:49:09Z sam $"; 13540516Swpaul#endif 13640516Swpaul 13740516Swpaul/* 13840516Swpaul * Various supported device vendors/types and their names. 13940516Swpaul */ 14040516Swpaulstatic struct rl_type rl_devs[] = { 14140516Swpaul { RT_VENDORID, RT_DEVICEID_8129, 14240516Swpaul "RealTek 8129 10/100BaseTX" }, 14340516Swpaul { RT_VENDORID, RT_DEVICEID_8139, 14440516Swpaul "RealTek 8139 10/100BaseTX" }, 14567771Swpaul { RT_VENDORID, RT_DEVICEID_8138, 14667771Swpaul "RealTek 8139 10/100BaseTX CardBus" }, 14741243Swpaul { ACCTON_VENDORID, ACCTON_DEVICEID_5030, 14841243Swpaul "Accton MPX 5030/5038 10/100BaseTX" }, 14944238Swpaul { DELTA_VENDORID, DELTA_DEVICEID_8139, 15044238Swpaul "Delta Electronics 8139 10/100BaseTX" }, 15144238Swpaul { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, 15244238Swpaul "Addtron Technolgy 8139 10/100BaseTX" }, 15372813Swpaul { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, 15472813Swpaul "D-Link DFE-530TX+ 10/100BaseTX" }, 15596112Sjhb { DLINK_VENDORID, DLINK_DEVICEID_690TXD, 15696112Sjhb "D-Link DFE-690TXD 10/100BaseTX" }, 15794400Swpaul { NORTEL_VENDORID, ACCTON_DEVICEID_5030, 15894400Swpaul "Nortel Networks 10/100BaseTX" }, 159103020Siwasaki { COREGA_VENDORID, COREGA_DEVICEID_CBTXD, 160103020Siwasaki "Corega FEther CB-TXD" }, 16140516Swpaul { 0, 0, NULL } 16240516Swpaul}; 16340516Swpaul 16492739Salfredstatic int rl_probe (device_t); 16592739Salfredstatic int rl_attach (device_t); 16692739Salfredstatic int rl_detach (device_t); 16740516Swpaul 16892739Salfredstatic int rl_encap (struct rl_softc *, struct mbuf * ); 16940516Swpaul 17092739Salfredstatic void rl_rxeof (struct rl_softc *); 17192739Salfredstatic void rl_txeof (struct rl_softc *); 17292739Salfredstatic void rl_intr (void *); 17392739Salfredstatic void rl_tick (void *); 17492739Salfredstatic void rl_start (struct ifnet *); 17592739Salfredstatic int rl_ioctl (struct ifnet *, u_long, caddr_t); 17692739Salfredstatic void rl_init (void *); 17792739Salfredstatic void rl_stop (struct rl_softc *); 17892739Salfredstatic void rl_watchdog (struct ifnet *); 17992739Salfredstatic int rl_suspend (device_t); 18092739Salfredstatic int rl_resume (device_t); 18192739Salfredstatic void rl_shutdown (device_t); 18292739Salfredstatic int rl_ifmedia_upd (struct ifnet *); 18392739Salfredstatic void rl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 18440516Swpaul 18592739Salfredstatic void rl_eeprom_putbyte (struct rl_softc *, int); 18692739Salfredstatic void rl_eeprom_getword (struct rl_softc *, int, u_int16_t *); 18792739Salfredstatic void rl_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 18892739Salfredstatic void rl_mii_sync (struct rl_softc *); 18992739Salfredstatic void rl_mii_send (struct rl_softc *, u_int32_t, int); 19092739Salfredstatic int rl_mii_readreg (struct rl_softc *, struct rl_mii_frame *); 19192739Salfredstatic int rl_mii_writereg (struct rl_softc *, struct rl_mii_frame *); 19240516Swpaul 19392739Salfredstatic int rl_miibus_readreg (device_t, int, int); 19492739Salfredstatic int rl_miibus_writereg (device_t, int, int, int); 19592739Salfredstatic void rl_miibus_statchg (device_t); 19640516Swpaul 19792739Salfredstatic u_int8_t rl_calchash (caddr_t); 19892739Salfredstatic void rl_setmulti (struct rl_softc *); 19992739Salfredstatic void rl_reset (struct rl_softc *); 20092739Salfredstatic int rl_list_tx_init (struct rl_softc *); 20140516Swpaul 20292739Salfredstatic void rl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, int); 20392739Salfredstatic void rl_dma_map_txbuf (void *, bus_dma_segment_t *, int, int); 20481713Swpaul 20550703Swpaul#ifdef RL_USEIOSPACE 20650703Swpaul#define RL_RES SYS_RES_IOPORT 20750703Swpaul#define RL_RID RL_PCI_LOIO 20850703Swpaul#else 20950703Swpaul#define RL_RES SYS_RES_MEMORY 21050703Swpaul#define RL_RID RL_PCI_LOMEM 21150703Swpaul#endif 21250703Swpaul 21350703Swpaulstatic device_method_t rl_methods[] = { 21450703Swpaul /* Device interface */ 21550703Swpaul DEVMETHOD(device_probe, rl_probe), 21650703Swpaul DEVMETHOD(device_attach, rl_attach), 21750703Swpaul DEVMETHOD(device_detach, rl_detach), 21886822Siwasaki DEVMETHOD(device_suspend, rl_suspend), 21986822Siwasaki DEVMETHOD(device_resume, rl_resume), 22050703Swpaul DEVMETHOD(device_shutdown, rl_shutdown), 22150703Swpaul 22250703Swpaul /* bus interface */ 22350703Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 22450703Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 22550703Swpaul 22650703Swpaul /* MII interface */ 22750703Swpaul DEVMETHOD(miibus_readreg, rl_miibus_readreg), 22850703Swpaul DEVMETHOD(miibus_writereg, rl_miibus_writereg), 22950703Swpaul DEVMETHOD(miibus_statchg, rl_miibus_statchg), 23050703Swpaul 23150703Swpaul { 0, 0 } 23250703Swpaul}; 23350703Swpaul 23450703Swpaulstatic driver_t rl_driver = { 23551455Swpaul "rl", 23650703Swpaul rl_methods, 23750703Swpaul sizeof(struct rl_softc) 23850703Swpaul}; 23950703Swpaul 24050703Swpaulstatic devclass_t rl_devclass; 24150703Swpaul 24251533SwpaulDRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0); 24367931SwpaulDRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0); 24451473SwpaulDRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0); 24550703Swpaul 24640516Swpaul#define EE_SET(x) \ 24740516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 24840516Swpaul CSR_READ_1(sc, RL_EECMD) | x) 24940516Swpaul 25040516Swpaul#define EE_CLR(x) \ 25140516Swpaul CSR_WRITE_1(sc, RL_EECMD, \ 25240516Swpaul CSR_READ_1(sc, RL_EECMD) & ~x) 25340516Swpaul 25481713Swpaulstatic void 25581713Swpaulrl_dma_map_rxbuf(arg, segs, nseg, error) 25681713Swpaul void *arg; 25781713Swpaul bus_dma_segment_t *segs; 25881713Swpaul int nseg, error; 25981713Swpaul{ 26081713Swpaul struct rl_softc *sc; 26181713Swpaul 26281713Swpaul sc = arg; 26381713Swpaul CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF); 26481713Swpaul 26581713Swpaul return; 26681713Swpaul} 26781713Swpaul 26881713Swpaulstatic void 26981713Swpaulrl_dma_map_txbuf(arg, segs, nseg, error) 27081713Swpaul void *arg; 27181713Swpaul bus_dma_segment_t *segs; 27281713Swpaul int nseg, error; 27381713Swpaul{ 27481713Swpaul struct rl_softc *sc; 27581713Swpaul 27681713Swpaul sc = arg; 27781713Swpaul CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF); 27881713Swpaul 27981713Swpaul return; 28081713Swpaul} 28181713Swpaul 28240516Swpaul/* 28340516Swpaul * Send a read command and address to the EEPROM, check for ACK. 28440516Swpaul */ 285102335Salfredstatic void 286102335Salfredrl_eeprom_putbyte(sc, addr) 28740516Swpaul struct rl_softc *sc; 28841656Swpaul int addr; 28940516Swpaul{ 29040516Swpaul register int d, i; 29140516Swpaul 29267931Swpaul d = addr | sc->rl_eecmd_read; 29340516Swpaul 29440516Swpaul /* 29555170Sbillf * Feed in each bit and strobe the clock. 29640516Swpaul */ 29740516Swpaul for (i = 0x400; i; i >>= 1) { 29840516Swpaul if (d & i) { 29940516Swpaul EE_SET(RL_EE_DATAIN); 30040516Swpaul } else { 30140516Swpaul EE_CLR(RL_EE_DATAIN); 30240516Swpaul } 30340516Swpaul DELAY(100); 30440516Swpaul EE_SET(RL_EE_CLK); 30540516Swpaul DELAY(150); 30640516Swpaul EE_CLR(RL_EE_CLK); 30740516Swpaul DELAY(100); 30840516Swpaul } 30940516Swpaul 31040516Swpaul return; 31140516Swpaul} 31240516Swpaul 31340516Swpaul/* 31440516Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 31540516Swpaul */ 316102335Salfredstatic void 317102335Salfredrl_eeprom_getword(sc, addr, dest) 31840516Swpaul struct rl_softc *sc; 31941656Swpaul int addr; 32040516Swpaul u_int16_t *dest; 32140516Swpaul{ 32240516Swpaul register int i; 32340516Swpaul u_int16_t word = 0; 32440516Swpaul 32540516Swpaul /* Enter EEPROM access mode. */ 32640516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 32740516Swpaul 32840516Swpaul /* 32940516Swpaul * Send address of word we want to read. 33040516Swpaul */ 33140516Swpaul rl_eeprom_putbyte(sc, addr); 33240516Swpaul 33340516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 33440516Swpaul 33540516Swpaul /* 33640516Swpaul * Start reading bits from EEPROM. 33740516Swpaul */ 33840516Swpaul for (i = 0x8000; i; i >>= 1) { 33940516Swpaul EE_SET(RL_EE_CLK); 34040516Swpaul DELAY(100); 34140516Swpaul if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 34240516Swpaul word |= i; 34340516Swpaul EE_CLR(RL_EE_CLK); 34440516Swpaul DELAY(100); 34540516Swpaul } 34640516Swpaul 34740516Swpaul /* Turn off EEPROM access mode. */ 34840516Swpaul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 34940516Swpaul 35040516Swpaul *dest = word; 35140516Swpaul 35240516Swpaul return; 35340516Swpaul} 35440516Swpaul 35540516Swpaul/* 35640516Swpaul * Read a sequence of words from the EEPROM. 35740516Swpaul */ 358102335Salfredstatic void 359102335Salfredrl_read_eeprom(sc, dest, off, cnt, swap) 36040516Swpaul struct rl_softc *sc; 36140516Swpaul caddr_t dest; 36240516Swpaul int off; 36340516Swpaul int cnt; 36440516Swpaul int swap; 36540516Swpaul{ 36640516Swpaul int i; 36740516Swpaul u_int16_t word = 0, *ptr; 36840516Swpaul 36940516Swpaul for (i = 0; i < cnt; i++) { 37040516Swpaul rl_eeprom_getword(sc, off + i, &word); 37140516Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 37240516Swpaul if (swap) 37340516Swpaul *ptr = ntohs(word); 37440516Swpaul else 37540516Swpaul *ptr = word; 37640516Swpaul } 37740516Swpaul 37840516Swpaul return; 37940516Swpaul} 38040516Swpaul 38140516Swpaul 38240516Swpaul/* 38340516Swpaul * MII access routines are provided for the 8129, which 38440516Swpaul * doesn't have a built-in PHY. For the 8139, we fake things 38540516Swpaul * up by diverting rl_phy_readreg()/rl_phy_writereg() to the 38640516Swpaul * direct access PHY registers. 38740516Swpaul */ 38840516Swpaul#define MII_SET(x) \ 38940516Swpaul CSR_WRITE_1(sc, RL_MII, \ 390105221Sphk CSR_READ_1(sc, RL_MII) | (x)) 39140516Swpaul 39240516Swpaul#define MII_CLR(x) \ 39340516Swpaul CSR_WRITE_1(sc, RL_MII, \ 394105221Sphk CSR_READ_1(sc, RL_MII) & ~(x)) 39540516Swpaul 39640516Swpaul/* 39740516Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 39840516Swpaul */ 399102335Salfredstatic void 400102335Salfredrl_mii_sync(sc) 40140516Swpaul struct rl_softc *sc; 40240516Swpaul{ 40340516Swpaul register int i; 40440516Swpaul 40540516Swpaul MII_SET(RL_MII_DIR|RL_MII_DATAOUT); 40640516Swpaul 40740516Swpaul for (i = 0; i < 32; i++) { 40840516Swpaul MII_SET(RL_MII_CLK); 40940516Swpaul DELAY(1); 41040516Swpaul MII_CLR(RL_MII_CLK); 41140516Swpaul DELAY(1); 41240516Swpaul } 41340516Swpaul 41440516Swpaul return; 41540516Swpaul} 41640516Swpaul 41740516Swpaul/* 41840516Swpaul * Clock a series of bits through the MII. 41940516Swpaul */ 420102335Salfredstatic void 421102335Salfredrl_mii_send(sc, bits, cnt) 42240516Swpaul struct rl_softc *sc; 42340516Swpaul u_int32_t bits; 42440516Swpaul int cnt; 42540516Swpaul{ 42640516Swpaul int i; 42740516Swpaul 42840516Swpaul MII_CLR(RL_MII_CLK); 42940516Swpaul 43040516Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 43140516Swpaul if (bits & i) { 43240516Swpaul MII_SET(RL_MII_DATAOUT); 43340516Swpaul } else { 43440516Swpaul MII_CLR(RL_MII_DATAOUT); 43540516Swpaul } 43640516Swpaul DELAY(1); 43740516Swpaul MII_CLR(RL_MII_CLK); 43840516Swpaul DELAY(1); 43940516Swpaul MII_SET(RL_MII_CLK); 44040516Swpaul } 44140516Swpaul} 44240516Swpaul 44340516Swpaul/* 44440516Swpaul * Read an PHY register through the MII. 44540516Swpaul */ 446102335Salfredstatic int 447102335Salfredrl_mii_readreg(sc, frame) 44840516Swpaul struct rl_softc *sc; 44940516Swpaul struct rl_mii_frame *frame; 45040516Swpaul 45140516Swpaul{ 45267087Swpaul int i, ack; 45340516Swpaul 45467087Swpaul RL_LOCK(sc); 45540516Swpaul 45640516Swpaul /* 45740516Swpaul * Set up frame for RX. 45840516Swpaul */ 45940516Swpaul frame->mii_stdelim = RL_MII_STARTDELIM; 46040516Swpaul frame->mii_opcode = RL_MII_READOP; 46140516Swpaul frame->mii_turnaround = 0; 46240516Swpaul frame->mii_data = 0; 46340516Swpaul 46440516Swpaul CSR_WRITE_2(sc, RL_MII, 0); 46540516Swpaul 46640516Swpaul /* 46740516Swpaul * Turn on data xmit. 46840516Swpaul */ 46940516Swpaul MII_SET(RL_MII_DIR); 47040516Swpaul 47140516Swpaul rl_mii_sync(sc); 47240516Swpaul 47340516Swpaul /* 47440516Swpaul * Send command/address info. 47540516Swpaul */ 47640516Swpaul rl_mii_send(sc, frame->mii_stdelim, 2); 47740516Swpaul rl_mii_send(sc, frame->mii_opcode, 2); 47840516Swpaul rl_mii_send(sc, frame->mii_phyaddr, 5); 47940516Swpaul rl_mii_send(sc, frame->mii_regaddr, 5); 48040516Swpaul 48140516Swpaul /* Idle bit */ 48240516Swpaul MII_CLR((RL_MII_CLK|RL_MII_DATAOUT)); 48340516Swpaul DELAY(1); 48440516Swpaul MII_SET(RL_MII_CLK); 48540516Swpaul DELAY(1); 48640516Swpaul 48740516Swpaul /* Turn off xmit. */ 48840516Swpaul MII_CLR(RL_MII_DIR); 48940516Swpaul 49040516Swpaul /* Check for ack */ 49140516Swpaul MII_CLR(RL_MII_CLK); 49240516Swpaul DELAY(1); 49340516Swpaul MII_SET(RL_MII_CLK); 49440516Swpaul DELAY(1); 49540516Swpaul ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN; 49640516Swpaul 49740516Swpaul /* 49840516Swpaul * Now try reading data bits. If the ack failed, we still 49940516Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 50040516Swpaul */ 50140516Swpaul if (ack) { 50240516Swpaul for(i = 0; i < 16; i++) { 50340516Swpaul MII_CLR(RL_MII_CLK); 50440516Swpaul DELAY(1); 50540516Swpaul MII_SET(RL_MII_CLK); 50640516Swpaul DELAY(1); 50740516Swpaul } 50840516Swpaul goto fail; 50940516Swpaul } 51040516Swpaul 51140516Swpaul for (i = 0x8000; i; i >>= 1) { 51240516Swpaul MII_CLR(RL_MII_CLK); 51340516Swpaul DELAY(1); 51440516Swpaul if (!ack) { 51540516Swpaul if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN) 51640516Swpaul frame->mii_data |= i; 51740516Swpaul DELAY(1); 51840516Swpaul } 51940516Swpaul MII_SET(RL_MII_CLK); 52040516Swpaul DELAY(1); 52140516Swpaul } 52240516Swpaul 52340516Swpaulfail: 52440516Swpaul 52540516Swpaul MII_CLR(RL_MII_CLK); 52640516Swpaul DELAY(1); 52740516Swpaul MII_SET(RL_MII_CLK); 52840516Swpaul DELAY(1); 52940516Swpaul 53067087Swpaul RL_UNLOCK(sc); 53140516Swpaul 53240516Swpaul if (ack) 53340516Swpaul return(1); 53440516Swpaul return(0); 53540516Swpaul} 53640516Swpaul 53740516Swpaul/* 53840516Swpaul * Write to a PHY register through the MII. 53940516Swpaul */ 540102335Salfredstatic int 541102335Salfredrl_mii_writereg(sc, frame) 54240516Swpaul struct rl_softc *sc; 54340516Swpaul struct rl_mii_frame *frame; 54440516Swpaul 54540516Swpaul{ 54667087Swpaul RL_LOCK(sc); 54740516Swpaul 54840516Swpaul /* 54940516Swpaul * Set up frame for TX. 55040516Swpaul */ 55140516Swpaul 55240516Swpaul frame->mii_stdelim = RL_MII_STARTDELIM; 55340516Swpaul frame->mii_opcode = RL_MII_WRITEOP; 55440516Swpaul frame->mii_turnaround = RL_MII_TURNAROUND; 55540516Swpaul 55640516Swpaul /* 55740516Swpaul * Turn on data output. 55840516Swpaul */ 55940516Swpaul MII_SET(RL_MII_DIR); 56040516Swpaul 56140516Swpaul rl_mii_sync(sc); 56240516Swpaul 56340516Swpaul rl_mii_send(sc, frame->mii_stdelim, 2); 56440516Swpaul rl_mii_send(sc, frame->mii_opcode, 2); 56540516Swpaul rl_mii_send(sc, frame->mii_phyaddr, 5); 56640516Swpaul rl_mii_send(sc, frame->mii_regaddr, 5); 56740516Swpaul rl_mii_send(sc, frame->mii_turnaround, 2); 56840516Swpaul rl_mii_send(sc, frame->mii_data, 16); 56940516Swpaul 57040516Swpaul /* Idle bit. */ 57140516Swpaul MII_SET(RL_MII_CLK); 57240516Swpaul DELAY(1); 57340516Swpaul MII_CLR(RL_MII_CLK); 57440516Swpaul DELAY(1); 57540516Swpaul 57640516Swpaul /* 57740516Swpaul * Turn off xmit. 57840516Swpaul */ 57940516Swpaul MII_CLR(RL_MII_DIR); 58040516Swpaul 58167087Swpaul RL_UNLOCK(sc); 58240516Swpaul 58340516Swpaul return(0); 58440516Swpaul} 58540516Swpaul 586102335Salfredstatic int 587102335Salfredrl_miibus_readreg(dev, phy, reg) 58850703Swpaul device_t dev; 58950703Swpaul int phy, reg; 59050703Swpaul{ 59140516Swpaul struct rl_softc *sc; 59240516Swpaul struct rl_mii_frame frame; 59340516Swpaul u_int16_t rval = 0; 59440516Swpaul u_int16_t rl8139_reg = 0; 59540516Swpaul 59650703Swpaul sc = device_get_softc(dev); 59767087Swpaul RL_LOCK(sc); 59850703Swpaul 59940516Swpaul if (sc->rl_type == RL_8139) { 60050703Swpaul /* Pretend the internal PHY is only at address 0 */ 60167087Swpaul if (phy) { 60267087Swpaul RL_UNLOCK(sc); 60350703Swpaul return(0); 60467087Swpaul } 60540516Swpaul switch(reg) { 60650703Swpaul case MII_BMCR: 60740516Swpaul rl8139_reg = RL_BMCR; 60840516Swpaul break; 60950703Swpaul case MII_BMSR: 61040516Swpaul rl8139_reg = RL_BMSR; 61140516Swpaul break; 61250703Swpaul case MII_ANAR: 61340516Swpaul rl8139_reg = RL_ANAR; 61440516Swpaul break; 61550703Swpaul case MII_ANER: 61650703Swpaul rl8139_reg = RL_ANER; 61750703Swpaul break; 61850703Swpaul case MII_ANLPAR: 61940516Swpaul rl8139_reg = RL_LPAR; 62040516Swpaul break; 62150703Swpaul case MII_PHYIDR1: 62250703Swpaul case MII_PHYIDR2: 62367087Swpaul RL_UNLOCK(sc); 62450703Swpaul return(0); 62550703Swpaul break; 62694149Swpaul /* 62794149Swpaul * Allow the rlphy driver to read the media status 62894149Swpaul * register. If we have a link partner which does not 62994149Swpaul * support NWAY, this is the register which will tell 63094149Swpaul * us the results of parallel detection. 63194149Swpaul */ 63294149Swpaul case RL_MEDIASTAT: 63394149Swpaul rval = CSR_READ_1(sc, RL_MEDIASTAT); 63494149Swpaul RL_UNLOCK(sc); 63594149Swpaul return(rval); 63694149Swpaul break; 63740516Swpaul default: 63840516Swpaul printf("rl%d: bad phy register\n", sc->rl_unit); 63967087Swpaul RL_UNLOCK(sc); 64040516Swpaul return(0); 64140516Swpaul } 64240516Swpaul rval = CSR_READ_2(sc, rl8139_reg); 64367087Swpaul RL_UNLOCK(sc); 64440516Swpaul return(rval); 64540516Swpaul } 64640516Swpaul 64740516Swpaul bzero((char *)&frame, sizeof(frame)); 64840516Swpaul 64950703Swpaul frame.mii_phyaddr = phy; 65040516Swpaul frame.mii_regaddr = reg; 65140516Swpaul rl_mii_readreg(sc, &frame); 65267087Swpaul RL_UNLOCK(sc); 65340516Swpaul 65440516Swpaul return(frame.mii_data); 65540516Swpaul} 65640516Swpaul 657102335Salfredstatic int 658102335Salfredrl_miibus_writereg(dev, phy, reg, data) 65950703Swpaul device_t dev; 66050703Swpaul int phy, reg, data; 66150703Swpaul{ 66240516Swpaul struct rl_softc *sc; 66340516Swpaul struct rl_mii_frame frame; 66440516Swpaul u_int16_t rl8139_reg = 0; 66540516Swpaul 66650703Swpaul sc = device_get_softc(dev); 66767087Swpaul RL_LOCK(sc); 66850703Swpaul 66940516Swpaul if (sc->rl_type == RL_8139) { 67050703Swpaul /* Pretend the internal PHY is only at address 0 */ 67167087Swpaul if (phy) { 67267087Swpaul RL_UNLOCK(sc); 67350703Swpaul return(0); 67467087Swpaul } 67540516Swpaul switch(reg) { 67650703Swpaul case MII_BMCR: 67740516Swpaul rl8139_reg = RL_BMCR; 67840516Swpaul break; 67950703Swpaul case MII_BMSR: 68040516Swpaul rl8139_reg = RL_BMSR; 68140516Swpaul break; 68250703Swpaul case MII_ANAR: 68340516Swpaul rl8139_reg = RL_ANAR; 68440516Swpaul break; 68550703Swpaul case MII_ANER: 68650703Swpaul rl8139_reg = RL_ANER; 68750703Swpaul break; 68850703Swpaul case MII_ANLPAR: 68940516Swpaul rl8139_reg = RL_LPAR; 69040516Swpaul break; 69150703Swpaul case MII_PHYIDR1: 69250703Swpaul case MII_PHYIDR2: 69367087Swpaul RL_UNLOCK(sc); 69450703Swpaul return(0); 69550703Swpaul break; 69640516Swpaul default: 69740516Swpaul printf("rl%d: bad phy register\n", sc->rl_unit); 69867087Swpaul RL_UNLOCK(sc); 69950703Swpaul return(0); 70040516Swpaul } 70140516Swpaul CSR_WRITE_2(sc, rl8139_reg, data); 70267087Swpaul RL_UNLOCK(sc); 70350703Swpaul return(0); 70440516Swpaul } 70540516Swpaul 70640516Swpaul bzero((char *)&frame, sizeof(frame)); 70740516Swpaul 70850703Swpaul frame.mii_phyaddr = phy; 70940516Swpaul frame.mii_regaddr = reg; 71040516Swpaul frame.mii_data = data; 71140516Swpaul 71240516Swpaul rl_mii_writereg(sc, &frame); 71340516Swpaul 71467087Swpaul RL_UNLOCK(sc); 71550703Swpaul return(0); 71650703Swpaul} 71750703Swpaul 718102335Salfredstatic void 719102335Salfredrl_miibus_statchg(dev) 72050703Swpaul device_t dev; 72150703Swpaul{ 72240516Swpaul return; 72340516Swpaul} 72440516Swpaul 72540516Swpaul/* 72643062Swpaul * Calculate CRC of a multicast group address, return the upper 6 bits. 72740516Swpaul */ 728102335Salfredstatic u_int8_t 729102335Salfredrl_calchash(addr) 73041656Swpaul caddr_t addr; 73140516Swpaul{ 73240516Swpaul u_int32_t crc, carry; 73340516Swpaul int i, j; 73440516Swpaul u_int8_t c; 73540516Swpaul 73640516Swpaul /* Compute CRC for the address value. */ 73740516Swpaul crc = 0xFFFFFFFF; /* initial value */ 73840516Swpaul 73940516Swpaul for (i = 0; i < 6; i++) { 74040516Swpaul c = *(addr + i); 74140516Swpaul for (j = 0; j < 8; j++) { 74240516Swpaul carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 74340516Swpaul crc <<= 1; 74440516Swpaul c >>= 1; 74540516Swpaul if (carry) 74640516Swpaul crc = (crc ^ 0x04c11db6) | carry; 74740516Swpaul } 74840516Swpaul } 74940516Swpaul 75040516Swpaul /* return the filter bit position */ 75143062Swpaul return(crc >> 26); 75240516Swpaul} 75340516Swpaul 75440516Swpaul/* 75540516Swpaul * Program the 64-bit multicast hash filter. 75640516Swpaul */ 757102335Salfredstatic void 758102335Salfredrl_setmulti(sc) 75940516Swpaul struct rl_softc *sc; 76040516Swpaul{ 76140516Swpaul struct ifnet *ifp; 76240516Swpaul int h = 0; 76340516Swpaul u_int32_t hashes[2] = { 0, 0 }; 76440516Swpaul struct ifmultiaddr *ifma; 76540516Swpaul u_int32_t rxfilt; 76640516Swpaul int mcnt = 0; 76740516Swpaul 76840516Swpaul ifp = &sc->arpcom.ac_if; 76940516Swpaul 77040516Swpaul rxfilt = CSR_READ_4(sc, RL_RXCFG); 77140516Swpaul 77243062Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 77340516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 77440516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 77540516Swpaul CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 77640516Swpaul CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 77740516Swpaul return; 77840516Swpaul } 77940516Swpaul 78040516Swpaul /* first, zot all the existing hash bits */ 78140516Swpaul CSR_WRITE_4(sc, RL_MAR0, 0); 78240516Swpaul CSR_WRITE_4(sc, RL_MAR4, 0); 78340516Swpaul 78440516Swpaul /* now program new ones */ 78572084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 78640516Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 78740516Swpaul continue; 78840516Swpaul h = rl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 78940516Swpaul if (h < 32) 79040516Swpaul hashes[0] |= (1 << h); 79140516Swpaul else 79240516Swpaul hashes[1] |= (1 << (h - 32)); 79340516Swpaul mcnt++; 79440516Swpaul } 79540516Swpaul 79640516Swpaul if (mcnt) 79740516Swpaul rxfilt |= RL_RXCFG_RX_MULTI; 79840516Swpaul else 79940516Swpaul rxfilt &= ~RL_RXCFG_RX_MULTI; 80040516Swpaul 80140516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 80240516Swpaul CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 80340516Swpaul CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 80440516Swpaul 80540516Swpaul return; 80640516Swpaul} 80740516Swpaul 808102335Salfredstatic void 809102335Salfredrl_reset(sc) 81040516Swpaul struct rl_softc *sc; 81140516Swpaul{ 81240516Swpaul register int i; 81340516Swpaul 81440516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 81540516Swpaul 81640516Swpaul for (i = 0; i < RL_TIMEOUT; i++) { 81740516Swpaul DELAY(10); 81840516Swpaul if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 81940516Swpaul break; 82040516Swpaul } 82140516Swpaul if (i == RL_TIMEOUT) 82240516Swpaul printf("rl%d: reset never completed!\n", sc->rl_unit); 82340516Swpaul 82440516Swpaul return; 82540516Swpaul} 82640516Swpaul 82740516Swpaul/* 82840516Swpaul * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 82940516Swpaul * IDs against our list and return a device name if we find a match. 83040516Swpaul */ 831102335Salfredstatic int 832102335Salfredrl_probe(dev) 83350703Swpaul device_t dev; 83440516Swpaul{ 83540516Swpaul struct rl_type *t; 83640516Swpaul 83740516Swpaul t = rl_devs; 83840516Swpaul 83940516Swpaul while(t->rl_name != NULL) { 84050703Swpaul if ((pci_get_vendor(dev) == t->rl_vid) && 84150703Swpaul (pci_get_device(dev) == t->rl_did)) { 84250703Swpaul device_set_desc(dev, t->rl_name); 84350703Swpaul return(0); 84440516Swpaul } 84540516Swpaul t++; 84640516Swpaul } 84740516Swpaul 84850703Swpaul return(ENXIO); 84940516Swpaul} 85040516Swpaul 85140516Swpaul/* 85240516Swpaul * Attach the interface. Allocate softc structures, do ifmedia 85340516Swpaul * setup and ethernet/BPF attach. 85440516Swpaul */ 855102335Salfredstatic int 856102335Salfredrl_attach(dev) 85750703Swpaul device_t dev; 85840516Swpaul{ 85940516Swpaul u_char eaddr[ETHER_ADDR_LEN]; 86040516Swpaul u_int32_t command; 86140516Swpaul struct rl_softc *sc; 86240516Swpaul struct ifnet *ifp; 86340516Swpaul u_int16_t rl_did = 0; 86450703Swpaul int unit, error = 0, rid; 86540516Swpaul 86650703Swpaul sc = device_get_softc(dev); 86750703Swpaul unit = device_get_unit(dev); 86840516Swpaul bzero(sc, sizeof(struct rl_softc)); 86940516Swpaul 87093818Sjhb mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 87193818Sjhb MTX_DEF | MTX_RECURSE); 87269583Swpaul 87340516Swpaul /* 87440516Swpaul * Handle power management nonsense. 87540516Swpaul */ 87640516Swpaul 87770167Swpaul if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 87870167Swpaul u_int32_t iobase, membase, irq; 87940516Swpaul 88070167Swpaul /* Save important PCI config data. */ 88170167Swpaul iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 88270167Swpaul membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 88370167Swpaul irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 88440516Swpaul 88570167Swpaul /* Reset the power state. */ 88670167Swpaul printf("rl%d: chip is is in D%d power mode " 88770167Swpaul "-- setting to D0\n", unit, 88870167Swpaul pci_get_powerstate(dev)); 88940516Swpaul 89070167Swpaul pci_set_powerstate(dev, PCI_POWERSTATE_D0); 89140516Swpaul 89270167Swpaul /* Restore PCI config data. */ 89370167Swpaul pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 89470167Swpaul pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 89570167Swpaul pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 89640516Swpaul } 89740516Swpaul 89840516Swpaul /* 89940516Swpaul * Map control/status registers. 90040516Swpaul */ 90172813Swpaul pci_enable_busmaster(dev); 90279472Swpaul pci_enable_io(dev, SYS_RES_IOPORT); 90379472Swpaul pci_enable_io(dev, SYS_RES_MEMORY); 90461041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 90540516Swpaul 90640516Swpaul#ifdef RL_USEIOSPACE 90740516Swpaul if (!(command & PCIM_CMD_PORTEN)) { 90840516Swpaul printf("rl%d: failed to enable I/O ports!\n", unit); 90950703Swpaul error = ENXIO; 91040516Swpaul goto fail; 91140516Swpaul } 91240516Swpaul#else 91340516Swpaul if (!(command & PCIM_CMD_MEMEN)) { 91440516Swpaul printf("rl%d: failed to enable memory mapping!\n", unit); 91550703Swpaul error = ENXIO; 91640516Swpaul goto fail; 91740516Swpaul } 91850703Swpaul#endif 91940516Swpaul 92050703Swpaul rid = RL_RID; 92150703Swpaul sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 92250703Swpaul 0, ~0, 1, RF_ACTIVE); 92350703Swpaul 92450703Swpaul if (sc->rl_res == NULL) { 92550703Swpaul printf ("rl%d: couldn't map ports/memory\n", unit); 92650703Swpaul error = ENXIO; 92740516Swpaul goto fail; 92840516Swpaul } 92940516Swpaul 93069127Sroger /* Detect the Realtek 8139B. For some reason, this chip is very 93169127Sroger * unstable when left to autoselect the media 93269127Sroger * The best workaround is to set the device to the required 93369127Sroger * media type or to set it to the 10 Meg speed. 93469127Sroger */ 93569127Sroger 93669127Sroger if ((rman_get_end(sc->rl_res)-rman_get_start(sc->rl_res))==0xff) { 93769127Sroger printf("rl%d: Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n", unit); 93869127Sroger } 93969127Sroger 94050703Swpaul sc->rl_btag = rman_get_bustag(sc->rl_res); 94150703Swpaul sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 94250703Swpaul 94350703Swpaul rid = 0; 94450703Swpaul sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 94550703Swpaul RF_SHAREABLE | RF_ACTIVE); 94650703Swpaul 94750703Swpaul if (sc->rl_irq == NULL) { 94840516Swpaul printf("rl%d: couldn't map interrupt\n", unit); 94950703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 95050703Swpaul error = ENXIO; 95140516Swpaul goto fail; 95240516Swpaul } 95340516Swpaul 95440516Swpaul /* Reset the adapter. */ 95540516Swpaul rl_reset(sc); 95667931Swpaul sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 95767931Swpaul rl_read_eeprom(sc, (caddr_t)&rl_did, 0, 1, 0); 95868215Swpaul if (rl_did != 0x8129) 95967931Swpaul sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 96040516Swpaul 96140516Swpaul /* 96240516Swpaul * Get station address from the EEPROM. 96340516Swpaul */ 96440516Swpaul rl_read_eeprom(sc, (caddr_t)&eaddr, RL_EE_EADDR, 3, 0); 96540516Swpaul 96640516Swpaul /* 96740516Swpaul * A RealTek chip was detected. Inform the world. 96840516Swpaul */ 96940516Swpaul printf("rl%d: Ethernet address: %6D\n", unit, eaddr, ":"); 97040516Swpaul 97140516Swpaul sc->rl_unit = unit; 97240516Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 97340516Swpaul 97440516Swpaul /* 97540516Swpaul * Now read the exact device type from the EEPROM to find 97640516Swpaul * out if it's an 8129 or 8139. 97740516Swpaul */ 97840516Swpaul rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0); 97940516Swpaul 98044238Swpaul if (rl_did == RT_DEVICEID_8139 || rl_did == ACCTON_DEVICEID_5030 || 98167771Swpaul rl_did == DELTA_DEVICEID_8139 || rl_did == ADDTRON_DEVICEID_8139 || 98296112Sjhb rl_did == RT_DEVICEID_8138 || rl_did == DLINK_DEVICEID_530TXPLUS || 983103020Siwasaki rl_did == DLINK_DEVICEID_690TXD || rl_did == COREGA_DEVICEID_CBTXD) 98440516Swpaul sc->rl_type = RL_8139; 98540516Swpaul else if (rl_did == RT_DEVICEID_8129) 98640516Swpaul sc->rl_type = RL_8129; 98740516Swpaul else { 98840516Swpaul printf("rl%d: unknown device ID: %x\n", unit, rl_did); 98968215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 99050703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 99150703Swpaul error = ENXIO; 99240516Swpaul goto fail; 99340516Swpaul } 99440516Swpaul 99581713Swpaul /* 99681713Swpaul * Allocate the parent bus DMA tag appropriate for PCI. 99781713Swpaul */ 99881713Swpaul#define RL_NSEG_NEW 32 999104324Sphk error = bus_dma_tag_create(NULL, /* parent */ 100081713Swpaul 1, 0, /* alignment, boundary */ 100181713Swpaul BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 100281713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 100381713Swpaul NULL, NULL, /* filter, filterarg */ 100481713Swpaul MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 100581713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 100681713Swpaul BUS_DMA_ALLOCNOW, /* flags */ 100781713Swpaul &sc->rl_parent_tag); 100840516Swpaul 100981713Swpaul /* 101081713Swpaul * Now allocate a tag for the DMA descriptor lists. 101181713Swpaul * All of our lists are allocated as a contiguous block 101281713Swpaul * of memory. 101381713Swpaul */ 101481713Swpaul error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 101581713Swpaul 1, 0, /* alignment, boundary */ 101681713Swpaul BUS_SPACE_MAXADDR, /* lowaddr */ 101781713Swpaul BUS_SPACE_MAXADDR, /* highaddr */ 101881713Swpaul NULL, NULL, /* filter, filterarg */ 101981713Swpaul RL_RXBUFLEN + 1518, 1, /* maxsize,nsegments */ 102081713Swpaul BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 102181713Swpaul 0, /* flags */ 102281713Swpaul &sc->rl_tag); 102381713Swpaul 102481713Swpaul /* 102581713Swpaul * Now allocate a chunk of DMA-able memory based on the 102681713Swpaul * tag we just created. 102781713Swpaul */ 102881713Swpaul error = bus_dmamem_alloc(sc->rl_tag, 102981713Swpaul (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_NOWAIT, 103081713Swpaul &sc->rl_cdata.rl_rx_dmamap); 103181713Swpaul 103240516Swpaul if (sc->rl_cdata.rl_rx_buf == NULL) { 103340516Swpaul printf("rl%d: no memory for list buffers!\n", unit); 103468215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 103550703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 103681713Swpaul bus_dma_tag_destroy(sc->rl_tag); 103750703Swpaul error = ENXIO; 103840516Swpaul goto fail; 103940516Swpaul } 104040516Swpaul 104148028Swpaul /* Leave a few bytes before the start of the RX ring buffer. */ 104248028Swpaul sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 104348028Swpaul sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t); 104448028Swpaul 104550703Swpaul /* Do MII setup */ 104650703Swpaul if (mii_phy_probe(dev, &sc->rl_miibus, 104750703Swpaul rl_ifmedia_upd, rl_ifmedia_sts)) { 104850703Swpaul printf("rl%d: MII without any phy!\n", sc->rl_unit); 104968215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 105050703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 105181713Swpaul bus_dmamem_free(sc->rl_tag, 105281713Swpaul sc->rl_cdata.rl_rx_buf, sc->rl_cdata.rl_rx_dmamap); 105381713Swpaul bus_dma_tag_destroy(sc->rl_tag); 105450703Swpaul error = ENXIO; 105550703Swpaul goto fail; 105650703Swpaul } 105750703Swpaul 105840516Swpaul ifp = &sc->arpcom.ac_if; 105940516Swpaul ifp->if_softc = sc; 106040516Swpaul ifp->if_unit = unit; 106140516Swpaul ifp->if_name = "rl"; 106240516Swpaul ifp->if_mtu = ETHERMTU; 106340516Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 106440516Swpaul ifp->if_ioctl = rl_ioctl; 106540516Swpaul ifp->if_output = ether_output; 106640516Swpaul ifp->if_start = rl_start; 106740516Swpaul ifp->if_watchdog = rl_watchdog; 106840516Swpaul ifp->if_init = rl_init; 106940516Swpaul ifp->if_baudrate = 10000000; 107045633Swpaul ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 107140516Swpaul 107240516Swpaul /* 107363090Sarchie * Call MI attach routine. 107440516Swpaul */ 1075106936Ssam ether_ifattach(ifp, eaddr); 1076106157Simp 1077106157Simp error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 1078106157Simp rl_intr, sc, &sc->rl_intrhand); 1079106157Simp 1080106157Simp if (error) { 1081106157Simp printf("rl%d: couldn't set up irq\n", unit); 1082106157Simp bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1083106157Simp bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1084106157Simp bus_dmamem_free(sc->rl_tag, 1085106157Simp sc->rl_cdata.rl_rx_buf, sc->rl_cdata.rl_rx_dmamap); 1086106157Simp bus_dma_tag_destroy(sc->rl_tag); 1087106157Simp goto fail; 1088106157Simp } 1089106157Simp 1090106157Simp callout_handle_init(&sc->rl_stat_ch); 109167087Swpaul return(0); 109240516Swpaulfail: 109367087Swpaul mtx_destroy(&sc->rl_mtx); 109450703Swpaul return(error); 109540516Swpaul} 109640516Swpaul 1097102335Salfredstatic int 1098102335Salfredrl_detach(dev) 109950703Swpaul device_t dev; 110050703Swpaul{ 110150703Swpaul struct rl_softc *sc; 110250703Swpaul struct ifnet *ifp; 110350703Swpaul 110450703Swpaul sc = device_get_softc(dev); 110567087Swpaul RL_LOCK(sc); 110650703Swpaul ifp = &sc->arpcom.ac_if; 110750703Swpaul 1108106936Ssam ether_ifdetach(ifp); 110950703Swpaul rl_stop(sc); 111050703Swpaul 111150703Swpaul bus_generic_detach(dev); 111250703Swpaul device_delete_child(dev, sc->rl_miibus); 111350703Swpaul 111450703Swpaul bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 111568215Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 111650703Swpaul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 111750703Swpaul 111881713Swpaul bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 111981713Swpaul bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf, 112081713Swpaul sc->rl_cdata.rl_rx_dmamap); 112181713Swpaul bus_dma_tag_destroy(sc->rl_tag); 112281713Swpaul bus_dma_tag_destroy(sc->rl_parent_tag); 112350703Swpaul 112467087Swpaul RL_UNLOCK(sc); 112567087Swpaul mtx_destroy(&sc->rl_mtx); 112650703Swpaul 112750703Swpaul return(0); 112850703Swpaul} 112950703Swpaul 113040516Swpaul/* 113140516Swpaul * Initialize the transmit descriptors. 113240516Swpaul */ 1133102335Salfredstatic int 1134102335Salfredrl_list_tx_init(sc) 113540516Swpaul struct rl_softc *sc; 113640516Swpaul{ 113740516Swpaul struct rl_chain_data *cd; 113840516Swpaul int i; 113940516Swpaul 114040516Swpaul cd = &sc->rl_cdata; 114140516Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 114245633Swpaul cd->rl_tx_chain[i] = NULL; 114348028Swpaul CSR_WRITE_4(sc, 114448028Swpaul RL_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 114540516Swpaul } 114640516Swpaul 114745633Swpaul sc->rl_cdata.cur_tx = 0; 114845633Swpaul sc->rl_cdata.last_tx = 0; 114940516Swpaul 115040516Swpaul return(0); 115140516Swpaul} 115240516Swpaul 115340516Swpaul/* 115440516Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 115540516Swpaul * the higher level protocols. 115640516Swpaul * 115740516Swpaul * You know there's something wrong with a PCI bus-master chip design 115840516Swpaul * when you have to use m_devget(). 115940516Swpaul * 116040516Swpaul * The receive operation is badly documented in the datasheet, so I'll 116140516Swpaul * attempt to document it here. The driver provides a buffer area and 116240516Swpaul * places its base address in the RX buffer start address register. 116340516Swpaul * The chip then begins copying frames into the RX buffer. Each frame 116472645Sasmodai * is preceded by a 32-bit RX status word which specifies the length 116540516Swpaul * of the frame and certain other status bits. Each frame (starting with 116640516Swpaul * the status word) is also 32-bit aligned. The frame length is in the 116740516Swpaul * first 16 bits of the status word; the lower 15 bits correspond with 116840516Swpaul * the 'rx status register' mentioned in the datasheet. 116948028Swpaul * 117048028Swpaul * Note: to make the Alpha happy, the frame payload needs to be aligned 117178508Sbmilekic * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 117278508Sbmilekic * as the offset argument to m_devget(). 117340516Swpaul */ 1174102335Salfredstatic void 1175102335Salfredrl_rxeof(sc) 117640516Swpaul struct rl_softc *sc; 117740516Swpaul{ 117840516Swpaul struct mbuf *m; 117940516Swpaul struct ifnet *ifp; 118040516Swpaul int total_len = 0; 118140516Swpaul u_int32_t rxstat; 118240516Swpaul caddr_t rxbufpos; 118340516Swpaul int wrap = 0; 118440516Swpaul u_int16_t cur_rx; 118540516Swpaul u_int16_t limit; 118640516Swpaul u_int16_t rx_bytes = 0, max_bytes; 118740516Swpaul 118840516Swpaul ifp = &sc->arpcom.ac_if; 118940516Swpaul 119081713Swpaul bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 119181713Swpaul BUS_DMASYNC_POSTWRITE); 119281713Swpaul 119340516Swpaul cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 119440516Swpaul 119540516Swpaul /* Do not try to read past this point. */ 119640516Swpaul limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 119740516Swpaul 119840516Swpaul if (limit < cur_rx) 119940516Swpaul max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 120040516Swpaul else 120140516Swpaul max_bytes = limit - cur_rx; 120240516Swpaul 120342738Swpaul while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 120494883Sluigi#ifdef DEVICE_POLLING 1205102052Ssobomax if (ifp->if_flags & IFF_POLLING) { 120694883Sluigi if (sc->rxcycles <= 0) 120794883Sluigi break; 120894883Sluigi sc->rxcycles--; 120994883Sluigi } 121094883Sluigi#endif /* DEVICE_POLLING */ 121140516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 121240516Swpaul rxstat = *(u_int32_t *)rxbufpos; 121340516Swpaul 121440516Swpaul /* 121540516Swpaul * Here's a totally undocumented fact for you. When the 121640516Swpaul * RealTek chip is in the process of copying a packet into 121740516Swpaul * RAM for you, the length will be 0xfff0. If you spot a 121840516Swpaul * packet header with this value, you need to stop. The 121940516Swpaul * datasheet makes absolutely no mention of this and 122040516Swpaul * RealTek should be shot for this. 122140516Swpaul */ 122240516Swpaul if ((u_int16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED) 122340516Swpaul break; 122440516Swpaul 122540516Swpaul if (!(rxstat & RL_RXSTAT_RXOK)) { 122640516Swpaul ifp->if_ierrors++; 122750703Swpaul rl_init(sc); 122850703Swpaul return; 122940516Swpaul } 123040516Swpaul 123140516Swpaul /* No errors; receive the packet. */ 123240516Swpaul total_len = rxstat >> 16; 123340516Swpaul rx_bytes += total_len + 4; 123440516Swpaul 123540516Swpaul /* 123642051Swpaul * XXX The RealTek chip includes the CRC with every 123742051Swpaul * received frame, and there's no way to turn this 123842051Swpaul * behavior off (at least, I can't find anything in 123942051Swpaul * the manual that explains how to do it) so we have 124042051Swpaul * to trim off the CRC manually. 124142051Swpaul */ 124242051Swpaul total_len -= ETHER_CRC_LEN; 124342051Swpaul 124442051Swpaul /* 124540516Swpaul * Avoid trying to read more bytes than we know 124640516Swpaul * the chip has prepared for us. 124740516Swpaul */ 124840516Swpaul if (rx_bytes > max_bytes) 124940516Swpaul break; 125040516Swpaul 125140516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf + 125240516Swpaul ((cur_rx + sizeof(u_int32_t)) % RL_RXBUFLEN); 125340516Swpaul 125440516Swpaul if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 125540516Swpaul rxbufpos = sc->rl_cdata.rl_rx_buf; 125640516Swpaul 125740516Swpaul wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 125840516Swpaul 125940516Swpaul if (total_len > wrap) { 126078508Sbmilekic m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 126178508Sbmilekic NULL); 126240516Swpaul if (m == NULL) { 126340516Swpaul ifp->if_ierrors++; 126452426Swpaul } else { 126540516Swpaul m_copyback(m, wrap, total_len - wrap, 126640516Swpaul sc->rl_cdata.rl_rx_buf); 126748028Swpaul } 126842051Swpaul cur_rx = (total_len - wrap + ETHER_CRC_LEN); 126940516Swpaul } else { 127078508Sbmilekic m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 127178508Sbmilekic NULL); 127240516Swpaul if (m == NULL) { 127340516Swpaul ifp->if_ierrors++; 127478508Sbmilekic } 127542051Swpaul cur_rx += total_len + 4 + ETHER_CRC_LEN; 127640516Swpaul } 127740516Swpaul 127840516Swpaul /* 127940516Swpaul * Round up to 32-bit boundary. 128040516Swpaul */ 128140516Swpaul cur_rx = (cur_rx + 3) & ~3; 128240516Swpaul CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 128340516Swpaul 128440516Swpaul if (m == NULL) 128540516Swpaul continue; 128640516Swpaul 128740516Swpaul ifp->if_ipackets++; 1288106936Ssam (*ifp->if_input)(ifp, m); 128940516Swpaul } 129040516Swpaul 129140516Swpaul return; 129240516Swpaul} 129340516Swpaul 129440516Swpaul/* 129540516Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 129640516Swpaul * the list buffers. 129740516Swpaul */ 1298102335Salfredstatic void 1299102335Salfredrl_txeof(sc) 130040516Swpaul struct rl_softc *sc; 130140516Swpaul{ 130240516Swpaul struct ifnet *ifp; 130340516Swpaul u_int32_t txstat; 130440516Swpaul 130540516Swpaul ifp = &sc->arpcom.ac_if; 130640516Swpaul 130740516Swpaul /* 130840516Swpaul * Go through our tx list and free mbufs for those 130940516Swpaul * frames that have been uploaded. 131040516Swpaul */ 131145633Swpaul do { 131245633Swpaul txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 131345633Swpaul if (!(txstat & (RL_TXSTAT_TX_OK| 131445633Swpaul RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 131540516Swpaul break; 131640516Swpaul 131745633Swpaul ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24; 131840516Swpaul 131945633Swpaul if (RL_LAST_TXMBUF(sc) != NULL) { 132081713Swpaul bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc)); 132181713Swpaul bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc)); 132245633Swpaul m_freem(RL_LAST_TXMBUF(sc)); 132345633Swpaul RL_LAST_TXMBUF(sc) = NULL; 132445633Swpaul } 132545633Swpaul if (txstat & RL_TXSTAT_TX_OK) 132645633Swpaul ifp->if_opackets++; 132745633Swpaul else { 132852426Swpaul int oldthresh; 132945633Swpaul ifp->if_oerrors++; 133045633Swpaul if ((txstat & RL_TXSTAT_TXABRT) || 133145633Swpaul (txstat & RL_TXSTAT_OUTOFWIN)) 133245633Swpaul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 133352426Swpaul oldthresh = sc->rl_txthresh; 133452426Swpaul /* error recovery */ 133552426Swpaul rl_reset(sc); 133652426Swpaul rl_init(sc); 133752426Swpaul /* 133852426Swpaul * If there was a transmit underrun, 133952426Swpaul * bump the TX threshold. 134052426Swpaul */ 134152426Swpaul if (txstat & RL_TXSTAT_TX_UNDERRUN) 134252426Swpaul sc->rl_txthresh = oldthresh + 32; 134352426Swpaul return; 134445633Swpaul } 134545633Swpaul RL_INC(sc->rl_cdata.last_tx); 134645633Swpaul ifp->if_flags &= ~IFF_OACTIVE; 134745633Swpaul } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 134840516Swpaul 134999165Sluigi ifp->if_timer = 135099165Sluigi (sc->rl_cdata.last_tx == sc->rl_cdata.cur_tx) ? 0 : 5; 135199165Sluigi 135250703Swpaul return; 135350703Swpaul} 135440516Swpaul 1355102335Salfredstatic void 1356102335Salfredrl_tick(xsc) 135750703Swpaul void *xsc; 135850703Swpaul{ 135950703Swpaul struct rl_softc *sc; 136050703Swpaul struct mii_data *mii; 136150703Swpaul 136250703Swpaul sc = xsc; 136367087Swpaul RL_LOCK(sc); 136450703Swpaul mii = device_get_softc(sc->rl_miibus); 136550703Swpaul 136650703Swpaul mii_tick(mii); 136750703Swpaul 136850703Swpaul sc->rl_stat_ch = timeout(rl_tick, sc, hz); 136967087Swpaul RL_UNLOCK(sc); 137050703Swpaul 137140516Swpaul return; 137240516Swpaul} 137340516Swpaul 137494883Sluigi#ifdef DEVICE_POLLING 137594883Sluigistatic void 137694883Sluigirl_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 137794883Sluigi{ 137894883Sluigi struct rl_softc *sc = ifp->if_softc; 137994883Sluigi 138094883Sluigi RL_LOCK(sc); 138194883Sluigi if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 138294883Sluigi CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 138394883Sluigi goto done; 138494883Sluigi } 138594883Sluigi 138694883Sluigi sc->rxcycles = count; 138794883Sluigi rl_rxeof(sc); 138894883Sluigi rl_txeof(sc); 138994883Sluigi if (ifp->if_snd.ifq_head != NULL) 139094883Sluigi rl_start(ifp); 139194883Sluigi 139294883Sluigi if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 139394883Sluigi u_int16_t status; 139494883Sluigi 139594883Sluigi status = CSR_READ_2(sc, RL_ISR); 1396100957Sjhb if (status == 0xffff) 1397100957Sjhb goto done; 139894883Sluigi if (status) 139994883Sluigi CSR_WRITE_2(sc, RL_ISR, status); 140094883Sluigi 140194883Sluigi /* 140294883Sluigi * XXX check behaviour on receiver stalls. 140394883Sluigi */ 140494883Sluigi 140594883Sluigi if (status & RL_ISR_SYSTEM_ERR) { 140694883Sluigi rl_reset(sc); 140794883Sluigi rl_init(sc); 140894883Sluigi } 140994883Sluigi } 141094883Sluigidone: 141194883Sluigi RL_UNLOCK(sc); 141294883Sluigi} 141394883Sluigi#endif /* DEVICE_POLLING */ 141494883Sluigi 1415102335Salfredstatic void 1416102335Salfredrl_intr(arg) 141740516Swpaul void *arg; 141840516Swpaul{ 141940516Swpaul struct rl_softc *sc; 142040516Swpaul struct ifnet *ifp; 142140516Swpaul u_int16_t status; 142240516Swpaul 142340516Swpaul sc = arg; 142486822Siwasaki 142586822Siwasaki if (sc->suspended) { 142686822Siwasaki return; 142786822Siwasaki } 142886822Siwasaki 142967087Swpaul RL_LOCK(sc); 143040516Swpaul ifp = &sc->arpcom.ac_if; 143140516Swpaul 143294883Sluigi#ifdef DEVICE_POLLING 1433102052Ssobomax if (ifp->if_flags & IFF_POLLING) 143494883Sluigi goto done; 143594883Sluigi if (ether_poll_register(rl_poll, ifp)) { /* ok, disable interrupts */ 143694883Sluigi CSR_WRITE_2(sc, RL_IMR, 0x0000); 143794883Sluigi rl_poll(ifp, 0, 1); 143894883Sluigi goto done; 143994883Sluigi } 144094883Sluigi#endif /* DEVICE_POLLING */ 144140516Swpaul 144240516Swpaul for (;;) { 144340516Swpaul 144440516Swpaul status = CSR_READ_2(sc, RL_ISR); 1445100957Sjhb /* If the card has gone away the read returns 0xffff. */ 1446100957Sjhb if (status == 0xffff) 1447100957Sjhb break; 144840516Swpaul if (status) 144940516Swpaul CSR_WRITE_2(sc, RL_ISR, status); 145040516Swpaul 145140516Swpaul if ((status & RL_INTRS) == 0) 145240516Swpaul break; 145340516Swpaul 145440516Swpaul if (status & RL_ISR_RX_OK) 145540516Swpaul rl_rxeof(sc); 145640516Swpaul 145740516Swpaul if (status & RL_ISR_RX_ERR) 145840516Swpaul rl_rxeof(sc); 145940516Swpaul 146045633Swpaul if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR)) 146140516Swpaul rl_txeof(sc); 146240516Swpaul 146340516Swpaul if (status & RL_ISR_SYSTEM_ERR) { 146440516Swpaul rl_reset(sc); 146540516Swpaul rl_init(sc); 146640516Swpaul } 146740516Swpaul 146840516Swpaul } 146940516Swpaul 147052426Swpaul if (ifp->if_snd.ifq_head != NULL) 147140516Swpaul rl_start(ifp); 147240516Swpaul 147394883Sluigi#ifdef DEVICE_POLLING 147494883Sluigidone: 147594883Sluigi#endif 147667087Swpaul RL_UNLOCK(sc); 147767087Swpaul 147840516Swpaul return; 147940516Swpaul} 148040516Swpaul 148140516Swpaul/* 148240516Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 148340516Swpaul * pointers to the fragment pointers. 148440516Swpaul */ 1485102335Salfredstatic int 1486102335Salfredrl_encap(sc, m_head) 148740516Swpaul struct rl_softc *sc; 148840516Swpaul struct mbuf *m_head; 148940516Swpaul{ 149041243Swpaul struct mbuf *m_new = NULL; 149140516Swpaul 149240516Swpaul /* 149345633Swpaul * The RealTek is brain damaged and wants longword-aligned 149445633Swpaul * TX buffers, plus we can only have one fragment buffer 149545633Swpaul * per packet. We have to copy pretty much all the time. 149640516Swpaul */ 149740516Swpaul 149841243Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 149987846Sluigi if (m_new == NULL) 150041243Swpaul return(1); 150141243Swpaul if (m_head->m_pkthdr.len > MHLEN) { 150241243Swpaul MCLGET(m_new, M_DONTWAIT); 150341243Swpaul if (!(m_new->m_flags & M_EXT)) { 150441243Swpaul m_freem(m_new); 150540516Swpaul return(1); 150640516Swpaul } 150740516Swpaul } 150852426Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 150941243Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 151041243Swpaul m_freem(m_head); 151141243Swpaul m_head = m_new; 151240516Swpaul 151340516Swpaul /* Pad frames to at least 60 bytes. */ 151441243Swpaul if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) { 151555058Swpaul /* 151655058Swpaul * Make security concious people happy: zero out the 151755058Swpaul * bytes in the pad area, since we don't know what 151855058Swpaul * this mbuf cluster buffer's previous user might 151955058Swpaul * have left in it. 152055058Swpaul */ 152155058Swpaul bzero(mtod(m_head, char *) + m_head->m_pkthdr.len, 152255058Swpaul RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 152340516Swpaul m_head->m_pkthdr.len += 152452426Swpaul (RL_MIN_FRAMELEN - m_head->m_pkthdr.len); 152541243Swpaul m_head->m_len = m_head->m_pkthdr.len; 152641243Swpaul } 152740516Swpaul 152845633Swpaul RL_CUR_TXMBUF(sc) = m_head; 152940516Swpaul 153040516Swpaul return(0); 153140516Swpaul} 153240516Swpaul 153340516Swpaul/* 153440516Swpaul * Main transmit routine. 153540516Swpaul */ 153640516Swpaul 1537102335Salfredstatic void 1538102335Salfredrl_start(ifp) 153940516Swpaul struct ifnet *ifp; 154040516Swpaul{ 154140516Swpaul struct rl_softc *sc; 154240516Swpaul struct mbuf *m_head = NULL; 154340516Swpaul 154440516Swpaul sc = ifp->if_softc; 154567087Swpaul RL_LOCK(sc); 154640516Swpaul 154745633Swpaul while(RL_CUR_TXMBUF(sc) == NULL) { 154840516Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 154940516Swpaul if (m_head == NULL) 155040516Swpaul break; 155140516Swpaul 155258801Swpaul if (rl_encap(sc, m_head)) { 155358801Swpaul IF_PREPEND(&ifp->if_snd, m_head); 155458801Swpaul ifp->if_flags |= IFF_OACTIVE; 155558801Swpaul break; 155658801Swpaul } 155740516Swpaul 155840516Swpaul /* 155940516Swpaul * If there's a BPF listener, bounce a copy of this frame 156040516Swpaul * to him. 156140516Swpaul */ 1562106936Ssam BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 156351583Swpaul 156440516Swpaul /* 156540516Swpaul * Transmit the frame. 156640516Swpaul */ 156781713Swpaul bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc)); 156881713Swpaul bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc), 156981713Swpaul mtod(RL_CUR_TXMBUF(sc), void *), 157081713Swpaul RL_CUR_TXMBUF(sc)->m_pkthdr.len, rl_dma_map_txbuf, sc, 0); 157181713Swpaul bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc), 157281713Swpaul BUS_DMASYNC_PREREAD); 157345633Swpaul CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 157452426Swpaul RL_TXTHRESH(sc->rl_txthresh) | 157552426Swpaul RL_CUR_TXMBUF(sc)->m_pkthdr.len); 157645633Swpaul 157745633Swpaul RL_INC(sc->rl_cdata.cur_tx); 157840516Swpaul } 157940516Swpaul 158040516Swpaul /* 158145633Swpaul * We broke out of the loop because all our TX slots are 158245633Swpaul * full. Mark the NIC as busy until it drains some of the 158345633Swpaul * packets from the queue. 158445633Swpaul */ 158545633Swpaul if (RL_CUR_TXMBUF(sc) != NULL) 158645633Swpaul ifp->if_flags |= IFF_OACTIVE; 158745633Swpaul 158845633Swpaul /* 158940516Swpaul * Set a timeout in case the chip goes out to lunch. 159040516Swpaul */ 159140516Swpaul ifp->if_timer = 5; 159267087Swpaul RL_UNLOCK(sc); 159340516Swpaul 159440516Swpaul return; 159540516Swpaul} 159640516Swpaul 1597102335Salfredstatic void 1598102335Salfredrl_init(xsc) 159940516Swpaul void *xsc; 160040516Swpaul{ 160140516Swpaul struct rl_softc *sc = xsc; 160240516Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 160350703Swpaul struct mii_data *mii; 160467087Swpaul int i; 160540516Swpaul u_int32_t rxcfg = 0; 160640516Swpaul 160767087Swpaul RL_LOCK(sc); 160850703Swpaul mii = device_get_softc(sc->rl_miibus); 160940516Swpaul 161040516Swpaul /* 161140516Swpaul * Cancel pending I/O and free all RX/TX buffers. 161240516Swpaul */ 161340516Swpaul rl_stop(sc); 161440516Swpaul 161540516Swpaul /* Init our MAC address */ 161640516Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) { 161740516Swpaul CSR_WRITE_1(sc, RL_IDR0 + i, sc->arpcom.ac_enaddr[i]); 161840516Swpaul } 161940516Swpaul 162040516Swpaul /* Init the RX buffer pointer register. */ 162181713Swpaul bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 162281713Swpaul sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf, sc, 0); 162381713Swpaul bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap, 162481713Swpaul BUS_DMASYNC_PREWRITE); 162540516Swpaul 162640516Swpaul /* Init TX descriptors. */ 162740516Swpaul rl_list_tx_init(sc); 162840516Swpaul 162940516Swpaul /* 163040516Swpaul * Enable transmit and receive. 163140516Swpaul */ 163240516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 163340516Swpaul 163440516Swpaul /* 163545633Swpaul * Set the initial TX and RX configuration. 163640516Swpaul */ 163745633Swpaul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 163840516Swpaul CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 163940516Swpaul 164040516Swpaul /* Set the individual bit to receive frames for this host only. */ 164140516Swpaul rxcfg = CSR_READ_4(sc, RL_RXCFG); 164240516Swpaul rxcfg |= RL_RXCFG_RX_INDIV; 164340516Swpaul 164440516Swpaul /* If we want promiscuous mode, set the allframes bit. */ 164540516Swpaul if (ifp->if_flags & IFF_PROMISC) { 164640516Swpaul rxcfg |= RL_RXCFG_RX_ALLPHYS; 164740516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 164840516Swpaul } else { 164940516Swpaul rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 165040516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 165140516Swpaul } 165240516Swpaul 165340516Swpaul /* 165440516Swpaul * Set capture broadcast bit to capture broadcast frames. 165540516Swpaul */ 165640516Swpaul if (ifp->if_flags & IFF_BROADCAST) { 165740516Swpaul rxcfg |= RL_RXCFG_RX_BROAD; 165840516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 165940516Swpaul } else { 166040516Swpaul rxcfg &= ~RL_RXCFG_RX_BROAD; 166140516Swpaul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 166240516Swpaul } 166340516Swpaul 166440516Swpaul /* 166540516Swpaul * Program the multicast filter, if necessary. 166640516Swpaul */ 166740516Swpaul rl_setmulti(sc); 166840516Swpaul 166994883Sluigi#ifdef DEVICE_POLLING 167040516Swpaul /* 167194883Sluigi * Disable interrupts if we are polling. 167294883Sluigi */ 1673102052Ssobomax if (ifp->if_flags & IFF_POLLING) 167494883Sluigi CSR_WRITE_2(sc, RL_IMR, 0); 167594883Sluigi else /* otherwise ... */ 167694883Sluigi#endif /* DEVICE_POLLING */ 167794883Sluigi /* 167840516Swpaul * Enable interrupts. 167940516Swpaul */ 168040516Swpaul CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 168140516Swpaul 168252426Swpaul /* Set initial TX threshold */ 168352426Swpaul sc->rl_txthresh = RL_TX_THRESH_INIT; 168452426Swpaul 168540516Swpaul /* Start RX/TX process. */ 168640516Swpaul CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 168740516Swpaul 168840516Swpaul /* Enable receiver and transmitter. */ 168940516Swpaul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 169040516Swpaul 169150703Swpaul mii_mediachg(mii); 169240516Swpaul 169340516Swpaul CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 169440516Swpaul 169540516Swpaul ifp->if_flags |= IFF_RUNNING; 169640516Swpaul ifp->if_flags &= ~IFF_OACTIVE; 169740516Swpaul 169850703Swpaul sc->rl_stat_ch = timeout(rl_tick, sc, hz); 169967087Swpaul RL_UNLOCK(sc); 170050703Swpaul 170140516Swpaul return; 170240516Swpaul} 170340516Swpaul 170440516Swpaul/* 170540516Swpaul * Set media options. 170640516Swpaul */ 1707102335Salfredstatic int 1708102335Salfredrl_ifmedia_upd(ifp) 170940516Swpaul struct ifnet *ifp; 171040516Swpaul{ 171140516Swpaul struct rl_softc *sc; 171250703Swpaul struct mii_data *mii; 171340516Swpaul 171440516Swpaul sc = ifp->if_softc; 171550703Swpaul mii = device_get_softc(sc->rl_miibus); 171650703Swpaul mii_mediachg(mii); 171740516Swpaul 171840516Swpaul return(0); 171940516Swpaul} 172040516Swpaul 172140516Swpaul/* 172240516Swpaul * Report current media status. 172340516Swpaul */ 1724102335Salfredstatic void 1725102335Salfredrl_ifmedia_sts(ifp, ifmr) 172640516Swpaul struct ifnet *ifp; 172740516Swpaul struct ifmediareq *ifmr; 172840516Swpaul{ 172940516Swpaul struct rl_softc *sc; 173050703Swpaul struct mii_data *mii; 173140516Swpaul 173240516Swpaul sc = ifp->if_softc; 173350703Swpaul mii = device_get_softc(sc->rl_miibus); 173440516Swpaul 173550703Swpaul mii_pollstat(mii); 173650703Swpaul ifmr->ifm_active = mii->mii_media_active; 173750703Swpaul ifmr->ifm_status = mii->mii_media_status; 173840516Swpaul 173940516Swpaul return; 174040516Swpaul} 174140516Swpaul 1742102335Salfredstatic int 1743102335Salfredrl_ioctl(ifp, command, data) 174440516Swpaul struct ifnet *ifp; 174540516Swpaul u_long command; 174640516Swpaul caddr_t data; 174740516Swpaul{ 174840516Swpaul struct rl_softc *sc = ifp->if_softc; 174940516Swpaul struct ifreq *ifr = (struct ifreq *) data; 175050703Swpaul struct mii_data *mii; 175167087Swpaul int error = 0; 175240516Swpaul 175367087Swpaul RL_LOCK(sc); 175440516Swpaul 175540516Swpaul switch(command) { 175640516Swpaul case SIOCSIFFLAGS: 175740516Swpaul if (ifp->if_flags & IFF_UP) { 175840516Swpaul rl_init(sc); 175940516Swpaul } else { 176040516Swpaul if (ifp->if_flags & IFF_RUNNING) 176140516Swpaul rl_stop(sc); 176240516Swpaul } 176340516Swpaul error = 0; 176440516Swpaul break; 176540516Swpaul case SIOCADDMULTI: 176640516Swpaul case SIOCDELMULTI: 176740516Swpaul rl_setmulti(sc); 176840516Swpaul error = 0; 176940516Swpaul break; 177040516Swpaul case SIOCGIFMEDIA: 177140516Swpaul case SIOCSIFMEDIA: 177250703Swpaul mii = device_get_softc(sc->rl_miibus); 177350703Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 177440516Swpaul break; 177540516Swpaul default: 1776106936Ssam error = ether_ioctl(ifp, command, data); 177740516Swpaul break; 177840516Swpaul } 177940516Swpaul 178067087Swpaul RL_UNLOCK(sc); 178140516Swpaul 178240516Swpaul return(error); 178340516Swpaul} 178440516Swpaul 1785102335Salfredstatic void 1786102335Salfredrl_watchdog(ifp) 178740516Swpaul struct ifnet *ifp; 178840516Swpaul{ 178940516Swpaul struct rl_softc *sc; 179040516Swpaul 179140516Swpaul sc = ifp->if_softc; 179267087Swpaul RL_LOCK(sc); 179340516Swpaul printf("rl%d: watchdog timeout\n", sc->rl_unit); 179440516Swpaul ifp->if_oerrors++; 179550703Swpaul 179640516Swpaul rl_txeof(sc); 179740516Swpaul rl_rxeof(sc); 179840516Swpaul rl_init(sc); 179967087Swpaul RL_UNLOCK(sc); 180040516Swpaul 180140516Swpaul return; 180240516Swpaul} 180340516Swpaul 180440516Swpaul/* 180540516Swpaul * Stop the adapter and free any mbufs allocated to the 180640516Swpaul * RX and TX lists. 180740516Swpaul */ 1808102335Salfredstatic void 1809102335Salfredrl_stop(sc) 181040516Swpaul struct rl_softc *sc; 181140516Swpaul{ 181240516Swpaul register int i; 181340516Swpaul struct ifnet *ifp; 181440516Swpaul 181567087Swpaul RL_LOCK(sc); 181640516Swpaul ifp = &sc->arpcom.ac_if; 181740516Swpaul ifp->if_timer = 0; 181840516Swpaul 181950703Swpaul untimeout(rl_tick, sc, sc->rl_stat_ch); 182094883Sluigi ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 182194883Sluigi#ifdef DEVICE_POLLING 182294883Sluigi ether_poll_deregister(ifp); 182394883Sluigi#endif /* DEVICE_POLLING */ 182450703Swpaul 182540516Swpaul CSR_WRITE_1(sc, RL_COMMAND, 0x00); 182640516Swpaul CSR_WRITE_2(sc, RL_IMR, 0x0000); 182781713Swpaul bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap); 182840516Swpaul 182940516Swpaul /* 183040516Swpaul * Free the TX list buffers. 183140516Swpaul */ 183240516Swpaul for (i = 0; i < RL_TX_LIST_CNT; i++) { 183345633Swpaul if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 183481713Swpaul bus_dmamap_unload(sc->rl_tag, 183581713Swpaul sc->rl_cdata.rl_tx_dmamap[i]); 183681713Swpaul bus_dmamap_destroy(sc->rl_tag, 183781713Swpaul sc->rl_cdata.rl_tx_dmamap[i]); 183845633Swpaul m_freem(sc->rl_cdata.rl_tx_chain[i]); 183945633Swpaul sc->rl_cdata.rl_tx_chain[i] = NULL; 184045633Swpaul CSR_WRITE_4(sc, RL_TXADDR0 + i, 0x0000000); 184140516Swpaul } 184240516Swpaul } 184340516Swpaul 184467087Swpaul RL_UNLOCK(sc); 184540516Swpaul return; 184640516Swpaul} 184740516Swpaul 184840516Swpaul/* 184986822Siwasaki * Device suspend routine. Stop the interface and save some PCI 185086822Siwasaki * settings in case the BIOS doesn't restore them properly on 185186822Siwasaki * resume. 185286822Siwasaki */ 1853102335Salfredstatic int 1854102335Salfredrl_suspend(dev) 185586822Siwasaki device_t dev; 185686822Siwasaki{ 185786822Siwasaki register int i; 185886822Siwasaki struct rl_softc *sc; 185986822Siwasaki 186086822Siwasaki sc = device_get_softc(dev); 186186822Siwasaki 186286822Siwasaki rl_stop(sc); 186386822Siwasaki 186486822Siwasaki for (i = 0; i < 5; i++) 186586822Siwasaki sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 186686822Siwasaki sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 186786822Siwasaki sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 186886822Siwasaki sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 186986822Siwasaki sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 187086822Siwasaki 187186822Siwasaki sc->suspended = 1; 187286822Siwasaki 187386822Siwasaki return (0); 187486822Siwasaki} 187586822Siwasaki 187686822Siwasaki/* 187786822Siwasaki * Device resume routine. Restore some PCI settings in case the BIOS 187886822Siwasaki * doesn't, re-enable busmastering, and restart the interface if 187986822Siwasaki * appropriate. 188086822Siwasaki */ 1881102335Salfredstatic int 1882102335Salfredrl_resume(dev) 188386822Siwasaki device_t dev; 188486822Siwasaki{ 188586822Siwasaki register int i; 188686822Siwasaki struct rl_softc *sc; 188786822Siwasaki struct ifnet *ifp; 188886822Siwasaki 188986822Siwasaki sc = device_get_softc(dev); 189086822Siwasaki ifp = &sc->arpcom.ac_if; 189186822Siwasaki 189286822Siwasaki /* better way to do this? */ 189386822Siwasaki for (i = 0; i < 5; i++) 189486822Siwasaki pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 189586822Siwasaki pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 189686822Siwasaki pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 189786822Siwasaki pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 189886822Siwasaki pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 189986822Siwasaki 190086822Siwasaki /* reenable busmastering */ 190186822Siwasaki pci_enable_busmaster(dev); 190286822Siwasaki pci_enable_io(dev, RL_RES); 190386822Siwasaki 190486822Siwasaki /* reinitialize interface if necessary */ 190586822Siwasaki if (ifp->if_flags & IFF_UP) 190686822Siwasaki rl_init(sc); 190786822Siwasaki 190886822Siwasaki sc->suspended = 0; 190986822Siwasaki 191086822Siwasaki return (0); 191186822Siwasaki} 191286822Siwasaki 191386822Siwasaki/* 191440516Swpaul * Stop all chip I/O so that the kernel's probe routines don't 191540516Swpaul * get confused by errant DMAs when rebooting. 191640516Swpaul */ 1917102335Salfredstatic void 1918102335Salfredrl_shutdown(dev) 191950703Swpaul device_t dev; 192040516Swpaul{ 192150703Swpaul struct rl_softc *sc; 192240516Swpaul 192350703Swpaul sc = device_get_softc(dev); 192450703Swpaul 192540516Swpaul rl_stop(sc); 192640516Swpaul 192740516Swpaul return; 192840516Swpaul} 1929