sio.c revision 93818
1104834Sobrien/*- 233965Sjdp * Copyright (c) 1991 The Regents of the University of California. 333965Sjdp * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Berkeley and its contributors. 17 * 4. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/pc98/cbus/sio.c 93818 2002-04-04 21:03:38Z jhb $ 34 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 35 * from: i386/isa sio.c,v 1.234 36 */ 37 38#include "opt_comconsole.h" 39#include "opt_compat.h" 40#include "opt_ddb.h" 41#include "opt_sio.h" 42 43/* 44 * Serial driver, based on 386BSD-0.1 com driver. 45 * Mostly rewritten to use pseudo-DMA. 46 * Works for National Semiconductor NS8250-NS16550AF UARTs. 47 * COM driver, based on HP dca driver. 48 * 49 * Changes for PC-Card integration: 50 * - Added PC-Card driver table and handlers 51 */ 52/*=============================================================== 53 * 386BSD(98),FreeBSD-1.1x(98) com driver. 54 * ----- 55 * modified for PC9801 by M.Ishii 56 * Kyoto University Microcomputer Club (KMC) 57 * Chou "TEFUTEFU" Hirotomi 58 * Kyoto Univ. the faculty of medicine 59 *=============================================================== 60 * FreeBSD-2.0.1(98) sio driver. 61 * ----- 62 * modified for pc98 Internal i8251 and MICRO CORE MC16550II 63 * T.Koike(hfc01340@niftyserve.or.jp) 64 * implement kernel device configuration 65 * aizu@orient.center.nitech.ac.jp 66 * 67 * Notes. 68 * ----- 69 * PC98 localization based on 386BSD(98) com driver. Using its PC98 local 70 * functions. 71 * This driver is under debugging,has bugs. 72 * 73 * 1) config 74 * options COM_MULTIPORT #if using MC16550II 75 * device sio0 at nec? port 0x30 tty irq 4 #internal 76 * device sio1 at nec? port 0xd2 tty irq 5 flags 0x101 #mc1 77 * device sio2 at nec? port 0x8d2 tty flags 0x101 #mc2 78 * # ~~~~~iobase ~~multi port flag 79 * # ~ master device is sio1 80 * 2) device 81 * cd /dev; MAKEDEV ttyd0 ttyd1 .. 82 * 3) /etc/rc.serial 83 * 57600bps is too fast for sio0(internal8251) 84 * my ex. 85 * #set default speed 9600 86 * modem() 87 * : 88 * stty </dev/ttyid$i crtscts 9600 89 * : # ~~~~ default speed(can change after init.) 90 * modem 0 1 2 91 * 4) COMCONSOLE 92 * not changed. 93 * 5) PC9861K,PIO9032B,B98_01 94 * not tested. 95 */ 96/* 97 * modified for AIWA B98-01 98 * by T.Hatanou <hatanou@yasuda.comm.waseda.ac.jp> last update: 15 Sep.1995 99 * 100 * How to configure... 101 * # options COM_MULTIPORT # support for MICROCORE MC16550II 102 * ... comment-out this line, which will conflict with B98_01. 103 * options "B98_01" # support for AIWA B98-01 104 * device sio1 at nec? port 0x00d1 tty irq ? 105 * device sio2 at nec? port 0x00d5 tty irq ? 106 * ... you can leave these lines `irq ?', irq will be autodetected. 107 */ 108/* 109 * Modified by Y.Takahashi of Kogakuin University. 110 */ 111/* 112 * modified for 8251(FIFO) by Seigo TANIMURA <tanimura@FreeBSD.org> 113 */ 114 115#include <sys/param.h> 116#include <sys/systm.h> 117#include <sys/bus.h> 118#include <sys/conf.h> 119#include <sys/dkstat.h> 120#include <sys/fcntl.h> 121#include <sys/interrupt.h> 122#include <sys/kernel.h> 123#include <sys/lock.h> 124#include <sys/malloc.h> 125#include <sys/module.h> 126#include <sys/mutex.h> 127#include <sys/proc.h> 128#include <sys/reboot.h> 129#include <sys/sysctl.h> 130#include <sys/syslog.h> 131#include <sys/tty.h> 132#include <machine/bus.h> 133#include <sys/rman.h> 134#include <sys/timetc.h> 135#include <sys/timepps.h> 136 137#include <isa/isavar.h> 138 139#include <machine/limits.h> 140#include <machine/resource.h> 141 142#include <dev/sio/sioreg.h> 143#include <dev/sio/siovar.h> 144 145#ifdef PC98 146#include <pc98/pc98/pc98.h> 147#include <pc98/pc98/pc98_machdep.h> 148#endif 149 150#ifdef COM_ESP 151#include <dev/ic/esp.h> 152#endif 153#include <dev/ic/ns16550.h> 154#ifdef PC98 155#include <dev/ic/i8251.h> 156#include <dev/ic/rsa.h> 157#endif 158 159#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */ 160 161#define CALLOUT_MASK 0x80 162#define CONTROL_MASK 0x60 163#define CONTROL_INIT_STATE 0x20 164#define CONTROL_LOCK_STATE 0x40 165#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev))) 166#define MINOR_MAGIC_MASK (CALLOUT_MASK | CONTROL_MASK) 167#define MINOR_TO_UNIT(mynor) ((mynor) & ~MINOR_MAGIC_MASK) 168 169#ifdef COM_MULTIPORT 170/* checks in flags for multiport and which is multiport "master chip" 171 * for a given card 172 */ 173#define COM_ISMULTIPORT(flags) ((flags) & 0x01) 174#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff) 175#define COM_NOTAST4(flags) ((flags) & 0x04) 176#endif /* COM_MULTIPORT */ 177 178#define COM_CONSOLE(flags) ((flags) & 0x10) 179#define COM_FORCECONSOLE(flags) ((flags) & 0x20) 180#define COM_LLCONSOLE(flags) ((flags) & 0x40) 181#define COM_DEBUGGER(flags) ((flags) & 0x80) 182#define COM_LOSESOUTINTS(flags) ((flags) & 0x08) 183#define COM_NOFIFO(flags) ((flags) & 0x02) 184#define COM_ST16650A(flags) ((flags) & 0x20000) 185#define COM_C_NOPROBE (0x40000) 186#define COM_NOPROBE(flags) ((flags) & COM_C_NOPROBE) 187#define COM_C_IIR_TXRDYBUG (0x80000) 188#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG) 189#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24) 190 191#ifdef PC98 192#define com_emr com_msr /* Extension mode register for RSB-2000/3000 */ 193#endif 194#define com_scr 7 /* scratch register for 16450-16550 (R/W) */ 195 196#define sio_getreg(com, off) \ 197 (bus_space_read_1((com)->bst, (com)->bsh, (off))) 198#define sio_setreg(com, off, value) \ 199 (bus_space_write_1((com)->bst, (com)->bsh, (off), (value))) 200 201/* 202 * com state bits. 203 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher 204 * than the other bits so that they can be tested as a group without masking 205 * off the low bits. 206 * 207 * The following com and tty flags correspond closely: 208 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and 209 * comstop()) 210 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart()) 211 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam()) 212 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam()) 213 * TS_FLUSH is not used. 214 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON. 215 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state). 216 */ 217#define CS_BUSY 0x80 /* output in progress */ 218#define CS_TTGO 0x40 /* output not stopped by XOFF */ 219#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */ 220#define CS_CHECKMSR 1 /* check of MSR scheduled */ 221#define CS_CTS_OFLOW 2 /* use CTS output flow control */ 222#define CS_DTR_OFF 0x10 /* DTR held off */ 223#define CS_ODONE 4 /* output completed */ 224#define CS_RTS_IFLOW 8 /* use RTS input flow control */ 225#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */ 226 227static char const * const error_desc[] = { 228#define CE_OVERRUN 0 229 "silo overflow", 230#define CE_INTERRUPT_BUF_OVERFLOW 1 231 "interrupt-level buffer overflow", 232#define CE_TTY_BUF_OVERFLOW 2 233 "tty-level buffer overflow", 234}; 235 236#define CE_NTYPES 3 237#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum]) 238 239/* types. XXX - should be elsewhere */ 240typedef u_int Port_t; /* hardware port */ 241typedef u_char bool_t; /* boolean */ 242 243/* queue of linear buffers */ 244struct lbq { 245 u_char *l_head; /* next char to process */ 246 u_char *l_tail; /* one past the last char to process */ 247 struct lbq *l_next; /* next in queue */ 248 bool_t l_queued; /* nonzero if queued */ 249}; 250 251/* com device structure */ 252struct com_s { 253 u_int flags; /* Copy isa device flags */ 254 u_char state; /* miscellaneous flag bits */ 255 bool_t active_out; /* nonzero if the callout device is open */ 256 u_char cfcr_image; /* copy of value written to CFCR */ 257#ifdef COM_ESP 258 bool_t esp; /* is this unit a hayes esp board? */ 259#endif 260 u_char extra_state; /* more flag bits, separate for order trick */ 261 u_char fifo_image; /* copy of value written to FIFO */ 262 bool_t hasfifo; /* nonzero for 16550 UARTs */ 263 bool_t st16650a; /* Is a Startech 16650A or RTS/CTS compat */ 264 bool_t loses_outints; /* nonzero if device loses output interrupts */ 265 u_char mcr_image; /* copy of value written to MCR */ 266#ifdef COM_MULTIPORT 267 bool_t multiport; /* is this unit part of a multiport device? */ 268#endif /* COM_MULTIPORT */ 269 bool_t no_irq; /* nonzero if irq is not attached */ 270 bool_t gone; /* hardware disappeared */ 271 bool_t poll; /* nonzero if polling is required */ 272 bool_t poll_output; /* nonzero if polling for output is required */ 273 int unit; /* unit number */ 274 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */ 275 u_int tx_fifo_size; 276 u_int wopeners; /* # processes waiting for DCD in open() */ 277 278 /* 279 * The high level of the driver never reads status registers directly 280 * because there would be too many side effects to handle conveniently. 281 * Instead, it reads copies of the registers stored here by the 282 * interrupt handler. 283 */ 284 u_char last_modem_status; /* last MSR read by intr handler */ 285 u_char prev_modem_status; /* last MSR handled by high level */ 286 287 u_char hotchar; /* ldisc-specific char to be handled ASAP */ 288 u_char *ibuf; /* start of input buffer */ 289 u_char *ibufend; /* end of input buffer */ 290 u_char *ibufold; /* old input buffer, to be freed */ 291 u_char *ihighwater; /* threshold in input buffer */ 292 u_char *iptr; /* next free spot in input buffer */ 293 int ibufsize; /* size of ibuf (not include error bytes) */ 294 int ierroff; /* offset of error bytes in ibuf */ 295 296 struct lbq obufq; /* head of queue of output buffers */ 297 struct lbq obufs[2]; /* output buffers */ 298 299 bus_space_tag_t bst; 300 bus_space_handle_t bsh; 301 302#ifdef PC98 303 Port_t cmd_port; 304 Port_t sts_port; 305 Port_t in_modem_port; 306 Port_t intr_ctrl_port; 307 Port_t rsabase; /* iobase address of a I/O-DATA RSA board */ 308 int intr_enable; 309 int pc98_prev_modem_status; 310 int pc98_modem_delta; 311 int modem_car_chg_timer; 312 int pc98_prev_siocmd; 313 int pc98_prev_siomod; 314 int modem_checking; 315 int pc98_if_type; 316 317 bool_t pc98_8251fifo; 318 bool_t pc98_8251fifo_enable; 319#endif /* PC98 */ 320 Port_t data_port; /* i/o ports */ 321#ifdef COM_ESP 322 Port_t esp_port; 323#endif 324 Port_t int_id_port; 325 Port_t modem_ctl_port; 326 Port_t line_status_port; 327 Port_t modem_status_port; 328 Port_t intr_ctl_port; /* Ports of IIR register */ 329 330 struct tty *tp; /* cross reference */ 331 332 /* Initial state. */ 333 struct termios it_in; /* should be in struct tty */ 334 struct termios it_out; 335 336 /* Lock state. */ 337 struct termios lt_in; /* should be in struct tty */ 338 struct termios lt_out; 339 340 bool_t do_timestamp; 341 bool_t do_dcd_timestamp; 342 struct timeval timestamp; 343 struct timeval dcd_timestamp; 344 struct pps_state pps; 345 346 u_long bytes_in; /* statistics */ 347 u_long bytes_out; 348 u_int delta_error_counts[CE_NTYPES]; 349 u_long error_counts[CE_NTYPES]; 350 351 u_long rclk; 352 353 struct resource *irqres; 354 struct resource *ioportres; 355 void *cookie; 356 dev_t devs[6]; 357 358 /* 359 * Data area for output buffers. Someday we should build the output 360 * buffer queue without copying data. 361 */ 362#ifdef PC98 363 int obufsize; 364 u_char *obuf1; 365 u_char *obuf2; 366#else 367 u_char obuf1[256]; 368 u_char obuf2[256]; 369#endif 370}; 371 372#ifdef COM_ESP 373static int espattach(struct com_s *com, Port_t esp_port); 374#endif 375 376static timeout_t siobusycheck; 377static u_int siodivisor(u_long rclk, speed_t speed); 378static timeout_t siodtrwakeup; 379static void comhardclose(struct com_s *com); 380static void sioinput(struct com_s *com); 381static void siointr1(struct com_s *com); 382static void siointr(void *arg); 383static int commctl(struct com_s *com, int bits, int how); 384static int comparam(struct tty *tp, struct termios *t); 385static void siopoll(void *); 386static void siosettimeout(void); 387static int siosetwater(struct com_s *com, speed_t speed); 388static void comstart(struct tty *tp); 389static void comstop(struct tty *tp, int rw); 390static timeout_t comwakeup; 391static void disc_optim(struct tty *tp, struct termios *t, 392 struct com_s *com); 393 394char sio_driver_name[] = "sio"; 395static struct mtx sio_lock; 396static int sio_inited; 397 398/* table and macro for fast conversion from a unit number to its com struct */ 399devclass_t sio_devclass; 400#define com_addr(unit) ((struct com_s *) \ 401 devclass_get_softc(sio_devclass, unit)) /* XXX */ 402 403static d_open_t sioopen; 404static d_close_t sioclose; 405static d_read_t sioread; 406static d_write_t siowrite; 407static d_ioctl_t sioioctl; 408 409#define CDEV_MAJOR 28 410static struct cdevsw sio_cdevsw = { 411 /* open */ sioopen, 412 /* close */ sioclose, 413 /* read */ sioread, 414 /* write */ siowrite, 415 /* ioctl */ sioioctl, 416 /* poll */ ttypoll, 417 /* mmap */ nommap, 418 /* strategy */ nostrategy, 419 /* name */ sio_driver_name, 420 /* maj */ CDEV_MAJOR, 421 /* dump */ nodump, 422 /* psize */ nopsize, 423 /* flags */ D_TTY | D_KQFILTER, 424 /* kqfilter */ ttykqfilter, 425}; 426 427int comconsole = -1; 428static volatile speed_t comdefaultrate = CONSPEED; 429static u_long comdefaultrclk = DEFAULT_RCLK; 430SYSCTL_ULONG(_machdep, OID_AUTO, conrclk, CTLFLAG_RW, &comdefaultrclk, 0, ""); 431#ifdef __alpha__ 432static volatile speed_t gdbdefaultrate = CONSPEED; 433#endif 434static u_int com_events; /* input chars + weighted output completions */ 435static Port_t siocniobase; 436#ifndef __alpha__ 437static int siocnunit; 438#endif 439static Port_t siogdbiobase; 440static int siogdbunit = -1; 441static void *sio_slow_ih; 442static void *sio_fast_ih; 443static int sio_timeout; 444static int sio_timeouts_until_log; 445static struct callout_handle sio_timeout_handle 446 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle); 447static int sio_numunits; 448 449#ifdef PC98 450struct siodev { 451 short if_type; 452 short irq; 453 Port_t cmd, sts, ctrl, mod; 454}; 455static int sysclock; 456 457#define COM_INT_DISABLE {int previpri; previpri=spltty(); 458#define COM_INT_ENABLE splx(previpri);} 459#define IEN_TxFLAG IEN_Tx 460 461#define COM_CARRIER_DETECT_EMULATE 0 462#define PC98_CHECK_MODEM_INTERVAL (hz/10) 463#define DCD_OFF_TOLERANCE 2 464#define DCD_ON_RECOGNITION 2 465#define IS_8251(if_type) (!(if_type & 0x10)) 466#define COM1_EXT_CLOCK 0x40000 467 468static void commint(dev_t dev); 469static void com_tiocm_set(struct com_s *com, int msr); 470static void com_tiocm_bis(struct com_s *com, int msr); 471static void com_tiocm_bic(struct com_s *com, int msr); 472static int com_tiocm_get(struct com_s *com); 473static int com_tiocm_get_delta(struct com_s *com); 474static void pc98_msrint_start(dev_t dev); 475static void com_cflag_and_speed_set(struct com_s *com, int cflag, int speed); 476static int pc98_ttspeedtab(struct com_s *com, int speed, u_int *divisor); 477static int pc98_get_modem_status(struct com_s *com); 478static timeout_t pc98_check_msr; 479static void pc98_set_baud_rate(struct com_s *com, u_int count); 480static void pc98_i8251_reset(struct com_s *com, int mode, int command); 481static void pc98_disable_i8251_interrupt(struct com_s *com, int mod); 482static void pc98_enable_i8251_interrupt(struct com_s *com, int mod); 483static int pc98_check_i8251_interrupt(struct com_s *com); 484static int pc98_i8251_get_cmd(struct com_s *com); 485static int pc98_i8251_get_mod(struct com_s *com); 486static void pc98_i8251_set_cmd(struct com_s *com, int x); 487static void pc98_i8251_or_cmd(struct com_s *com, int x); 488static void pc98_i8251_clear_cmd(struct com_s *com, int x); 489static void pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x); 490static int pc98_check_if_type(device_t dev, struct siodev *iod); 491static int pc98_check_8251vfast(void); 492static int pc98_check_8251fifo(void); 493static void pc98_check_sysclock(void); 494static void pc98_set_ioport(struct com_s *com); 495 496#define com_int_Tx_disable(com) \ 497 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP) 498#define com_int_Tx_enable(com) \ 499 pc98_enable_i8251_interrupt(com,IEN_TxFLAG) 500#define com_int_Rx_disable(com) \ 501 pc98_disable_i8251_interrupt(com,IEN_Rx) 502#define com_int_Rx_enable(com) \ 503 pc98_enable_i8251_interrupt(com,IEN_Rx) 504#define com_int_TxRx_disable(com) \ 505 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP|IEN_Rx) 506#define com_int_TxRx_enable(com) \ 507 pc98_enable_i8251_interrupt(com,IEN_TxFLAG|IEN_Rx) 508#define com_send_break_on(com) \ 509 pc98_i8251_or_cmd(com,CMD8251_SBRK) 510#define com_send_break_off(com) \ 511 pc98_i8251_clear_cmd(com,CMD8251_SBRK) 512 513static struct speedtab pc98speedtab[] = { /* internal RS232C interface */ 514 { 0, 0, }, 515 { 50, 50, }, 516 { 75, 75, }, 517 { 150, 150, }, 518 { 200, 200, }, 519 { 300, 300, }, 520 { 600, 600, }, 521 { 1200, 1200, }, 522 { 2400, 2400, }, 523 { 4800, 4800, }, 524 { 9600, 9600, }, 525 { 19200, 19200, }, 526 { 38400, 38400, }, 527 { 51200, 51200, }, 528 { 76800, 76800, }, 529 { 20800, 20800, }, 530 { 31200, 31200, }, 531 { 41600, 41600, }, 532 { 62400, 62400, }, 533 { -1, -1 } 534}; 535static struct speedtab pc98fast_speedtab[] = { 536 { 9600, 0x80 | (DEFAULT_RCLK / (16 * (9600))), }, 537 { 19200, 0x80 | (DEFAULT_RCLK / (16 * (19200))), }, 538 { 38400, 0x80 | (DEFAULT_RCLK / (16 * (38400))), }, 539 { 57600, 0x80 | (DEFAULT_RCLK / (16 * (57600))), }, 540 { 115200, 0x80 | (DEFAULT_RCLK / (16 * (115200))), }, 541 { -1, -1 } 542}; 543static struct speedtab comspeedtab_pio9032b[] = { 544 { 300, 6, }, 545 { 600, 5, }, 546 { 1200, 4, }, 547 { 2400, 3, }, 548 { 4800, 2, }, 549 { 9600, 1, }, 550 { 19200, 0, }, 551 { 38400, 7, }, 552 { -1, -1 } 553}; 554static struct speedtab comspeedtab_b98_01[] = { 555 { 75, 11, }, 556 { 150, 10, }, 557 { 300, 9, }, 558 { 600, 8, }, 559 { 1200, 7, }, 560 { 2400, 6, }, 561 { 4800, 5, }, 562 { 9600, 4, }, 563 { 19200, 3, }, 564 { 38400, 2, }, 565 { 76800, 1, }, 566 { 153600, 0, }, 567 { -1, -1 } 568}; 569static struct speedtab comspeedtab_ind[] = { 570 { 300, 1536, }, 571 { 600, 768, }, 572 { 1200, 384, }, 573 { 2400, 192, }, 574 { 4800, 96, }, 575 { 9600, 48, }, 576 { 19200, 24, }, 577 { 38400, 12, }, 578 { 57600, 8, }, 579 { 115200, 4, }, 580 { 153600, 3, }, 581 { 230400, 2, }, 582 { 460800, 1, }, 583 { -1, -1 } 584}; 585 586struct { 587 char *name; 588 short port_table[7]; 589 short irr_mask; 590 struct speedtab *speedtab; 591 short check_irq; 592} if_8251_type[] = { 593 /* COM_IF_INTERNAL */ 594 { " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1}, 595 -1, pc98speedtab, 1 }, 596 /* COM_IF_PC9861K_1 */ 597 { " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1}, 598 3, NULL, 1 }, 599 /* COM_IF_PC9861K_2 */ 600 { " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1}, 601 3, NULL, 1 }, 602 /* COM_IF_IND_SS_1 */ 603 { " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1}, 604 3, comspeedtab_ind, 1 }, 605 /* COM_IF_IND_SS_2 */ 606 { " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1}, 607 3, comspeedtab_ind, 1 }, 608 /* COM_IF_PIO9032B_1 */ 609 { " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1}, 610 7, comspeedtab_pio9032b, 1 }, 611 /* COM_IF_PIO9032B_2 */ 612 { " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1}, 613 7, comspeedtab_pio9032b, 1 }, 614 /* COM_IF_B98_01_1 */ 615 { " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3}, 616 7, comspeedtab_b98_01, 0 }, 617 /* COM_IF_B98_01_2 */ 618 { " (B98-01)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xd5, 0xd7}, 619 7, comspeedtab_b98_01, 0 }, 620}; 621#define PC98SIO_data_port(type) (if_8251_type[type].port_table[0]) 622#define PC98SIO_cmd_port(type) (if_8251_type[type].port_table[1]) 623#define PC98SIO_sts_port(type) (if_8251_type[type].port_table[2]) 624#define PC98SIO_in_modem_port(type) (if_8251_type[type].port_table[3]) 625#define PC98SIO_intr_ctrl_port(type) (if_8251_type[type].port_table[4]) 626#define PC98SIO_baud_rate_port(type) (if_8251_type[type].port_table[5]) 627#define PC98SIO_func_port(type) (if_8251_type[type].port_table[6]) 628 629#define I8251F_data 0x130 630#define I8251F_lsr 0x132 631#define I8251F_msr 0x134 632#define I8251F_iir 0x136 633#define I8251F_fcr 0x138 634#define I8251F_div 0x13a 635 636 637static bus_addr_t port_table_0[] = 638 {0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007}; 639static bus_addr_t port_table_1[] = 640 {0x000, 0x002, 0x004, 0x006, 0x008, 0x00a, 0x00c, 0x00e}; 641static bus_addr_t port_table_8[] = 642 {0x000, 0x100, 0x200, 0x300, 0x400, 0x500, 0x600, 0x700}; 643static bus_addr_t port_table_rsa[] = { 644 0x008, 0x009, 0x00a, 0x00b, 0x00c, 0x00d, 0x00e, 0x00f, 645 0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007 646}; 647 648struct { 649 char *name; 650 short irr_read; 651 short irr_write; 652 bus_addr_t *iat; 653 bus_size_t iatsz; 654 u_long rclk; 655} if_16550a_type[] = { 656 /* COM_IF_RSA98 */ 657 {" (RSA-98)", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 658 /* COM_IF_NS16550 */ 659 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 660 /* COM_IF_SECOND_CCU */ 661 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 662 /* COM_IF_MC16550II */ 663 {" (MC16550II)", -1, 0x1000, port_table_8, IO_COMSIZE, 664 DEFAULT_RCLK * 4}, 665 /* COM_IF_MCRS98 */ 666 {" (MC-RS98)", -1, 0x1000, port_table_8, IO_COMSIZE, DEFAULT_RCLK * 4}, 667 /* COM_IF_RSB3000 */ 668 {" (RSB-3000)", 0xbf, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 10}, 669 /* COM_IF_RSB384 */ 670 {" (RSB-384)", 0xbf, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 10}, 671 /* COM_IF_MODEM_CARD */ 672 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 673 /* COM_IF_RSA98III */ 674 {" (RSA-98III)", -1, -1, port_table_rsa, 16, DEFAULT_RCLK * 8}, 675 /* COM_IF_ESP98 */ 676 {" (ESP98)", -1, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 4}, 677}; 678#endif /* PC98 */ 679 680#ifdef COM_ESP 681#ifdef PC98 682 683/* XXX configure this properly. */ 684/* XXX quite broken for new-bus. */ 685static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 }; 686static Port_t likely_esp_ports[] = { 0xc0d0, 0 }; 687 688#define ESP98_CMD1 (ESP_CMD1 * 0x100) 689#define ESP98_CMD2 (ESP_CMD2 * 0x100) 690#define ESP98_STATUS1 (ESP_STATUS1 * 0x100) 691#define ESP98_STATUS2 (ESP_STATUS2 * 0x100) 692 693#else /* PC98 */ 694 695/* XXX configure this properly. */ 696static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, }; 697static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 }; 698 699#endif /* PC98 */ 700#endif 701 702/* 703 * handle sysctl read/write requests for console speed 704 * 705 * In addition to setting comdefaultrate for I/O through /dev/console, 706 * also set the initial and lock values for the /dev/ttyXX device 707 * if there is one associated with the console. Finally, if the /dev/tty 708 * device has already been open, change the speed on the open running port 709 * itself. 710 */ 711 712static int 713sysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS) 714{ 715 int error, s; 716 speed_t newspeed; 717 struct com_s *com; 718 struct tty *tp; 719 720 newspeed = comdefaultrate; 721 722 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req); 723 if (error || !req->newptr) 724 return (error); 725 726 comdefaultrate = newspeed; 727 728 if (comconsole < 0) /* serial console not selected? */ 729 return (0); 730 731 com = com_addr(comconsole); 732 if (com == NULL) 733 return (ENXIO); 734 735 /* 736 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX 737 * (note, the lock rates really are boolean -- if non-zero, disallow 738 * speed changes) 739 */ 740 com->it_in.c_ispeed = com->it_in.c_ospeed = 741 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 742 com->it_out.c_ispeed = com->it_out.c_ospeed = 743 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate; 744 745 /* 746 * if we're open, change the running rate too 747 */ 748 tp = com->tp; 749 if (tp && (tp->t_state & TS_ISOPEN)) { 750 tp->t_termios.c_ispeed = 751 tp->t_termios.c_ospeed = comdefaultrate; 752 s = spltty(); 753 error = comparam(tp, &tp->t_termios); 754 splx(s); 755 } 756 return error; 757} 758 759SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW, 760 0, 0, sysctl_machdep_comdefaultrate, "I", ""); 761 762/* 763 * Unload the driver and clear the table. 764 * XXX this is mostly wrong. 765 * XXX TODO: 766 * This is usually called when the card is ejected, but 767 * can be caused by a modunload of a controller driver. 768 * The idea is to reset the driver's view of the device 769 * and ensure that any driver entry points such as 770 * read and write do not hang. 771 */ 772int 773siodetach(dev) 774 device_t dev; 775{ 776 struct com_s *com; 777 int i; 778 779 com = (struct com_s *) device_get_softc(dev); 780 if (com == NULL) { 781 device_printf(dev, "NULL com in siounload\n"); 782 return (0); 783 } 784 com->gone = 1; 785 for (i = 0 ; i < 6; i++) 786 destroy_dev(com->devs[i]); 787 if (com->irqres) { 788 bus_teardown_intr(dev, com->irqres, com->cookie); 789 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres); 790 } 791 if (com->ioportres) 792 bus_release_resource(dev, SYS_RES_IOPORT, 0, com->ioportres); 793 if (com->tp && (com->tp->t_state & TS_ISOPEN)) { 794 device_printf(dev, "still open, forcing close\n"); 795 (*linesw[com->tp->t_line].l_close)(com->tp, 0); 796 com->tp->t_gen++; 797 ttyclose(com->tp); 798 ttwakeup(com->tp); 799 ttwwakeup(com->tp); 800 } else { 801 if (com->ibuf != NULL) 802 free(com->ibuf, M_DEVBUF); 803#ifdef PC98 804 if (com->obuf1 != NULL) 805 free(com->obuf1, M_DEVBUF); 806#endif 807 device_set_softc(dev, NULL); 808 free(com, M_DEVBUF); 809 } 810 return (0); 811} 812 813int 814sioprobe(dev, xrid, rclk, noprobe) 815 device_t dev; 816 int xrid; 817 u_long rclk; 818 int noprobe; 819{ 820#if 0 821 static bool_t already_init; 822 device_t xdev; 823#endif 824 struct com_s *com; 825 u_int divisor; 826 bool_t failures[10]; 827 int fn; 828 device_t idev; 829 Port_t iobase; 830 intrmask_t irqmap[4]; 831 intrmask_t irqs; 832 u_char mcr_image; 833 int result; 834 u_long xirq; 835 u_int flags = device_get_flags(dev); 836 int rid; 837 struct resource *port; 838#ifdef PC98 839 int tmp; 840 struct siodev iod; 841#endif 842 843#ifdef PC98 844 iod.if_type = GET_IFTYPE(flags); 845 if ((iod.if_type < 0 || iod.if_type > COM_IF_END1) && 846 (iod.if_type < 0x10 || iod.if_type > COM_IF_END2)) 847 return ENXIO; 848#endif 849 850 rid = xrid; 851#ifdef PC98 852 if (IS_8251(iod.if_type)) { 853 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 854 0, ~0, 1, RF_ACTIVE); 855 } else if (iod.if_type == COM_IF_MODEM_CARD || 856 iod.if_type == COM_IF_RSA98III || 857 isa_get_vendorid(dev)) { 858 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 859 if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE); 860 } else { 861 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, 862 if_16550a_type[iod.if_type & 0x0f].iat, 863 if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE); 864 } 865#else 866 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 867 0, ~0, IO_COMSIZE, RF_ACTIVE); 868#endif 869 if (!port) 870 return (ENXIO); 871#ifdef PC98 872 if (!IS_8251(iod.if_type)) { 873 if (isa_load_resourcev(port, 874 if_16550a_type[iod.if_type & 0x0f].iat, 875 if_16550a_type[iod.if_type & 0x0f].iatsz) != 0) { 876 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 877 return ENXIO; 878 } 879 } 880#endif 881 882 com = malloc(sizeof(*com), M_DEVBUF, M_NOWAIT | M_ZERO); 883 if (com == NULL) 884 return (ENOMEM); 885 device_set_softc(dev, com); 886 com->bst = rman_get_bustag(port); 887 com->bsh = rman_get_bushandle(port); 888#ifdef PC98 889 if (!IS_8251(iod.if_type) && rclk == 0) 890 rclk = if_16550a_type[iod.if_type & 0x0f].rclk; 891#else 892 if (rclk == 0) 893 rclk = DEFAULT_RCLK; 894#endif 895 com->rclk = rclk; 896 897 while (sio_inited != 2) 898 if (atomic_cmpset_int(&sio_inited, 0, 1)) { 899 mtx_init(&sio_lock, sio_driver_name, NULL, 900 (comconsole != -1) ? 901 MTX_SPIN | MTX_QUIET : MTX_SPIN); 902 atomic_store_rel_int(&sio_inited, 2); 903 } 904 905#if 0 906 /* 907 * XXX this is broken - when we are first called, there are no 908 * previously configured IO ports. We could hard code 909 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse. 910 * This code has been doing nothing since the conversion since 911 * "count" is zero the first time around. 912 */ 913 if (!already_init) { 914 /* 915 * Turn off MCR_IENABLE for all likely serial ports. An unused 916 * port with its MCR_IENABLE gate open will inhibit interrupts 917 * from any used port that shares the interrupt vector. 918 * XXX the gate enable is elsewhere for some multiports. 919 */ 920 device_t *devs; 921 int count, i, xioport; 922#ifdef PC98 923 int xiftype; 924#endif 925 926 devclass_get_devices(sio_devclass, &devs, &count); 927#ifdef PC98 928 for (i = 0; i < count; i++) { 929 xdev = devs[i]; 930 xioport = bus_get_resource_start(xdev, SYS_RES_IOPORT, 0); 931 xiftype = GET_IFTYPE(device_get_flags(xdev)); 932 if (device_is_enabled(xdev) && xioport > 0) { 933 if (IS_8251(xiftype)) 934 outb((xioport & 0xff00) | PC98SIO_cmd_port(xiftype & 0x0f), 0xf2); 935 else 936 outb(xioport + if_16550a_type[xiftype & 0x0f].iat[com_mcr], 0); 937 } 938 } 939#else 940 for (i = 0; i < count; i++) { 941 xdev = devs[i]; 942 if (device_is_enabled(xdev) && 943 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport, 944 NULL) == 0) 945 outb(xioport + com_mcr, 0); 946 } 947#endif 948 free(devs, M_TEMP); 949 already_init = TRUE; 950 } 951#endif 952 953 if (COM_LLCONSOLE(flags)) { 954 printf("sio%d: reserved for low-level i/o\n", 955 device_get_unit(dev)); 956 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 957 device_set_softc(dev, NULL); 958 free(com, M_DEVBUF); 959 return (ENXIO); 960 } 961 962#ifdef PC98 963 DELAY(10); 964 965 /* 966 * If the port is i8251 UART (internal, B98_01) 967 */ 968 if (pc98_check_if_type(dev, &iod) == -1) { 969 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 970 device_set_softc(dev, NULL); 971 free(com, M_DEVBUF); 972 return (ENXIO); 973 } 974 if (iod.irq > 0) 975 bus_set_resource(dev, SYS_RES_IRQ, 0, iod.irq, 1); 976 if (IS_8251(iod.if_type)) { 977 outb(iod.cmd, 0); 978 DELAY(10); 979 outb(iod.cmd, 0); 980 DELAY(10); 981 outb(iod.cmd, 0); 982 DELAY(10); 983 outb(iod.cmd, CMD8251_RESET); 984 DELAY(1000); /* for a while...*/ 985 outb(iod.cmd, 0xf2); /* MODE (dummy) */ 986 DELAY(10); 987 outb(iod.cmd, 0x01); /* CMD (dummy) */ 988 DELAY(1000); /* for a while...*/ 989 if (( inb(iod.sts) & STS8251_TxEMP ) == 0 ) { 990 result = (ENXIO); 991 } 992 if (if_8251_type[iod.if_type & 0x0f].check_irq) { 993 COM_INT_DISABLE 994 tmp = ( inb( iod.ctrl ) & ~(IEN_Rx|IEN_TxEMP|IEN_Tx)); 995 outb( iod.ctrl, tmp|IEN_TxEMP ); 996 DELAY(10); 997 result = isa_irq_pending() ? 0 : ENXIO; 998 outb( iod.ctrl, tmp ); 999 COM_INT_ENABLE 1000 } else { 1001 /* 1002 * B98_01 doesn't activate TxEMP interrupt line 1003 * when being reset, so we can't check irq pending. 1004 */ 1005 result = 0; 1006 } 1007 if (epson_machine_id==0x20) { /* XXX */ 1008 result = 0; 1009 } 1010 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1011 if (result) { 1012 device_set_softc(dev, NULL); 1013 free(com, M_DEVBUF); 1014 } 1015 return result; 1016 } 1017#endif /* PC98 */ 1018 /* 1019 * If the device is on a multiport card and has an AST/4 1020 * compatible interrupt control register, initialize this 1021 * register and prepare to leave MCR_IENABLE clear in the mcr. 1022 * Otherwise, prepare to set MCR_IENABLE in the mcr. 1023 * Point idev to the device struct giving the correct id_irq. 1024 * This is the struct for the master device if there is one. 1025 */ 1026 idev = dev; 1027 mcr_image = MCR_IENABLE; 1028#ifdef COM_MULTIPORT 1029 if (COM_ISMULTIPORT(flags)) { 1030#ifndef PC98 1031 Port_t xiobase; 1032 u_long io; 1033#endif 1034 1035 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags)); 1036 if (idev == NULL) { 1037 printf("sio%d: master device %d not configured\n", 1038 device_get_unit(dev), COM_MPMASTER(flags)); 1039 idev = dev; 1040 } 1041#ifndef PC98 1042 if (!COM_NOTAST4(flags)) { 1043 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io, 1044 NULL) == 0) { 1045 xiobase = io; 1046 if (bus_get_resource(idev, SYS_RES_IRQ, 0, 1047 NULL, NULL) == 0) 1048 outb(xiobase + com_scr, 0x80); 1049 else 1050 outb(xiobase + com_scr, 0); 1051 } 1052 mcr_image = 0; 1053 } 1054#endif 1055 } 1056#endif /* COM_MULTIPORT */ 1057 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0) 1058 mcr_image = 0; 1059 1060 bzero(failures, sizeof failures); 1061 iobase = rman_get_start(port); 1062 1063#ifdef PC98 1064 if (iod.if_type == COM_IF_RSA98III) { 1065 mcr_image = 0; 1066 1067 outb(iobase + rsa_msr, 0x04); 1068 outb(iobase + rsa_frr, 0x00); 1069 if ((inb(iobase + rsa_srr) & 0x36) != 0x36) { 1070 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1071 device_set_softc(dev, NULL); 1072 free(com, M_DEVBUF); 1073 return (ENXIO); 1074 } 1075 outb(iobase + rsa_ier, 0x00); 1076 outb(iobase + rsa_frr, 0x00); 1077 outb(iobase + rsa_tivsr, 0x00); 1078 outb(iobase + rsa_tcr, 0x00); 1079 } 1080 1081 tmp = if_16550a_type[iod.if_type & 0x0f].irr_write; 1082 if (tmp != -1) { 1083 /* MC16550II */ 1084 int irqout; 1085 switch (isa_get_irq(idev)) { 1086 case 3: irqout = 4; break; 1087 case 5: irqout = 5; break; 1088 case 6: irqout = 6; break; 1089 case 12: irqout = 7; break; 1090 default: 1091 printf("sio%d: irq configuration error\n", 1092 device_get_unit(dev)); 1093 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1094 device_set_softc(dev, NULL); 1095 free(com, M_DEVBUF); 1096 return (ENXIO); 1097 } 1098 outb((iobase & 0x00ff) | tmp, irqout); 1099 } 1100#endif 1101 1102 /* 1103 * We don't want to get actual interrupts, just masked ones. 1104 * Interrupts from this line should already be masked in the ICU, 1105 * but mask them in the processor as well in case there are some 1106 * (misconfigured) shared interrupts. 1107 */ 1108 mtx_lock_spin(&sio_lock); 1109/* EXTRA DELAY? */ 1110 1111 /* 1112 * Initialize the speed and the word size and wait long enough to 1113 * drain the maximum of 16 bytes of junk in device output queues. 1114 * The speed is undefined after a master reset and must be set 1115 * before relying on anything related to output. There may be 1116 * junk after a (very fast) soft reboot and (apparently) after 1117 * master reset. 1118 * XXX what about the UART bug avoided by waiting in comparam()? 1119 * We don't want to to wait long enough to drain at 2 bps. 1120 */ 1121 if (iobase == siocniobase) 1122 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10)); 1123 else { 1124 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS); 1125 divisor = siodivisor(rclk, SIO_TEST_SPEED); 1126 sio_setreg(com, com_dlbl, divisor & 0xff); 1127 sio_setreg(com, com_dlbh, divisor >> 8); 1128 sio_setreg(com, com_cfcr, CFCR_8BITS); 1129 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10)); 1130 } 1131 1132 /* 1133 * Enable the interrupt gate and disable device interupts. This 1134 * should leave the device driving the interrupt line low and 1135 * guarantee an edge trigger if an interrupt can be generated. 1136 */ 1137/* EXTRA DELAY? */ 1138 sio_setreg(com, com_mcr, mcr_image); 1139 sio_setreg(com, com_ier, 0); 1140 DELAY(1000); /* XXX */ 1141 irqmap[0] = isa_irq_pending(); 1142 1143 /* 1144 * Attempt to set loopback mode so that we can send a null byte 1145 * without annoying any external device. 1146 */ 1147/* EXTRA DELAY? */ 1148 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK); 1149 1150 /* 1151 * Attempt to generate an output interrupt. On 8250's, setting 1152 * IER_ETXRDY generates an interrupt independent of the current 1153 * setting and independent of whether the THR is empty. On 16450's, 1154 * setting IER_ETXRDY generates an interrupt independent of the 1155 * current setting. On 16550A's, setting IER_ETXRDY only 1156 * generates an interrupt when IER_ETXRDY is not already set. 1157 */ 1158 sio_setreg(com, com_ier, IER_ETXRDY); 1159#ifdef PC98 1160 if (iod.if_type == COM_IF_RSA98III) 1161 outb(iobase + rsa_ier, 0x04); 1162#endif 1163 1164 /* 1165 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate 1166 * an interrupt. They'd better generate one for actually doing 1167 * output. Loopback may be broken on the same incompatibles but 1168 * it's unlikely to do more than allow the null byte out. 1169 */ 1170 sio_setreg(com, com_data, 0); 1171 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10)); 1172 1173 /* 1174 * Turn off loopback mode so that the interrupt gate works again 1175 * (MCR_IENABLE was hidden). This should leave the device driving 1176 * an interrupt line high. It doesn't matter if the interrupt 1177 * line oscillates while we are not looking at it, since interrupts 1178 * are disabled. 1179 */ 1180/* EXTRA DELAY? */ 1181 sio_setreg(com, com_mcr, mcr_image); 1182 1183 /* 1184 * It seems my Xircom CBEM56G Cardbus modem wants to be reset 1185 * to 8 bits *again*, or else probe test 0 will fail. 1186 * gwk@sgi.com, 4/19/2001 1187 */ 1188 sio_setreg(com, com_cfcr, CFCR_8BITS); 1189 1190 /* 1191 * Some pcmcia cards have the "TXRDY bug", so we check everyone 1192 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... ) 1193 */ 1194 if (noprobe) { 1195 /* Reading IIR register twice */ 1196 for (fn = 0; fn < 2; fn ++) { 1197 DELAY(10000); 1198 failures[6] = sio_getreg(com, com_iir); 1199 } 1200 /* Check IIR_TXRDY clear ? */ 1201 result = 0; 1202 if (failures[6] & IIR_TXRDY) { 1203 /* No, Double check with clearing IER */ 1204 sio_setreg(com, com_ier, 0); 1205 if (sio_getreg(com, com_iir) & IIR_NOPEND) { 1206 /* Ok. We discovered TXRDY bug! */ 1207 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); 1208 } else { 1209 /* Unknown, Just omit this chip.. XXX */ 1210 result = ENXIO; 1211 sio_setreg(com, com_mcr, 0); 1212 } 1213 } else { 1214 /* OK. this is well-known guys */ 1215 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); 1216 } 1217 sio_setreg(com, com_ier, 0); 1218 sio_setreg(com, com_cfcr, CFCR_8BITS); 1219 mtx_unlock_spin(&sio_lock); 1220 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1221 if (iobase == siocniobase) 1222 result = 0; 1223 if (result != 0) { 1224 device_set_softc(dev, NULL); 1225 free(com, M_DEVBUF); 1226 } 1227 return (result); 1228 } 1229 1230 /* 1231 * Check that 1232 * o the CFCR, IER and MCR in UART hold the values written to them 1233 * (the values happen to be all distinct - this is good for 1234 * avoiding false positive tests from bus echoes). 1235 * o an output interrupt is generated and its vector is correct. 1236 * o the interrupt goes away when the IIR in the UART is read. 1237 */ 1238/* EXTRA DELAY? */ 1239 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS; 1240 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY; 1241 failures[2] = sio_getreg(com, com_mcr) - mcr_image; 1242 DELAY(10000); /* Some internal modems need this time */ 1243 irqmap[1] = isa_irq_pending(); 1244 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY; 1245#ifdef PC98 1246 if (iod.if_type == COM_IF_RSA98III) 1247 inb(iobase + rsa_srr); 1248#endif 1249 DELAY(1000); /* XXX */ 1250 irqmap[2] = isa_irq_pending(); 1251 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 1252#ifdef PC98 1253 if (iod.if_type == COM_IF_RSA98III) 1254 inb(iobase + rsa_srr); 1255#endif 1256 1257 /* 1258 * Turn off all device interrupts and check that they go off properly. 1259 * Leave MCR_IENABLE alone. For ports without a master port, it gates 1260 * the OUT2 output of the UART to 1261 * the ICU input. Closing the gate would give a floating ICU input 1262 * (unless there is another device driving it) and spurious interrupts. 1263 * (On the system that this was first tested on, the input floats high 1264 * and gives a (masked) interrupt as soon as the gate is closed.) 1265 */ 1266 sio_setreg(com, com_ier, 0); 1267 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */ 1268 failures[7] = sio_getreg(com, com_ier); 1269#ifdef PC98 1270 if (iod.if_type == COM_IF_RSA98III) 1271 outb(iobase + rsa_ier, 0x00); 1272#endif 1273 DELAY(1000); /* XXX */ 1274 irqmap[3] = isa_irq_pending(); 1275 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 1276#ifdef PC98 1277 if (iod.if_type == COM_IF_RSA98III) { 1278 inb(iobase + rsa_srr); 1279 outb(iobase + rsa_frr, 0x00); 1280 } 1281#endif 1282 1283 mtx_unlock_spin(&sio_lock); 1284 1285 irqs = irqmap[1] & ~irqmap[0]; 1286 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 && 1287 ((1 << xirq) & irqs) == 0) { 1288 printf( 1289 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n", 1290 device_get_unit(dev), xirq, irqs); 1291 printf( 1292 "sio%d: port may not be enabled\n", 1293 device_get_unit(dev)); 1294 } 1295 if (bootverbose) 1296 printf("sio%d: irq maps: %#x %#x %#x %#x\n", 1297 device_get_unit(dev), 1298 irqmap[0], irqmap[1], irqmap[2], irqmap[3]); 1299 1300 result = 0; 1301 for (fn = 0; fn < sizeof failures; ++fn) 1302 if (failures[fn]) { 1303 sio_setreg(com, com_mcr, 0); 1304 result = ENXIO; 1305 if (bootverbose) { 1306 printf("sio%d: probe failed test(s):", 1307 device_get_unit(dev)); 1308 for (fn = 0; fn < sizeof failures; ++fn) 1309 if (failures[fn]) 1310 printf(" %d", fn); 1311 printf("\n"); 1312 } 1313 break; 1314 } 1315 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1316 if (iobase == siocniobase) 1317 result = 0; 1318 if (result != 0) { 1319 device_set_softc(dev, NULL); 1320 free(com, M_DEVBUF); 1321 } 1322 return (result); 1323} 1324 1325#ifdef COM_ESP 1326static int 1327espattach(com, esp_port) 1328 struct com_s *com; 1329 Port_t esp_port; 1330{ 1331 u_char dips; 1332 u_char val; 1333 1334 /* 1335 * Check the ESP-specific I/O port to see if we're an ESP 1336 * card. If not, return failure immediately. 1337 */ 1338 if ((inb(esp_port) & 0xf3) == 0) { 1339 printf(" port 0x%x is not an ESP board?\n", esp_port); 1340 return (0); 1341 } 1342 1343 /* 1344 * We've got something that claims to be a Hayes ESP card. 1345 * Let's hope so. 1346 */ 1347 1348 /* Get the dip-switch configuration */ 1349#ifdef PC98 1350 outb(esp_port + ESP98_CMD1, ESP_GETDIPS); 1351 dips = inb(esp_port + ESP98_STATUS1); 1352#else 1353 outb(esp_port + ESP_CMD1, ESP_GETDIPS); 1354 dips = inb(esp_port + ESP_STATUS1); 1355#endif 1356 1357 /* 1358 * Bits 0,1 of dips say which COM port we are. 1359 */ 1360#ifdef PC98 1361 if ((rman_get_start(com->ioportres) & 0xff) == 1362 likely_com_ports[dips & 0x03]) 1363#else 1364 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03]) 1365#endif 1366 printf(" : ESP"); 1367 else { 1368 printf(" esp_port has com %d\n", dips & 0x03); 1369 return (0); 1370 } 1371 1372 /* 1373 * Check for ESP version 2.0 or later: bits 4,5,6 = 010. 1374 */ 1375#ifdef PC98 1376 outb(esp_port + ESP98_CMD1, ESP_GETTEST); 1377 val = inb(esp_port + ESP98_STATUS1); /* clear reg 1 */ 1378 val = inb(esp_port + ESP98_STATUS2); 1379#else 1380 outb(esp_port + ESP_CMD1, ESP_GETTEST); 1381 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */ 1382 val = inb(esp_port + ESP_STATUS2); 1383#endif 1384 if ((val & 0x70) < 0x20) { 1385 printf("-old (%o)", val & 0x70); 1386 return (0); 1387 } 1388 1389 /* 1390 * Check for ability to emulate 16550: bit 7 == 1 1391 */ 1392 if ((dips & 0x80) == 0) { 1393 printf(" slave"); 1394 return (0); 1395 } 1396 1397 /* 1398 * Okay, we seem to be a Hayes ESP card. Whee. 1399 */ 1400 com->esp = TRUE; 1401 com->esp_port = esp_port; 1402 return (1); 1403} 1404#endif /* COM_ESP */ 1405 1406int 1407sioattach(dev, xrid, rclk) 1408 device_t dev; 1409 int xrid; 1410 u_long rclk; 1411{ 1412 struct com_s *com; 1413#ifdef COM_ESP 1414 Port_t *espp; 1415#endif 1416 Port_t iobase; 1417 int unit; 1418 u_int flags; 1419 int rid; 1420 struct resource *port; 1421 int ret; 1422#ifdef PC98 1423 u_char *obuf; 1424 u_long obufsize; 1425 int if_type = GET_IFTYPE(device_get_flags(dev)); 1426#endif 1427 1428 rid = xrid; 1429#ifdef PC98 1430 if (IS_8251(if_type)) { 1431 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1432 0, ~0, 1, RF_ACTIVE); 1433 } else if (if_type == COM_IF_MODEM_CARD || 1434 if_type == COM_IF_RSA98III || 1435 isa_get_vendorid(dev)) { 1436 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 1437 if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE); 1438 } else { 1439 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, 1440 if_16550a_type[if_type & 0x0f].iat, 1441 if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE); 1442 } 1443#else 1444 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1445 0, ~0, IO_COMSIZE, RF_ACTIVE); 1446#endif 1447 if (!port) 1448 return (ENXIO); 1449#ifdef PC98 1450 if (!IS_8251(if_type)) { 1451 if (isa_load_resourcev(port, 1452 if_16550a_type[if_type & 0x0f].iat, 1453 if_16550a_type[if_type & 0x0f].iatsz) != 0) { 1454 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1455 return ENXIO; 1456 } 1457 } 1458#endif 1459 1460 iobase = rman_get_start(port); 1461 unit = device_get_unit(dev); 1462 com = device_get_softc(dev); 1463 flags = device_get_flags(dev); 1464 1465 if (unit >= sio_numunits) 1466 sio_numunits = unit + 1; 1467 1468#ifdef PC98 1469 obufsize = 256; 1470 if (if_type == COM_IF_RSA98III) 1471 obufsize = 2048; 1472 if ((obuf = malloc(obufsize * 2, M_DEVBUF, M_NOWAIT)) == NULL) { 1473 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1474 return ENXIO; 1475 } 1476 bzero(obuf, obufsize * 2); 1477#endif 1478 1479 /* 1480 * sioprobe() has initialized the device registers as follows: 1481 * o cfcr = CFCR_8BITS. 1482 * It is most important that CFCR_DLAB is off, so that the 1483 * data port is not hidden when we enable interrupts. 1484 * o ier = 0. 1485 * Interrupts are only enabled when the line is open. 1486 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible 1487 * interrupt control register or the config specifies no irq. 1488 * Keeping MCR_DTR and MCR_RTS off might stop the external 1489 * device from sending before we are ready. 1490 */ 1491 bzero(com, sizeof *com); 1492 com->unit = unit; 1493 com->ioportres = port; 1494 com->bst = rman_get_bustag(port); 1495 com->bsh = rman_get_bushandle(port); 1496 com->cfcr_image = CFCR_8BITS; 1497 com->dtr_wait = 3 * hz; 1498 com->loses_outints = COM_LOSESOUTINTS(flags) != 0; 1499 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0; 1500 com->tx_fifo_size = 1; 1501#ifdef PC98 1502 com->obufsize = obufsize; 1503 com->obuf1 = obuf; 1504 com->obuf2 = obuf + obufsize; 1505#endif 1506 com->obufs[0].l_head = com->obuf1; 1507 com->obufs[1].l_head = com->obuf2; 1508 1509#ifdef PC98 1510 com->pc98_if_type = if_type; 1511 1512 if (IS_8251(if_type)) { 1513 pc98_set_ioport(com); 1514 1515 if (if_type == COM_IF_INTERNAL && pc98_check_8251fifo()) { 1516 com->pc98_8251fifo = 1; 1517 com->pc98_8251fifo_enable = 0; 1518 } 1519 } else { 1520 bus_addr_t *iat = if_16550a_type[if_type & 0x0f].iat; 1521 1522 com->data_port = iobase + iat[com_data]; 1523 com->int_id_port = iobase + iat[com_iir]; 1524 com->modem_ctl_port = iobase + iat[com_mcr]; 1525 com->mcr_image = inb(com->modem_ctl_port); 1526 com->line_status_port = iobase + iat[com_lsr]; 1527 com->modem_status_port = iobase + iat[com_msr]; 1528 com->intr_ctl_port = iobase + iat[com_ier]; 1529 } 1530#else /* not PC98 */ 1531 com->data_port = iobase + com_data; 1532 com->int_id_port = iobase + com_iir; 1533 com->modem_ctl_port = iobase + com_mcr; 1534 com->mcr_image = inb(com->modem_ctl_port); 1535 com->line_status_port = iobase + com_lsr; 1536 com->modem_status_port = iobase + com_msr; 1537 com->intr_ctl_port = iobase + com_ier; 1538#endif 1539 1540#ifdef PC98 1541 if (!IS_8251(if_type) && rclk == 0) 1542 rclk = if_16550a_type[if_type & 0x0f].rclk; 1543#else 1544 if (rclk == 0) 1545 rclk = DEFAULT_RCLK; 1546#endif 1547 com->rclk = rclk; 1548 1549 /* 1550 * We don't use all the flags from <sys/ttydefaults.h> since they 1551 * are only relevant for logins. It's important to have echo off 1552 * initially so that the line doesn't start blathering before the 1553 * echo flag can be turned off. 1554 */ 1555 com->it_in.c_iflag = 0; 1556 com->it_in.c_oflag = 0; 1557 com->it_in.c_cflag = TTYDEF_CFLAG; 1558 com->it_in.c_lflag = 0; 1559 if (unit == comconsole) { 1560#ifdef PC98 1561 if (IS_8251(com->pc98_if_type)) 1562 DELAY(100000); 1563#endif 1564 com->it_in.c_iflag = TTYDEF_IFLAG; 1565 com->it_in.c_oflag = TTYDEF_OFLAG; 1566 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL; 1567 com->it_in.c_lflag = TTYDEF_LFLAG; 1568 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL; 1569 com->lt_out.c_ispeed = com->lt_out.c_ospeed = 1570 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 1571 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate; 1572 } else 1573 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED; 1574 if (siosetwater(com, com->it_in.c_ispeed) != 0) { 1575 mtx_unlock_spin(&sio_lock); 1576 /* 1577 * Leave i/o resources allocated if this is a `cn'-level 1578 * console, so that other devices can't snarf them. 1579 */ 1580 if (iobase != siocniobase) 1581 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1582 return (ENOMEM); 1583 } 1584 mtx_unlock_spin(&sio_lock); 1585 termioschars(&com->it_in); 1586 com->it_out = com->it_in; 1587 1588 /* attempt to determine UART type */ 1589 printf("sio%d: type", unit); 1590 1591 1592#ifndef PC98 1593#ifdef COM_MULTIPORT 1594 if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags)) 1595#else 1596 if (!COM_IIR_TXRDYBUG(flags)) 1597#endif 1598 { 1599 u_char scr; 1600 u_char scr1; 1601 u_char scr2; 1602 1603 scr = sio_getreg(com, com_scr); 1604 sio_setreg(com, com_scr, 0xa5); 1605 scr1 = sio_getreg(com, com_scr); 1606 sio_setreg(com, com_scr, 0x5a); 1607 scr2 = sio_getreg(com, com_scr); 1608 sio_setreg(com, com_scr, scr); 1609 if (scr1 != 0xa5 || scr2 != 0x5a) { 1610 printf(" 8250 or not responding"); 1611 goto determined_type; 1612 } 1613 } 1614#endif /* !PC98 */ 1615#ifdef PC98 1616 if (IS_8251(com->pc98_if_type)) { 1617 if (com->pc98_8251fifo && !COM_NOFIFO(flags)) 1618 com->tx_fifo_size = 16; 1619 com_int_TxRx_disable( com ); 1620 com_cflag_and_speed_set( com, com->it_in.c_cflag, comdefaultrate ); 1621 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE ); 1622 com_send_break_off( com ); 1623 1624 if (com->pc98_if_type == COM_IF_INTERNAL) { 1625 printf(" (internal%s%s)", 1626 com->pc98_8251fifo ? " fifo" : "", 1627 PC98SIO_baud_rate_port(com->pc98_if_type) != -1 ? 1628 " v-fast" : ""); 1629 } else { 1630 printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name); 1631 } 1632 } else { 1633#endif /* PC98 */ 1634 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH); 1635 DELAY(100); 1636 com->st16650a = 0; 1637 switch (inb(com->int_id_port) & IIR_FIFO_MASK) { 1638 case FIFO_RX_LOW: 1639 printf(" 16450"); 1640 break; 1641 case FIFO_RX_MEDL: 1642 printf(" 16450?"); 1643 break; 1644 case FIFO_RX_MEDH: 1645 printf(" 16550?"); 1646 break; 1647 case FIFO_RX_HIGH: 1648 if (COM_NOFIFO(flags)) { 1649 printf(" 16550A fifo disabled"); 1650 } else { 1651 com->hasfifo = TRUE; 1652#ifdef PC98 1653 com->tx_fifo_size = 0; /* XXX flag conflicts. */ 1654 printf(" 16550A"); 1655#else 1656 if (COM_ST16650A(flags)) { 1657 com->st16650a = 1; 1658 com->tx_fifo_size = 32; 1659 printf(" ST16650A"); 1660 } else { 1661 com->tx_fifo_size = COM_FIFOSIZE(flags); 1662 printf(" 16550A"); 1663 } 1664#endif 1665 } 1666#ifdef PC98 1667 if (com->pc98_if_type == COM_IF_RSA98III) { 1668 com->tx_fifo_size = 2048; 1669 com->rsabase = iobase; 1670 outb(com->rsabase + rsa_ier, 0x00); 1671 outb(com->rsabase + rsa_frr, 0x00); 1672 } 1673#endif 1674 1675#ifdef COM_ESP 1676#ifdef PC98 1677 if (com->pc98_if_type == COM_IF_ESP98) 1678#endif 1679 for (espp = likely_esp_ports; *espp != 0; espp++) 1680 if (espattach(com, *espp)) { 1681 com->tx_fifo_size = 1024; 1682 break; 1683 } 1684#endif 1685 if (!com->st16650a) { 1686 if (!com->tx_fifo_size) 1687 com->tx_fifo_size = 16; 1688 else 1689 printf(" lookalike with %d bytes FIFO", 1690 com->tx_fifo_size); 1691 } 1692 1693 break; 1694 } 1695 1696#ifdef PC98 1697 if (com->pc98_if_type == COM_IF_RSB3000) { 1698 /* Set RSB-2000/3000 Extended Buffer mode. */ 1699 u_char lcr; 1700 lcr = sio_getreg(com, com_cfcr); 1701 sio_setreg(com, com_cfcr, lcr | CFCR_DLAB); 1702 sio_setreg(com, com_emr, EMR_EXBUFF | EMR_EFMODE); 1703 sio_setreg(com, com_cfcr, lcr); 1704 } 1705#endif 1706 1707#ifdef COM_ESP 1708 if (com->esp) { 1709 /* 1710 * Set 16550 compatibility mode. 1711 * We don't use the ESP_MODE_SCALE bit to increase the 1712 * fifo trigger levels because we can't handle large 1713 * bursts of input. 1714 * XXX flow control should be set in comparam(), not here. 1715 */ 1716#ifdef PC98 1717 outb(com->esp_port + ESP98_CMD1, ESP_SETMODE); 1718 outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1719#else 1720 outb(com->esp_port + ESP_CMD1, ESP_SETMODE); 1721 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1722#endif 1723 1724 /* Set RTS/CTS flow control. */ 1725#ifdef PC98 1726 outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE); 1727 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS); 1728 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS); 1729#else 1730 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE); 1731 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS); 1732 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS); 1733#endif 1734 1735 /* Set flow-control levels. */ 1736#ifdef PC98 1737 outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW); 1738 outb(com->esp_port + ESP98_CMD2, HIBYTE(768)); 1739 outb(com->esp_port + ESP98_CMD2, LOBYTE(768)); 1740 outb(com->esp_port + ESP98_CMD2, HIBYTE(512)); 1741 outb(com->esp_port + ESP98_CMD2, LOBYTE(512)); 1742#else 1743 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW); 1744 outb(com->esp_port + ESP_CMD2, HIBYTE(768)); 1745 outb(com->esp_port + ESP_CMD2, LOBYTE(768)); 1746 outb(com->esp_port + ESP_CMD2, HIBYTE(512)); 1747 outb(com->esp_port + ESP_CMD2, LOBYTE(512)); 1748#endif 1749 1750#ifdef PC98 1751 /* Set UART clock prescaler. */ 1752 outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK); 1753 outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */ 1754#endif 1755 } 1756#endif /* COM_ESP */ 1757 sio_setreg(com, com_fifo, 0); 1758#ifdef PC98 1759 printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name); 1760#else 1761determined_type: ; 1762#endif 1763 1764#ifdef COM_MULTIPORT 1765 if (COM_ISMULTIPORT(flags)) { 1766 device_t masterdev; 1767 1768 com->multiport = TRUE; 1769 printf(" (multiport"); 1770 if (unit == COM_MPMASTER(flags)) 1771 printf(" master"); 1772 printf(")"); 1773 masterdev = devclass_get_device(sio_devclass, 1774 COM_MPMASTER(flags)); 1775 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev, 1776 SYS_RES_IRQ, 0, NULL, NULL) != 0); 1777 } 1778#endif /* COM_MULTIPORT */ 1779#ifdef PC98 1780 } 1781#endif 1782 if (unit == comconsole) 1783 printf(", console"); 1784 if (COM_IIR_TXRDYBUG(flags)) 1785 printf(" with a bogus IIR_TXRDY register"); 1786 printf("\n"); 1787 1788 if (sio_fast_ih == NULL) { 1789 swi_add(&tty_ithd, "tty:sio", siopoll, NULL, SWI_TTY, 0, 1790 &sio_fast_ih); 1791 swi_add(&clk_ithd, "tty:sio", siopoll, NULL, SWI_TTY, 0, 1792 &sio_slow_ih); 1793 } 1794 com->devs[0] = make_dev(&sio_cdevsw, unit, 1795 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit); 1796 com->devs[1] = make_dev(&sio_cdevsw, unit | CONTROL_INIT_STATE, 1797 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit); 1798 com->devs[2] = make_dev(&sio_cdevsw, unit | CONTROL_LOCK_STATE, 1799 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit); 1800 com->devs[3] = make_dev(&sio_cdevsw, unit | CALLOUT_MASK, 1801 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit); 1802 com->devs[4] = make_dev(&sio_cdevsw, 1803 unit | CALLOUT_MASK | CONTROL_INIT_STATE, 1804 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit); 1805 com->devs[5] = make_dev(&sio_cdevsw, 1806 unit | CALLOUT_MASK | CONTROL_LOCK_STATE, 1807 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit); 1808 com->flags = flags; 1809 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1810 pps_init(&com->pps); 1811 1812 rid = 0; 1813 com->irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1, 1814 RF_ACTIVE); 1815 if (com->irqres) { 1816 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres, 1817 INTR_TYPE_TTY | INTR_FAST, 1818 siointr, com, &com->cookie); 1819 if (ret) { 1820 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, 1821 com->irqres, INTR_TYPE_TTY, 1822 siointr, com, &com->cookie); 1823 if (ret == 0) 1824 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode\n"); 1825 } 1826 if (ret) 1827 device_printf(dev, "could not activate interrupt\n"); 1828#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \ 1829 defined(ALT_BREAK_TO_DEBUGGER)) 1830 /* 1831 * Enable interrupts for early break-to-debugger support 1832 * on the console. 1833 */ 1834 if (ret == 0 && unit == comconsole) 1835 outb(siocniobase + com_ier, IER_ERXRDY | IER_ERLS | 1836 IER_EMSC); 1837#endif 1838 } 1839 1840 return (0); 1841} 1842 1843static int 1844sioopen(dev, flag, mode, td) 1845 dev_t dev; 1846 int flag; 1847 int mode; 1848 struct thread *td; 1849{ 1850 struct com_s *com; 1851 int error; 1852 int mynor; 1853 int s; 1854 struct tty *tp; 1855 int unit; 1856 1857 mynor = minor(dev); 1858 unit = MINOR_TO_UNIT(mynor); 1859 com = com_addr(unit); 1860 if (com == NULL) 1861 return (ENXIO); 1862 if (com->gone) 1863 return (ENXIO); 1864 if (mynor & CONTROL_MASK) 1865 return (0); 1866 tp = dev->si_tty = com->tp = ttymalloc(com->tp); 1867 s = spltty(); 1868 /* 1869 * We jump to this label after all non-interrupted sleeps to pick 1870 * up any changes of the device state. 1871 */ 1872open_top: 1873 while (com->state & CS_DTR_OFF) { 1874 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0); 1875 if (com_addr(unit) == NULL) 1876 return (ENXIO); 1877 if (error != 0 || com->gone) 1878 goto out; 1879 } 1880 if (tp->t_state & TS_ISOPEN) { 1881 /* 1882 * The device is open, so everything has been initialized. 1883 * Handle conflicts. 1884 */ 1885 if (mynor & CALLOUT_MASK) { 1886 if (!com->active_out) { 1887 error = EBUSY; 1888 goto out; 1889 } 1890 } else { 1891 if (com->active_out) { 1892 if (flag & O_NONBLOCK) { 1893 error = EBUSY; 1894 goto out; 1895 } 1896 error = tsleep(&com->active_out, 1897 TTIPRI | PCATCH, "siobi", 0); 1898 if (com_addr(unit) == NULL) 1899 return (ENXIO); 1900 if (error != 0 || com->gone) 1901 goto out; 1902 goto open_top; 1903 } 1904 } 1905 if (tp->t_state & TS_XCLUDE && 1906 suser(td)) { 1907 error = EBUSY; 1908 goto out; 1909 } 1910 } else { 1911 /* 1912 * The device isn't open, so there are no conflicts. 1913 * Initialize it. Initialization is done twice in many 1914 * cases: to preempt sleeping callin opens if we are 1915 * callout, and to complete a callin open after DCD rises. 1916 */ 1917 tp->t_oproc = comstart; 1918 tp->t_param = comparam; 1919 tp->t_stop = comstop; 1920 tp->t_dev = dev; 1921 tp->t_termios = mynor & CALLOUT_MASK 1922 ? com->it_out : com->it_in; 1923#ifdef PC98 1924 if (!IS_8251(com->pc98_if_type)) 1925#endif 1926 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET); 1927 com->poll = com->no_irq; 1928 com->poll_output = com->loses_outints; 1929 ++com->wopeners; 1930 error = comparam(tp, &tp->t_termios); 1931 --com->wopeners; 1932 if (error != 0) 1933 goto out; 1934#ifdef PC98 1935 if (IS_8251(com->pc98_if_type)) { 1936 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS); 1937 pc98_msrint_start(dev); 1938 if (com->pc98_8251fifo) { 1939 com->pc98_8251fifo_enable = 1; 1940 outb(I8251F_fcr, CTRL8251F_ENABLE | 1941 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 1942 } 1943 } 1944#endif 1945 /* 1946 * XXX we should goto open_top if comparam() slept. 1947 */ 1948 if (com->hasfifo) { 1949 /* 1950 * (Re)enable and drain fifos. 1951 * 1952 * Certain SMC chips cause problems if the fifos 1953 * are enabled while input is ready. Turn off the 1954 * fifo if necessary to clear the input. We test 1955 * the input ready bit after enabling the fifos 1956 * since we've already enabled them in comparam() 1957 * and to handle races between enabling and fresh 1958 * input. 1959 */ 1960 while (TRUE) { 1961 sio_setreg(com, com_fifo, 1962 FIFO_RCV_RST | FIFO_XMT_RST 1963 | com->fifo_image); 1964#ifdef PC98 1965 if (com->pc98_if_type == COM_IF_RSA98III) 1966 outb(com->rsabase + rsa_frr , 0x00); 1967#endif 1968 /* 1969 * XXX the delays are for superstitious 1970 * historical reasons. It must be less than 1971 * the character time at the maximum 1972 * supported speed (87 usec at 115200 bps 1973 * 8N1). Otherwise we might loop endlessly 1974 * if data is streaming in. We used to use 1975 * delays of 100. That usually worked 1976 * because DELAY(100) used to usually delay 1977 * for about 85 usec instead of 100. 1978 */ 1979 DELAY(50); 1980#ifdef PC98 1981 if (com->pc98_if_type == COM_IF_RSA98III ? 1982 !(inb(com->rsabase + rsa_srr) & 0x08) : 1983 !(inb(com->line_status_port) & LSR_RXRDY)) 1984 break; 1985#else 1986 if (!(inb(com->line_status_port) & LSR_RXRDY)) 1987 break; 1988#endif 1989 sio_setreg(com, com_fifo, 0); 1990 DELAY(50); 1991 (void) inb(com->data_port); 1992 } 1993 } 1994 1995 mtx_lock_spin(&sio_lock); 1996#ifdef PC98 1997 if (IS_8251(com->pc98_if_type)) { 1998 com_tiocm_bis(com, TIOCM_LE); 1999 com->pc98_prev_modem_status = pc98_get_modem_status(com); 2000 com_int_Rx_enable(com); 2001 } else { 2002#endif 2003 (void) inb(com->line_status_port); 2004 (void) inb(com->data_port); 2005 com->prev_modem_status = com->last_modem_status 2006 = inb(com->modem_status_port); 2007 if (COM_IIR_TXRDYBUG(com->flags)) { 2008 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS 2009 | IER_EMSC); 2010 } else { 2011 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY 2012 | IER_ERLS | IER_EMSC); 2013 } 2014#ifdef PC98 2015 if (com->pc98_if_type == COM_IF_RSA98III) { 2016 outb(com->rsabase + rsa_ier, 0x1d); 2017 outb(com->intr_ctl_port, IER_ERLS | IER_EMSC); 2018 } 2019#endif 2020#ifdef PC98 2021 } 2022#endif 2023 mtx_unlock_spin(&sio_lock); 2024 /* 2025 * Handle initial DCD. Callout devices get a fake initial 2026 * DCD (trapdoor DCD). If we are callout, then any sleeping 2027 * callin opens get woken up and resume sleeping on "siobi" 2028 * instead of "siodcd". 2029 */ 2030 /* 2031 * XXX `mynor & CALLOUT_MASK' should be 2032 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where 2033 * TRAPDOOR_CARRIER is the default initial state for callout 2034 * devices and SOFT_CARRIER is like CLOCAL except it hides 2035 * the true carrier. 2036 */ 2037#ifdef PC98 2038 if ((IS_8251(com->pc98_if_type) && 2039 (pc98_get_modem_status(com) & TIOCM_CAR)) || 2040 (!IS_8251(com->pc98_if_type) && 2041 (com->prev_modem_status & MSR_DCD)) || 2042 mynor & CALLOUT_MASK) 2043 (*linesw[tp->t_line].l_modem)(tp, 1); 2044#else 2045 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK) 2046 (*linesw[tp->t_line].l_modem)(tp, 1); 2047#endif 2048 } 2049 /* 2050 * Wait for DCD if necessary. 2051 */ 2052 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK) 2053 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 2054 ++com->wopeners; 2055 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0); 2056 if (com_addr(unit) == NULL) 2057 return (ENXIO); 2058 --com->wopeners; 2059 if (error != 0 || com->gone) 2060 goto out; 2061 goto open_top; 2062 } 2063 error = (*linesw[tp->t_line].l_open)(dev, tp); 2064 disc_optim(tp, &tp->t_termios, com); 2065 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK) 2066 com->active_out = TRUE; 2067 siosettimeout(); 2068out: 2069 splx(s); 2070 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0) 2071 comhardclose(com); 2072 return (error); 2073} 2074 2075static int 2076sioclose(dev, flag, mode, td) 2077 dev_t dev; 2078 int flag; 2079 int mode; 2080 struct thread *td; 2081{ 2082 struct com_s *com; 2083 int mynor; 2084 int s; 2085 struct tty *tp; 2086 2087 mynor = minor(dev); 2088 if (mynor & CONTROL_MASK) 2089 return (0); 2090 com = com_addr(MINOR_TO_UNIT(mynor)); 2091 if (com == NULL) 2092 return (ENODEV); 2093 tp = com->tp; 2094 s = spltty(); 2095 (*linesw[tp->t_line].l_close)(tp, flag); 2096#ifdef PC98 2097 com->modem_checking = 0; 2098#endif 2099 disc_optim(tp, &tp->t_termios, com); 2100 comstop(tp, FREAD | FWRITE); 2101 comhardclose(com); 2102 ttyclose(tp); 2103 siosettimeout(); 2104 splx(s); 2105 if (com->gone) { 2106 printf("sio%d: gone\n", com->unit); 2107 s = spltty(); 2108 if (com->ibuf != NULL) 2109 free(com->ibuf, M_DEVBUF); 2110 bzero(tp, sizeof *tp); 2111 splx(s); 2112 } 2113 return (0); 2114} 2115 2116static void 2117comhardclose(com) 2118 struct com_s *com; 2119{ 2120 int s; 2121 struct tty *tp; 2122 int unit; 2123 2124 unit = com->unit; 2125 s = spltty(); 2126 com->poll = FALSE; 2127 com->poll_output = FALSE; 2128 com->do_timestamp = FALSE; 2129 com->do_dcd_timestamp = FALSE; 2130 com->pps.ppsparam.mode = 0; 2131#ifdef PC98 2132 if (IS_8251(com->pc98_if_type)) 2133 com_send_break_off(com); 2134 else 2135#endif 2136 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 2137 tp = com->tp; 2138 2139#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \ 2140 defined(ALT_BREAK_TO_DEBUGGER)) 2141 /* 2142 * Leave interrupts enabled and don't clear DTR if this is the 2143 * console. This allows us to detect break-to-debugger events 2144 * while the console device is closed. 2145 */ 2146 if (com->unit != comconsole) 2147#endif 2148 { 2149#ifdef PC98 2150 int tmp; 2151 if (IS_8251(com->pc98_if_type)) 2152 com_int_TxRx_disable(com); 2153 else 2154 sio_setreg(com, com_ier, 0); 2155 if (com->pc98_if_type == COM_IF_RSA98III) 2156 outb(com->rsabase + rsa_ier, 0x00); 2157 if (IS_8251(com->pc98_if_type)) 2158 tmp = pc98_get_modem_status(com) & TIOCM_CAR; 2159 else 2160 tmp = com->prev_modem_status & MSR_DCD; 2161#else 2162 sio_setreg(com, com_ier, 0); 2163#endif 2164 if (tp->t_cflag & HUPCL 2165 /* 2166 * XXX we will miss any carrier drop between here and the 2167 * next open. Perhaps we should watch DCD even when the 2168 * port is closed; it is not sufficient to check it at 2169 * the next open because it might go up and down while 2170 * we're not watching. 2171 */ 2172 || (!com->active_out 2173#ifdef PC98 2174 && !(tmp) 2175#else 2176 && !(com->prev_modem_status & MSR_DCD) 2177#endif 2178 && !(com->it_in.c_cflag & CLOCAL)) 2179 || !(tp->t_state & TS_ISOPEN)) { 2180#ifdef PC98 2181 if (IS_8251(com->pc98_if_type)) 2182 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 2183 else 2184#endif 2185 (void)commctl(com, TIOCM_DTR, DMBIC); 2186 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) { 2187 timeout(siodtrwakeup, com, com->dtr_wait); 2188 com->state |= CS_DTR_OFF; 2189 } 2190 } 2191#ifdef PC98 2192 else { 2193 if (IS_8251(com->pc98_if_type)) 2194 com_tiocm_bic(com, TIOCM_LE); 2195 } 2196#endif 2197 } 2198#ifdef PC98 2199 if (com->pc98_8251fifo) { 2200 if (com->pc98_8251fifo_enable) 2201 outb(I8251F_fcr, CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 2202 com->pc98_8251fifo_enable = 0; 2203 } 2204#endif 2205 if (com->hasfifo) { 2206 /* 2207 * Disable fifos so that they are off after controlled 2208 * reboots. Some BIOSes fail to detect 16550s when the 2209 * fifos are enabled. 2210 */ 2211 sio_setreg(com, com_fifo, 0); 2212 } 2213 com->active_out = FALSE; 2214 wakeup(&com->active_out); 2215 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */ 2216 splx(s); 2217} 2218 2219static int 2220sioread(dev, uio, flag) 2221 dev_t dev; 2222 struct uio *uio; 2223 int flag; 2224{ 2225 int mynor; 2226 struct com_s *com; 2227 2228 mynor = minor(dev); 2229 if (mynor & CONTROL_MASK) 2230 return (ENODEV); 2231 com = com_addr(MINOR_TO_UNIT(mynor)); 2232 if (com == NULL || com->gone) 2233 return (ENODEV); 2234 return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag)); 2235} 2236 2237static int 2238siowrite(dev, uio, flag) 2239 dev_t dev; 2240 struct uio *uio; 2241 int flag; 2242{ 2243 int mynor; 2244 struct com_s *com; 2245 int unit; 2246 2247 mynor = minor(dev); 2248 if (mynor & CONTROL_MASK) 2249 return (ENODEV); 2250 2251 unit = MINOR_TO_UNIT(mynor); 2252 com = com_addr(unit); 2253 if (com == NULL || com->gone) 2254 return (ENODEV); 2255 /* 2256 * (XXX) We disallow virtual consoles if the physical console is 2257 * a serial port. This is in case there is a display attached that 2258 * is not the console. In that situation we don't need/want the X 2259 * server taking over the console. 2260 */ 2261 if (constty != NULL && unit == comconsole) 2262 constty = NULL; 2263 return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag)); 2264} 2265 2266static void 2267siobusycheck(chan) 2268 void *chan; 2269{ 2270 struct com_s *com; 2271 int s; 2272 2273 com = (struct com_s *)chan; 2274 2275 /* 2276 * Clear TS_BUSY if low-level output is complete. 2277 * spl locking is sufficient because siointr1() does not set CS_BUSY. 2278 * If siointr1() clears CS_BUSY after we look at it, then we'll get 2279 * called again. Reading the line status port outside of siointr1() 2280 * is safe because CS_BUSY is clear so there are no output interrupts 2281 * to lose. 2282 */ 2283 s = spltty(); 2284 if (com->state & CS_BUSY) 2285 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */ 2286#ifdef PC98 2287 else if ((IS_8251(com->pc98_if_type) && 2288 ((com->pc98_8251fifo_enable && 2289 (inb(I8251F_lsr) & (STS8251F_TxRDY | STS8251F_TxEMP)) 2290 == (STS8251F_TxRDY | STS8251F_TxEMP)) || 2291 (!com->pc98_8251fifo_enable && 2292 (inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP)) 2293 == (STS8251_TxRDY | STS8251_TxEMP)))) || 2294 ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2295 == (LSR_TSRE | LSR_TXRDY))) { 2296#else 2297 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2298 == (LSR_TSRE | LSR_TXRDY)) { 2299#endif 2300 com->tp->t_state &= ~TS_BUSY; 2301 ttwwakeup(com->tp); 2302 com->extra_state &= ~CSE_BUSYCHECK; 2303 } else 2304 timeout(siobusycheck, com, hz / 100); 2305 splx(s); 2306} 2307 2308static u_int 2309siodivisor(rclk, speed) 2310 u_long rclk; 2311 speed_t speed; 2312{ 2313 long actual_speed; 2314 u_int divisor; 2315 int error; 2316 2317 if (speed == 0 || speed > (ULONG_MAX - 1) / 8) 2318 return (0); 2319 divisor = (rclk / (8UL * speed) + 1) / 2; 2320 if (divisor == 0 || divisor >= 65536) 2321 return (0); 2322 actual_speed = rclk / (16UL * divisor); 2323 2324 /* 10 times error in percent: */ 2325 error = ((actual_speed - (long)speed) * 2000 / (long)speed + 1) / 2; 2326 2327 /* 3.0% maximum error tolerance: */ 2328 if (error < -30 || error > 30) 2329 return (0); 2330 2331 return (divisor); 2332} 2333 2334static void 2335siodtrwakeup(chan) 2336 void *chan; 2337{ 2338 struct com_s *com; 2339 2340 com = (struct com_s *)chan; 2341 com->state &= ~CS_DTR_OFF; 2342 wakeup(&com->dtr_wait); 2343} 2344 2345/* 2346 * Call this function with the sio_lock mutex held. It will return with the 2347 * lock still held. 2348 */ 2349static void 2350sioinput(com) 2351 struct com_s *com; 2352{ 2353 u_char *buf; 2354 int incc; 2355 u_char line_status; 2356 int recv_data; 2357 struct tty *tp; 2358 2359 buf = com->ibuf; 2360 tp = com->tp; 2361 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) { 2362 com_events -= (com->iptr - com->ibuf); 2363 com->iptr = com->ibuf; 2364 return; 2365 } 2366 if (tp->t_state & TS_CAN_BYPASS_L_RINT) { 2367 /* 2368 * Avoid the grotesquely inefficient lineswitch routine 2369 * (ttyinput) in "raw" mode. It usually takes about 450 2370 * instructions (that's without canonical processing or echo!). 2371 * slinput is reasonably fast (usually 40 instructions plus 2372 * call overhead). 2373 */ 2374 do { 2375 /* 2376 * This may look odd, but it is using save-and-enable 2377 * semantics instead of the save-and-disable semantics 2378 * that are used everywhere else. 2379 */ 2380 mtx_unlock_spin(&sio_lock); 2381 incc = com->iptr - buf; 2382 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat 2383 && (com->state & CS_RTS_IFLOW 2384 || tp->t_iflag & IXOFF) 2385 && !(tp->t_state & TS_TBLOCK)) 2386 ttyblock(tp); 2387 com->delta_error_counts[CE_TTY_BUF_OVERFLOW] 2388 += b_to_q((char *)buf, incc, &tp->t_rawq); 2389 buf += incc; 2390 tk_nin += incc; 2391 tk_rawcc += incc; 2392 tp->t_rawcc += incc; 2393 ttwakeup(tp); 2394 if (tp->t_state & TS_TTSTOP 2395 && (tp->t_iflag & IXANY 2396 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) { 2397 tp->t_state &= ~TS_TTSTOP; 2398 tp->t_lflag &= ~FLUSHO; 2399 comstart(tp); 2400 } 2401 mtx_lock_spin(&sio_lock); 2402 } while (buf < com->iptr); 2403 } else { 2404 do { 2405 /* 2406 * This may look odd, but it is using save-and-enable 2407 * semantics instead of the save-and-disable semantics 2408 * that are used everywhere else. 2409 */ 2410 mtx_unlock_spin(&sio_lock); 2411 line_status = buf[com->ierroff]; 2412 recv_data = *buf++; 2413 if (line_status 2414 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) { 2415 if (line_status & LSR_BI) 2416 recv_data |= TTY_BI; 2417 if (line_status & LSR_FE) 2418 recv_data |= TTY_FE; 2419 if (line_status & LSR_OE) 2420 recv_data |= TTY_OE; 2421 if (line_status & LSR_PE) 2422 recv_data |= TTY_PE; 2423 } 2424 (*linesw[tp->t_line].l_rint)(recv_data, tp); 2425 mtx_lock_spin(&sio_lock); 2426 } while (buf < com->iptr); 2427 } 2428 com_events -= (com->iptr - com->ibuf); 2429 com->iptr = com->ibuf; 2430 2431 /* 2432 * There is now room for another low-level buffer full of input, 2433 * so enable RTS if it is now disabled and there is room in the 2434 * high-level buffer. 2435 */ 2436#ifdef PC98 2437 if (IS_8251(com->pc98_if_type)) { 2438 if ((com->state & CS_RTS_IFLOW) && 2439 !(com_tiocm_get(com) & TIOCM_RTS) && 2440 !(tp->t_state & TS_TBLOCK)) 2441 com_tiocm_bis(com, TIOCM_RTS); 2442 } else { 2443 if ((com->state & CS_RTS_IFLOW) && 2444 !(com->mcr_image & MCR_RTS) && 2445 !(tp->t_state & TS_TBLOCK)) 2446 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2447 } 2448#else 2449 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) && 2450 !(tp->t_state & TS_TBLOCK)) 2451 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2452#endif 2453} 2454 2455void 2456siointr(arg) 2457 void *arg; 2458{ 2459 struct com_s *com; 2460#ifdef PC98 2461 u_char rsa_buf_status; 2462#endif 2463 2464#ifndef COM_MULTIPORT 2465 com = (struct com_s *)arg; 2466 2467 mtx_lock_spin(&sio_lock); 2468 siointr1(com); 2469 mtx_unlock_spin(&sio_lock); 2470#else /* COM_MULTIPORT */ 2471 bool_t possibly_more_intrs; 2472 int unit; 2473 2474 /* 2475 * Loop until there is no activity on any port. This is necessary 2476 * to get an interrupt edge more than to avoid another interrupt. 2477 * If the IRQ signal is just an OR of the IRQ signals from several 2478 * devices, then the edge from one may be lost because another is 2479 * on. 2480 */ 2481 mtx_lock_spin(&sio_lock); 2482 do { 2483 possibly_more_intrs = FALSE; 2484 for (unit = 0; unit < sio_numunits; ++unit) { 2485 com = com_addr(unit); 2486 /* 2487 * XXX COM_LOCK(); 2488 * would it work here, or be counter-productive? 2489 */ 2490#ifdef PC98 2491 if (com != NULL 2492 && !com->gone 2493 && IS_8251(com->pc98_if_type)) { 2494 siointr1(com); 2495 } else if (com != NULL 2496 && !com->gone 2497 && com->pc98_if_type == COM_IF_RSA98III) { 2498 rsa_buf_status = 2499 inb(com->rsabase + rsa_srr) & 0xc9; 2500 if ((rsa_buf_status & 0xc8) 2501 || !(rsa_buf_status & 0x01)) { 2502 siointr1(com); 2503 if (rsa_buf_status != 2504 (inb(com->rsabase + rsa_srr) & 0xc9)) 2505 possibly_more_intrs = TRUE; 2506 } 2507 } else 2508#endif 2509 if (com != NULL 2510 && !com->gone 2511 && (inb(com->int_id_port) & IIR_IMASK) 2512 != IIR_NOPEND) { 2513 siointr1(com); 2514 possibly_more_intrs = TRUE; 2515 } 2516 /* XXX COM_UNLOCK(); */ 2517 } 2518 } while (possibly_more_intrs); 2519 mtx_unlock_spin(&sio_lock); 2520#endif /* COM_MULTIPORT */ 2521} 2522 2523static void 2524siointr1(com) 2525 struct com_s *com; 2526{ 2527 u_char line_status; 2528 u_char modem_status; 2529 u_char *ioptr; 2530 u_char recv_data; 2531 u_char int_ctl; 2532 u_char int_ctl_new; 2533 struct timecounter *tc; 2534 u_int count; 2535 2536#ifdef PC98 2537 u_char tmp = 0; 2538 u_char rsa_buf_status = 0; 2539 int rsa_tx_fifo_size = 0; 2540#endif /* PC98 */ 2541 2542 int_ctl = inb(com->intr_ctl_port); 2543 int_ctl_new = int_ctl; 2544 2545 while (!com->gone) { 2546#ifdef PC98 2547status_read:; 2548 if (IS_8251(com->pc98_if_type)) { 2549 if (com->pc98_8251fifo_enable) 2550 tmp = inb(I8251F_lsr); 2551 else 2552 tmp = inb(com->sts_port); 2553more_intr: 2554 line_status = 0; 2555 if (com->pc98_8251fifo_enable) { 2556 if (tmp & STS8251F_TxRDY) line_status |= LSR_TXRDY; 2557 if (tmp & STS8251F_RxRDY) line_status |= LSR_RXRDY; 2558 if (tmp & STS8251F_TxEMP) line_status |= LSR_TSRE; 2559 if (tmp & STS8251F_PE) line_status |= LSR_PE; 2560 if (tmp & STS8251F_OE) line_status |= LSR_OE; 2561 if (tmp & STS8251F_BD_SD) line_status |= LSR_BI; 2562 } else { 2563 if (tmp & STS8251_TxRDY) line_status |= LSR_TXRDY; 2564 if (tmp & STS8251_RxRDY) line_status |= LSR_RXRDY; 2565 if (tmp & STS8251_TxEMP) line_status |= LSR_TSRE; 2566 if (tmp & STS8251_PE) line_status |= LSR_PE; 2567 if (tmp & STS8251_OE) line_status |= LSR_OE; 2568 if (tmp & STS8251_FE) line_status |= LSR_FE; 2569 if (tmp & STS8251_BD_SD) line_status |= LSR_BI; 2570 } 2571 } else { 2572#endif /* PC98 */ 2573 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) { 2574 modem_status = inb(com->modem_status_port); 2575 if ((modem_status ^ com->last_modem_status) & MSR_DCD) { 2576 tc = timecounter; 2577 count = tc->tc_get_timecount(tc); 2578 pps_event(&com->pps, tc, count, 2579 (modem_status & MSR_DCD) ? 2580 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR); 2581 } 2582 } 2583 line_status = inb(com->line_status_port); 2584#ifdef PC98 2585 } 2586 if (com->pc98_if_type == COM_IF_RSA98III) 2587 rsa_buf_status = inb(com->rsabase + rsa_srr); 2588#endif /* PC98 */ 2589 2590 /* input event? (check first to help avoid overruns) */ 2591#ifndef PC98 2592 while (line_status & LSR_RCV_MASK) { 2593#else 2594 while ((line_status & LSR_RCV_MASK) 2595 || (com->pc98_if_type == COM_IF_RSA98III 2596 && (rsa_buf_status & 0x08))) { 2597#endif /* PC98 */ 2598 /* break/unnattached error bits or real input? */ 2599#ifdef PC98 2600 if (IS_8251(com->pc98_if_type)) { 2601 if (com->pc98_8251fifo_enable) { 2602 recv_data = inb(I8251F_data); 2603 if (tmp & (STS8251F_PE | STS8251F_OE | 2604 STS8251F_BD_SD)) { 2605 pc98_i8251_or_cmd(com, CMD8251_ER); 2606 recv_data = 0; 2607 } 2608 } else { 2609 recv_data = inb(com->data_port); 2610 if (tmp & (STS8251_PE | STS8251_OE | 2611 STS8251_FE | STS8251_BD_SD)) { 2612 pc98_i8251_or_cmd(com, CMD8251_ER); 2613 recv_data = 0; 2614 } 2615 } 2616 } else if (com->pc98_if_type == COM_IF_RSA98III) { 2617 if (!(rsa_buf_status & 0x08)) 2618 recv_data = 0; 2619 else 2620 recv_data = inb(com->data_port); 2621 } else 2622#endif 2623 if (!(line_status & LSR_RXRDY)) 2624 recv_data = 0; 2625 else 2626 recv_data = inb(com->data_port); 2627#if defined(DDB) && defined(ALT_BREAK_TO_DEBUGGER) 2628 /* 2629 * Solaris implements a new BREAK which is initiated 2630 * by a character sequence CR ~ ^b which is similar 2631 * to a familiar pattern used on Sun servers by the 2632 * Remote Console. 2633 */ 2634#define KEY_CRTLB 2 /* ^B */ 2635#define KEY_CR 13 /* CR '\r' */ 2636#define KEY_TILDE 126 /* ~ */ 2637 2638 if (com->unit == comconsole) { 2639 static int brk_state1 = 0, brk_state2 = 0; 2640 if (recv_data == KEY_CR) { 2641 brk_state1 = recv_data; 2642 brk_state2 = 0; 2643 } else if (brk_state1 == KEY_CR && (recv_data == KEY_TILDE || recv_data == KEY_CRTLB)) { 2644 if (recv_data == KEY_TILDE) 2645 brk_state2 = recv_data; 2646 else if (brk_state2 == KEY_TILDE && recv_data == KEY_CRTLB) { 2647 breakpoint(); 2648 brk_state1 = brk_state2 = 0; 2649 goto cont; 2650 } else 2651 brk_state2 = 0; 2652 } else 2653 brk_state1 = 0; 2654 } 2655#endif 2656 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) { 2657 /* 2658 * Don't store BI if IGNBRK or FE/PE if IGNPAR. 2659 * Otherwise, push the work to a higher level 2660 * (to handle PARMRK) if we're bypassing. 2661 * Otherwise, convert BI/FE and PE+INPCK to 0. 2662 * 2663 * This makes bypassing work right in the 2664 * usual "raw" case (IGNBRK set, and IGNPAR 2665 * and INPCK clear). 2666 * 2667 * Note: BI together with FE/PE means just BI. 2668 */ 2669 if (line_status & LSR_BI) { 2670#if defined(DDB) && defined(BREAK_TO_DEBUGGER) 2671 if (com->unit == comconsole) { 2672 breakpoint(); 2673 goto cont; 2674 } 2675#endif 2676 if (com->tp == NULL 2677 || com->tp->t_iflag & IGNBRK) 2678 goto cont; 2679 } else { 2680 if (com->tp == NULL 2681 || com->tp->t_iflag & IGNPAR) 2682 goto cont; 2683 } 2684 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT 2685 && (line_status & (LSR_BI | LSR_FE) 2686 || com->tp->t_iflag & INPCK)) 2687 recv_data = 0; 2688 } 2689 ++com->bytes_in; 2690 if (com->hotchar != 0 && recv_data == com->hotchar) 2691 swi_sched(sio_fast_ih, 0); 2692 ioptr = com->iptr; 2693 if (ioptr >= com->ibufend) 2694 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW); 2695 else { 2696 if (com->do_timestamp) 2697 microtime(&com->timestamp); 2698 ++com_events; 2699 swi_sched(sio_slow_ih, SWI_DELAY); 2700#if 0 /* for testing input latency vs efficiency */ 2701if (com->iptr - com->ibuf == 8) 2702 swi_sched(sio_fast_ih, 0); 2703#endif 2704 ioptr[0] = recv_data; 2705 ioptr[com->ierroff] = line_status; 2706 com->iptr = ++ioptr; 2707 if (ioptr == com->ihighwater 2708 && com->state & CS_RTS_IFLOW) 2709#ifdef PC98 2710 IS_8251(com->pc98_if_type) ? 2711 com_tiocm_bic(com, TIOCM_RTS) : 2712#endif 2713 outb(com->modem_ctl_port, 2714 com->mcr_image &= ~MCR_RTS); 2715 if (line_status & LSR_OE) 2716 CE_RECORD(com, CE_OVERRUN); 2717 } 2718cont: 2719 /* 2720 * "& 0x7F" is to avoid the gcc-1.40 generating a slow 2721 * jump from the top of the loop to here 2722 */ 2723#ifdef PC98 2724 if (IS_8251(com->pc98_if_type)) 2725 goto status_read; 2726 else 2727#endif 2728 line_status = inb(com->line_status_port) & 0x7F; 2729#ifdef PC98 2730 if (com->pc98_if_type == COM_IF_RSA98III) 2731 rsa_buf_status = inb(com->rsabase + rsa_srr); 2732#endif /* PC98 */ 2733 } 2734 2735 /* modem status change? (always check before doing output) */ 2736#ifdef PC98 2737 if (!IS_8251(com->pc98_if_type)) { 2738#endif 2739 modem_status = inb(com->modem_status_port); 2740 if (modem_status != com->last_modem_status) { 2741 if (com->do_dcd_timestamp 2742 && !(com->last_modem_status & MSR_DCD) 2743 && modem_status & MSR_DCD) 2744 microtime(&com->dcd_timestamp); 2745 2746 /* 2747 * Schedule high level to handle DCD changes. Note 2748 * that we don't use the delta bits anywhere. Some 2749 * UARTs mess them up, and it's easy to remember the 2750 * previous bits and calculate the delta. 2751 */ 2752 com->last_modem_status = modem_status; 2753 if (!(com->state & CS_CHECKMSR)) { 2754 com_events += LOTS_OF_EVENTS; 2755 com->state |= CS_CHECKMSR; 2756 swi_sched(sio_fast_ih, 0); 2757 } 2758 2759 /* handle CTS change immediately for crisp flow ctl */ 2760 if (com->state & CS_CTS_OFLOW) { 2761 if (modem_status & MSR_CTS) 2762 com->state |= CS_ODEVREADY; 2763 else 2764 com->state &= ~CS_ODEVREADY; 2765 } 2766 } 2767#ifdef PC98 2768 } 2769#endif 2770 2771 /* output queued and everything ready? */ 2772#ifndef PC98 2773 if (line_status & LSR_TXRDY 2774 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 2775#else 2776 if (((com->pc98_if_type == COM_IF_RSA98III) 2777 ? (rsa_buf_status & 0x02) 2778 : (line_status & LSR_TXRDY)) 2779 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 2780#endif 2781#ifdef PC98 2782 Port_t tmp_data_port; 2783 2784 if (IS_8251(com->pc98_if_type) && 2785 com->pc98_8251fifo_enable) 2786 tmp_data_port = I8251F_data; 2787 else 2788 tmp_data_port = com->data_port; 2789#endif 2790 2791 ioptr = com->obufq.l_head; 2792 if (com->tx_fifo_size > 1) { 2793 u_int ocount; 2794 2795 ocount = com->obufq.l_tail - ioptr; 2796#ifdef PC98 2797 if (com->pc98_if_type == COM_IF_RSA98III) { 2798 rsa_buf_status = inb(com->rsabase + rsa_srr); 2799 rsa_tx_fifo_size = 1024; 2800 if (!(rsa_buf_status & 0x01)) 2801 rsa_tx_fifo_size = 2048; 2802 if (ocount > rsa_tx_fifo_size) 2803 ocount = rsa_tx_fifo_size; 2804 } else 2805#endif 2806 if (ocount > com->tx_fifo_size) 2807 ocount = com->tx_fifo_size; 2808 com->bytes_out += ocount; 2809 do 2810#ifdef PC98 2811 outb(tmp_data_port, *ioptr++); 2812#else 2813 outb(com->data_port, *ioptr++); 2814#endif 2815 while (--ocount != 0); 2816 } else { 2817#ifdef PC98 2818 outb(tmp_data_port, *ioptr++); 2819#else 2820 outb(com->data_port, *ioptr++); 2821#endif 2822 ++com->bytes_out; 2823 } 2824#ifdef PC98 2825 if (IS_8251(com->pc98_if_type)) 2826 if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG)) 2827 com_int_Tx_enable(com); 2828#endif 2829 com->obufq.l_head = ioptr; 2830 if (COM_IIR_TXRDYBUG(com->flags)) { 2831 int_ctl_new = int_ctl | IER_ETXRDY; 2832 } 2833 if (ioptr >= com->obufq.l_tail) { 2834 struct lbq *qp; 2835 2836 qp = com->obufq.l_next; 2837 qp->l_queued = FALSE; 2838 qp = qp->l_next; 2839 if (qp != NULL) { 2840 com->obufq.l_head = qp->l_head; 2841 com->obufq.l_tail = qp->l_tail; 2842 com->obufq.l_next = qp; 2843 } else { 2844 /* output just completed */ 2845 if (COM_IIR_TXRDYBUG(com->flags)) { 2846 int_ctl_new = int_ctl & ~IER_ETXRDY; 2847 } 2848 com->state &= ~CS_BUSY; 2849#if defined(PC98) 2850 if (IS_8251(com->pc98_if_type) && 2851 pc98_check_i8251_interrupt(com) & IEN_TxFLAG) 2852 com_int_Tx_disable(com); 2853#endif 2854 } 2855 if (!(com->state & CS_ODONE)) { 2856 com_events += LOTS_OF_EVENTS; 2857 com->state |= CS_ODONE; 2858 /* handle at high level ASAP */ 2859 swi_sched(sio_fast_ih, 0); 2860 } 2861 } 2862 if (COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) { 2863#ifdef PC98 2864 if (com->pc98_if_type == COM_IF_RSA98III) { 2865 int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY); 2866 outb(com->intr_ctl_port, int_ctl_new); 2867 outb(com->rsabase + rsa_ier, 0x1d); 2868 } else 2869#endif 2870 outb(com->intr_ctl_port, int_ctl_new); 2871 } 2872 } 2873#ifdef PC98 2874 else if (line_status & LSR_TXRDY) { 2875 if (IS_8251(com->pc98_if_type)) 2876 if (pc98_check_i8251_interrupt(com) & IEN_TxFLAG) 2877 com_int_Tx_disable(com); 2878 } 2879 if (IS_8251(com->pc98_if_type)) { 2880 if (com->pc98_8251fifo_enable) { 2881 if ((tmp = inb(I8251F_lsr)) & STS8251F_RxRDY) 2882 goto more_intr; 2883 } else { 2884 if ((tmp = inb(com->sts_port)) & STS8251_RxRDY) 2885 goto more_intr; 2886 } 2887 } 2888#endif 2889 2890 /* finished? */ 2891#ifndef COM_MULTIPORT 2892#ifdef PC98 2893 if (IS_8251(com->pc98_if_type)) 2894 return; 2895#endif 2896 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND) 2897#endif /* COM_MULTIPORT */ 2898 return; 2899 } 2900} 2901 2902static int 2903sioioctl(dev, cmd, data, flag, td) 2904 dev_t dev; 2905 u_long cmd; 2906 caddr_t data; 2907 int flag; 2908 struct thread *td; 2909{ 2910 struct com_s *com; 2911 int error; 2912 int mynor; 2913 int s; 2914 struct tty *tp; 2915#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 2916 u_long oldcmd; 2917 struct termios term; 2918#endif 2919 2920 mynor = minor(dev); 2921 com = com_addr(MINOR_TO_UNIT(mynor)); 2922 if (com == NULL || com->gone) 2923 return (ENODEV); 2924 if (mynor & CONTROL_MASK) { 2925 struct termios *ct; 2926 2927 switch (mynor & CONTROL_MASK) { 2928 case CONTROL_INIT_STATE: 2929 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in; 2930 break; 2931 case CONTROL_LOCK_STATE: 2932 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in; 2933 break; 2934 default: 2935 return (ENODEV); /* /dev/nodev */ 2936 } 2937 switch (cmd) { 2938 case TIOCSETA: 2939 error = suser(td); 2940 if (error != 0) 2941 return (error); 2942 *ct = *(struct termios *)data; 2943 return (0); 2944 case TIOCGETA: 2945 *(struct termios *)data = *ct; 2946 return (0); 2947 case TIOCGETD: 2948 *(int *)data = TTYDISC; 2949 return (0); 2950 case TIOCGWINSZ: 2951 bzero(data, sizeof(struct winsize)); 2952 return (0); 2953 default: 2954 return (ENOTTY); 2955 } 2956 } 2957 tp = com->tp; 2958#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 2959 term = tp->t_termios; 2960 oldcmd = cmd; 2961 error = ttsetcompat(tp, &cmd, data, &term); 2962 if (error != 0) 2963 return (error); 2964 if (cmd != oldcmd) 2965 data = (caddr_t)&term; 2966#endif 2967 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) { 2968 int cc; 2969 struct termios *dt = (struct termios *)data; 2970 struct termios *lt = mynor & CALLOUT_MASK 2971 ? &com->lt_out : &com->lt_in; 2972 2973 dt->c_iflag = (tp->t_iflag & lt->c_iflag) 2974 | (dt->c_iflag & ~lt->c_iflag); 2975 dt->c_oflag = (tp->t_oflag & lt->c_oflag) 2976 | (dt->c_oflag & ~lt->c_oflag); 2977 dt->c_cflag = (tp->t_cflag & lt->c_cflag) 2978 | (dt->c_cflag & ~lt->c_cflag); 2979 dt->c_lflag = (tp->t_lflag & lt->c_lflag) 2980 | (dt->c_lflag & ~lt->c_lflag); 2981 for (cc = 0; cc < NCCS; ++cc) 2982 if (lt->c_cc[cc] != 0) 2983 dt->c_cc[cc] = tp->t_cc[cc]; 2984 if (lt->c_ispeed != 0) 2985 dt->c_ispeed = tp->t_ispeed; 2986 if (lt->c_ospeed != 0) 2987 dt->c_ospeed = tp->t_ospeed; 2988 } 2989 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, td); 2990 if (error != ENOIOCTL) 2991 return (error); 2992 s = spltty(); 2993 error = ttioctl(tp, cmd, data, flag); 2994 disc_optim(tp, &tp->t_termios, com); 2995 if (error != ENOIOCTL) { 2996 splx(s); 2997 return (error); 2998 } 2999#ifdef PC98 3000 if (IS_8251(com->pc98_if_type)) { 3001 switch (cmd) { 3002 case TIOCSBRK: 3003 com_send_break_on(com); 3004 break; 3005 case TIOCCBRK: 3006 com_send_break_off(com); 3007 break; 3008 case TIOCSDTR: 3009 com_tiocm_bis(com, TIOCM_DTR | TIOCM_RTS); 3010 break; 3011 case TIOCCDTR: 3012 com_tiocm_bic(com, TIOCM_DTR); 3013 break; 3014 /* 3015 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 3016 * changes get undone on the next call to comparam(). 3017 */ 3018 case TIOCMSET: 3019 com_tiocm_set(com, *(int *)data); 3020 break; 3021 case TIOCMBIS: 3022 com_tiocm_bis(com, *(int *)data); 3023 break; 3024 case TIOCMBIC: 3025 com_tiocm_bic(com, *(int *)data); 3026 break; 3027 case TIOCMGET: 3028 *(int *)data = com_tiocm_get(com); 3029 break; 3030 case TIOCMSDTRWAIT: 3031 /* must be root since the wait applies to following logins */ 3032 error = suser(td); 3033 if (error != 0) { 3034 splx(s); 3035 return (error); 3036 } 3037 com->dtr_wait = *(int *)data * hz / 100; 3038 break; 3039 case TIOCMGDTRWAIT: 3040 *(int *)data = com->dtr_wait * 100 / hz; 3041 break; 3042 case TIOCTIMESTAMP: 3043 com->do_timestamp = TRUE; 3044 *(struct timeval *)data = com->timestamp; 3045 break; 3046 case TIOCDCDTIMESTAMP: 3047 com->do_dcd_timestamp = TRUE; 3048 *(struct timeval *)data = com->dcd_timestamp; 3049 break; 3050 default: 3051 splx(s); 3052 error = pps_ioctl(cmd, data, &com->pps); 3053 if (error == ENODEV) 3054 error = ENOTTY; 3055 return (error); 3056 } 3057 } else { 3058#endif 3059 switch (cmd) { 3060 case TIOCSBRK: 3061 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK); 3062 break; 3063 case TIOCCBRK: 3064 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 3065 break; 3066 case TIOCSDTR: 3067 (void)commctl(com, TIOCM_DTR, DMBIS); 3068 break; 3069 case TIOCCDTR: 3070 (void)commctl(com, TIOCM_DTR, DMBIC); 3071 break; 3072 /* 3073 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 3074 * changes get undone on the next call to comparam(). 3075 */ 3076 case TIOCMSET: 3077 (void)commctl(com, *(int *)data, DMSET); 3078 break; 3079 case TIOCMBIS: 3080 (void)commctl(com, *(int *)data, DMBIS); 3081 break; 3082 case TIOCMBIC: 3083 (void)commctl(com, *(int *)data, DMBIC); 3084 break; 3085 case TIOCMGET: 3086 *(int *)data = commctl(com, 0, DMGET); 3087 break; 3088 case TIOCMSDTRWAIT: 3089 /* must be root since the wait applies to following logins */ 3090 error = suser(td); 3091 if (error != 0) { 3092 splx(s); 3093 return (error); 3094 } 3095 com->dtr_wait = *(int *)data * hz / 100; 3096 break; 3097 case TIOCMGDTRWAIT: 3098 *(int *)data = com->dtr_wait * 100 / hz; 3099 break; 3100 case TIOCTIMESTAMP: 3101 com->do_timestamp = TRUE; 3102 *(struct timeval *)data = com->timestamp; 3103 break; 3104 case TIOCDCDTIMESTAMP: 3105 com->do_dcd_timestamp = TRUE; 3106 *(struct timeval *)data = com->dcd_timestamp; 3107 break; 3108 default: 3109 splx(s); 3110 error = pps_ioctl(cmd, data, &com->pps); 3111 if (error == ENODEV) 3112 error = ENOTTY; 3113 return (error); 3114 } 3115#ifdef PC98 3116 } 3117#endif 3118 splx(s); 3119 return (0); 3120} 3121 3122/* software interrupt handler for SWI_TTY */ 3123static void 3124siopoll(void *dummy) 3125{ 3126 int unit; 3127 3128 if (com_events == 0) 3129 return; 3130repeat: 3131 for (unit = 0; unit < sio_numunits; ++unit) { 3132 struct com_s *com; 3133 int incc; 3134 struct tty *tp; 3135 3136 com = com_addr(unit); 3137 if (com == NULL) 3138 continue; 3139 tp = com->tp; 3140 if (tp == NULL || com->gone) { 3141 /* 3142 * Discard any events related to never-opened or 3143 * going-away devices. 3144 */ 3145 mtx_lock_spin(&sio_lock); 3146 incc = com->iptr - com->ibuf; 3147 com->iptr = com->ibuf; 3148 if (com->state & CS_CHECKMSR) { 3149 incc += LOTS_OF_EVENTS; 3150 com->state &= ~CS_CHECKMSR; 3151 } 3152 com_events -= incc; 3153 mtx_unlock_spin(&sio_lock); 3154 continue; 3155 } 3156 if (com->iptr != com->ibuf) { 3157 mtx_lock_spin(&sio_lock); 3158 sioinput(com); 3159 mtx_unlock_spin(&sio_lock); 3160 } 3161 if (com->state & CS_CHECKMSR) { 3162 u_char delta_modem_status; 3163 3164#ifdef PC98 3165 if (!IS_8251(com->pc98_if_type)) { 3166#endif 3167 mtx_lock_spin(&sio_lock); 3168 delta_modem_status = com->last_modem_status 3169 ^ com->prev_modem_status; 3170 com->prev_modem_status = com->last_modem_status; 3171 com_events -= LOTS_OF_EVENTS; 3172 com->state &= ~CS_CHECKMSR; 3173 mtx_unlock_spin(&sio_lock); 3174 if (delta_modem_status & MSR_DCD) 3175 (*linesw[tp->t_line].l_modem) 3176 (tp, com->prev_modem_status & MSR_DCD); 3177#ifdef PC98 3178 } 3179#endif 3180 } 3181 if (com->state & CS_ODONE) { 3182 mtx_lock_spin(&sio_lock); 3183 com_events -= LOTS_OF_EVENTS; 3184 com->state &= ~CS_ODONE; 3185 mtx_unlock_spin(&sio_lock); 3186 if (!(com->state & CS_BUSY) 3187 && !(com->extra_state & CSE_BUSYCHECK)) { 3188 timeout(siobusycheck, com, hz / 100); 3189 com->extra_state |= CSE_BUSYCHECK; 3190 } 3191 (*linesw[tp->t_line].l_start)(tp); 3192 } 3193 if (com_events == 0) 3194 break; 3195 } 3196 if (com_events >= LOTS_OF_EVENTS) 3197 goto repeat; 3198} 3199 3200static int 3201comparam(tp, t) 3202 struct tty *tp; 3203 struct termios *t; 3204{ 3205 u_int cfcr; 3206 int cflag; 3207 struct com_s *com; 3208 u_int divisor; 3209 u_char dlbh; 3210 u_char dlbl; 3211 int s; 3212 int unit; 3213#ifdef PC98 3214 u_char param = 0; 3215#endif 3216 3217 unit = DEV_TO_UNIT(tp->t_dev); 3218 com = com_addr(unit); 3219 if (com == NULL) 3220 return (ENODEV); 3221 3222#ifdef PC98 3223 cfcr = 0; 3224 3225 if (IS_8251(com->pc98_if_type)) { 3226 if (pc98_ttspeedtab(com, t->c_ospeed, &divisor) != 0) 3227 return (EINVAL); 3228 } else { 3229#endif 3230 /* do historical conversions */ 3231 if (t->c_ispeed == 0) 3232 t->c_ispeed = t->c_ospeed; 3233 3234 /* check requested parameters */ 3235 if (t->c_ospeed == 0) 3236 divisor = 0; 3237 else { 3238 if (t->c_ispeed != t->c_ospeed) 3239 return (EINVAL); 3240 divisor = siodivisor(com->rclk, t->c_ispeed); 3241 if (divisor == 0) 3242 return (EINVAL); 3243 } 3244#ifdef PC98 3245 } 3246#endif 3247 3248 /* parameters are OK, convert them to the com struct and the device */ 3249 s = spltty(); 3250#ifdef PC98 3251 if (IS_8251(com->pc98_if_type)) { 3252 if (divisor == 0) 3253 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 3254 else 3255 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 3256 } else 3257#endif 3258 if (divisor == 0) 3259 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */ 3260 else 3261 (void)commctl(com, TIOCM_DTR, DMBIS); 3262 cflag = t->c_cflag; 3263#ifdef PC98 3264 if (!IS_8251(com->pc98_if_type)) { 3265#endif 3266 switch (cflag & CSIZE) { 3267 case CS5: 3268 cfcr = CFCR_5BITS; 3269 break; 3270 case CS6: 3271 cfcr = CFCR_6BITS; 3272 break; 3273 case CS7: 3274 cfcr = CFCR_7BITS; 3275 break; 3276 default: 3277 cfcr = CFCR_8BITS; 3278 break; 3279 } 3280 if (cflag & PARENB) { 3281 cfcr |= CFCR_PENAB; 3282 if (!(cflag & PARODD)) 3283 cfcr |= CFCR_PEVEN; 3284 } 3285 if (cflag & CSTOPB) 3286 cfcr |= CFCR_STOPB; 3287 3288 if (com->hasfifo && divisor != 0) { 3289 /* 3290 * Use a fifo trigger level low enough so that the input 3291 * latency from the fifo is less than about 16 msec and 3292 * the total latency is less than about 30 msec. These 3293 * latencies are reasonable for humans. Serial comms 3294 * protocols shouldn't expect anything better since modem 3295 * latencies are larger. 3296 * 3297 * We have to set the FIFO trigger point such that we 3298 * don't overflow it accidently if a serial interrupt 3299 * is delayed. At high speeds, FIFO_RX_HIGH does not 3300 * leave enough slots free. 3301 */ 3302 com->fifo_image = t->c_ospeed <= 4800 3303 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_MEDH; 3304#ifdef COM_ESP 3305 /* 3306 * The Hayes ESP card needs the fifo DMA mode bit set 3307 * in compatibility mode. If not, it will interrupt 3308 * for each character received. 3309 */ 3310 if (com->esp) 3311 com->fifo_image |= FIFO_DMA_MODE; 3312#endif 3313 sio_setreg(com, com_fifo, com->fifo_image); 3314 } 3315#ifdef PC98 3316 } 3317#endif 3318 3319 /* 3320 * This returns with interrupts disabled so that we can complete 3321 * the speed change atomically. Keeping interrupts disabled is 3322 * especially important while com_data is hidden. 3323 */ 3324 (void) siosetwater(com, t->c_ispeed); 3325 3326#ifdef PC98 3327 if (IS_8251(com->pc98_if_type)) 3328 com_cflag_and_speed_set(com, cflag, t->c_ospeed); 3329 else { 3330#endif 3331 if (divisor != 0) { 3332 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB); 3333 /* 3334 * Only set the divisor registers if they would change, 3335 * since on some 16550 incompatibles (UMC8669F), setting 3336 * them while input is arriving them loses sync until 3337 * data stops arriving. 3338 */ 3339 dlbl = divisor & 0xFF; 3340 if (sio_getreg(com, com_dlbl) != dlbl) 3341 sio_setreg(com, com_dlbl, dlbl); 3342 dlbh = divisor >> 8; 3343 if (sio_getreg(com, com_dlbh) != dlbh) 3344 sio_setreg(com, com_dlbh, dlbh); 3345 } 3346 3347 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr); 3348#ifdef PC98 3349 } 3350#endif 3351 3352 if (!(tp->t_state & TS_TTSTOP)) 3353 com->state |= CS_TTGO; 3354 3355 if (cflag & CRTS_IFLOW) { 3356#ifndef PC98 3357 if (com->st16650a) { 3358 sio_setreg(com, com_cfcr, 0xbf); 3359 sio_setreg(com, com_fifo, 3360 sio_getreg(com, com_fifo) | 0x40); 3361 } 3362#endif 3363 com->state |= CS_RTS_IFLOW; 3364 /* 3365 * If CS_RTS_IFLOW just changed from off to on, the change 3366 * needs to be propagated to MCR_RTS. This isn't urgent, 3367 * so do it later by calling comstart() instead of repeating 3368 * a lot of code from comstart() here. 3369 */ 3370 } else if (com->state & CS_RTS_IFLOW) { 3371 com->state &= ~CS_RTS_IFLOW; 3372 /* 3373 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS 3374 * on here, since comstart() won't do it later. 3375 */ 3376#ifdef PC98 3377 if (IS_8251(com->pc98_if_type)) 3378 com_tiocm_bis(com, TIOCM_RTS); 3379 else 3380 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3381#else 3382 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3383 if (com->st16650a) { 3384 sio_setreg(com, com_cfcr, 0xbf); 3385 sio_setreg(com, com_fifo, 3386 sio_getreg(com, com_fifo) & ~0x40); 3387 } 3388#endif 3389 } 3390 3391 3392 /* 3393 * Set up state to handle output flow control. 3394 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level? 3395 * Now has 10+ msec latency, while CTS flow has 50- usec latency. 3396 */ 3397 com->state |= CS_ODEVREADY; 3398 com->state &= ~CS_CTS_OFLOW; 3399#ifdef PC98 3400 if (com->pc98_if_type == COM_IF_RSA98III) { 3401 param = inb(com->rsabase + rsa_msr); 3402 outb(com->rsabase + rsa_msr, param & 0x14); 3403 } 3404#endif 3405 if (cflag & CCTS_OFLOW) { 3406 com->state |= CS_CTS_OFLOW; 3407#ifdef PC98 3408 if (IS_8251(com->pc98_if_type)) { 3409 if (!(pc98_get_modem_status(com) & TIOCM_CTS)) 3410 com->state &= ~CS_ODEVREADY; 3411 } else { 3412 if (com->pc98_if_type == COM_IF_RSA98III) { 3413 /* Set automatic flow control mode */ 3414 outb(com->rsabase + rsa_msr, param | 0x08); 3415 } else 3416#endif 3417 if (!(com->last_modem_status & MSR_CTS)) 3418 com->state &= ~CS_ODEVREADY; 3419#ifdef PC98 3420 } 3421#else 3422 if (com->st16650a) { 3423 sio_setreg(com, com_cfcr, 0xbf); 3424 sio_setreg(com, com_fifo, 3425 sio_getreg(com, com_fifo) | 0x80); 3426 } 3427 } else { 3428 if (com->st16650a) { 3429 sio_setreg(com, com_cfcr, 0xbf); 3430 sio_setreg(com, com_fifo, 3431 sio_getreg(com, com_fifo) & ~0x80); 3432 } 3433#endif 3434 } 3435 3436#ifdef PC98 3437 if (!IS_8251(com->pc98_if_type)) 3438#endif 3439 sio_setreg(com, com_cfcr, com->cfcr_image); 3440 3441 /* XXX shouldn't call functions while intrs are disabled. */ 3442 disc_optim(tp, t, com); 3443 /* 3444 * Recover from fiddling with CS_TTGO. We used to call siointr1() 3445 * unconditionally, but that defeated the careful discarding of 3446 * stale input in sioopen(). 3447 */ 3448 if (com->state >= (CS_BUSY | CS_TTGO)) 3449 siointr1(com); 3450 3451 mtx_unlock_spin(&sio_lock); 3452 splx(s); 3453 comstart(tp); 3454 if (com->ibufold != NULL) { 3455 free(com->ibufold, M_DEVBUF); 3456 com->ibufold = NULL; 3457 } 3458 return (0); 3459} 3460 3461/* 3462 * This function must be called with the sio_lock mutex released and will 3463 * return with it obtained. 3464 */ 3465static int 3466siosetwater(com, speed) 3467 struct com_s *com; 3468 speed_t speed; 3469{ 3470 int cp4ticks; 3471 u_char *ibuf; 3472 int ibufsize; 3473 struct tty *tp; 3474 3475 /* 3476 * Make the buffer size large enough to handle a softtty interrupt 3477 * latency of about 2 ticks without loss of throughput or data 3478 * (about 3 ticks if input flow control is not used or not honoured, 3479 * but a bit less for CS5-CS7 modes). 3480 */ 3481 cp4ticks = speed / 10 / hz * 4; 3482 for (ibufsize = 128; ibufsize < cp4ticks;) 3483 ibufsize <<= 1; 3484#ifdef PC98 3485 if (com->pc98_if_type == COM_IF_RSA98III) 3486 ibufsize = 2048; 3487#endif 3488 if (ibufsize == com->ibufsize) { 3489 mtx_lock_spin(&sio_lock); 3490 return (0); 3491 } 3492 3493 /* 3494 * Allocate input buffer. The extra factor of 2 in the size is 3495 * to allow for an error byte for each input byte. 3496 */ 3497 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT); 3498 if (ibuf == NULL) { 3499 mtx_lock_spin(&sio_lock); 3500 return (ENOMEM); 3501 } 3502 3503 /* Initialize non-critical variables. */ 3504 com->ibufold = com->ibuf; 3505 com->ibufsize = ibufsize; 3506 tp = com->tp; 3507 if (tp != NULL) { 3508 tp->t_ififosize = 2 * ibufsize; 3509 tp->t_ispeedwat = (speed_t)-1; 3510 tp->t_ospeedwat = (speed_t)-1; 3511 } 3512 3513 /* 3514 * Read current input buffer, if any. Continue with interrupts 3515 * disabled. 3516 */ 3517 mtx_lock_spin(&sio_lock); 3518 if (com->iptr != com->ibuf) 3519 sioinput(com); 3520 3521 /*- 3522 * Initialize critical variables, including input buffer watermarks. 3523 * The external device is asked to stop sending when the buffer 3524 * exactly reaches high water, or when the high level requests it. 3525 * The high level is notified immediately (rather than at a later 3526 * clock tick) when this watermark is reached. 3527 * The buffer size is chosen so the watermark should almost never 3528 * be reached. 3529 * The low watermark is invisibly 0 since the buffer is always 3530 * emptied all at once. 3531 */ 3532 com->iptr = com->ibuf = ibuf; 3533 com->ibufend = ibuf + ibufsize; 3534 com->ierroff = ibufsize; 3535 com->ihighwater = ibuf + 3 * ibufsize / 4; 3536 return (0); 3537} 3538 3539static void 3540comstart(tp) 3541 struct tty *tp; 3542{ 3543 struct com_s *com; 3544 int s; 3545 int unit; 3546 3547 unit = DEV_TO_UNIT(tp->t_dev); 3548 com = com_addr(unit); 3549 if (com == NULL) 3550 return; 3551 s = spltty(); 3552 mtx_lock_spin(&sio_lock); 3553 if (tp->t_state & TS_TTSTOP) 3554 com->state &= ~CS_TTGO; 3555 else 3556 com->state |= CS_TTGO; 3557 if (tp->t_state & TS_TBLOCK) { 3558#ifdef PC98 3559 if (IS_8251(com->pc98_if_type)) { 3560 if ((com_tiocm_get(com) & TIOCM_RTS) && 3561 (com->state & CS_RTS_IFLOW)) 3562 com_tiocm_bic(com, TIOCM_RTS); 3563 } else { 3564 if ((com->mcr_image & MCR_RTS) && 3565 (com->state & CS_RTS_IFLOW)) 3566 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3567 } 3568#else 3569 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW) 3570 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3571#endif 3572 } else { 3573#ifdef PC98 3574 if (IS_8251(com->pc98_if_type)) { 3575 if (!(com_tiocm_get(com) & TIOCM_RTS) && 3576 com->iptr < com->ihighwater && 3577 com->state & CS_RTS_IFLOW) 3578 com_tiocm_bis(com, TIOCM_RTS); 3579 } else { 3580 if (!(com->mcr_image & MCR_RTS) && 3581 com->iptr < com->ihighwater && 3582 com->state & CS_RTS_IFLOW) 3583 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3584 } 3585#else 3586 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater 3587 && com->state & CS_RTS_IFLOW) 3588 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3589#endif 3590 } 3591 mtx_unlock_spin(&sio_lock); 3592 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) { 3593 ttwwakeup(tp); 3594 splx(s); 3595 return; 3596 } 3597 if (tp->t_outq.c_cc != 0) { 3598 struct lbq *qp; 3599 struct lbq *next; 3600 3601 if (!com->obufs[0].l_queued) { 3602 com->obufs[0].l_tail 3603 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1, 3604#ifdef PC98 3605 com->obufsize); 3606#else 3607 sizeof com->obuf1); 3608#endif 3609 com->obufs[0].l_next = NULL; 3610 com->obufs[0].l_queued = TRUE; 3611 mtx_lock_spin(&sio_lock); 3612 if (com->state & CS_BUSY) { 3613 qp = com->obufq.l_next; 3614 while ((next = qp->l_next) != NULL) 3615 qp = next; 3616 qp->l_next = &com->obufs[0]; 3617 } else { 3618 com->obufq.l_head = com->obufs[0].l_head; 3619 com->obufq.l_tail = com->obufs[0].l_tail; 3620 com->obufq.l_next = &com->obufs[0]; 3621 com->state |= CS_BUSY; 3622 } 3623 mtx_unlock_spin(&sio_lock); 3624 } 3625 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) { 3626 com->obufs[1].l_tail 3627 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2, 3628#ifdef PC98 3629 com->obufsize); 3630#else 3631 sizeof com->obuf2); 3632#endif 3633 com->obufs[1].l_next = NULL; 3634 com->obufs[1].l_queued = TRUE; 3635 mtx_lock_spin(&sio_lock); 3636 if (com->state & CS_BUSY) { 3637 qp = com->obufq.l_next; 3638 while ((next = qp->l_next) != NULL) 3639 qp = next; 3640 qp->l_next = &com->obufs[1]; 3641 } else { 3642 com->obufq.l_head = com->obufs[1].l_head; 3643 com->obufq.l_tail = com->obufs[1].l_tail; 3644 com->obufq.l_next = &com->obufs[1]; 3645 com->state |= CS_BUSY; 3646 } 3647 mtx_unlock_spin(&sio_lock); 3648 } 3649 tp->t_state |= TS_BUSY; 3650 } 3651 mtx_lock_spin(&sio_lock); 3652 if (com->state >= (CS_BUSY | CS_TTGO)) 3653 siointr1(com); /* fake interrupt to start output */ 3654 mtx_unlock_spin(&sio_lock); 3655 ttwwakeup(tp); 3656 splx(s); 3657} 3658 3659static void 3660comstop(tp, rw) 3661 struct tty *tp; 3662 int rw; 3663{ 3664 struct com_s *com; 3665#ifdef PC98 3666 int rsa98_tmp = 0; 3667#endif 3668 3669 com = com_addr(DEV_TO_UNIT(tp->t_dev)); 3670 if (com == NULL || com->gone) 3671 return; 3672 mtx_lock_spin(&sio_lock); 3673 if (rw & FWRITE) { 3674#ifdef PC98 3675 if (!IS_8251(com->pc98_if_type)) { 3676#endif 3677 if (com->hasfifo) 3678#ifdef COM_ESP 3679 /* XXX avoid h/w bug. */ 3680 if (!com->esp) 3681#endif 3682 sio_setreg(com, com_fifo, 3683 FIFO_XMT_RST | com->fifo_image); 3684#ifdef PC98 3685 if (com->pc98_if_type == COM_IF_RSA98III) 3686 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3687 sio_setreg(com, com_fifo, 3688 FIFO_XMT_RST | com->fifo_image); 3689 } 3690#endif 3691 com->obufs[0].l_queued = FALSE; 3692 com->obufs[1].l_queued = FALSE; 3693 if (com->state & CS_ODONE) 3694 com_events -= LOTS_OF_EVENTS; 3695 com->state &= ~(CS_ODONE | CS_BUSY); 3696 com->tp->t_state &= ~TS_BUSY; 3697 } 3698 if (rw & FREAD) { 3699#ifdef PC98 3700 if (!IS_8251(com->pc98_if_type)) { 3701 if (com->pc98_if_type == COM_IF_RSA98III) 3702 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3703 sio_getreg(com, com_data); 3704#endif 3705 if (com->hasfifo) 3706#ifdef COM_ESP 3707 /* XXX avoid h/w bug. */ 3708 if (!com->esp) 3709#endif 3710 sio_setreg(com, com_fifo, 3711 FIFO_RCV_RST | com->fifo_image); 3712#ifdef PC98 3713 } 3714#endif 3715 com_events -= (com->iptr - com->ibuf); 3716 com->iptr = com->ibuf; 3717 } 3718 mtx_unlock_spin(&sio_lock); 3719 comstart(tp); 3720} 3721 3722static int 3723commctl(com, bits, how) 3724 struct com_s *com; 3725 int bits; 3726 int how; 3727{ 3728 int mcr; 3729 int msr; 3730 3731 if (how == DMGET) { 3732 bits = TIOCM_LE; /* XXX - always enabled while open */ 3733 mcr = com->mcr_image; 3734 if (mcr & MCR_DTR) 3735 bits |= TIOCM_DTR; 3736 if (mcr & MCR_RTS) 3737 bits |= TIOCM_RTS; 3738 msr = com->prev_modem_status; 3739 if (msr & MSR_CTS) 3740 bits |= TIOCM_CTS; 3741 if (msr & MSR_DCD) 3742 bits |= TIOCM_CD; 3743 if (msr & MSR_DSR) 3744 bits |= TIOCM_DSR; 3745 /* 3746 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI 3747 * more volatile by reading the modem status a lot. Perhaps 3748 * we should latch both bits until the status is read here. 3749 */ 3750 if (msr & (MSR_RI | MSR_TERI)) 3751 bits |= TIOCM_RI; 3752 return (bits); 3753 } 3754 mcr = 0; 3755 if (bits & TIOCM_DTR) 3756 mcr |= MCR_DTR; 3757 if (bits & TIOCM_RTS) 3758 mcr |= MCR_RTS; 3759 if (com->gone) 3760 return(0); 3761 mtx_lock_spin(&sio_lock); 3762 switch (how) { 3763 case DMSET: 3764 outb(com->modem_ctl_port, 3765 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE)); 3766 break; 3767 case DMBIS: 3768 outb(com->modem_ctl_port, com->mcr_image |= mcr); 3769 break; 3770 case DMBIC: 3771 outb(com->modem_ctl_port, com->mcr_image &= ~mcr); 3772 break; 3773 } 3774 mtx_unlock_spin(&sio_lock); 3775 return (0); 3776} 3777 3778static void 3779siosettimeout() 3780{ 3781 struct com_s *com; 3782 bool_t someopen; 3783 int unit; 3784 3785 /* 3786 * Set our timeout period to 1 second if no polled devices are open. 3787 * Otherwise set it to max(1/200, 1/hz). 3788 * Enable timeouts iff some device is open. 3789 */ 3790 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 3791 sio_timeout = hz; 3792 someopen = FALSE; 3793 for (unit = 0; unit < sio_numunits; ++unit) { 3794 com = com_addr(unit); 3795 if (com != NULL && com->tp != NULL 3796 && com->tp->t_state & TS_ISOPEN && !com->gone) { 3797 someopen = TRUE; 3798 if (com->poll || com->poll_output) { 3799 sio_timeout = hz > 200 ? hz / 200 : 1; 3800 break; 3801 } 3802 } 3803 } 3804 if (someopen) { 3805 sio_timeouts_until_log = hz / sio_timeout; 3806 sio_timeout_handle = timeout(comwakeup, (void *)NULL, 3807 sio_timeout); 3808 } else { 3809 /* Flush error messages, if any. */ 3810 sio_timeouts_until_log = 1; 3811 comwakeup((void *)NULL); 3812 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 3813 } 3814} 3815 3816static void 3817comwakeup(chan) 3818 void *chan; 3819{ 3820 struct com_s *com; 3821 int unit; 3822 3823 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout); 3824 3825 /* 3826 * Recover from lost output interrupts. 3827 * Poll any lines that don't use interrupts. 3828 */ 3829 for (unit = 0; unit < sio_numunits; ++unit) { 3830 com = com_addr(unit); 3831 if (com != NULL && !com->gone 3832 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) { 3833 mtx_lock_spin(&sio_lock); 3834 siointr1(com); 3835 mtx_unlock_spin(&sio_lock); 3836 } 3837 } 3838 3839 /* 3840 * Check for and log errors, but not too often. 3841 */ 3842 if (--sio_timeouts_until_log > 0) 3843 return; 3844 sio_timeouts_until_log = hz / sio_timeout; 3845 for (unit = 0; unit < sio_numunits; ++unit) { 3846 int errnum; 3847 3848 com = com_addr(unit); 3849 if (com == NULL) 3850 continue; 3851 if (com->gone) 3852 continue; 3853 for (errnum = 0; errnum < CE_NTYPES; ++errnum) { 3854 u_int delta; 3855 u_long total; 3856 3857 mtx_lock_spin(&sio_lock); 3858 delta = com->delta_error_counts[errnum]; 3859 com->delta_error_counts[errnum] = 0; 3860 mtx_unlock_spin(&sio_lock); 3861 if (delta == 0) 3862 continue; 3863 total = com->error_counts[errnum] += delta; 3864 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n", 3865 unit, delta, error_desc[errnum], 3866 delta == 1 ? "" : "s", total); 3867 } 3868 } 3869} 3870 3871#ifdef PC98 3872/* commint is called when modem control line changes */ 3873static void 3874commint(dev_t dev) 3875{ 3876 register struct tty *tp; 3877 int stat,delta; 3878 struct com_s *com; 3879 int mynor,unit; 3880 3881 mynor = minor(dev); 3882 unit = MINOR_TO_UNIT(mynor); 3883 com = com_addr(unit); 3884 tp = com->tp; 3885 3886 stat = com_tiocm_get(com); 3887 delta = com_tiocm_get_delta(com); 3888 3889 if (com->state & CS_CTS_OFLOW) { 3890 if (stat & TIOCM_CTS) 3891 com->state |= CS_ODEVREADY; 3892 else 3893 com->state &= ~CS_ODEVREADY; 3894 } 3895 if ((delta & TIOCM_CAR) && (mynor & CALLOUT_MASK) == 0) { 3896 if (stat & TIOCM_CAR ) 3897 (void)(*linesw[tp->t_line].l_modem)(tp, 1); 3898 else if ((*linesw[tp->t_line].l_modem)(tp, 0) == 0) { 3899 /* negate DTR, RTS */ 3900 com_tiocm_bic(com, (tp->t_cflag & HUPCL) ? 3901 TIOCM_DTR|TIOCM_RTS|TIOCM_LE : TIOCM_LE ); 3902 /* disable IENABLE */ 3903 com_int_TxRx_disable( com ); 3904 } 3905 } 3906} 3907#endif 3908 3909static void 3910disc_optim(tp, t, com) 3911 struct tty *tp; 3912 struct termios *t; 3913 struct com_s *com; 3914{ 3915 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 3916 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 3917 && (!(t->c_iflag & PARMRK) 3918 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 3919 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 3920 && linesw[tp->t_line].l_rint == ttyinput) 3921 tp->t_state |= TS_CAN_BYPASS_L_RINT; 3922 else 3923 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 3924 com->hotchar = linesw[tp->t_line].l_hotchar; 3925} 3926 3927/* 3928 * Following are all routines needed for SIO to act as console 3929 */ 3930#include <sys/cons.h> 3931 3932struct siocnstate { 3933 u_char dlbl; 3934 u_char dlbh; 3935 u_char ier; 3936 u_char cfcr; 3937 u_char mcr; 3938}; 3939 3940#ifndef __alpha__ 3941static speed_t siocngetspeed(Port_t, u_long rclk); 3942#endif 3943static void siocnclose(struct siocnstate *sp, Port_t iobase); 3944static void siocnopen(struct siocnstate *sp, Port_t iobase, int speed); 3945static void siocntxwait(Port_t iobase); 3946 3947#ifdef __alpha__ 3948int siocnattach(int port, int speed); 3949int siogdbattach(int port, int speed); 3950int siogdbgetc(void); 3951void siogdbputc(int c); 3952#else 3953static cn_probe_t siocnprobe; 3954static cn_init_t siocninit; 3955static cn_term_t siocnterm; 3956#endif 3957static cn_checkc_t siocncheckc; 3958static cn_getc_t siocngetc; 3959static cn_putc_t siocnputc; 3960 3961#ifndef __alpha__ 3962CONS_DRIVER(sio, siocnprobe, siocninit, siocnterm, siocngetc, siocncheckc, 3963 siocnputc, NULL); 3964#endif 3965 3966/* To get the GDB related variables */ 3967#if DDB > 0 3968#include <ddb/ddb.h> 3969#endif 3970 3971static void 3972siocntxwait(iobase) 3973 Port_t iobase; 3974{ 3975 int timo; 3976 3977 /* 3978 * Wait for any pending transmission to finish. Required to avoid 3979 * the UART lockup bug when the speed is changed, and for normal 3980 * transmits. 3981 */ 3982 timo = 100000; 3983 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY)) 3984 != (LSR_TSRE | LSR_TXRDY) && --timo != 0) 3985 ; 3986} 3987 3988#ifndef __alpha__ 3989 3990/* 3991 * Read the serial port specified and try to figure out what speed 3992 * it's currently running at. We're assuming the serial port has 3993 * been initialized and is basicly idle. This routine is only intended 3994 * to be run at system startup. 3995 * 3996 * If the value read from the serial port doesn't make sense, return 0. 3997 */ 3998 3999static speed_t 4000siocngetspeed(iobase, rclk) 4001 Port_t iobase; 4002 u_long rclk; 4003{ 4004 u_int divisor; 4005 u_char dlbh; 4006 u_char dlbl; 4007 u_char cfcr; 4008 4009 cfcr = inb(iobase + com_cfcr); 4010 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 4011 4012 dlbl = inb(iobase + com_dlbl); 4013 dlbh = inb(iobase + com_dlbh); 4014 4015 outb(iobase + com_cfcr, cfcr); 4016 4017 divisor = dlbh << 8 | dlbl; 4018 4019 /* XXX there should be more sanity checking. */ 4020 if (divisor == 0) 4021 return (CONSPEED); 4022 return (rclk / (16UL * divisor)); 4023} 4024 4025#endif 4026 4027static void 4028siocnopen(sp, iobase, speed) 4029 struct siocnstate *sp; 4030 Port_t iobase; 4031 int speed; 4032{ 4033 u_int divisor; 4034 u_char dlbh; 4035 u_char dlbl; 4036 4037 /* 4038 * Save all the device control registers except the fifo register 4039 * and set our default ones (cs8 -parenb speed=comdefaultrate). 4040 * We can't save the fifo register since it is read-only. 4041 */ 4042 sp->ier = inb(iobase + com_ier); 4043 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */ 4044 siocntxwait(iobase); 4045 sp->cfcr = inb(iobase + com_cfcr); 4046 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 4047 sp->dlbl = inb(iobase + com_dlbl); 4048 sp->dlbh = inb(iobase + com_dlbh); 4049 /* 4050 * Only set the divisor registers if they would change, since on 4051 * some 16550 incompatibles (Startech), setting them clears the 4052 * data input register. This also reduces the effects of the 4053 * UMC8669F bug. 4054 */ 4055 divisor = siodivisor(comdefaultrclk, speed); 4056 dlbl = divisor & 0xFF; 4057 if (sp->dlbl != dlbl) 4058 outb(iobase + com_dlbl, dlbl); 4059 dlbh = divisor >> 8; 4060 if (sp->dlbh != dlbh) 4061 outb(iobase + com_dlbh, dlbh); 4062 outb(iobase + com_cfcr, CFCR_8BITS); 4063 sp->mcr = inb(iobase + com_mcr); 4064 /* 4065 * We don't want interrupts, but must be careful not to "disable" 4066 * them by clearing the MCR_IENABLE bit, since that might cause 4067 * an interrupt by floating the IRQ line. 4068 */ 4069 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS); 4070} 4071 4072static void 4073siocnclose(sp, iobase) 4074 struct siocnstate *sp; 4075 Port_t iobase; 4076{ 4077 /* 4078 * Restore the device control registers. 4079 */ 4080 siocntxwait(iobase); 4081 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 4082 if (sp->dlbl != inb(iobase + com_dlbl)) 4083 outb(iobase + com_dlbl, sp->dlbl); 4084 if (sp->dlbh != inb(iobase + com_dlbh)) 4085 outb(iobase + com_dlbh, sp->dlbh); 4086 outb(iobase + com_cfcr, sp->cfcr); 4087 /* 4088 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them. 4089 */ 4090 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS); 4091 outb(iobase + com_ier, sp->ier); 4092} 4093 4094#ifndef __alpha__ 4095 4096static void 4097siocnprobe(cp) 4098 struct consdev *cp; 4099{ 4100 speed_t boot_speed; 4101 u_char cfcr; 4102 u_int divisor; 4103 int s, unit; 4104 struct siocnstate sp; 4105 4106 /* 4107 * Find our first enabled console, if any. If it is a high-level 4108 * console device, then initialize it and return successfully. 4109 * If it is a low-level console device, then initialize it and 4110 * return unsuccessfully. It must be initialized in both cases 4111 * for early use by console drivers and debuggers. Initializing 4112 * the hardware is not necessary in all cases, since the i/o 4113 * routines initialize it on the fly, but it is necessary if 4114 * input might arrive while the hardware is switched back to an 4115 * uninitialized state. We can't handle multiple console devices 4116 * yet because our low-level routines don't take a device arg. 4117 * We trust the user to set the console flags properly so that we 4118 * don't need to probe. 4119 */ 4120 cp->cn_pri = CN_DEAD; 4121 4122 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */ 4123 int flags; 4124 int disabled; 4125 if (resource_int_value("sio", unit, "disabled", &disabled) == 0) { 4126 if (disabled) 4127 continue; 4128 } 4129 if (resource_int_value("sio", unit, "flags", &flags)) 4130 continue; 4131 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) { 4132 int port; 4133 Port_t iobase; 4134 4135 if (resource_int_value("sio", unit, "port", &port)) 4136 continue; 4137 iobase = port; 4138 s = spltty(); 4139 if (boothowto & RB_SERIAL) { 4140 boot_speed = 4141 siocngetspeed(iobase, comdefaultrclk); 4142 if (boot_speed) 4143 comdefaultrate = boot_speed; 4144 } 4145 4146 /* 4147 * Initialize the divisor latch. We can't rely on 4148 * siocnopen() to do this the first time, since it 4149 * avoids writing to the latch if the latch appears 4150 * to have the correct value. Also, if we didn't 4151 * just read the speed from the hardware, then we 4152 * need to set the speed in hardware so that 4153 * switching it later is null. 4154 */ 4155 cfcr = inb(iobase + com_cfcr); 4156 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 4157 divisor = siodivisor(comdefaultrclk, comdefaultrate); 4158 outb(iobase + com_dlbl, divisor & 0xff); 4159 outb(iobase + com_dlbh, divisor >> 8); 4160 outb(iobase + com_cfcr, cfcr); 4161 4162 siocnopen(&sp, iobase, comdefaultrate); 4163 4164 splx(s); 4165 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) { 4166 cp->cn_dev = makedev(CDEV_MAJOR, unit); 4167 cp->cn_pri = COM_FORCECONSOLE(flags) 4168 || boothowto & RB_SERIAL 4169 ? CN_REMOTE : CN_NORMAL; 4170 siocniobase = iobase; 4171 siocnunit = unit; 4172 } 4173 if (COM_DEBUGGER(flags)) { 4174 printf("sio%d: gdb debugging port\n", unit); 4175 siogdbiobase = iobase; 4176 siogdbunit = unit; 4177#if DDB > 0 4178 gdbdev = makedev(CDEV_MAJOR, unit); 4179 gdb_getc = siocngetc; 4180 gdb_putc = siocnputc; 4181#endif 4182 } 4183 } 4184 } 4185#ifdef __i386__ 4186#if DDB > 0 4187 /* 4188 * XXX Ugly Compatability. 4189 * If no gdb port has been specified, set it to be the console 4190 * as some configuration files don't specify the gdb port. 4191 */ 4192 if (gdbdev == NODEV && (boothowto & RB_GDB)) { 4193 printf("Warning: no GDB port specified. Defaulting to sio%d.\n", 4194 siocnunit); 4195 printf("Set flag 0x80 on desired GDB port in your\n"); 4196 printf("configuration file (currently sio only).\n"); 4197 siogdbiobase = siocniobase; 4198 siogdbunit = siocnunit; 4199 gdbdev = makedev(CDEV_MAJOR, siocnunit); 4200 gdb_getc = siocngetc; 4201 gdb_putc = siocnputc; 4202 } 4203#endif 4204#endif 4205} 4206 4207static void 4208siocninit(cp) 4209 struct consdev *cp; 4210{ 4211 comconsole = DEV_TO_UNIT(cp->cn_dev); 4212} 4213 4214static void 4215siocnterm(cp) 4216 struct consdev *cp; 4217{ 4218 comconsole = -1; 4219} 4220 4221#endif 4222 4223#ifdef __alpha__ 4224 4225CONS_DRIVER(sio, NULL, NULL, NULL, siocngetc, siocncheckc, siocnputc, NULL); 4226 4227int 4228siocnattach(port, speed) 4229 int port; 4230 int speed; 4231{ 4232 int s; 4233 u_char cfcr; 4234 u_int divisor; 4235 struct siocnstate sp; 4236 4237 siocniobase = port; 4238 comdefaultrate = speed; 4239 sio_consdev.cn_pri = CN_NORMAL; 4240 sio_consdev.cn_dev = makedev(CDEV_MAJOR, 0); 4241 4242 s = spltty(); 4243 4244 /* 4245 * Initialize the divisor latch. We can't rely on 4246 * siocnopen() to do this the first time, since it 4247 * avoids writing to the latch if the latch appears 4248 * to have the correct value. Also, if we didn't 4249 * just read the speed from the hardware, then we 4250 * need to set the speed in hardware so that 4251 * switching it later is null. 4252 */ 4253 cfcr = inb(siocniobase + com_cfcr); 4254 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr); 4255 divisor = siodivisor(comdefaultrclk, comdefaultrate); 4256 outb(siocniobase + com_dlbl, divisor & 0xff); 4257 outb(siocniobase + com_dlbh, divisor >> 8); 4258 outb(siocniobase + com_cfcr, cfcr); 4259 4260 siocnopen(&sp, siocniobase, comdefaultrate); 4261 splx(s); 4262 4263 cnadd(&sio_consdev); 4264 return (0); 4265} 4266 4267int 4268siogdbattach(port, speed) 4269 int port; 4270 int speed; 4271{ 4272 int s; 4273 u_char cfcr; 4274 u_int divisor; 4275 struct siocnstate sp; 4276 int unit = 1; /* XXX !!! */ 4277 4278 siogdbiobase = port; 4279 gdbdefaultrate = speed; 4280 4281 printf("sio%d: gdb debugging port\n", unit); 4282 siogdbunit = unit; 4283#if DDB > 0 4284 gdbdev = makedev(CDEV_MAJOR, unit); 4285 gdb_getc = siocngetc; 4286 gdb_putc = siocnputc; 4287#endif 4288 4289 s = spltty(); 4290 4291 /* 4292 * Initialize the divisor latch. We can't rely on 4293 * siocnopen() to do this the first time, since it 4294 * avoids writing to the latch if the latch appears 4295 * to have the correct value. Also, if we didn't 4296 * just read the speed from the hardware, then we 4297 * need to set the speed in hardware so that 4298 * switching it later is null. 4299 */ 4300 cfcr = inb(siogdbiobase + com_cfcr); 4301 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr); 4302 divisor = siodivisor(comdefaultrclk, gdbdefaultrate); 4303 outb(siogdbiobase + com_dlbl, divisor & 0xff); 4304 outb(siogdbiobase + com_dlbh, divisor >> 8); 4305 outb(siogdbiobase + com_cfcr, cfcr); 4306 4307 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 4308 splx(s); 4309 4310 return (0); 4311} 4312 4313#endif 4314 4315static int 4316siocncheckc(dev) 4317 dev_t dev; 4318{ 4319 int c; 4320 Port_t iobase; 4321 int s; 4322 struct siocnstate sp; 4323 4324 if (minor(dev) == siogdbunit) 4325 iobase = siogdbiobase; 4326 else 4327 iobase = siocniobase; 4328 s = spltty(); 4329 siocnopen(&sp, iobase, comdefaultrate); 4330 if (inb(iobase + com_lsr) & LSR_RXRDY) 4331 c = inb(iobase + com_data); 4332 else 4333 c = -1; 4334 siocnclose(&sp, iobase); 4335 splx(s); 4336 return (c); 4337} 4338 4339 4340int 4341siocngetc(dev) 4342 dev_t dev; 4343{ 4344 int c; 4345 Port_t iobase; 4346 int s; 4347 struct siocnstate sp; 4348 4349 if (minor(dev) == siogdbunit) 4350 iobase = siogdbiobase; 4351 else 4352 iobase = siocniobase; 4353 s = spltty(); 4354 siocnopen(&sp, iobase, comdefaultrate); 4355 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 4356 ; 4357 c = inb(iobase + com_data); 4358 siocnclose(&sp, iobase); 4359 splx(s); 4360 return (c); 4361} 4362 4363void 4364siocnputc(dev, c) 4365 dev_t dev; 4366 int c; 4367{ 4368 int need_unlock; 4369 int s; 4370 struct siocnstate sp; 4371 Port_t iobase; 4372 4373 if (minor(dev) == siogdbunit) 4374 iobase = siogdbiobase; 4375 else 4376 iobase = siocniobase; 4377 s = spltty(); 4378 need_unlock = 0; 4379 if (sio_inited == 2 && !mtx_owned(&sio_lock)) { 4380 mtx_lock_spin(&sio_lock); 4381 need_unlock = 1; 4382 } 4383 siocnopen(&sp, iobase, comdefaultrate); 4384 siocntxwait(iobase); 4385 outb(iobase + com_data, c); 4386 siocnclose(&sp, iobase); 4387 if (need_unlock) 4388 mtx_unlock_spin(&sio_lock); 4389 splx(s); 4390} 4391 4392#ifdef __alpha__ 4393int 4394siogdbgetc() 4395{ 4396 int c; 4397 Port_t iobase; 4398 int s; 4399 struct siocnstate sp; 4400 4401 iobase = siogdbiobase; 4402 s = spltty(); 4403 siocnopen(&sp, iobase, gdbdefaultrate); 4404 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 4405 ; 4406 c = inb(iobase + com_data); 4407 siocnclose(&sp, iobase); 4408 splx(s); 4409 return (c); 4410} 4411 4412void 4413siogdbputc(c) 4414 int c; 4415{ 4416 int s; 4417 struct siocnstate sp; 4418 4419 s = spltty(); 4420 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 4421 siocntxwait(siogdbiobase); 4422 outb(siogdbiobase + com_data, c); 4423 siocnclose(&sp, siogdbiobase); 4424 splx(s); 4425} 4426#endif 4427 4428#ifdef PC98 4429/* 4430 * pc98 local function 4431 */ 4432 4433static void 4434com_tiocm_set(struct com_s *com, int msr) 4435{ 4436 int s; 4437 int tmp = 0; 4438 int mask = CMD8251_TxEN|CMD8251_RxEN|CMD8251_DTR|CMD8251_RTS; 4439 4440 s=spltty(); 4441 com->pc98_prev_modem_status = ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ) 4442 | ( com->pc98_prev_modem_status & ~(TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4443 tmp |= (CMD8251_TxEN|CMD8251_RxEN); 4444 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4445 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4446 pc98_i8251_clear_or_cmd( com, mask, tmp ); 4447 splx(s); 4448} 4449 4450static void 4451com_tiocm_bis(struct com_s *com, int msr) 4452{ 4453 int s; 4454 int tmp = 0; 4455 4456 s=spltty(); 4457 com->pc98_prev_modem_status |= ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4458 tmp |= CMD8251_TxEN|CMD8251_RxEN; 4459 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4460 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4461 4462 pc98_i8251_or_cmd( com, tmp ); 4463 splx(s); 4464} 4465 4466static void 4467com_tiocm_bic(struct com_s *com, int msr) 4468{ 4469 int s; 4470 int tmp = msr; 4471 4472 s=spltty(); 4473 com->pc98_prev_modem_status &= ~( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4474 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4475 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4476 4477 pc98_i8251_clear_cmd( com, tmp ); 4478 splx(s); 4479} 4480 4481static int 4482com_tiocm_get(struct com_s *com) 4483{ 4484 return( com->pc98_prev_modem_status ); 4485} 4486 4487static int 4488com_tiocm_get_delta(struct com_s *com) 4489{ 4490 int tmp; 4491 4492 tmp = com->pc98_modem_delta; 4493 com->pc98_modem_delta = 0; 4494 return( tmp ); 4495} 4496 4497/* convert to TIOCM_?? ( ioctl.h ) */ 4498static int 4499pc98_get_modem_status(struct com_s *com) 4500{ 4501 register int msr; 4502 4503 msr = com->pc98_prev_modem_status 4504 & ~(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 4505 if (com->pc98_8251fifo_enable) { 4506 int stat2; 4507 4508 stat2 = inb(I8251F_msr); 4509 if ( stat2 & CICSCDF_CD ) msr |= TIOCM_CAR; 4510 if ( stat2 & CICSCDF_CI ) msr |= TIOCM_RI; 4511 if ( stat2 & CICSCDF_DR ) msr |= TIOCM_DSR; 4512 if ( stat2 & CICSCDF_CS ) msr |= TIOCM_CTS; 4513#if COM_CARRIER_DETECT_EMULATE 4514 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 4515 msr |= TIOCM_CAR; 4516 } 4517#endif 4518 } else { 4519 int stat, stat2; 4520 4521 stat = inb(com->sts_port); 4522 stat2 = inb(com->in_modem_port); 4523 if ( !(stat2 & CICSCD_CD) ) msr |= TIOCM_CAR; 4524 if ( !(stat2 & CICSCD_CI) ) msr |= TIOCM_RI; 4525 if ( stat & STS8251_DSR ) msr |= TIOCM_DSR; 4526 if ( !(stat2 & CICSCD_CS) ) msr |= TIOCM_CTS; 4527#if COM_CARRIER_DETECT_EMULATE 4528 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 4529 msr |= TIOCM_CAR; 4530 } 4531#endif 4532 } 4533 return(msr); 4534} 4535 4536static void 4537pc98_check_msr(void* chan) 4538{ 4539 int msr, delta; 4540 int s; 4541 register struct tty *tp; 4542 struct com_s *com; 4543 int mynor; 4544 int unit; 4545 dev_t dev; 4546 4547 dev=(dev_t)chan; 4548 mynor = minor(dev); 4549 unit = MINOR_TO_UNIT(mynor); 4550 com = com_addr(unit); 4551 tp = com->tp; 4552 4553 s = spltty(); 4554 msr = pc98_get_modem_status(com); 4555 /* make change flag */ 4556 delta = msr ^ com->pc98_prev_modem_status; 4557 if ( delta & TIOCM_CAR ) { 4558 if ( com->modem_car_chg_timer ) { 4559 if ( -- com->modem_car_chg_timer ) 4560 msr ^= TIOCM_CAR; 4561 } else { 4562 if ((com->modem_car_chg_timer = (msr & TIOCM_CAR) ? 4563 DCD_ON_RECOGNITION : DCD_OFF_TOLERANCE) != 0) 4564 msr ^= TIOCM_CAR; 4565 } 4566 } else 4567 com->modem_car_chg_timer = 0; 4568 delta = ( msr ^ com->pc98_prev_modem_status ) & 4569 (TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 4570 com->pc98_prev_modem_status = msr; 4571 delta = ( com->pc98_modem_delta |= delta ); 4572 splx(s); 4573 if ( com->modem_checking || (tp->t_state & (TS_ISOPEN)) ) { 4574 if ( delta ) { 4575 commint(dev); 4576 } 4577 timeout(pc98_check_msr, (caddr_t)dev, 4578 PC98_CHECK_MODEM_INTERVAL); 4579 } else { 4580 com->modem_checking = 0; 4581 } 4582} 4583 4584static void 4585pc98_msrint_start(dev_t dev) 4586{ 4587 struct com_s *com; 4588 int mynor; 4589 int unit; 4590 int s = spltty(); 4591 4592 mynor = minor(dev); 4593 unit = MINOR_TO_UNIT(mynor); 4594 com = com_addr(unit); 4595 /* modem control line check routine envoke interval is 1/10 sec */ 4596 if ( com->modem_checking == 0 ) { 4597 com->pc98_prev_modem_status = pc98_get_modem_status(com); 4598 com->pc98_modem_delta = 0; 4599 timeout(pc98_check_msr, (caddr_t)dev, 4600 PC98_CHECK_MODEM_INTERVAL); 4601 com->modem_checking = 1; 4602 } 4603 splx(s); 4604} 4605 4606static void 4607pc98_disable_i8251_interrupt(struct com_s *com, int mod) 4608{ 4609 /* disable interrupt */ 4610 register int tmp; 4611 4612 mod |= ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4613 COM_INT_DISABLE 4614 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4615 outb( com->intr_ctrl_port, (com->intr_enable&=~mod) | tmp ); 4616 COM_INT_ENABLE 4617} 4618 4619static void 4620pc98_enable_i8251_interrupt(struct com_s *com, int mod) 4621{ 4622 register int tmp; 4623 4624 COM_INT_DISABLE 4625 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4626 outb( com->intr_ctrl_port, (com->intr_enable|=mod) | tmp ); 4627 COM_INT_ENABLE 4628} 4629 4630static int 4631pc98_check_i8251_interrupt(struct com_s *com) 4632{ 4633 return ( com->intr_enable & 0x07 ); 4634} 4635 4636static void 4637pc98_i8251_clear_cmd(struct com_s *com, int x) 4638{ 4639 int tmp; 4640 4641 COM_INT_DISABLE 4642 tmp = com->pc98_prev_siocmd & ~(x); 4643 if (com->pc98_8251fifo_enable) 4644 outb(I8251F_fcr, 0); 4645 outb(com->cmd_port, tmp); 4646 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4647 if (com->pc98_8251fifo_enable) 4648 outb(I8251F_fcr, CTRL8251F_ENABLE); 4649 COM_INT_ENABLE 4650} 4651 4652static void 4653pc98_i8251_or_cmd(struct com_s *com, int x) 4654{ 4655 int tmp; 4656 4657 COM_INT_DISABLE 4658 if (com->pc98_8251fifo_enable) 4659 outb(I8251F_fcr, 0); 4660 tmp = com->pc98_prev_siocmd | (x); 4661 outb(com->cmd_port, tmp); 4662 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4663 if (com->pc98_8251fifo_enable) 4664 outb(I8251F_fcr, CTRL8251F_ENABLE); 4665 COM_INT_ENABLE 4666} 4667 4668static void 4669pc98_i8251_set_cmd(struct com_s *com, int x) 4670{ 4671 int tmp; 4672 4673 COM_INT_DISABLE 4674 if (com->pc98_8251fifo_enable) 4675 outb(I8251F_fcr, 0); 4676 tmp = (x); 4677 outb(com->cmd_port, tmp); 4678 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4679 if (com->pc98_8251fifo_enable) 4680 outb(I8251F_fcr, CTRL8251F_ENABLE); 4681 COM_INT_ENABLE 4682} 4683 4684static void 4685pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x) 4686{ 4687 int tmp; 4688 COM_INT_DISABLE 4689 if (com->pc98_8251fifo_enable) 4690 outb(I8251F_fcr, 0); 4691 tmp = com->pc98_prev_siocmd & ~(clr); 4692 tmp |= (x); 4693 outb(com->cmd_port, tmp); 4694 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4695 if (com->pc98_8251fifo_enable) 4696 outb(I8251F_fcr, CTRL8251F_ENABLE); 4697 COM_INT_ENABLE 4698} 4699 4700static int 4701pc98_i8251_get_cmd(struct com_s *com) 4702{ 4703 return com->pc98_prev_siocmd; 4704} 4705 4706static int 4707pc98_i8251_get_mod(struct com_s *com) 4708{ 4709 return com->pc98_prev_siomod; 4710} 4711 4712static void 4713pc98_i8251_reset(struct com_s *com, int mode, int command) 4714{ 4715 if (com->pc98_8251fifo_enable) 4716 outb(I8251F_fcr, 0); 4717 outb(com->cmd_port, 0); /* dummy */ 4718 DELAY(2); 4719 outb(com->cmd_port, 0); /* dummy */ 4720 DELAY(2); 4721 outb(com->cmd_port, 0); /* dummy */ 4722 DELAY(2); 4723 outb(com->cmd_port, CMD8251_RESET); /* internal reset */ 4724 DELAY(2); 4725 outb(com->cmd_port, mode ); /* mode register */ 4726 com->pc98_prev_siomod = mode; 4727 DELAY(2); 4728 pc98_i8251_set_cmd( com, (command|CMD8251_ER) ); 4729 DELAY(10); 4730 if (com->pc98_8251fifo_enable) 4731 outb(I8251F_fcr, CTRL8251F_ENABLE | 4732 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 4733} 4734 4735static void 4736pc98_check_sysclock(void) 4737{ 4738 /* get system clock from port */ 4739 if ( pc98_machine_type & M_8M ) { 4740 /* 8 MHz system & H98 */ 4741 sysclock = 8; 4742 } else { 4743 /* 5 MHz system */ 4744 sysclock = 5; 4745 } 4746} 4747 4748static void 4749com_cflag_and_speed_set( struct com_s *com, int cflag, int speed) 4750{ 4751 int cfcr=0; 4752 int previnterrupt; 4753 u_int count; 4754 4755 if (pc98_ttspeedtab(com, speed, &count) != 0) 4756 return; 4757 4758 previnterrupt = pc98_check_i8251_interrupt(com); 4759 pc98_disable_i8251_interrupt( com, IEN_Tx|IEN_TxEMP|IEN_Rx ); 4760 4761 switch ( cflag&CSIZE ) { 4762 case CS5: 4763 cfcr = MOD8251_5BITS; break; 4764 case CS6: 4765 cfcr = MOD8251_6BITS; break; 4766 case CS7: 4767 cfcr = MOD8251_7BITS; break; 4768 case CS8: 4769 cfcr = MOD8251_8BITS; break; 4770 } 4771 if ( cflag&PARENB ) { 4772 if ( cflag&PARODD ) 4773 cfcr |= MOD8251_PODD; 4774 else 4775 cfcr |= MOD8251_PEVEN; 4776 } else 4777 cfcr |= MOD8251_PDISAB; 4778 4779 if ( cflag&CSTOPB ) 4780 cfcr |= MOD8251_STOP2; 4781 else 4782 cfcr |= MOD8251_STOP1; 4783 4784 if ( count & 0x10000 ) 4785 cfcr |= MOD8251_CLKX1; 4786 else 4787 cfcr |= MOD8251_CLKX16; 4788 4789 if (epson_machine_id != 0x20) { /* XXX */ 4790 int tmp; 4791 while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP)) 4792 ; 4793 } 4794 /* set baud rate from ospeed */ 4795 pc98_set_baud_rate( com, count ); 4796 4797 if ( cfcr != pc98_i8251_get_mod(com) ) 4798 pc98_i8251_reset(com, cfcr, pc98_i8251_get_cmd(com) ); 4799 4800 pc98_enable_i8251_interrupt( com, previnterrupt ); 4801} 4802 4803static int 4804pc98_ttspeedtab(struct com_s *com, int speed, u_int *divisor) 4805{ 4806 int if_type, effect_sp, count = -1, mod; 4807 4808 if_type = com->pc98_if_type & 0x0f; 4809 4810 switch (com->pc98_if_type) { 4811 case COM_IF_INTERNAL: 4812 if (PC98SIO_baud_rate_port(if_type) != -1) { 4813 count = ttspeedtab(speed, if_8251_type[if_type].speedtab); 4814 if (count > 0) { 4815 count |= COM1_EXT_CLOCK; 4816 break; 4817 } 4818 } 4819 4820 /* for *1CLK asynchronous! mode, TEFUTEFU */ 4821 mod = (sysclock == 5) ? 2457600 : 1996800; 4822 effect_sp = ttspeedtab( speed, pc98speedtab ); 4823 if ( effect_sp < 0 ) /* XXX */ 4824 effect_sp = ttspeedtab( (speed - 1), pc98speedtab ); 4825 if ( effect_sp <= 0 ) 4826 return effect_sp; 4827 if ( effect_sp == speed ) 4828 mod /= 16; 4829 if ( mod % effect_sp ) 4830 return(-1); 4831 count = mod / effect_sp; 4832 if ( count > 65535 ) 4833 return(-1); 4834 if ( effect_sp != speed ) 4835 count |= 0x10000; 4836 break; 4837 case COM_IF_PC9861K_1: 4838 case COM_IF_PC9861K_2: 4839 count = 1; 4840 break; 4841 case COM_IF_IND_SS_1: 4842 case COM_IF_IND_SS_2: 4843 case COM_IF_PIO9032B_1: 4844 case COM_IF_PIO9032B_2: 4845 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 4846 break; 4847 case COM_IF_B98_01_1: 4848 case COM_IF_B98_01_2: 4849 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 4850#ifdef B98_01_OLD 4851 if (count == 0 || count == 1) { 4852 count += 4; 4853 count |= 0x20000; /* x1 mode for 76800 and 153600 */ 4854 } 4855#endif 4856 break; 4857 } 4858 4859 if (count < 0) 4860 return count; 4861 4862 *divisor = (u_int) count; 4863 return 0; 4864} 4865 4866static void 4867pc98_set_baud_rate( struct com_s *com, u_int count ) 4868{ 4869 int if_type, io, s; 4870 4871 if_type = com->pc98_if_type & 0x0f; 4872 io = rman_get_start(com->ioportres) & 0xff00; 4873 4874 switch (com->pc98_if_type) { 4875 case COM_IF_INTERNAL: 4876 if (PC98SIO_baud_rate_port(if_type) != -1) { 4877 if (count & COM1_EXT_CLOCK) { 4878 outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff); 4879 break; 4880 } else { 4881 outb((Port_t)PC98SIO_baud_rate_port(if_type), 0x09); 4882 } 4883 } 4884 4885 if (count == 0) 4886 return; 4887 4888 /* set i8253 */ 4889 s = splclock(); 4890 if (count != 3) 4891 outb( 0x77, 0xb6 ); 4892 else 4893 outb( 0x77, 0xb4 ); 4894 outb( 0x5f, 0); 4895 outb( 0x75, count & 0xff ); 4896 outb( 0x5f, 0); 4897 outb( 0x75, (count >> 8) & 0xff ); 4898 splx(s); 4899 break; 4900 case COM_IF_IND_SS_1: 4901 case COM_IF_IND_SS_2: 4902 outb(io | PC98SIO_intr_ctrl_port(if_type), 0); 4903 outb(io | PC98SIO_baud_rate_port(if_type), 0); 4904 outb(io | PC98SIO_baud_rate_port(if_type), 0xc0); 4905 outb(io | PC98SIO_baud_rate_port(if_type), (count >> 8) | 0x80); 4906 outb(io | PC98SIO_baud_rate_port(if_type), count & 0xff); 4907 break; 4908 case COM_IF_PIO9032B_1: 4909 case COM_IF_PIO9032B_2: 4910 outb(io | PC98SIO_baud_rate_port(if_type), count); 4911 break; 4912 case COM_IF_B98_01_1: 4913 case COM_IF_B98_01_2: 4914 outb(io | PC98SIO_baud_rate_port(if_type), count & 0x0f); 4915#ifdef B98_01_OLD 4916 /* 4917 * Some old B98_01 board should be controlled 4918 * in different way, but this hasn't been tested yet. 4919 */ 4920 outb(io | PC98SIO_func_port(if_type), 4921 (count & 0x20000) ? 0xf0 : 0xf2); 4922#endif 4923 break; 4924 } 4925} 4926static int 4927pc98_check_if_type(device_t dev, struct siodev *iod) 4928{ 4929 int irr, io, if_type, tmp; 4930 static short irq_tab[2][8] = { 4931 { 3, 5, 6, 9, 10, 12, 13, -1}, 4932 { 3, 10, 12, 13, 5, 6, 9, -1} 4933 }; 4934 4935 if_type = iod->if_type & 0x0f; 4936 iod->irq = 0; 4937 io = isa_get_port(dev) & 0xff00; 4938 4939 if (IS_8251(iod->if_type)) { 4940 if (PC98SIO_func_port(if_type) != -1) { 4941 outb(io | PC98SIO_func_port(if_type), 0xf2); 4942 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab); 4943 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1) 4944 outb(io | PC98SIO_baud_rate_port(if_type), tmp); 4945 } 4946 4947 iod->cmd = io | PC98SIO_cmd_port(if_type); 4948 iod->sts = io | PC98SIO_sts_port(if_type); 4949 iod->mod = io | PC98SIO_in_modem_port(if_type); 4950 iod->ctrl = io | PC98SIO_intr_ctrl_port(if_type); 4951 4952 if (iod->if_type == COM_IF_INTERNAL) { 4953 iod->irq = 4; 4954 4955 if (pc98_check_8251vfast()) { 4956 PC98SIO_baud_rate_port(if_type) = I8251F_div; 4957 if_8251_type[if_type].speedtab = pc98fast_speedtab; 4958 } 4959 } else { 4960 tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask; 4961 if ((isa_get_port(dev) & 0xff) == IO_COM2) 4962 iod->irq = irq_tab[0][tmp]; 4963 else 4964 iod->irq = irq_tab[1][tmp]; 4965 } 4966 } else { 4967 irr = if_16550a_type[if_type].irr_read; 4968#ifdef COM_MULTIPORT 4969 if (!COM_ISMULTIPORT(device_get_flags(dev)) || 4970 device_get_unit(dev) == COM_MPMASTER(device_get_flags(dev))) 4971#endif 4972 if (irr != -1) { 4973 tmp = inb(io | irr); 4974 if (isa_get_port(dev) & 0x01) /* XXX depend on RSB-384 */ 4975 iod->irq = irq_tab[1][tmp >> 3]; 4976 else 4977 iod->irq = irq_tab[0][tmp & 0x07]; 4978 } 4979 } 4980 if ( iod->irq == -1 ) return -1; 4981 4982 return 0; 4983} 4984static void 4985pc98_set_ioport(struct com_s *com) 4986{ 4987 int if_type = com->pc98_if_type & 0x0f; 4988 Port_t io = rman_get_start(com->ioportres) & 0xff00; 4989 4990 pc98_check_sysclock(); 4991 com->data_port = io | PC98SIO_data_port(if_type); 4992 com->cmd_port = io | PC98SIO_cmd_port(if_type); 4993 com->sts_port = io | PC98SIO_sts_port(if_type); 4994 com->in_modem_port = io | PC98SIO_in_modem_port(if_type); 4995 com->intr_ctrl_port = io | PC98SIO_intr_ctrl_port(if_type); 4996} 4997static int 4998pc98_check_8251vfast(void) 4999{ 5000 int i; 5001 5002 outb(I8251F_div, 0x8c); 5003 DELAY(10); 5004 for (i = 0; i < 100; i++) { 5005 if ((inb(I8251F_div) & 0x80) != 0) { 5006 i = 0; 5007 break; 5008 } 5009 DELAY(1); 5010 } 5011 outb(I8251F_div, 0); 5012 DELAY(10); 5013 for (; i < 100; i++) { 5014 if ((inb(I8251F_div) & 0x80) == 0) 5015 return 1; 5016 DELAY(1); 5017 } 5018 5019 return 0; 5020} 5021static int 5022pc98_check_8251fifo(void) 5023{ 5024 u_char tmp1, tmp2; 5025 5026 tmp1 = inb(I8251F_iir); 5027 DELAY(10); 5028 tmp2 = inb(I8251F_iir); 5029 if (((tmp1 ^ tmp2) & 0x40) != 0 && ((tmp1 | tmp2) & 0x20) == 0) 5030 return 1; 5031 5032 return 0; 5033} 5034#endif /* PC98 defined */ 5035