sio.c revision 93147
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Berkeley and its contributors. 17 * 4. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/pc98/cbus/sio.c 93147 2002-03-25 13:41:06Z nyan $ 34 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 35 * from: i386/isa sio.c,v 1.234 36 */ 37 38#include "opt_comconsole.h" 39#include "opt_compat.h" 40#include "opt_ddb.h" 41#include "opt_sio.h" 42 43/* 44 * Serial driver, based on 386BSD-0.1 com driver. 45 * Mostly rewritten to use pseudo-DMA. 46 * Works for National Semiconductor NS8250-NS16550AF UARTs. 47 * COM driver, based on HP dca driver. 48 * 49 * Changes for PC-Card integration: 50 * - Added PC-Card driver table and handlers 51 */ 52/*=============================================================== 53 * 386BSD(98),FreeBSD-1.1x(98) com driver. 54 * ----- 55 * modified for PC9801 by M.Ishii 56 * Kyoto University Microcomputer Club (KMC) 57 * Chou "TEFUTEFU" Hirotomi 58 * Kyoto Univ. the faculty of medicine 59 *=============================================================== 60 * FreeBSD-2.0.1(98) sio driver. 61 * ----- 62 * modified for pc98 Internal i8251 and MICRO CORE MC16550II 63 * T.Koike(hfc01340@niftyserve.or.jp) 64 * implement kernel device configuration 65 * aizu@orient.center.nitech.ac.jp 66 * 67 * Notes. 68 * ----- 69 * PC98 localization based on 386BSD(98) com driver. Using its PC98 local 70 * functions. 71 * This driver is under debugging,has bugs. 72 * 73 * 1) config 74 * options COM_MULTIPORT #if using MC16550II 75 * device sio0 at nec? port 0x30 tty irq 4 #internal 76 * device sio1 at nec? port 0xd2 tty irq 5 flags 0x101 #mc1 77 * device sio2 at nec? port 0x8d2 tty flags 0x101 #mc2 78 * # ~~~~~iobase ~~multi port flag 79 * # ~ master device is sio1 80 * 2) device 81 * cd /dev; MAKEDEV ttyd0 ttyd1 .. 82 * 3) /etc/rc.serial 83 * 57600bps is too fast for sio0(internal8251) 84 * my ex. 85 * #set default speed 9600 86 * modem() 87 * : 88 * stty </dev/ttyid$i crtscts 9600 89 * : # ~~~~ default speed(can change after init.) 90 * modem 0 1 2 91 * 4) COMCONSOLE 92 * not changed. 93 * 5) PC9861K,PIO9032B,B98_01 94 * not tested. 95 */ 96/* 97 * modified for AIWA B98-01 98 * by T.Hatanou <hatanou@yasuda.comm.waseda.ac.jp> last update: 15 Sep.1995 99 * 100 * How to configure... 101 * # options COM_MULTIPORT # support for MICROCORE MC16550II 102 * ... comment-out this line, which will conflict with B98_01. 103 * options "B98_01" # support for AIWA B98-01 104 * device sio1 at nec? port 0x00d1 tty irq ? 105 * device sio2 at nec? port 0x00d5 tty irq ? 106 * ... you can leave these lines `irq ?', irq will be autodetected. 107 */ 108/* 109 * Modified by Y.Takahashi of Kogakuin University. 110 */ 111/* 112 * modified for 8251(FIFO) by Seigo TANIMURA <tanimura@FreeBSD.org> 113 */ 114 115#include <sys/param.h> 116#include <sys/systm.h> 117#include <sys/bus.h> 118#include <sys/conf.h> 119#include <sys/dkstat.h> 120#include <sys/fcntl.h> 121#include <sys/interrupt.h> 122#include <sys/kernel.h> 123#include <sys/lock.h> 124#include <sys/malloc.h> 125#include <sys/module.h> 126#include <sys/mutex.h> 127#include <sys/proc.h> 128#include <sys/reboot.h> 129#include <sys/sysctl.h> 130#include <sys/syslog.h> 131#include <sys/tty.h> 132#include <machine/bus.h> 133#include <sys/rman.h> 134#include <sys/timetc.h> 135#include <sys/timepps.h> 136 137#include <isa/isavar.h> 138 139#include <machine/limits.h> 140#include <machine/resource.h> 141 142#include <dev/sio/sioreg.h> 143#include <dev/sio/siovar.h> 144 145#ifdef PC98 146#include <pc98/pc98/pc98.h> 147#include <pc98/pc98/pc98_machdep.h> 148#endif 149 150#ifdef COM_ESP 151#include <dev/ic/esp.h> 152#endif 153#include <dev/ic/ns16550.h> 154#ifdef PC98 155#include <dev/ic/i8251.h> 156#include <dev/ic/rsa.h> 157#endif 158 159#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */ 160 161#define CALLOUT_MASK 0x80 162#define CONTROL_MASK 0x60 163#define CONTROL_INIT_STATE 0x20 164#define CONTROL_LOCK_STATE 0x40 165#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev))) 166#define MINOR_MAGIC_MASK (CALLOUT_MASK | CONTROL_MASK) 167#define MINOR_TO_UNIT(mynor) ((mynor) & ~MINOR_MAGIC_MASK) 168 169#ifdef COM_MULTIPORT 170/* checks in flags for multiport and which is multiport "master chip" 171 * for a given card 172 */ 173#define COM_ISMULTIPORT(flags) ((flags) & 0x01) 174#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff) 175#define COM_NOTAST4(flags) ((flags) & 0x04) 176#endif /* COM_MULTIPORT */ 177 178#define COM_CONSOLE(flags) ((flags) & 0x10) 179#define COM_FORCECONSOLE(flags) ((flags) & 0x20) 180#define COM_LLCONSOLE(flags) ((flags) & 0x40) 181#define COM_DEBUGGER(flags) ((flags) & 0x80) 182#define COM_LOSESOUTINTS(flags) ((flags) & 0x08) 183#define COM_NOFIFO(flags) ((flags) & 0x02) 184#define COM_ST16650A(flags) ((flags) & 0x20000) 185#define COM_C_NOPROBE (0x40000) 186#define COM_NOPROBE(flags) ((flags) & COM_C_NOPROBE) 187#define COM_C_IIR_TXRDYBUG (0x80000) 188#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG) 189#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24) 190 191#ifdef PC98 192#define com_emr com_msr /* Extension mode register for RSB-2000/3000 */ 193#endif 194#define com_scr 7 /* scratch register for 16450-16550 (R/W) */ 195 196#define sio_getreg(com, off) \ 197 (bus_space_read_1((com)->bst, (com)->bsh, (off))) 198#define sio_setreg(com, off, value) \ 199 (bus_space_write_1((com)->bst, (com)->bsh, (off), (value))) 200 201/* 202 * com state bits. 203 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher 204 * than the other bits so that they can be tested as a group without masking 205 * off the low bits. 206 * 207 * The following com and tty flags correspond closely: 208 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and 209 * comstop()) 210 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart()) 211 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam()) 212 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam()) 213 * TS_FLUSH is not used. 214 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON. 215 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state). 216 */ 217#define CS_BUSY 0x80 /* output in progress */ 218#define CS_TTGO 0x40 /* output not stopped by XOFF */ 219#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */ 220#define CS_CHECKMSR 1 /* check of MSR scheduled */ 221#define CS_CTS_OFLOW 2 /* use CTS output flow control */ 222#define CS_DTR_OFF 0x10 /* DTR held off */ 223#define CS_ODONE 4 /* output completed */ 224#define CS_RTS_IFLOW 8 /* use RTS input flow control */ 225#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */ 226 227static char const * const error_desc[] = { 228#define CE_OVERRUN 0 229 "silo overflow", 230#define CE_INTERRUPT_BUF_OVERFLOW 1 231 "interrupt-level buffer overflow", 232#define CE_TTY_BUF_OVERFLOW 2 233 "tty-level buffer overflow", 234}; 235 236#define CE_NTYPES 3 237#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum]) 238 239/* types. XXX - should be elsewhere */ 240typedef u_int Port_t; /* hardware port */ 241typedef u_char bool_t; /* boolean */ 242 243/* queue of linear buffers */ 244struct lbq { 245 u_char *l_head; /* next char to process */ 246 u_char *l_tail; /* one past the last char to process */ 247 struct lbq *l_next; /* next in queue */ 248 bool_t l_queued; /* nonzero if queued */ 249}; 250 251/* com device structure */ 252struct com_s { 253 u_int flags; /* Copy isa device flags */ 254 u_char state; /* miscellaneous flag bits */ 255 bool_t active_out; /* nonzero if the callout device is open */ 256 u_char cfcr_image; /* copy of value written to CFCR */ 257#ifdef COM_ESP 258 bool_t esp; /* is this unit a hayes esp board? */ 259#endif 260 u_char extra_state; /* more flag bits, separate for order trick */ 261 u_char fifo_image; /* copy of value written to FIFO */ 262 bool_t hasfifo; /* nonzero for 16550 UARTs */ 263 bool_t st16650a; /* Is a Startech 16650A or RTS/CTS compat */ 264 bool_t loses_outints; /* nonzero if device loses output interrupts */ 265 u_char mcr_image; /* copy of value written to MCR */ 266#ifdef COM_MULTIPORT 267 bool_t multiport; /* is this unit part of a multiport device? */ 268#endif /* COM_MULTIPORT */ 269 bool_t no_irq; /* nonzero if irq is not attached */ 270 bool_t gone; /* hardware disappeared */ 271 bool_t poll; /* nonzero if polling is required */ 272 bool_t poll_output; /* nonzero if polling for output is required */ 273 int unit; /* unit number */ 274 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */ 275 u_int tx_fifo_size; 276 u_int wopeners; /* # processes waiting for DCD in open() */ 277 278 /* 279 * The high level of the driver never reads status registers directly 280 * because there would be too many side effects to handle conveniently. 281 * Instead, it reads copies of the registers stored here by the 282 * interrupt handler. 283 */ 284 u_char last_modem_status; /* last MSR read by intr handler */ 285 u_char prev_modem_status; /* last MSR handled by high level */ 286 287 u_char hotchar; /* ldisc-specific char to be handled ASAP */ 288 u_char *ibuf; /* start of input buffer */ 289 u_char *ibufend; /* end of input buffer */ 290 u_char *ibufold; /* old input buffer, to be freed */ 291 u_char *ihighwater; /* threshold in input buffer */ 292 u_char *iptr; /* next free spot in input buffer */ 293 int ibufsize; /* size of ibuf (not include error bytes) */ 294 int ierroff; /* offset of error bytes in ibuf */ 295 296 struct lbq obufq; /* head of queue of output buffers */ 297 struct lbq obufs[2]; /* output buffers */ 298 299 bus_space_tag_t bst; 300 bus_space_handle_t bsh; 301 302#ifdef PC98 303 Port_t cmd_port; 304 Port_t sts_port; 305 Port_t in_modem_port; 306 Port_t intr_ctrl_port; 307 Port_t rsabase; /* iobase address of a I/O-DATA RSA board */ 308 int intr_enable; 309 int pc98_prev_modem_status; 310 int pc98_modem_delta; 311 int modem_car_chg_timer; 312 int pc98_prev_siocmd; 313 int pc98_prev_siomod; 314 int modem_checking; 315 int pc98_if_type; 316 317 bool_t pc98_8251fifo; 318 bool_t pc98_8251fifo_enable; 319#endif /* PC98 */ 320 Port_t data_port; /* i/o ports */ 321#ifdef COM_ESP 322 Port_t esp_port; 323#endif 324 Port_t int_id_port; 325 Port_t modem_ctl_port; 326 Port_t line_status_port; 327 Port_t modem_status_port; 328 Port_t intr_ctl_port; /* Ports of IIR register */ 329 330 struct tty *tp; /* cross reference */ 331 332 /* Initial state. */ 333 struct termios it_in; /* should be in struct tty */ 334 struct termios it_out; 335 336 /* Lock state. */ 337 struct termios lt_in; /* should be in struct tty */ 338 struct termios lt_out; 339 340 bool_t do_timestamp; 341 bool_t do_dcd_timestamp; 342 struct timeval timestamp; 343 struct timeval dcd_timestamp; 344 struct pps_state pps; 345 346 u_long bytes_in; /* statistics */ 347 u_long bytes_out; 348 u_int delta_error_counts[CE_NTYPES]; 349 u_long error_counts[CE_NTYPES]; 350 351 u_long rclk; 352 353 struct resource *irqres; 354 struct resource *ioportres; 355 void *cookie; 356 dev_t devs[6]; 357 358 /* 359 * Data area for output buffers. Someday we should build the output 360 * buffer queue without copying data. 361 */ 362#ifdef PC98 363 int obufsize; 364 u_char *obuf1; 365 u_char *obuf2; 366#else 367 u_char obuf1[256]; 368 u_char obuf2[256]; 369#endif 370}; 371 372#ifdef COM_ESP 373static int espattach(struct com_s *com, Port_t esp_port); 374#endif 375 376static timeout_t siobusycheck; 377static u_int siodivisor(u_long rclk, speed_t speed); 378static timeout_t siodtrwakeup; 379static void comhardclose(struct com_s *com); 380static void sioinput(struct com_s *com); 381static void siointr1(struct com_s *com); 382static void siointr(void *arg); 383static int commctl(struct com_s *com, int bits, int how); 384static int comparam(struct tty *tp, struct termios *t); 385static void siopoll(void *); 386static void siosettimeout(void); 387static int siosetwater(struct com_s *com, speed_t speed); 388static void comstart(struct tty *tp); 389static void comstop(struct tty *tp, int rw); 390static timeout_t comwakeup; 391static void disc_optim(struct tty *tp, struct termios *t, 392 struct com_s *com); 393 394char sio_driver_name[] = "sio"; 395static struct mtx sio_lock; 396static int sio_inited; 397 398/* table and macro for fast conversion from a unit number to its com struct */ 399devclass_t sio_devclass; 400#define com_addr(unit) ((struct com_s *) \ 401 devclass_get_softc(sio_devclass, unit)) /* XXX */ 402 403static d_open_t sioopen; 404static d_close_t sioclose; 405static d_read_t sioread; 406static d_write_t siowrite; 407static d_ioctl_t sioioctl; 408 409#define CDEV_MAJOR 28 410static struct cdevsw sio_cdevsw = { 411 /* open */ sioopen, 412 /* close */ sioclose, 413 /* read */ sioread, 414 /* write */ siowrite, 415 /* ioctl */ sioioctl, 416 /* poll */ ttypoll, 417 /* mmap */ nommap, 418 /* strategy */ nostrategy, 419 /* name */ sio_driver_name, 420 /* maj */ CDEV_MAJOR, 421 /* dump */ nodump, 422 /* psize */ nopsize, 423 /* flags */ D_TTY | D_KQFILTER, 424 /* kqfilter */ ttykqfilter, 425}; 426 427int comconsole = -1; 428static volatile speed_t comdefaultrate = CONSPEED; 429static u_long comdefaultrclk = DEFAULT_RCLK; 430SYSCTL_ULONG(_machdep, OID_AUTO, conrclk, CTLFLAG_RW, &comdefaultrclk, 0, ""); 431#ifdef __alpha__ 432static volatile speed_t gdbdefaultrate = CONSPEED; 433#endif 434static u_int com_events; /* input chars + weighted output completions */ 435static Port_t siocniobase; 436#ifndef __alpha__ 437static int siocnunit; 438#endif 439static Port_t siogdbiobase; 440static int siogdbunit = -1; 441static void *sio_slow_ih; 442static void *sio_fast_ih; 443static int sio_timeout; 444static int sio_timeouts_until_log; 445static struct callout_handle sio_timeout_handle 446 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle); 447static int sio_numunits; 448 449#ifdef PC98 450struct siodev { 451 short if_type; 452 short irq; 453 Port_t cmd, sts, ctrl, mod; 454}; 455static int sysclock; 456 457#define COM_INT_DISABLE {int previpri; previpri=spltty(); 458#define COM_INT_ENABLE splx(previpri);} 459#define IEN_TxFLAG IEN_Tx 460 461#define COM_CARRIER_DETECT_EMULATE 0 462#define PC98_CHECK_MODEM_INTERVAL (hz/10) 463#define DCD_OFF_TOLERANCE 2 464#define DCD_ON_RECOGNITION 2 465#define IS_8251(if_type) (!(if_type & 0x10)) 466#define COM1_EXT_CLOCK 0x40000 467 468static void commint(dev_t dev); 469static void com_tiocm_set(struct com_s *com, int msr); 470static void com_tiocm_bis(struct com_s *com, int msr); 471static void com_tiocm_bic(struct com_s *com, int msr); 472static int com_tiocm_get(struct com_s *com); 473static int com_tiocm_get_delta(struct com_s *com); 474static void pc98_msrint_start(dev_t dev); 475static void com_cflag_and_speed_set(struct com_s *com, int cflag, int speed); 476static int pc98_ttspeedtab(struct com_s *com, int speed, u_int *divisor); 477static int pc98_get_modem_status(struct com_s *com); 478static timeout_t pc98_check_msr; 479static void pc98_set_baud_rate(struct com_s *com, u_int count); 480static void pc98_i8251_reset(struct com_s *com, int mode, int command); 481static void pc98_disable_i8251_interrupt(struct com_s *com, int mod); 482static void pc98_enable_i8251_interrupt(struct com_s *com, int mod); 483static int pc98_check_i8251_interrupt(struct com_s *com); 484static int pc98_i8251_get_cmd(struct com_s *com); 485static int pc98_i8251_get_mod(struct com_s *com); 486static void pc98_i8251_set_cmd(struct com_s *com, int x); 487static void pc98_i8251_or_cmd(struct com_s *com, int x); 488static void pc98_i8251_clear_cmd(struct com_s *com, int x); 489static void pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x); 490static int pc98_check_if_type(device_t dev, struct siodev *iod); 491static int pc98_check_8251vfast(void); 492static int pc98_check_8251fifo(void); 493static void pc98_check_sysclock(void); 494static void pc98_set_ioport(struct com_s *com); 495 496#define com_int_Tx_disable(com) \ 497 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP) 498#define com_int_Tx_enable(com) \ 499 pc98_enable_i8251_interrupt(com,IEN_TxFLAG) 500#define com_int_Rx_disable(com) \ 501 pc98_disable_i8251_interrupt(com,IEN_Rx) 502#define com_int_Rx_enable(com) \ 503 pc98_enable_i8251_interrupt(com,IEN_Rx) 504#define com_int_TxRx_disable(com) \ 505 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP|IEN_Rx) 506#define com_int_TxRx_enable(com) \ 507 pc98_enable_i8251_interrupt(com,IEN_TxFLAG|IEN_Rx) 508#define com_send_break_on(com) \ 509 pc98_i8251_or_cmd(com,CMD8251_SBRK) 510#define com_send_break_off(com) \ 511 pc98_i8251_clear_cmd(com,CMD8251_SBRK) 512 513static struct speedtab pc98speedtab[] = { /* internal RS232C interface */ 514 { 0, 0, }, 515 { 50, 50, }, 516 { 75, 75, }, 517 { 150, 150, }, 518 { 200, 200, }, 519 { 300, 300, }, 520 { 600, 600, }, 521 { 1200, 1200, }, 522 { 2400, 2400, }, 523 { 4800, 4800, }, 524 { 9600, 9600, }, 525 { 19200, 19200, }, 526 { 38400, 38400, }, 527 { 51200, 51200, }, 528 { 76800, 76800, }, 529 { 20800, 20800, }, 530 { 31200, 31200, }, 531 { 41600, 41600, }, 532 { 62400, 62400, }, 533 { -1, -1 } 534}; 535static struct speedtab pc98fast_speedtab[] = { 536 { 9600, 0x80 | (DEFAULT_RCLK / (16 * (9600))), }, 537 { 19200, 0x80 | (DEFAULT_RCLK / (16 * (19200))), }, 538 { 38400, 0x80 | (DEFAULT_RCLK / (16 * (38400))), }, 539 { 57600, 0x80 | (DEFAULT_RCLK / (16 * (57600))), }, 540 { 115200, 0x80 | (DEFAULT_RCLK / (16 * (115200))), }, 541 { -1, -1 } 542}; 543static struct speedtab comspeedtab_pio9032b[] = { 544 { 300, 6, }, 545 { 600, 5, }, 546 { 1200, 4, }, 547 { 2400, 3, }, 548 { 4800, 2, }, 549 { 9600, 1, }, 550 { 19200, 0, }, 551 { 38400, 7, }, 552 { -1, -1 } 553}; 554static struct speedtab comspeedtab_b98_01[] = { 555 { 75, 11, }, 556 { 150, 10, }, 557 { 300, 9, }, 558 { 600, 8, }, 559 { 1200, 7, }, 560 { 2400, 6, }, 561 { 4800, 5, }, 562 { 9600, 4, }, 563 { 19200, 3, }, 564 { 38400, 2, }, 565 { 76800, 1, }, 566 { 153600, 0, }, 567 { -1, -1 } 568}; 569static struct speedtab comspeedtab_ind[] = { 570 { 300, 1536, }, 571 { 600, 768, }, 572 { 1200, 384, }, 573 { 2400, 192, }, 574 { 4800, 96, }, 575 { 9600, 48, }, 576 { 19200, 24, }, 577 { 38400, 12, }, 578 { 57600, 8, }, 579 { 115200, 4, }, 580 { 153600, 3, }, 581 { 230400, 2, }, 582 { 460800, 1, }, 583 { -1, -1 } 584}; 585 586struct { 587 char *name; 588 short port_table[7]; 589 short irr_mask; 590 struct speedtab *speedtab; 591 short check_irq; 592} if_8251_type[] = { 593 /* COM_IF_INTERNAL */ 594 { " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1}, 595 -1, pc98speedtab, 1 }, 596 /* COM_IF_PC9861K_1 */ 597 { " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1}, 598 3, NULL, 1 }, 599 /* COM_IF_PC9861K_2 */ 600 { " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1}, 601 3, NULL, 1 }, 602 /* COM_IF_IND_SS_1 */ 603 { " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1}, 604 3, comspeedtab_ind, 1 }, 605 /* COM_IF_IND_SS_2 */ 606 { " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1}, 607 3, comspeedtab_ind, 1 }, 608 /* COM_IF_PIO9032B_1 */ 609 { " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1}, 610 7, comspeedtab_pio9032b, 1 }, 611 /* COM_IF_PIO9032B_2 */ 612 { " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1}, 613 7, comspeedtab_pio9032b, 1 }, 614 /* COM_IF_B98_01_1 */ 615 { " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3}, 616 7, comspeedtab_b98_01, 0 }, 617 /* COM_IF_B98_01_2 */ 618 { " (B98-01)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xd5, 0xd7}, 619 7, comspeedtab_b98_01, 0 }, 620}; 621#define PC98SIO_data_port(type) (if_8251_type[type].port_table[0]) 622#define PC98SIO_cmd_port(type) (if_8251_type[type].port_table[1]) 623#define PC98SIO_sts_port(type) (if_8251_type[type].port_table[2]) 624#define PC98SIO_in_modem_port(type) (if_8251_type[type].port_table[3]) 625#define PC98SIO_intr_ctrl_port(type) (if_8251_type[type].port_table[4]) 626#define PC98SIO_baud_rate_port(type) (if_8251_type[type].port_table[5]) 627#define PC98SIO_func_port(type) (if_8251_type[type].port_table[6]) 628 629#define I8251F_data 0x130 630#define I8251F_lsr 0x132 631#define I8251F_msr 0x134 632#define I8251F_iir 0x136 633#define I8251F_fcr 0x138 634#define I8251F_div 0x13a 635 636 637static bus_addr_t port_table_0[] = 638 {0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007}; 639static bus_addr_t port_table_1[] = 640 {0x000, 0x002, 0x004, 0x006, 0x008, 0x00a, 0x00c, 0x00e}; 641static bus_addr_t port_table_8[] = 642 {0x000, 0x100, 0x200, 0x300, 0x400, 0x500, 0x600, 0x700}; 643static bus_addr_t port_table_rsa[] = { 644 0x008, 0x009, 0x00a, 0x00b, 0x00c, 0x00d, 0x00e, 0x00f, 645 0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007 646}; 647 648struct { 649 char *name; 650 short irr_read; 651 short irr_write; 652 bus_addr_t *iat; 653 bus_size_t iatsz; 654 u_long rclk; 655} if_16550a_type[] = { 656 /* COM_IF_RSA98 */ 657 {" (RSA-98)", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 658 /* COM_IF_NS16550 */ 659 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 660 /* COM_IF_SECOND_CCU */ 661 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 662 /* COM_IF_MC16550II */ 663 {" (MC16550II)", -1, 0x1000, port_table_8, IO_COMSIZE, 664 DEFAULT_RCLK * 4}, 665 /* COM_IF_MCRS98 */ 666 {" (MC-RS98)", -1, 0x1000, port_table_8, IO_COMSIZE, DEFAULT_RCLK * 4}, 667 /* COM_IF_RSB3000 */ 668 {" (RSB-3000)", 0xbf, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 10}, 669 /* COM_IF_RSB384 */ 670 {" (RSB-384)", 0xbf, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 10}, 671 /* COM_IF_MODEM_CARD */ 672 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 673 /* COM_IF_RSA98III */ 674 {" (RSA-98III)", -1, -1, port_table_rsa, 16, DEFAULT_RCLK * 8}, 675 /* COM_IF_ESP98 */ 676 {" (ESP98)", -1, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 4}, 677}; 678#endif /* PC98 */ 679 680#ifdef COM_ESP 681#ifdef PC98 682 683/* XXX configure this properly. */ 684/* XXX quite broken for new-bus. */ 685static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 }; 686static Port_t likely_esp_ports[] = { 0xc0d0, 0 }; 687 688#define ESP98_CMD1 (ESP_CMD1 * 0x100) 689#define ESP98_CMD2 (ESP_CMD2 * 0x100) 690#define ESP98_STATUS1 (ESP_STATUS1 * 0x100) 691#define ESP98_STATUS2 (ESP_STATUS2 * 0x100) 692 693#else /* PC98 */ 694 695/* XXX configure this properly. */ 696static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, }; 697static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 }; 698 699#endif /* PC98 */ 700#endif 701 702/* 703 * handle sysctl read/write requests for console speed 704 * 705 * In addition to setting comdefaultrate for I/O through /dev/console, 706 * also set the initial and lock values for the /dev/ttyXX device 707 * if there is one associated with the console. Finally, if the /dev/tty 708 * device has already been open, change the speed on the open running port 709 * itself. 710 */ 711 712static int 713sysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS) 714{ 715 int error, s; 716 speed_t newspeed; 717 struct com_s *com; 718 struct tty *tp; 719 720 newspeed = comdefaultrate; 721 722 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req); 723 if (error || !req->newptr) 724 return (error); 725 726 comdefaultrate = newspeed; 727 728 if (comconsole < 0) /* serial console not selected? */ 729 return (0); 730 731 com = com_addr(comconsole); 732 if (com == NULL) 733 return (ENXIO); 734 735 /* 736 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX 737 * (note, the lock rates really are boolean -- if non-zero, disallow 738 * speed changes) 739 */ 740 com->it_in.c_ispeed = com->it_in.c_ospeed = 741 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 742 com->it_out.c_ispeed = com->it_out.c_ospeed = 743 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate; 744 745 /* 746 * if we're open, change the running rate too 747 */ 748 tp = com->tp; 749 if (tp && (tp->t_state & TS_ISOPEN)) { 750 tp->t_termios.c_ispeed = 751 tp->t_termios.c_ospeed = comdefaultrate; 752 s = spltty(); 753 error = comparam(tp, &tp->t_termios); 754 splx(s); 755 } 756 return error; 757} 758 759SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW, 760 0, 0, sysctl_machdep_comdefaultrate, "I", ""); 761 762/* 763 * Unload the driver and clear the table. 764 * XXX this is mostly wrong. 765 * XXX TODO: 766 * This is usually called when the card is ejected, but 767 * can be caused by a modunload of a controller driver. 768 * The idea is to reset the driver's view of the device 769 * and ensure that any driver entry points such as 770 * read and write do not hang. 771 */ 772int 773siodetach(dev) 774 device_t dev; 775{ 776 struct com_s *com; 777 int i; 778 779 com = (struct com_s *) device_get_softc(dev); 780 if (com == NULL) { 781 device_printf(dev, "NULL com in siounload\n"); 782 return (0); 783 } 784 com->gone = 1; 785 for (i = 0 ; i < 6; i++) 786 destroy_dev(com->devs[i]); 787 if (com->irqres) { 788 bus_teardown_intr(dev, com->irqres, com->cookie); 789 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres); 790 } 791 if (com->ioportres) 792 bus_release_resource(dev, SYS_RES_IOPORT, 0, com->ioportres); 793 if (com->tp && (com->tp->t_state & TS_ISOPEN)) { 794 device_printf(dev, "still open, forcing close\n"); 795 (*linesw[com->tp->t_line].l_close)(com->tp, 0); 796 com->tp->t_gen++; 797 ttyclose(com->tp); 798 ttwakeup(com->tp); 799 ttwwakeup(com->tp); 800 } else { 801 if (com->ibuf != NULL) 802 free(com->ibuf, M_DEVBUF); 803#ifdef PC98 804 if (com->obuf1 != NULL) 805 free(com->obuf1, M_DEVBUF); 806#endif 807 device_set_softc(dev, NULL); 808 free(com, M_DEVBUF); 809 } 810 return (0); 811} 812 813int 814sioprobe(dev, xrid, rclk, noprobe) 815 device_t dev; 816 int xrid; 817 u_long rclk; 818 int noprobe; 819{ 820#if 0 821 static bool_t already_init; 822 device_t xdev; 823#endif 824 struct com_s *com; 825 u_int divisor; 826 bool_t failures[10]; 827 int fn; 828 device_t idev; 829 Port_t iobase; 830 intrmask_t irqmap[4]; 831 intrmask_t irqs; 832 u_char mcr_image; 833 int result; 834 u_long xirq; 835 u_int flags = device_get_flags(dev); 836 int rid; 837 struct resource *port; 838#ifdef PC98 839 int tmp; 840 struct siodev iod; 841#endif 842 843#ifdef PC98 844 iod.if_type = GET_IFTYPE(flags); 845 if ((iod.if_type < 0 || iod.if_type > COM_IF_END1) && 846 (iod.if_type < 0x10 || iod.if_type > COM_IF_END2)) 847 return ENXIO; 848#endif 849 850 rid = xrid; 851#ifdef PC98 852 if (IS_8251(iod.if_type)) { 853 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 854 0, ~0, 1, RF_ACTIVE); 855 } else if (iod.if_type == COM_IF_MODEM_CARD || 856 iod.if_type == COM_IF_RSA98III || 857 isa_get_vendorid(dev)) { 858 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 859 if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE); 860 } else { 861 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, 862 if_16550a_type[iod.if_type & 0x0f].iat, 863 if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE); 864 } 865#else 866 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 867 0, ~0, IO_COMSIZE, RF_ACTIVE); 868#endif 869 if (!port) 870 return (ENXIO); 871#ifdef PC98 872 if (!IS_8251(iod.if_type)) { 873 if (isa_load_resourcev(port, 874 if_16550a_type[iod.if_type & 0x0f].iat, 875 if_16550a_type[iod.if_type & 0x0f].iatsz) != 0) { 876 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 877 return ENXIO; 878 } 879 } 880#endif 881 882 com = malloc(sizeof(*com), M_DEVBUF, M_NOWAIT | M_ZERO); 883 if (com == NULL) 884 return (ENOMEM); 885 device_set_softc(dev, com); 886 com->bst = rman_get_bustag(port); 887 com->bsh = rman_get_bushandle(port); 888#ifdef PC98 889 if (!IS_8251(iod.if_type) && rclk == 0) 890 rclk = if_16550a_type[iod.if_type & 0x0f].rclk; 891#else 892 if (rclk == 0) 893 rclk = DEFAULT_RCLK; 894#endif 895 com->rclk = rclk; 896 897 while (sio_inited != 2) 898 if (atomic_cmpset_int(&sio_inited, 0, 1)) { 899 mtx_init(&sio_lock, sio_driver_name, (comconsole != -1) ? 900 MTX_SPIN | MTX_QUIET : MTX_SPIN); 901 atomic_store_rel_int(&sio_inited, 2); 902 } 903 904#if 0 905 /* 906 * XXX this is broken - when we are first called, there are no 907 * previously configured IO ports. We could hard code 908 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse. 909 * This code has been doing nothing since the conversion since 910 * "count" is zero the first time around. 911 */ 912 if (!already_init) { 913 /* 914 * Turn off MCR_IENABLE for all likely serial ports. An unused 915 * port with its MCR_IENABLE gate open will inhibit interrupts 916 * from any used port that shares the interrupt vector. 917 * XXX the gate enable is elsewhere for some multiports. 918 */ 919 device_t *devs; 920 int count, i, xioport; 921#ifdef PC98 922 int xiftype; 923#endif 924 925 devclass_get_devices(sio_devclass, &devs, &count); 926#ifdef PC98 927 for (i = 0; i < count; i++) { 928 xdev = devs[i]; 929 xioport = bus_get_resource_start(xdev, SYS_RES_IOPORT, 0); 930 xiftype = GET_IFTYPE(device_get_flags(xdev)); 931 if (device_is_enabled(xdev) && xioport > 0) { 932 if (IS_8251(xiftype)) 933 outb((xioport & 0xff00) | PC98SIO_cmd_port(xiftype & 0x0f), 0xf2); 934 else 935 outb(xioport + if_16550a_type[xiftype & 0x0f].iat[com_mcr], 0); 936 } 937 } 938#else 939 for (i = 0; i < count; i++) { 940 xdev = devs[i]; 941 if (device_is_enabled(xdev) && 942 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport, 943 NULL) == 0) 944 outb(xioport + com_mcr, 0); 945 } 946#endif 947 free(devs, M_TEMP); 948 already_init = TRUE; 949 } 950#endif 951 952 if (COM_LLCONSOLE(flags)) { 953 printf("sio%d: reserved for low-level i/o\n", 954 device_get_unit(dev)); 955 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 956 device_set_softc(dev, NULL); 957 free(com, M_DEVBUF); 958 return (ENXIO); 959 } 960 961#ifdef PC98 962 DELAY(10); 963 964 /* 965 * If the port is i8251 UART (internal, B98_01) 966 */ 967 if (pc98_check_if_type(dev, &iod) == -1) { 968 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 969 device_set_softc(dev, NULL); 970 free(com, M_DEVBUF); 971 return (ENXIO); 972 } 973 if (iod.irq > 0) 974 bus_set_resource(dev, SYS_RES_IRQ, 0, iod.irq, 1); 975 if (IS_8251(iod.if_type)) { 976 outb(iod.cmd, 0); 977 DELAY(10); 978 outb(iod.cmd, 0); 979 DELAY(10); 980 outb(iod.cmd, 0); 981 DELAY(10); 982 outb(iod.cmd, CMD8251_RESET); 983 DELAY(1000); /* for a while...*/ 984 outb(iod.cmd, 0xf2); /* MODE (dummy) */ 985 DELAY(10); 986 outb(iod.cmd, 0x01); /* CMD (dummy) */ 987 DELAY(1000); /* for a while...*/ 988 if (( inb(iod.sts) & STS8251_TxEMP ) == 0 ) { 989 result = (ENXIO); 990 } 991 if (if_8251_type[iod.if_type & 0x0f].check_irq) { 992 COM_INT_DISABLE 993 tmp = ( inb( iod.ctrl ) & ~(IEN_Rx|IEN_TxEMP|IEN_Tx)); 994 outb( iod.ctrl, tmp|IEN_TxEMP ); 995 DELAY(10); 996 result = isa_irq_pending() ? 0 : ENXIO; 997 outb( iod.ctrl, tmp ); 998 COM_INT_ENABLE 999 } else { 1000 /* 1001 * B98_01 doesn't activate TxEMP interrupt line 1002 * when being reset, so we can't check irq pending. 1003 */ 1004 result = 0; 1005 } 1006 if (epson_machine_id==0x20) { /* XXX */ 1007 result = 0; 1008 } 1009 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1010 if (result) { 1011 device_set_softc(dev, NULL); 1012 free(com, M_DEVBUF); 1013 } 1014 return result; 1015 } 1016#endif /* PC98 */ 1017 /* 1018 * If the device is on a multiport card and has an AST/4 1019 * compatible interrupt control register, initialize this 1020 * register and prepare to leave MCR_IENABLE clear in the mcr. 1021 * Otherwise, prepare to set MCR_IENABLE in the mcr. 1022 * Point idev to the device struct giving the correct id_irq. 1023 * This is the struct for the master device if there is one. 1024 */ 1025 idev = dev; 1026 mcr_image = MCR_IENABLE; 1027#ifdef COM_MULTIPORT 1028 if (COM_ISMULTIPORT(flags)) { 1029#ifndef PC98 1030 Port_t xiobase; 1031 u_long io; 1032#endif 1033 1034 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags)); 1035 if (idev == NULL) { 1036 printf("sio%d: master device %d not configured\n", 1037 device_get_unit(dev), COM_MPMASTER(flags)); 1038 idev = dev; 1039 } 1040#ifndef PC98 1041 if (!COM_NOTAST4(flags)) { 1042 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io, 1043 NULL) == 0) { 1044 xiobase = io; 1045 if (bus_get_resource(idev, SYS_RES_IRQ, 0, 1046 NULL, NULL) == 0) 1047 outb(xiobase + com_scr, 0x80); 1048 else 1049 outb(xiobase + com_scr, 0); 1050 } 1051 mcr_image = 0; 1052 } 1053#endif 1054 } 1055#endif /* COM_MULTIPORT */ 1056 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0) 1057 mcr_image = 0; 1058 1059 bzero(failures, sizeof failures); 1060 iobase = rman_get_start(port); 1061 1062#ifdef PC98 1063 if (iod.if_type == COM_IF_RSA98III) { 1064 mcr_image = 0; 1065 1066 outb(iobase + rsa_msr, 0x04); 1067 outb(iobase + rsa_frr, 0x00); 1068 if ((inb(iobase + rsa_srr) & 0x36) != 0x36) { 1069 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1070 device_set_softc(dev, NULL); 1071 free(com, M_DEVBUF); 1072 return (ENXIO); 1073 } 1074 outb(iobase + rsa_ier, 0x00); 1075 outb(iobase + rsa_frr, 0x00); 1076 outb(iobase + rsa_tivsr, 0x00); 1077 outb(iobase + rsa_tcr, 0x00); 1078 } 1079 1080 tmp = if_16550a_type[iod.if_type & 0x0f].irr_write; 1081 if (tmp != -1) { 1082 /* MC16550II */ 1083 int irqout; 1084 switch (isa_get_irq(idev)) { 1085 case 3: irqout = 4; break; 1086 case 5: irqout = 5; break; 1087 case 6: irqout = 6; break; 1088 case 12: irqout = 7; break; 1089 default: 1090 printf("sio%d: irq configuration error\n", 1091 device_get_unit(dev)); 1092 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1093 device_set_softc(dev, NULL); 1094 free(com, M_DEVBUF); 1095 return (ENXIO); 1096 } 1097 outb((iobase & 0x00ff) | tmp, irqout); 1098 } 1099#endif 1100 1101 /* 1102 * We don't want to get actual interrupts, just masked ones. 1103 * Interrupts from this line should already be masked in the ICU, 1104 * but mask them in the processor as well in case there are some 1105 * (misconfigured) shared interrupts. 1106 */ 1107 mtx_lock_spin(&sio_lock); 1108/* EXTRA DELAY? */ 1109 1110 /* 1111 * Initialize the speed and the word size and wait long enough to 1112 * drain the maximum of 16 bytes of junk in device output queues. 1113 * The speed is undefined after a master reset and must be set 1114 * before relying on anything related to output. There may be 1115 * junk after a (very fast) soft reboot and (apparently) after 1116 * master reset. 1117 * XXX what about the UART bug avoided by waiting in comparam()? 1118 * We don't want to to wait long enough to drain at 2 bps. 1119 */ 1120 if (iobase == siocniobase) 1121 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10)); 1122 else { 1123 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS); 1124 divisor = siodivisor(rclk, SIO_TEST_SPEED); 1125 sio_setreg(com, com_dlbl, divisor & 0xff); 1126 sio_setreg(com, com_dlbh, divisor >> 8); 1127 sio_setreg(com, com_cfcr, CFCR_8BITS); 1128 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10)); 1129 } 1130 1131 /* 1132 * Enable the interrupt gate and disable device interupts. This 1133 * should leave the device driving the interrupt line low and 1134 * guarantee an edge trigger if an interrupt can be generated. 1135 */ 1136/* EXTRA DELAY? */ 1137 sio_setreg(com, com_mcr, mcr_image); 1138 sio_setreg(com, com_ier, 0); 1139 DELAY(1000); /* XXX */ 1140 irqmap[0] = isa_irq_pending(); 1141 1142 /* 1143 * Attempt to set loopback mode so that we can send a null byte 1144 * without annoying any external device. 1145 */ 1146/* EXTRA DELAY? */ 1147 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK); 1148 1149 /* 1150 * Attempt to generate an output interrupt. On 8250's, setting 1151 * IER_ETXRDY generates an interrupt independent of the current 1152 * setting and independent of whether the THR is empty. On 16450's, 1153 * setting IER_ETXRDY generates an interrupt independent of the 1154 * current setting. On 16550A's, setting IER_ETXRDY only 1155 * generates an interrupt when IER_ETXRDY is not already set. 1156 */ 1157 sio_setreg(com, com_ier, IER_ETXRDY); 1158#ifdef PC98 1159 if (iod.if_type == COM_IF_RSA98III) 1160 outb(iobase + rsa_ier, 0x04); 1161#endif 1162 1163 /* 1164 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate 1165 * an interrupt. They'd better generate one for actually doing 1166 * output. Loopback may be broken on the same incompatibles but 1167 * it's unlikely to do more than allow the null byte out. 1168 */ 1169 sio_setreg(com, com_data, 0); 1170 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10)); 1171 1172 /* 1173 * Turn off loopback mode so that the interrupt gate works again 1174 * (MCR_IENABLE was hidden). This should leave the device driving 1175 * an interrupt line high. It doesn't matter if the interrupt 1176 * line oscillates while we are not looking at it, since interrupts 1177 * are disabled. 1178 */ 1179/* EXTRA DELAY? */ 1180 sio_setreg(com, com_mcr, mcr_image); 1181 1182 /* 1183 * It seems my Xircom CBEM56G Cardbus modem wants to be reset 1184 * to 8 bits *again*, or else probe test 0 will fail. 1185 * gwk@sgi.com, 4/19/2001 1186 */ 1187 sio_setreg(com, com_cfcr, CFCR_8BITS); 1188 1189 /* 1190 * Some pcmcia cards have the "TXRDY bug", so we check everyone 1191 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... ) 1192 */ 1193 if (noprobe) { 1194 /* Reading IIR register twice */ 1195 for (fn = 0; fn < 2; fn ++) { 1196 DELAY(10000); 1197 failures[6] = sio_getreg(com, com_iir); 1198 } 1199 /* Check IIR_TXRDY clear ? */ 1200 result = 0; 1201 if (failures[6] & IIR_TXRDY) { 1202 /* No, Double check with clearing IER */ 1203 sio_setreg(com, com_ier, 0); 1204 if (sio_getreg(com, com_iir) & IIR_NOPEND) { 1205 /* Ok. We discovered TXRDY bug! */ 1206 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); 1207 } else { 1208 /* Unknown, Just omit this chip.. XXX */ 1209 result = ENXIO; 1210 sio_setreg(com, com_mcr, 0); 1211 } 1212 } else { 1213 /* OK. this is well-known guys */ 1214 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); 1215 } 1216 sio_setreg(com, com_ier, 0); 1217 sio_setreg(com, com_cfcr, CFCR_8BITS); 1218 mtx_unlock_spin(&sio_lock); 1219 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1220 if (iobase == siocniobase) 1221 result = 0; 1222 if (result != 0) { 1223 device_set_softc(dev, NULL); 1224 free(com, M_DEVBUF); 1225 } 1226 return (result); 1227 } 1228 1229 /* 1230 * Check that 1231 * o the CFCR, IER and MCR in UART hold the values written to them 1232 * (the values happen to be all distinct - this is good for 1233 * avoiding false positive tests from bus echoes). 1234 * o an output interrupt is generated and its vector is correct. 1235 * o the interrupt goes away when the IIR in the UART is read. 1236 */ 1237/* EXTRA DELAY? */ 1238 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS; 1239 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY; 1240 failures[2] = sio_getreg(com, com_mcr) - mcr_image; 1241 DELAY(10000); /* Some internal modems need this time */ 1242 irqmap[1] = isa_irq_pending(); 1243 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY; 1244#ifdef PC98 1245 if (iod.if_type == COM_IF_RSA98III) 1246 inb(iobase + rsa_srr); 1247#endif 1248 DELAY(1000); /* XXX */ 1249 irqmap[2] = isa_irq_pending(); 1250 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 1251#ifdef PC98 1252 if (iod.if_type == COM_IF_RSA98III) 1253 inb(iobase + rsa_srr); 1254#endif 1255 1256 /* 1257 * Turn off all device interrupts and check that they go off properly. 1258 * Leave MCR_IENABLE alone. For ports without a master port, it gates 1259 * the OUT2 output of the UART to 1260 * the ICU input. Closing the gate would give a floating ICU input 1261 * (unless there is another device driving it) and spurious interrupts. 1262 * (On the system that this was first tested on, the input floats high 1263 * and gives a (masked) interrupt as soon as the gate is closed.) 1264 */ 1265 sio_setreg(com, com_ier, 0); 1266 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */ 1267 failures[7] = sio_getreg(com, com_ier); 1268#ifdef PC98 1269 if (iod.if_type == COM_IF_RSA98III) 1270 outb(iobase + rsa_ier, 0x00); 1271#endif 1272 DELAY(1000); /* XXX */ 1273 irqmap[3] = isa_irq_pending(); 1274 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 1275#ifdef PC98 1276 if (iod.if_type == COM_IF_RSA98III) { 1277 inb(iobase + rsa_srr); 1278 outb(iobase + rsa_frr, 0x00); 1279 } 1280#endif 1281 1282 mtx_unlock_spin(&sio_lock); 1283 1284 irqs = irqmap[1] & ~irqmap[0]; 1285 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 && 1286 ((1 << xirq) & irqs) == 0) { 1287 printf( 1288 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n", 1289 device_get_unit(dev), xirq, irqs); 1290 printf( 1291 "sio%d: port may not be enabled\n", 1292 device_get_unit(dev)); 1293 } 1294 if (bootverbose) 1295 printf("sio%d: irq maps: %#x %#x %#x %#x\n", 1296 device_get_unit(dev), 1297 irqmap[0], irqmap[1], irqmap[2], irqmap[3]); 1298 1299 result = 0; 1300 for (fn = 0; fn < sizeof failures; ++fn) 1301 if (failures[fn]) { 1302 sio_setreg(com, com_mcr, 0); 1303 result = ENXIO; 1304 if (bootverbose) { 1305 printf("sio%d: probe failed test(s):", 1306 device_get_unit(dev)); 1307 for (fn = 0; fn < sizeof failures; ++fn) 1308 if (failures[fn]) 1309 printf(" %d", fn); 1310 printf("\n"); 1311 } 1312 break; 1313 } 1314 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1315 if (iobase == siocniobase) 1316 result = 0; 1317 if (result != 0) { 1318 device_set_softc(dev, NULL); 1319 free(com, M_DEVBUF); 1320 } 1321 return (result); 1322} 1323 1324#ifdef COM_ESP 1325static int 1326espattach(com, esp_port) 1327 struct com_s *com; 1328 Port_t esp_port; 1329{ 1330 u_char dips; 1331 u_char val; 1332 1333 /* 1334 * Check the ESP-specific I/O port to see if we're an ESP 1335 * card. If not, return failure immediately. 1336 */ 1337 if ((inb(esp_port) & 0xf3) == 0) { 1338 printf(" port 0x%x is not an ESP board?\n", esp_port); 1339 return (0); 1340 } 1341 1342 /* 1343 * We've got something that claims to be a Hayes ESP card. 1344 * Let's hope so. 1345 */ 1346 1347 /* Get the dip-switch configuration */ 1348#ifdef PC98 1349 outb(esp_port + ESP98_CMD1, ESP_GETDIPS); 1350 dips = inb(esp_port + ESP98_STATUS1); 1351#else 1352 outb(esp_port + ESP_CMD1, ESP_GETDIPS); 1353 dips = inb(esp_port + ESP_STATUS1); 1354#endif 1355 1356 /* 1357 * Bits 0,1 of dips say which COM port we are. 1358 */ 1359#ifdef PC98 1360 if ((rman_get_start(com->ioportres) & 0xff) == 1361 likely_com_ports[dips & 0x03]) 1362#else 1363 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03]) 1364#endif 1365 printf(" : ESP"); 1366 else { 1367 printf(" esp_port has com %d\n", dips & 0x03); 1368 return (0); 1369 } 1370 1371 /* 1372 * Check for ESP version 2.0 or later: bits 4,5,6 = 010. 1373 */ 1374#ifdef PC98 1375 outb(esp_port + ESP98_CMD1, ESP_GETTEST); 1376 val = inb(esp_port + ESP98_STATUS1); /* clear reg 1 */ 1377 val = inb(esp_port + ESP98_STATUS2); 1378#else 1379 outb(esp_port + ESP_CMD1, ESP_GETTEST); 1380 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */ 1381 val = inb(esp_port + ESP_STATUS2); 1382#endif 1383 if ((val & 0x70) < 0x20) { 1384 printf("-old (%o)", val & 0x70); 1385 return (0); 1386 } 1387 1388 /* 1389 * Check for ability to emulate 16550: bit 7 == 1 1390 */ 1391 if ((dips & 0x80) == 0) { 1392 printf(" slave"); 1393 return (0); 1394 } 1395 1396 /* 1397 * Okay, we seem to be a Hayes ESP card. Whee. 1398 */ 1399 com->esp = TRUE; 1400 com->esp_port = esp_port; 1401 return (1); 1402} 1403#endif /* COM_ESP */ 1404 1405int 1406sioattach(dev, xrid, rclk) 1407 device_t dev; 1408 int xrid; 1409 u_long rclk; 1410{ 1411 struct com_s *com; 1412#ifdef COM_ESP 1413 Port_t *espp; 1414#endif 1415 Port_t iobase; 1416 int unit; 1417 u_int flags; 1418 int rid; 1419 struct resource *port; 1420 int ret; 1421#ifdef PC98 1422 u_char *obuf; 1423 u_long obufsize; 1424 int if_type = GET_IFTYPE(device_get_flags(dev)); 1425#endif 1426 1427 rid = xrid; 1428#ifdef PC98 1429 if (IS_8251(if_type)) { 1430 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1431 0, ~0, 1, RF_ACTIVE); 1432 } else if (if_type == COM_IF_MODEM_CARD || 1433 if_type == COM_IF_RSA98III || 1434 isa_get_vendorid(dev)) { 1435 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 1436 if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE); 1437 } else { 1438 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, 1439 if_16550a_type[if_type & 0x0f].iat, 1440 if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE); 1441 } 1442#else 1443 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1444 0, ~0, IO_COMSIZE, RF_ACTIVE); 1445#endif 1446 if (!port) 1447 return (ENXIO); 1448#ifdef PC98 1449 if (!IS_8251(if_type)) { 1450 if (isa_load_resourcev(port, 1451 if_16550a_type[if_type & 0x0f].iat, 1452 if_16550a_type[if_type & 0x0f].iatsz) != 0) { 1453 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1454 return ENXIO; 1455 } 1456 } 1457#endif 1458 1459 iobase = rman_get_start(port); 1460 unit = device_get_unit(dev); 1461 com = device_get_softc(dev); 1462 flags = device_get_flags(dev); 1463 1464 if (unit >= sio_numunits) 1465 sio_numunits = unit + 1; 1466 1467#ifdef PC98 1468 obufsize = 256; 1469 if (if_type == COM_IF_RSA98III) 1470 obufsize = 2048; 1471 if ((obuf = malloc(obufsize * 2, M_DEVBUF, M_NOWAIT)) == NULL) { 1472 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1473 return ENXIO; 1474 } 1475 bzero(obuf, obufsize * 2); 1476#endif 1477 1478 /* 1479 * sioprobe() has initialized the device registers as follows: 1480 * o cfcr = CFCR_8BITS. 1481 * It is most important that CFCR_DLAB is off, so that the 1482 * data port is not hidden when we enable interrupts. 1483 * o ier = 0. 1484 * Interrupts are only enabled when the line is open. 1485 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible 1486 * interrupt control register or the config specifies no irq. 1487 * Keeping MCR_DTR and MCR_RTS off might stop the external 1488 * device from sending before we are ready. 1489 */ 1490 bzero(com, sizeof *com); 1491 com->unit = unit; 1492 com->ioportres = port; 1493 com->bst = rman_get_bustag(port); 1494 com->bsh = rman_get_bushandle(port); 1495 com->cfcr_image = CFCR_8BITS; 1496 com->dtr_wait = 3 * hz; 1497 com->loses_outints = COM_LOSESOUTINTS(flags) != 0; 1498 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0; 1499 com->tx_fifo_size = 1; 1500#ifdef PC98 1501 com->obufsize = obufsize; 1502 com->obuf1 = obuf; 1503 com->obuf2 = obuf + obufsize; 1504#endif 1505 com->obufs[0].l_head = com->obuf1; 1506 com->obufs[1].l_head = com->obuf2; 1507 1508#ifdef PC98 1509 com->pc98_if_type = if_type; 1510 1511 if (IS_8251(if_type)) { 1512 pc98_set_ioport(com); 1513 1514 if (if_type == COM_IF_INTERNAL && pc98_check_8251fifo()) { 1515 com->pc98_8251fifo = 1; 1516 com->pc98_8251fifo_enable = 0; 1517 } 1518 } else { 1519 bus_addr_t *iat = if_16550a_type[if_type & 0x0f].iat; 1520 1521 com->data_port = iobase + iat[com_data]; 1522 com->int_id_port = iobase + iat[com_iir]; 1523 com->modem_ctl_port = iobase + iat[com_mcr]; 1524 com->mcr_image = inb(com->modem_ctl_port); 1525 com->line_status_port = iobase + iat[com_lsr]; 1526 com->modem_status_port = iobase + iat[com_msr]; 1527 com->intr_ctl_port = iobase + iat[com_ier]; 1528 } 1529#else /* not PC98 */ 1530 com->data_port = iobase + com_data; 1531 com->int_id_port = iobase + com_iir; 1532 com->modem_ctl_port = iobase + com_mcr; 1533 com->mcr_image = inb(com->modem_ctl_port); 1534 com->line_status_port = iobase + com_lsr; 1535 com->modem_status_port = iobase + com_msr; 1536 com->intr_ctl_port = iobase + com_ier; 1537#endif 1538 1539#ifdef PC98 1540 if (!IS_8251(if_type) && rclk == 0) 1541 rclk = if_16550a_type[if_type & 0x0f].rclk; 1542#else 1543 if (rclk == 0) 1544 rclk = DEFAULT_RCLK; 1545#endif 1546 com->rclk = rclk; 1547 1548 /* 1549 * We don't use all the flags from <sys/ttydefaults.h> since they 1550 * are only relevant for logins. It's important to have echo off 1551 * initially so that the line doesn't start blathering before the 1552 * echo flag can be turned off. 1553 */ 1554 com->it_in.c_iflag = 0; 1555 com->it_in.c_oflag = 0; 1556 com->it_in.c_cflag = TTYDEF_CFLAG; 1557 com->it_in.c_lflag = 0; 1558 if (unit == comconsole) { 1559#ifdef PC98 1560 if (IS_8251(com->pc98_if_type)) 1561 DELAY(100000); 1562#endif 1563 com->it_in.c_iflag = TTYDEF_IFLAG; 1564 com->it_in.c_oflag = TTYDEF_OFLAG; 1565 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL; 1566 com->it_in.c_lflag = TTYDEF_LFLAG; 1567 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL; 1568 com->lt_out.c_ispeed = com->lt_out.c_ospeed = 1569 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 1570 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate; 1571 } else 1572 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED; 1573 if (siosetwater(com, com->it_in.c_ispeed) != 0) { 1574 mtx_unlock_spin(&sio_lock); 1575 /* 1576 * Leave i/o resources allocated if this is a `cn'-level 1577 * console, so that other devices can't snarf them. 1578 */ 1579 if (iobase != siocniobase) 1580 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1581 return (ENOMEM); 1582 } 1583 mtx_unlock_spin(&sio_lock); 1584 termioschars(&com->it_in); 1585 com->it_out = com->it_in; 1586 1587 /* attempt to determine UART type */ 1588 printf("sio%d: type", unit); 1589 1590 1591#ifndef PC98 1592#ifdef COM_MULTIPORT 1593 if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags)) 1594#else 1595 if (!COM_IIR_TXRDYBUG(flags)) 1596#endif 1597 { 1598 u_char scr; 1599 u_char scr1; 1600 u_char scr2; 1601 1602 scr = sio_getreg(com, com_scr); 1603 sio_setreg(com, com_scr, 0xa5); 1604 scr1 = sio_getreg(com, com_scr); 1605 sio_setreg(com, com_scr, 0x5a); 1606 scr2 = sio_getreg(com, com_scr); 1607 sio_setreg(com, com_scr, scr); 1608 if (scr1 != 0xa5 || scr2 != 0x5a) { 1609 printf(" 8250 or not responding"); 1610 goto determined_type; 1611 } 1612 } 1613#endif /* !PC98 */ 1614#ifdef PC98 1615 if (IS_8251(com->pc98_if_type)) { 1616 if (com->pc98_8251fifo && !COM_NOFIFO(flags)) 1617 com->tx_fifo_size = 16; 1618 com_int_TxRx_disable( com ); 1619 com_cflag_and_speed_set( com, com->it_in.c_cflag, comdefaultrate ); 1620 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE ); 1621 com_send_break_off( com ); 1622 1623 if (com->pc98_if_type == COM_IF_INTERNAL) { 1624 printf(" (internal%s%s)", 1625 com->pc98_8251fifo ? " fifo" : "", 1626 PC98SIO_baud_rate_port(com->pc98_if_type) != -1 ? 1627 " v-fast" : ""); 1628 } else { 1629 printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name); 1630 } 1631 } else { 1632#endif /* PC98 */ 1633 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH); 1634 DELAY(100); 1635 com->st16650a = 0; 1636 switch (inb(com->int_id_port) & IIR_FIFO_MASK) { 1637 case FIFO_RX_LOW: 1638 printf(" 16450"); 1639 break; 1640 case FIFO_RX_MEDL: 1641 printf(" 16450?"); 1642 break; 1643 case FIFO_RX_MEDH: 1644 printf(" 16550?"); 1645 break; 1646 case FIFO_RX_HIGH: 1647 if (COM_NOFIFO(flags)) { 1648 printf(" 16550A fifo disabled"); 1649 } else { 1650 com->hasfifo = TRUE; 1651#ifdef PC98 1652 com->tx_fifo_size = 0; /* XXX flag conflicts. */ 1653 printf(" 16550A"); 1654#else 1655 if (COM_ST16650A(flags)) { 1656 com->st16650a = 1; 1657 com->tx_fifo_size = 32; 1658 printf(" ST16650A"); 1659 } else { 1660 com->tx_fifo_size = COM_FIFOSIZE(flags); 1661 printf(" 16550A"); 1662 } 1663#endif 1664 } 1665#ifdef PC98 1666 if (com->pc98_if_type == COM_IF_RSA98III) { 1667 com->tx_fifo_size = 2048; 1668 com->rsabase = iobase; 1669 outb(com->rsabase + rsa_ier, 0x00); 1670 outb(com->rsabase + rsa_frr, 0x00); 1671 } 1672#endif 1673 1674#ifdef COM_ESP 1675#ifdef PC98 1676 if (com->pc98_if_type == COM_IF_ESP98) 1677#endif 1678 for (espp = likely_esp_ports; *espp != 0; espp++) 1679 if (espattach(com, *espp)) { 1680 com->tx_fifo_size = 1024; 1681 break; 1682 } 1683#endif 1684 if (!com->st16650a) { 1685 if (!com->tx_fifo_size) 1686 com->tx_fifo_size = 16; 1687 else 1688 printf(" lookalike with %d bytes FIFO", 1689 com->tx_fifo_size); 1690 } 1691 1692 break; 1693 } 1694 1695#ifdef PC98 1696 if (com->pc98_if_type == COM_IF_RSB3000) { 1697 /* Set RSB-2000/3000 Extended Buffer mode. */ 1698 u_char lcr; 1699 lcr = sio_getreg(com, com_cfcr); 1700 sio_setreg(com, com_cfcr, lcr | CFCR_DLAB); 1701 sio_setreg(com, com_emr, EMR_EXBUFF | EMR_EFMODE); 1702 sio_setreg(com, com_cfcr, lcr); 1703 } 1704#endif 1705 1706#ifdef COM_ESP 1707 if (com->esp) { 1708 /* 1709 * Set 16550 compatibility mode. 1710 * We don't use the ESP_MODE_SCALE bit to increase the 1711 * fifo trigger levels because we can't handle large 1712 * bursts of input. 1713 * XXX flow control should be set in comparam(), not here. 1714 */ 1715#ifdef PC98 1716 outb(com->esp_port + ESP98_CMD1, ESP_SETMODE); 1717 outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1718#else 1719 outb(com->esp_port + ESP_CMD1, ESP_SETMODE); 1720 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1721#endif 1722 1723 /* Set RTS/CTS flow control. */ 1724#ifdef PC98 1725 outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE); 1726 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS); 1727 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS); 1728#else 1729 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE); 1730 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS); 1731 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS); 1732#endif 1733 1734 /* Set flow-control levels. */ 1735#ifdef PC98 1736 outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW); 1737 outb(com->esp_port + ESP98_CMD2, HIBYTE(768)); 1738 outb(com->esp_port + ESP98_CMD2, LOBYTE(768)); 1739 outb(com->esp_port + ESP98_CMD2, HIBYTE(512)); 1740 outb(com->esp_port + ESP98_CMD2, LOBYTE(512)); 1741#else 1742 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW); 1743 outb(com->esp_port + ESP_CMD2, HIBYTE(768)); 1744 outb(com->esp_port + ESP_CMD2, LOBYTE(768)); 1745 outb(com->esp_port + ESP_CMD2, HIBYTE(512)); 1746 outb(com->esp_port + ESP_CMD2, LOBYTE(512)); 1747#endif 1748 1749#ifdef PC98 1750 /* Set UART clock prescaler. */ 1751 outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK); 1752 outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */ 1753#endif 1754 } 1755#endif /* COM_ESP */ 1756 sio_setreg(com, com_fifo, 0); 1757#ifdef PC98 1758 printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name); 1759#else 1760determined_type: ; 1761#endif 1762 1763#ifdef COM_MULTIPORT 1764 if (COM_ISMULTIPORT(flags)) { 1765 device_t masterdev; 1766 1767 com->multiport = TRUE; 1768 printf(" (multiport"); 1769 if (unit == COM_MPMASTER(flags)) 1770 printf(" master"); 1771 printf(")"); 1772 masterdev = devclass_get_device(sio_devclass, 1773 COM_MPMASTER(flags)); 1774 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev, 1775 SYS_RES_IRQ, 0, NULL, NULL) != 0); 1776 } 1777#endif /* COM_MULTIPORT */ 1778#ifdef PC98 1779 } 1780#endif 1781 if (unit == comconsole) 1782 printf(", console"); 1783 if (COM_IIR_TXRDYBUG(flags)) 1784 printf(" with a bogus IIR_TXRDY register"); 1785 printf("\n"); 1786 1787 if (sio_fast_ih == NULL) { 1788 swi_add(&tty_ithd, "tty:sio", siopoll, NULL, SWI_TTY, 0, 1789 &sio_fast_ih); 1790 swi_add(&clk_ithd, "tty:sio", siopoll, NULL, SWI_TTY, 0, 1791 &sio_slow_ih); 1792 } 1793 com->devs[0] = make_dev(&sio_cdevsw, unit, 1794 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit); 1795 com->devs[1] = make_dev(&sio_cdevsw, unit | CONTROL_INIT_STATE, 1796 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit); 1797 com->devs[2] = make_dev(&sio_cdevsw, unit | CONTROL_LOCK_STATE, 1798 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit); 1799 com->devs[3] = make_dev(&sio_cdevsw, unit | CALLOUT_MASK, 1800 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit); 1801 com->devs[4] = make_dev(&sio_cdevsw, 1802 unit | CALLOUT_MASK | CONTROL_INIT_STATE, 1803 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit); 1804 com->devs[5] = make_dev(&sio_cdevsw, 1805 unit | CALLOUT_MASK | CONTROL_LOCK_STATE, 1806 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit); 1807 com->flags = flags; 1808 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1809 pps_init(&com->pps); 1810 1811 rid = 0; 1812 com->irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1, 1813 RF_ACTIVE); 1814 if (com->irqres) { 1815 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres, 1816 INTR_TYPE_TTY | INTR_FAST, 1817 siointr, com, &com->cookie); 1818 if (ret) { 1819 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, 1820 com->irqres, INTR_TYPE_TTY, 1821 siointr, com, &com->cookie); 1822 if (ret == 0) 1823 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode\n"); 1824 } 1825 if (ret) 1826 device_printf(dev, "could not activate interrupt\n"); 1827#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \ 1828 defined(ALT_BREAK_TO_DEBUGGER)) 1829 /* 1830 * Enable interrupts for early break-to-debugger support 1831 * on the console. 1832 */ 1833 if (ret == 0 && unit == comconsole) 1834 outb(siocniobase + com_ier, IER_ERXRDY | IER_ERLS | 1835 IER_EMSC); 1836#endif 1837 } 1838 1839 return (0); 1840} 1841 1842static int 1843sioopen(dev, flag, mode, td) 1844 dev_t dev; 1845 int flag; 1846 int mode; 1847 struct thread *td; 1848{ 1849 struct com_s *com; 1850 int error; 1851 int mynor; 1852 int s; 1853 struct tty *tp; 1854 int unit; 1855 1856 mynor = minor(dev); 1857 unit = MINOR_TO_UNIT(mynor); 1858 com = com_addr(unit); 1859 if (com == NULL) 1860 return (ENXIO); 1861 if (com->gone) 1862 return (ENXIO); 1863 if (mynor & CONTROL_MASK) 1864 return (0); 1865 tp = dev->si_tty = com->tp = ttymalloc(com->tp); 1866 s = spltty(); 1867 /* 1868 * We jump to this label after all non-interrupted sleeps to pick 1869 * up any changes of the device state. 1870 */ 1871open_top: 1872 while (com->state & CS_DTR_OFF) { 1873 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0); 1874 if (com_addr(unit) == NULL) 1875 return (ENXIO); 1876 if (error != 0 || com->gone) 1877 goto out; 1878 } 1879 if (tp->t_state & TS_ISOPEN) { 1880 /* 1881 * The device is open, so everything has been initialized. 1882 * Handle conflicts. 1883 */ 1884 if (mynor & CALLOUT_MASK) { 1885 if (!com->active_out) { 1886 error = EBUSY; 1887 goto out; 1888 } 1889 } else { 1890 if (com->active_out) { 1891 if (flag & O_NONBLOCK) { 1892 error = EBUSY; 1893 goto out; 1894 } 1895 error = tsleep(&com->active_out, 1896 TTIPRI | PCATCH, "siobi", 0); 1897 if (com_addr(unit) == NULL) 1898 return (ENXIO); 1899 if (error != 0 || com->gone) 1900 goto out; 1901 goto open_top; 1902 } 1903 } 1904 if (tp->t_state & TS_XCLUDE && 1905 suser_td(td)) { 1906 error = EBUSY; 1907 goto out; 1908 } 1909 } else { 1910 /* 1911 * The device isn't open, so there are no conflicts. 1912 * Initialize it. Initialization is done twice in many 1913 * cases: to preempt sleeping callin opens if we are 1914 * callout, and to complete a callin open after DCD rises. 1915 */ 1916 tp->t_oproc = comstart; 1917 tp->t_param = comparam; 1918 tp->t_stop = comstop; 1919 tp->t_dev = dev; 1920 tp->t_termios = mynor & CALLOUT_MASK 1921 ? com->it_out : com->it_in; 1922#ifdef PC98 1923 if (!IS_8251(com->pc98_if_type)) 1924#endif 1925 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET); 1926 com->poll = com->no_irq; 1927 com->poll_output = com->loses_outints; 1928 ++com->wopeners; 1929 error = comparam(tp, &tp->t_termios); 1930 --com->wopeners; 1931 if (error != 0) 1932 goto out; 1933#ifdef PC98 1934 if (IS_8251(com->pc98_if_type)) { 1935 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS); 1936 pc98_msrint_start(dev); 1937 if (com->pc98_8251fifo) { 1938 com->pc98_8251fifo_enable = 1; 1939 outb(I8251F_fcr, CTRL8251F_ENABLE | 1940 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 1941 } 1942 } 1943#endif 1944 /* 1945 * XXX we should goto open_top if comparam() slept. 1946 */ 1947 if (com->hasfifo) { 1948 /* 1949 * (Re)enable and drain fifos. 1950 * 1951 * Certain SMC chips cause problems if the fifos 1952 * are enabled while input is ready. Turn off the 1953 * fifo if necessary to clear the input. We test 1954 * the input ready bit after enabling the fifos 1955 * since we've already enabled them in comparam() 1956 * and to handle races between enabling and fresh 1957 * input. 1958 */ 1959 while (TRUE) { 1960 sio_setreg(com, com_fifo, 1961 FIFO_RCV_RST | FIFO_XMT_RST 1962 | com->fifo_image); 1963#ifdef PC98 1964 if (com->pc98_if_type == COM_IF_RSA98III) 1965 outb(com->rsabase + rsa_frr , 0x00); 1966#endif 1967 /* 1968 * XXX the delays are for superstitious 1969 * historical reasons. It must be less than 1970 * the character time at the maximum 1971 * supported speed (87 usec at 115200 bps 1972 * 8N1). Otherwise we might loop endlessly 1973 * if data is streaming in. We used to use 1974 * delays of 100. That usually worked 1975 * because DELAY(100) used to usually delay 1976 * for about 85 usec instead of 100. 1977 */ 1978 DELAY(50); 1979#ifdef PC98 1980 if (com->pc98_if_type == COM_IF_RSA98III ? 1981 !(inb(com->rsabase + rsa_srr) & 0x08) : 1982 !(inb(com->line_status_port) & LSR_RXRDY)) 1983 break; 1984#else 1985 if (!(inb(com->line_status_port) & LSR_RXRDY)) 1986 break; 1987#endif 1988 sio_setreg(com, com_fifo, 0); 1989 DELAY(50); 1990 (void) inb(com->data_port); 1991 } 1992 } 1993 1994 mtx_lock_spin(&sio_lock); 1995#ifdef PC98 1996 if (IS_8251(com->pc98_if_type)) { 1997 com_tiocm_bis(com, TIOCM_LE); 1998 com->pc98_prev_modem_status = pc98_get_modem_status(com); 1999 com_int_Rx_enable(com); 2000 } else { 2001#endif 2002 (void) inb(com->line_status_port); 2003 (void) inb(com->data_port); 2004 com->prev_modem_status = com->last_modem_status 2005 = inb(com->modem_status_port); 2006 if (COM_IIR_TXRDYBUG(com->flags)) { 2007 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS 2008 | IER_EMSC); 2009 } else { 2010 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY 2011 | IER_ERLS | IER_EMSC); 2012 } 2013#ifdef PC98 2014 if (com->pc98_if_type == COM_IF_RSA98III) { 2015 outb(com->rsabase + rsa_ier, 0x1d); 2016 outb(com->intr_ctl_port, IER_ERLS | IER_EMSC); 2017 } 2018#endif 2019#ifdef PC98 2020 } 2021#endif 2022 mtx_unlock_spin(&sio_lock); 2023 /* 2024 * Handle initial DCD. Callout devices get a fake initial 2025 * DCD (trapdoor DCD). If we are callout, then any sleeping 2026 * callin opens get woken up and resume sleeping on "siobi" 2027 * instead of "siodcd". 2028 */ 2029 /* 2030 * XXX `mynor & CALLOUT_MASK' should be 2031 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where 2032 * TRAPDOOR_CARRIER is the default initial state for callout 2033 * devices and SOFT_CARRIER is like CLOCAL except it hides 2034 * the true carrier. 2035 */ 2036#ifdef PC98 2037 if ((IS_8251(com->pc98_if_type) && 2038 (pc98_get_modem_status(com) & TIOCM_CAR)) || 2039 (!IS_8251(com->pc98_if_type) && 2040 (com->prev_modem_status & MSR_DCD)) || 2041 mynor & CALLOUT_MASK) 2042 (*linesw[tp->t_line].l_modem)(tp, 1); 2043#else 2044 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK) 2045 (*linesw[tp->t_line].l_modem)(tp, 1); 2046#endif 2047 } 2048 /* 2049 * Wait for DCD if necessary. 2050 */ 2051 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK) 2052 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 2053 ++com->wopeners; 2054 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0); 2055 if (com_addr(unit) == NULL) 2056 return (ENXIO); 2057 --com->wopeners; 2058 if (error != 0 || com->gone) 2059 goto out; 2060 goto open_top; 2061 } 2062 error = (*linesw[tp->t_line].l_open)(dev, tp); 2063 disc_optim(tp, &tp->t_termios, com); 2064 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK) 2065 com->active_out = TRUE; 2066 siosettimeout(); 2067out: 2068 splx(s); 2069 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0) 2070 comhardclose(com); 2071 return (error); 2072} 2073 2074static int 2075sioclose(dev, flag, mode, td) 2076 dev_t dev; 2077 int flag; 2078 int mode; 2079 struct thread *td; 2080{ 2081 struct com_s *com; 2082 int mynor; 2083 int s; 2084 struct tty *tp; 2085 2086 mynor = minor(dev); 2087 if (mynor & CONTROL_MASK) 2088 return (0); 2089 com = com_addr(MINOR_TO_UNIT(mynor)); 2090 if (com == NULL) 2091 return (ENODEV); 2092 tp = com->tp; 2093 s = spltty(); 2094 (*linesw[tp->t_line].l_close)(tp, flag); 2095#ifdef PC98 2096 com->modem_checking = 0; 2097#endif 2098 disc_optim(tp, &tp->t_termios, com); 2099 comstop(tp, FREAD | FWRITE); 2100 comhardclose(com); 2101 ttyclose(tp); 2102 siosettimeout(); 2103 splx(s); 2104 if (com->gone) { 2105 printf("sio%d: gone\n", com->unit); 2106 s = spltty(); 2107 if (com->ibuf != NULL) 2108 free(com->ibuf, M_DEVBUF); 2109 bzero(tp, sizeof *tp); 2110 splx(s); 2111 } 2112 return (0); 2113} 2114 2115static void 2116comhardclose(com) 2117 struct com_s *com; 2118{ 2119 int s; 2120 struct tty *tp; 2121 int unit; 2122 2123 unit = com->unit; 2124 s = spltty(); 2125 com->poll = FALSE; 2126 com->poll_output = FALSE; 2127 com->do_timestamp = FALSE; 2128 com->do_dcd_timestamp = FALSE; 2129 com->pps.ppsparam.mode = 0; 2130#ifdef PC98 2131 if (IS_8251(com->pc98_if_type)) 2132 com_send_break_off(com); 2133 else 2134#endif 2135 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 2136 tp = com->tp; 2137 2138#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \ 2139 defined(ALT_BREAK_TO_DEBUGGER)) 2140 /* 2141 * Leave interrupts enabled and don't clear DTR if this is the 2142 * console. This allows us to detect break-to-debugger events 2143 * while the console device is closed. 2144 */ 2145 if (com->unit != comconsole) 2146#endif 2147 { 2148#ifdef PC98 2149 int tmp; 2150 if (IS_8251(com->pc98_if_type)) 2151 com_int_TxRx_disable(com); 2152 else 2153 sio_setreg(com, com_ier, 0); 2154 if (com->pc98_if_type == COM_IF_RSA98III) 2155 outb(com->rsabase + rsa_ier, 0x00); 2156 if (IS_8251(com->pc98_if_type)) 2157 tmp = pc98_get_modem_status(com) & TIOCM_CAR; 2158 else 2159 tmp = com->prev_modem_status & MSR_DCD; 2160#else 2161 sio_setreg(com, com_ier, 0); 2162#endif 2163 if (tp->t_cflag & HUPCL 2164 /* 2165 * XXX we will miss any carrier drop between here and the 2166 * next open. Perhaps we should watch DCD even when the 2167 * port is closed; it is not sufficient to check it at 2168 * the next open because it might go up and down while 2169 * we're not watching. 2170 */ 2171 || (!com->active_out 2172#ifdef PC98 2173 && !(tmp) 2174#else 2175 && !(com->prev_modem_status & MSR_DCD) 2176#endif 2177 && !(com->it_in.c_cflag & CLOCAL)) 2178 || !(tp->t_state & TS_ISOPEN)) { 2179#ifdef PC98 2180 if (IS_8251(com->pc98_if_type)) 2181 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 2182 else 2183#endif 2184 (void)commctl(com, TIOCM_DTR, DMBIC); 2185 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) { 2186 timeout(siodtrwakeup, com, com->dtr_wait); 2187 com->state |= CS_DTR_OFF; 2188 } 2189 } 2190#ifdef PC98 2191 else { 2192 if (IS_8251(com->pc98_if_type)) 2193 com_tiocm_bic(com, TIOCM_LE); 2194 } 2195#endif 2196 } 2197#ifdef PC98 2198 if (com->pc98_8251fifo) { 2199 if (com->pc98_8251fifo_enable) 2200 outb(I8251F_fcr, CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 2201 com->pc98_8251fifo_enable = 0; 2202 } 2203#endif 2204 if (com->hasfifo) { 2205 /* 2206 * Disable fifos so that they are off after controlled 2207 * reboots. Some BIOSes fail to detect 16550s when the 2208 * fifos are enabled. 2209 */ 2210 sio_setreg(com, com_fifo, 0); 2211 } 2212 com->active_out = FALSE; 2213 wakeup(&com->active_out); 2214 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */ 2215 splx(s); 2216} 2217 2218static int 2219sioread(dev, uio, flag) 2220 dev_t dev; 2221 struct uio *uio; 2222 int flag; 2223{ 2224 int mynor; 2225 struct com_s *com; 2226 2227 mynor = minor(dev); 2228 if (mynor & CONTROL_MASK) 2229 return (ENODEV); 2230 com = com_addr(MINOR_TO_UNIT(mynor)); 2231 if (com == NULL || com->gone) 2232 return (ENODEV); 2233 return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag)); 2234} 2235 2236static int 2237siowrite(dev, uio, flag) 2238 dev_t dev; 2239 struct uio *uio; 2240 int flag; 2241{ 2242 int mynor; 2243 struct com_s *com; 2244 int unit; 2245 2246 mynor = minor(dev); 2247 if (mynor & CONTROL_MASK) 2248 return (ENODEV); 2249 2250 unit = MINOR_TO_UNIT(mynor); 2251 com = com_addr(unit); 2252 if (com == NULL || com->gone) 2253 return (ENODEV); 2254 /* 2255 * (XXX) We disallow virtual consoles if the physical console is 2256 * a serial port. This is in case there is a display attached that 2257 * is not the console. In that situation we don't need/want the X 2258 * server taking over the console. 2259 */ 2260 if (constty != NULL && unit == comconsole) 2261 constty = NULL; 2262 return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag)); 2263} 2264 2265static void 2266siobusycheck(chan) 2267 void *chan; 2268{ 2269 struct com_s *com; 2270 int s; 2271 2272 com = (struct com_s *)chan; 2273 2274 /* 2275 * Clear TS_BUSY if low-level output is complete. 2276 * spl locking is sufficient because siointr1() does not set CS_BUSY. 2277 * If siointr1() clears CS_BUSY after we look at it, then we'll get 2278 * called again. Reading the line status port outside of siointr1() 2279 * is safe because CS_BUSY is clear so there are no output interrupts 2280 * to lose. 2281 */ 2282 s = spltty(); 2283 if (com->state & CS_BUSY) 2284 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */ 2285#ifdef PC98 2286 else if ((IS_8251(com->pc98_if_type) && 2287 ((com->pc98_8251fifo_enable && 2288 (inb(I8251F_lsr) & (STS8251F_TxRDY | STS8251F_TxEMP)) 2289 == (STS8251F_TxRDY | STS8251F_TxEMP)) || 2290 (!com->pc98_8251fifo_enable && 2291 (inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP)) 2292 == (STS8251_TxRDY | STS8251_TxEMP)))) || 2293 ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2294 == (LSR_TSRE | LSR_TXRDY))) { 2295#else 2296 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2297 == (LSR_TSRE | LSR_TXRDY)) { 2298#endif 2299 com->tp->t_state &= ~TS_BUSY; 2300 ttwwakeup(com->tp); 2301 com->extra_state &= ~CSE_BUSYCHECK; 2302 } else 2303 timeout(siobusycheck, com, hz / 100); 2304 splx(s); 2305} 2306 2307static u_int 2308siodivisor(rclk, speed) 2309 u_long rclk; 2310 speed_t speed; 2311{ 2312 long actual_speed; 2313 u_int divisor; 2314 int error; 2315 2316 if (speed == 0 || speed > (ULONG_MAX - 1) / 8) 2317 return (0); 2318 divisor = (rclk / (8UL * speed) + 1) / 2; 2319 if (divisor == 0 || divisor >= 65536) 2320 return (0); 2321 actual_speed = rclk / (16UL * divisor); 2322 2323 /* 10 times error in percent: */ 2324 error = ((actual_speed - (long)speed) * 2000 / (long)speed + 1) / 2; 2325 2326 /* 3.0% maximum error tolerance: */ 2327 if (error < -30 || error > 30) 2328 return (0); 2329 2330 return (divisor); 2331} 2332 2333static void 2334siodtrwakeup(chan) 2335 void *chan; 2336{ 2337 struct com_s *com; 2338 2339 com = (struct com_s *)chan; 2340 com->state &= ~CS_DTR_OFF; 2341 wakeup(&com->dtr_wait); 2342} 2343 2344/* 2345 * Call this function with the sio_lock mutex held. It will return with the 2346 * lock still held. 2347 */ 2348static void 2349sioinput(com) 2350 struct com_s *com; 2351{ 2352 u_char *buf; 2353 int incc; 2354 u_char line_status; 2355 int recv_data; 2356 struct tty *tp; 2357 2358 buf = com->ibuf; 2359 tp = com->tp; 2360 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) { 2361 com_events -= (com->iptr - com->ibuf); 2362 com->iptr = com->ibuf; 2363 return; 2364 } 2365 if (tp->t_state & TS_CAN_BYPASS_L_RINT) { 2366 /* 2367 * Avoid the grotesquely inefficient lineswitch routine 2368 * (ttyinput) in "raw" mode. It usually takes about 450 2369 * instructions (that's without canonical processing or echo!). 2370 * slinput is reasonably fast (usually 40 instructions plus 2371 * call overhead). 2372 */ 2373 do { 2374 /* 2375 * This may look odd, but it is using save-and-enable 2376 * semantics instead of the save-and-disable semantics 2377 * that are used everywhere else. 2378 */ 2379 mtx_unlock_spin(&sio_lock); 2380 incc = com->iptr - buf; 2381 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat 2382 && (com->state & CS_RTS_IFLOW 2383 || tp->t_iflag & IXOFF) 2384 && !(tp->t_state & TS_TBLOCK)) 2385 ttyblock(tp); 2386 com->delta_error_counts[CE_TTY_BUF_OVERFLOW] 2387 += b_to_q((char *)buf, incc, &tp->t_rawq); 2388 buf += incc; 2389 tk_nin += incc; 2390 tk_rawcc += incc; 2391 tp->t_rawcc += incc; 2392 ttwakeup(tp); 2393 if (tp->t_state & TS_TTSTOP 2394 && (tp->t_iflag & IXANY 2395 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) { 2396 tp->t_state &= ~TS_TTSTOP; 2397 tp->t_lflag &= ~FLUSHO; 2398 comstart(tp); 2399 } 2400 mtx_lock_spin(&sio_lock); 2401 } while (buf < com->iptr); 2402 } else { 2403 do { 2404 /* 2405 * This may look odd, but it is using save-and-enable 2406 * semantics instead of the save-and-disable semantics 2407 * that are used everywhere else. 2408 */ 2409 mtx_unlock_spin(&sio_lock); 2410 line_status = buf[com->ierroff]; 2411 recv_data = *buf++; 2412 if (line_status 2413 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) { 2414 if (line_status & LSR_BI) 2415 recv_data |= TTY_BI; 2416 if (line_status & LSR_FE) 2417 recv_data |= TTY_FE; 2418 if (line_status & LSR_OE) 2419 recv_data |= TTY_OE; 2420 if (line_status & LSR_PE) 2421 recv_data |= TTY_PE; 2422 } 2423 (*linesw[tp->t_line].l_rint)(recv_data, tp); 2424 mtx_lock_spin(&sio_lock); 2425 } while (buf < com->iptr); 2426 } 2427 com_events -= (com->iptr - com->ibuf); 2428 com->iptr = com->ibuf; 2429 2430 /* 2431 * There is now room for another low-level buffer full of input, 2432 * so enable RTS if it is now disabled and there is room in the 2433 * high-level buffer. 2434 */ 2435#ifdef PC98 2436 if (IS_8251(com->pc98_if_type)) { 2437 if ((com->state & CS_RTS_IFLOW) && 2438 !(com_tiocm_get(com) & TIOCM_RTS) && 2439 !(tp->t_state & TS_TBLOCK)) 2440 com_tiocm_bis(com, TIOCM_RTS); 2441 } else { 2442 if ((com->state & CS_RTS_IFLOW) && 2443 !(com->mcr_image & MCR_RTS) && 2444 !(tp->t_state & TS_TBLOCK)) 2445 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2446 } 2447#else 2448 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) && 2449 !(tp->t_state & TS_TBLOCK)) 2450 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2451#endif 2452} 2453 2454void 2455siointr(arg) 2456 void *arg; 2457{ 2458 struct com_s *com; 2459#ifdef PC98 2460 u_char rsa_buf_status; 2461#endif 2462 2463#ifndef COM_MULTIPORT 2464 com = (struct com_s *)arg; 2465 2466 mtx_lock_spin(&sio_lock); 2467 siointr1(com); 2468 mtx_unlock_spin(&sio_lock); 2469#else /* COM_MULTIPORT */ 2470 bool_t possibly_more_intrs; 2471 int unit; 2472 2473 /* 2474 * Loop until there is no activity on any port. This is necessary 2475 * to get an interrupt edge more than to avoid another interrupt. 2476 * If the IRQ signal is just an OR of the IRQ signals from several 2477 * devices, then the edge from one may be lost because another is 2478 * on. 2479 */ 2480 mtx_lock_spin(&sio_lock); 2481 do { 2482 possibly_more_intrs = FALSE; 2483 for (unit = 0; unit < sio_numunits; ++unit) { 2484 com = com_addr(unit); 2485 /* 2486 * XXX COM_LOCK(); 2487 * would it work here, or be counter-productive? 2488 */ 2489#ifdef PC98 2490 if (com != NULL 2491 && !com->gone 2492 && IS_8251(com->pc98_if_type)) { 2493 siointr1(com); 2494 } else if (com != NULL 2495 && !com->gone 2496 && com->pc98_if_type == COM_IF_RSA98III) { 2497 rsa_buf_status = 2498 inb(com->rsabase + rsa_srr) & 0xc9; 2499 if ((rsa_buf_status & 0xc8) 2500 || !(rsa_buf_status & 0x01)) { 2501 siointr1(com); 2502 if (rsa_buf_status != 2503 (inb(com->rsabase + rsa_srr) & 0xc9)) 2504 possibly_more_intrs = TRUE; 2505 } 2506 } else 2507#endif 2508 if (com != NULL 2509 && !com->gone 2510 && (inb(com->int_id_port) & IIR_IMASK) 2511 != IIR_NOPEND) { 2512 siointr1(com); 2513 possibly_more_intrs = TRUE; 2514 } 2515 /* XXX COM_UNLOCK(); */ 2516 } 2517 } while (possibly_more_intrs); 2518 mtx_unlock_spin(&sio_lock); 2519#endif /* COM_MULTIPORT */ 2520} 2521 2522static void 2523siointr1(com) 2524 struct com_s *com; 2525{ 2526 u_char line_status; 2527 u_char modem_status; 2528 u_char *ioptr; 2529 u_char recv_data; 2530 u_char int_ctl; 2531 u_char int_ctl_new; 2532 struct timecounter *tc; 2533 u_int count; 2534 2535#ifdef PC98 2536 u_char tmp = 0; 2537 u_char rsa_buf_status = 0; 2538 int rsa_tx_fifo_size = 0; 2539#endif /* PC98 */ 2540 2541 int_ctl = inb(com->intr_ctl_port); 2542 int_ctl_new = int_ctl; 2543 2544 while (!com->gone) { 2545#ifdef PC98 2546status_read:; 2547 if (IS_8251(com->pc98_if_type)) { 2548 if (com->pc98_8251fifo_enable) 2549 tmp = inb(I8251F_lsr); 2550 else 2551 tmp = inb(com->sts_port); 2552more_intr: 2553 line_status = 0; 2554 if (com->pc98_8251fifo_enable) { 2555 if (tmp & STS8251F_TxRDY) line_status |= LSR_TXRDY; 2556 if (tmp & STS8251F_RxRDY) line_status |= LSR_RXRDY; 2557 if (tmp & STS8251F_TxEMP) line_status |= LSR_TSRE; 2558 if (tmp & STS8251F_PE) line_status |= LSR_PE; 2559 if (tmp & STS8251F_OE) line_status |= LSR_OE; 2560 if (tmp & STS8251F_BD_SD) line_status |= LSR_BI; 2561 } else { 2562 if (tmp & STS8251_TxRDY) line_status |= LSR_TXRDY; 2563 if (tmp & STS8251_RxRDY) line_status |= LSR_RXRDY; 2564 if (tmp & STS8251_TxEMP) line_status |= LSR_TSRE; 2565 if (tmp & STS8251_PE) line_status |= LSR_PE; 2566 if (tmp & STS8251_OE) line_status |= LSR_OE; 2567 if (tmp & STS8251_FE) line_status |= LSR_FE; 2568 if (tmp & STS8251_BD_SD) line_status |= LSR_BI; 2569 } 2570 } else { 2571#endif /* PC98 */ 2572 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) { 2573 modem_status = inb(com->modem_status_port); 2574 if ((modem_status ^ com->last_modem_status) & MSR_DCD) { 2575 tc = timecounter; 2576 count = tc->tc_get_timecount(tc); 2577 pps_event(&com->pps, tc, count, 2578 (modem_status & MSR_DCD) ? 2579 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR); 2580 } 2581 } 2582 line_status = inb(com->line_status_port); 2583#ifdef PC98 2584 } 2585 if (com->pc98_if_type == COM_IF_RSA98III) 2586 rsa_buf_status = inb(com->rsabase + rsa_srr); 2587#endif /* PC98 */ 2588 2589 /* input event? (check first to help avoid overruns) */ 2590#ifndef PC98 2591 while (line_status & LSR_RCV_MASK) { 2592#else 2593 while ((line_status & LSR_RCV_MASK) 2594 || (com->pc98_if_type == COM_IF_RSA98III 2595 && (rsa_buf_status & 0x08))) { 2596#endif /* PC98 */ 2597 /* break/unnattached error bits or real input? */ 2598#ifdef PC98 2599 if (IS_8251(com->pc98_if_type)) { 2600 if (com->pc98_8251fifo_enable) { 2601 recv_data = inb(I8251F_data); 2602 if (tmp & (STS8251F_PE | STS8251F_OE | 2603 STS8251F_BD_SD)) { 2604 pc98_i8251_or_cmd(com, CMD8251_ER); 2605 recv_data = 0; 2606 } 2607 } else { 2608 recv_data = inb(com->data_port); 2609 if (tmp & (STS8251_PE | STS8251_OE | 2610 STS8251_FE | STS8251_BD_SD)) { 2611 pc98_i8251_or_cmd(com, CMD8251_ER); 2612 recv_data = 0; 2613 } 2614 } 2615 } else if (com->pc98_if_type == COM_IF_RSA98III) { 2616 if (!(rsa_buf_status & 0x08)) 2617 recv_data = 0; 2618 else 2619 recv_data = inb(com->data_port); 2620 } else 2621#endif 2622 if (!(line_status & LSR_RXRDY)) 2623 recv_data = 0; 2624 else 2625 recv_data = inb(com->data_port); 2626#if defined(DDB) && defined(ALT_BREAK_TO_DEBUGGER) 2627 /* 2628 * Solaris implements a new BREAK which is initiated 2629 * by a character sequence CR ~ ^b which is similar 2630 * to a familiar pattern used on Sun servers by the 2631 * Remote Console. 2632 */ 2633#define KEY_CRTLB 2 /* ^B */ 2634#define KEY_CR 13 /* CR '\r' */ 2635#define KEY_TILDE 126 /* ~ */ 2636 2637 if (com->unit == comconsole) { 2638 static int brk_state1 = 0, brk_state2 = 0; 2639 if (recv_data == KEY_CR) { 2640 brk_state1 = recv_data; 2641 brk_state2 = 0; 2642 } else if (brk_state1 == KEY_CR && (recv_data == KEY_TILDE || recv_data == KEY_CRTLB)) { 2643 if (recv_data == KEY_TILDE) 2644 brk_state2 = recv_data; 2645 else if (brk_state2 == KEY_TILDE && recv_data == KEY_CRTLB) { 2646 breakpoint(); 2647 brk_state1 = brk_state2 = 0; 2648 goto cont; 2649 } else 2650 brk_state2 = 0; 2651 } else 2652 brk_state1 = 0; 2653 } 2654#endif 2655 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) { 2656 /* 2657 * Don't store BI if IGNBRK or FE/PE if IGNPAR. 2658 * Otherwise, push the work to a higher level 2659 * (to handle PARMRK) if we're bypassing. 2660 * Otherwise, convert BI/FE and PE+INPCK to 0. 2661 * 2662 * This makes bypassing work right in the 2663 * usual "raw" case (IGNBRK set, and IGNPAR 2664 * and INPCK clear). 2665 * 2666 * Note: BI together with FE/PE means just BI. 2667 */ 2668 if (line_status & LSR_BI) { 2669#if defined(DDB) && defined(BREAK_TO_DEBUGGER) 2670 if (com->unit == comconsole) { 2671 breakpoint(); 2672 goto cont; 2673 } 2674#endif 2675 if (com->tp == NULL 2676 || com->tp->t_iflag & IGNBRK) 2677 goto cont; 2678 } else { 2679 if (com->tp == NULL 2680 || com->tp->t_iflag & IGNPAR) 2681 goto cont; 2682 } 2683 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT 2684 && (line_status & (LSR_BI | LSR_FE) 2685 || com->tp->t_iflag & INPCK)) 2686 recv_data = 0; 2687 } 2688 ++com->bytes_in; 2689 if (com->hotchar != 0 && recv_data == com->hotchar) 2690 swi_sched(sio_fast_ih, 0); 2691 ioptr = com->iptr; 2692 if (ioptr >= com->ibufend) 2693 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW); 2694 else { 2695 if (com->do_timestamp) 2696 microtime(&com->timestamp); 2697 ++com_events; 2698 swi_sched(sio_slow_ih, SWI_DELAY); 2699#if 0 /* for testing input latency vs efficiency */ 2700if (com->iptr - com->ibuf == 8) 2701 swi_sched(sio_fast_ih, 0); 2702#endif 2703 ioptr[0] = recv_data; 2704 ioptr[com->ierroff] = line_status; 2705 com->iptr = ++ioptr; 2706 if (ioptr == com->ihighwater 2707 && com->state & CS_RTS_IFLOW) 2708#ifdef PC98 2709 IS_8251(com->pc98_if_type) ? 2710 com_tiocm_bic(com, TIOCM_RTS) : 2711#endif 2712 outb(com->modem_ctl_port, 2713 com->mcr_image &= ~MCR_RTS); 2714 if (line_status & LSR_OE) 2715 CE_RECORD(com, CE_OVERRUN); 2716 } 2717cont: 2718 /* 2719 * "& 0x7F" is to avoid the gcc-1.40 generating a slow 2720 * jump from the top of the loop to here 2721 */ 2722#ifdef PC98 2723 if (IS_8251(com->pc98_if_type)) 2724 goto status_read; 2725 else 2726#endif 2727 line_status = inb(com->line_status_port) & 0x7F; 2728#ifdef PC98 2729 if (com->pc98_if_type == COM_IF_RSA98III) 2730 rsa_buf_status = inb(com->rsabase + rsa_srr); 2731#endif /* PC98 */ 2732 } 2733 2734 /* modem status change? (always check before doing output) */ 2735#ifdef PC98 2736 if (!IS_8251(com->pc98_if_type)) { 2737#endif 2738 modem_status = inb(com->modem_status_port); 2739 if (modem_status != com->last_modem_status) { 2740 if (com->do_dcd_timestamp 2741 && !(com->last_modem_status & MSR_DCD) 2742 && modem_status & MSR_DCD) 2743 microtime(&com->dcd_timestamp); 2744 2745 /* 2746 * Schedule high level to handle DCD changes. Note 2747 * that we don't use the delta bits anywhere. Some 2748 * UARTs mess them up, and it's easy to remember the 2749 * previous bits and calculate the delta. 2750 */ 2751 com->last_modem_status = modem_status; 2752 if (!(com->state & CS_CHECKMSR)) { 2753 com_events += LOTS_OF_EVENTS; 2754 com->state |= CS_CHECKMSR; 2755 swi_sched(sio_fast_ih, 0); 2756 } 2757 2758 /* handle CTS change immediately for crisp flow ctl */ 2759 if (com->state & CS_CTS_OFLOW) { 2760 if (modem_status & MSR_CTS) 2761 com->state |= CS_ODEVREADY; 2762 else 2763 com->state &= ~CS_ODEVREADY; 2764 } 2765 } 2766#ifdef PC98 2767 } 2768#endif 2769 2770 /* output queued and everything ready? */ 2771#ifndef PC98 2772 if (line_status & LSR_TXRDY 2773 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 2774#else 2775 if (((com->pc98_if_type == COM_IF_RSA98III) 2776 ? (rsa_buf_status & 0x02) 2777 : (line_status & LSR_TXRDY)) 2778 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 2779#endif 2780#ifdef PC98 2781 Port_t tmp_data_port; 2782 2783 if (IS_8251(com->pc98_if_type) && 2784 com->pc98_8251fifo_enable) 2785 tmp_data_port = I8251F_data; 2786 else 2787 tmp_data_port = com->data_port; 2788#endif 2789 2790 ioptr = com->obufq.l_head; 2791 if (com->tx_fifo_size > 1) { 2792 u_int ocount; 2793 2794 ocount = com->obufq.l_tail - ioptr; 2795#ifdef PC98 2796 if (com->pc98_if_type == COM_IF_RSA98III) { 2797 rsa_buf_status = inb(com->rsabase + rsa_srr); 2798 rsa_tx_fifo_size = 1024; 2799 if (!(rsa_buf_status & 0x01)) 2800 rsa_tx_fifo_size = 2048; 2801 if (ocount > rsa_tx_fifo_size) 2802 ocount = rsa_tx_fifo_size; 2803 } else 2804#endif 2805 if (ocount > com->tx_fifo_size) 2806 ocount = com->tx_fifo_size; 2807 com->bytes_out += ocount; 2808 do 2809#ifdef PC98 2810 outb(tmp_data_port, *ioptr++); 2811#else 2812 outb(com->data_port, *ioptr++); 2813#endif 2814 while (--ocount != 0); 2815 } else { 2816#ifdef PC98 2817 outb(tmp_data_port, *ioptr++); 2818#else 2819 outb(com->data_port, *ioptr++); 2820#endif 2821 ++com->bytes_out; 2822 } 2823#ifdef PC98 2824 if (IS_8251(com->pc98_if_type)) 2825 if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG)) 2826 com_int_Tx_enable(com); 2827#endif 2828 com->obufq.l_head = ioptr; 2829 if (COM_IIR_TXRDYBUG(com->flags)) { 2830 int_ctl_new = int_ctl | IER_ETXRDY; 2831 } 2832 if (ioptr >= com->obufq.l_tail) { 2833 struct lbq *qp; 2834 2835 qp = com->obufq.l_next; 2836 qp->l_queued = FALSE; 2837 qp = qp->l_next; 2838 if (qp != NULL) { 2839 com->obufq.l_head = qp->l_head; 2840 com->obufq.l_tail = qp->l_tail; 2841 com->obufq.l_next = qp; 2842 } else { 2843 /* output just completed */ 2844 if (COM_IIR_TXRDYBUG(com->flags)) { 2845 int_ctl_new = int_ctl & ~IER_ETXRDY; 2846 } 2847 com->state &= ~CS_BUSY; 2848#if defined(PC98) 2849 if (IS_8251(com->pc98_if_type) && 2850 pc98_check_i8251_interrupt(com) & IEN_TxFLAG) 2851 com_int_Tx_disable(com); 2852#endif 2853 } 2854 if (!(com->state & CS_ODONE)) { 2855 com_events += LOTS_OF_EVENTS; 2856 com->state |= CS_ODONE; 2857 /* handle at high level ASAP */ 2858 swi_sched(sio_fast_ih, 0); 2859 } 2860 } 2861 if (COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) { 2862#ifdef PC98 2863 if (com->pc98_if_type == COM_IF_RSA98III) { 2864 int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY); 2865 outb(com->intr_ctl_port, int_ctl_new); 2866 outb(com->rsabase + rsa_ier, 0x1d); 2867 } else 2868#endif 2869 outb(com->intr_ctl_port, int_ctl_new); 2870 } 2871 } 2872#ifdef PC98 2873 else if (line_status & LSR_TXRDY) { 2874 if (IS_8251(com->pc98_if_type)) 2875 if (pc98_check_i8251_interrupt(com) & IEN_TxFLAG) 2876 com_int_Tx_disable(com); 2877 } 2878 if (IS_8251(com->pc98_if_type)) { 2879 if (com->pc98_8251fifo_enable) { 2880 if ((tmp = inb(I8251F_lsr)) & STS8251F_RxRDY) 2881 goto more_intr; 2882 } else { 2883 if ((tmp = inb(com->sts_port)) & STS8251_RxRDY) 2884 goto more_intr; 2885 } 2886 } 2887#endif 2888 2889 /* finished? */ 2890#ifndef COM_MULTIPORT 2891#ifdef PC98 2892 if (IS_8251(com->pc98_if_type)) 2893 return; 2894#endif 2895 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND) 2896#endif /* COM_MULTIPORT */ 2897 return; 2898 } 2899} 2900 2901static int 2902sioioctl(dev, cmd, data, flag, td) 2903 dev_t dev; 2904 u_long cmd; 2905 caddr_t data; 2906 int flag; 2907 struct thread *td; 2908{ 2909 struct com_s *com; 2910 int error; 2911 int mynor; 2912 int s; 2913 struct tty *tp; 2914#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 2915 u_long oldcmd; 2916 struct termios term; 2917#endif 2918 2919 mynor = minor(dev); 2920 com = com_addr(MINOR_TO_UNIT(mynor)); 2921 if (com == NULL || com->gone) 2922 return (ENODEV); 2923 if (mynor & CONTROL_MASK) { 2924 struct termios *ct; 2925 2926 switch (mynor & CONTROL_MASK) { 2927 case CONTROL_INIT_STATE: 2928 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in; 2929 break; 2930 case CONTROL_LOCK_STATE: 2931 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in; 2932 break; 2933 default: 2934 return (ENODEV); /* /dev/nodev */ 2935 } 2936 switch (cmd) { 2937 case TIOCSETA: 2938 error = suser_td(td); 2939 if (error != 0) 2940 return (error); 2941 *ct = *(struct termios *)data; 2942 return (0); 2943 case TIOCGETA: 2944 *(struct termios *)data = *ct; 2945 return (0); 2946 case TIOCGETD: 2947 *(int *)data = TTYDISC; 2948 return (0); 2949 case TIOCGWINSZ: 2950 bzero(data, sizeof(struct winsize)); 2951 return (0); 2952 default: 2953 return (ENOTTY); 2954 } 2955 } 2956 tp = com->tp; 2957#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 2958 term = tp->t_termios; 2959 oldcmd = cmd; 2960 error = ttsetcompat(tp, &cmd, data, &term); 2961 if (error != 0) 2962 return (error); 2963 if (cmd != oldcmd) 2964 data = (caddr_t)&term; 2965#endif 2966 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) { 2967 int cc; 2968 struct termios *dt = (struct termios *)data; 2969 struct termios *lt = mynor & CALLOUT_MASK 2970 ? &com->lt_out : &com->lt_in; 2971 2972 dt->c_iflag = (tp->t_iflag & lt->c_iflag) 2973 | (dt->c_iflag & ~lt->c_iflag); 2974 dt->c_oflag = (tp->t_oflag & lt->c_oflag) 2975 | (dt->c_oflag & ~lt->c_oflag); 2976 dt->c_cflag = (tp->t_cflag & lt->c_cflag) 2977 | (dt->c_cflag & ~lt->c_cflag); 2978 dt->c_lflag = (tp->t_lflag & lt->c_lflag) 2979 | (dt->c_lflag & ~lt->c_lflag); 2980 for (cc = 0; cc < NCCS; ++cc) 2981 if (lt->c_cc[cc] != 0) 2982 dt->c_cc[cc] = tp->t_cc[cc]; 2983 if (lt->c_ispeed != 0) 2984 dt->c_ispeed = tp->t_ispeed; 2985 if (lt->c_ospeed != 0) 2986 dt->c_ospeed = tp->t_ospeed; 2987 } 2988 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, td); 2989 if (error != ENOIOCTL) 2990 return (error); 2991 s = spltty(); 2992 error = ttioctl(tp, cmd, data, flag); 2993 disc_optim(tp, &tp->t_termios, com); 2994 if (error != ENOIOCTL) { 2995 splx(s); 2996 return (error); 2997 } 2998#ifdef PC98 2999 if (IS_8251(com->pc98_if_type)) { 3000 switch (cmd) { 3001 case TIOCSBRK: 3002 com_send_break_on(com); 3003 break; 3004 case TIOCCBRK: 3005 com_send_break_off(com); 3006 break; 3007 case TIOCSDTR: 3008 com_tiocm_bis(com, TIOCM_DTR | TIOCM_RTS); 3009 break; 3010 case TIOCCDTR: 3011 com_tiocm_bic(com, TIOCM_DTR); 3012 break; 3013 /* 3014 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 3015 * changes get undone on the next call to comparam(). 3016 */ 3017 case TIOCMSET: 3018 com_tiocm_set(com, *(int *)data); 3019 break; 3020 case TIOCMBIS: 3021 com_tiocm_bis(com, *(int *)data); 3022 break; 3023 case TIOCMBIC: 3024 com_tiocm_bic(com, *(int *)data); 3025 break; 3026 case TIOCMGET: 3027 *(int *)data = com_tiocm_get(com); 3028 break; 3029 case TIOCMSDTRWAIT: 3030 /* must be root since the wait applies to following logins */ 3031 error = suser_td(td); 3032 if (error != 0) { 3033 splx(s); 3034 return (error); 3035 } 3036 com->dtr_wait = *(int *)data * hz / 100; 3037 break; 3038 case TIOCMGDTRWAIT: 3039 *(int *)data = com->dtr_wait * 100 / hz; 3040 break; 3041 case TIOCTIMESTAMP: 3042 com->do_timestamp = TRUE; 3043 *(struct timeval *)data = com->timestamp; 3044 break; 3045 case TIOCDCDTIMESTAMP: 3046 com->do_dcd_timestamp = TRUE; 3047 *(struct timeval *)data = com->dcd_timestamp; 3048 break; 3049 default: 3050 splx(s); 3051 error = pps_ioctl(cmd, data, &com->pps); 3052 if (error == ENODEV) 3053 error = ENOTTY; 3054 return (error); 3055 } 3056 } else { 3057#endif 3058 switch (cmd) { 3059 case TIOCSBRK: 3060 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK); 3061 break; 3062 case TIOCCBRK: 3063 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 3064 break; 3065 case TIOCSDTR: 3066 (void)commctl(com, TIOCM_DTR, DMBIS); 3067 break; 3068 case TIOCCDTR: 3069 (void)commctl(com, TIOCM_DTR, DMBIC); 3070 break; 3071 /* 3072 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 3073 * changes get undone on the next call to comparam(). 3074 */ 3075 case TIOCMSET: 3076 (void)commctl(com, *(int *)data, DMSET); 3077 break; 3078 case TIOCMBIS: 3079 (void)commctl(com, *(int *)data, DMBIS); 3080 break; 3081 case TIOCMBIC: 3082 (void)commctl(com, *(int *)data, DMBIC); 3083 break; 3084 case TIOCMGET: 3085 *(int *)data = commctl(com, 0, DMGET); 3086 break; 3087 case TIOCMSDTRWAIT: 3088 /* must be root since the wait applies to following logins */ 3089 error = suser_td(td); 3090 if (error != 0) { 3091 splx(s); 3092 return (error); 3093 } 3094 com->dtr_wait = *(int *)data * hz / 100; 3095 break; 3096 case TIOCMGDTRWAIT: 3097 *(int *)data = com->dtr_wait * 100 / hz; 3098 break; 3099 case TIOCTIMESTAMP: 3100 com->do_timestamp = TRUE; 3101 *(struct timeval *)data = com->timestamp; 3102 break; 3103 case TIOCDCDTIMESTAMP: 3104 com->do_dcd_timestamp = TRUE; 3105 *(struct timeval *)data = com->dcd_timestamp; 3106 break; 3107 default: 3108 splx(s); 3109 error = pps_ioctl(cmd, data, &com->pps); 3110 if (error == ENODEV) 3111 error = ENOTTY; 3112 return (error); 3113 } 3114#ifdef PC98 3115 } 3116#endif 3117 splx(s); 3118 return (0); 3119} 3120 3121/* software interrupt handler for SWI_TTY */ 3122static void 3123siopoll(void *dummy) 3124{ 3125 int unit; 3126 3127 if (com_events == 0) 3128 return; 3129repeat: 3130 for (unit = 0; unit < sio_numunits; ++unit) { 3131 struct com_s *com; 3132 int incc; 3133 struct tty *tp; 3134 3135 com = com_addr(unit); 3136 if (com == NULL) 3137 continue; 3138 tp = com->tp; 3139 if (tp == NULL || com->gone) { 3140 /* 3141 * Discard any events related to never-opened or 3142 * going-away devices. 3143 */ 3144 mtx_lock_spin(&sio_lock); 3145 incc = com->iptr - com->ibuf; 3146 com->iptr = com->ibuf; 3147 if (com->state & CS_CHECKMSR) { 3148 incc += LOTS_OF_EVENTS; 3149 com->state &= ~CS_CHECKMSR; 3150 } 3151 com_events -= incc; 3152 mtx_unlock_spin(&sio_lock); 3153 continue; 3154 } 3155 if (com->iptr != com->ibuf) { 3156 mtx_lock_spin(&sio_lock); 3157 sioinput(com); 3158 mtx_unlock_spin(&sio_lock); 3159 } 3160 if (com->state & CS_CHECKMSR) { 3161 u_char delta_modem_status; 3162 3163#ifdef PC98 3164 if (!IS_8251(com->pc98_if_type)) { 3165#endif 3166 mtx_lock_spin(&sio_lock); 3167 delta_modem_status = com->last_modem_status 3168 ^ com->prev_modem_status; 3169 com->prev_modem_status = com->last_modem_status; 3170 com_events -= LOTS_OF_EVENTS; 3171 com->state &= ~CS_CHECKMSR; 3172 mtx_unlock_spin(&sio_lock); 3173 if (delta_modem_status & MSR_DCD) 3174 (*linesw[tp->t_line].l_modem) 3175 (tp, com->prev_modem_status & MSR_DCD); 3176#ifdef PC98 3177 } 3178#endif 3179 } 3180 if (com->state & CS_ODONE) { 3181 mtx_lock_spin(&sio_lock); 3182 com_events -= LOTS_OF_EVENTS; 3183 com->state &= ~CS_ODONE; 3184 mtx_unlock_spin(&sio_lock); 3185 if (!(com->state & CS_BUSY) 3186 && !(com->extra_state & CSE_BUSYCHECK)) { 3187 timeout(siobusycheck, com, hz / 100); 3188 com->extra_state |= CSE_BUSYCHECK; 3189 } 3190 (*linesw[tp->t_line].l_start)(tp); 3191 } 3192 if (com_events == 0) 3193 break; 3194 } 3195 if (com_events >= LOTS_OF_EVENTS) 3196 goto repeat; 3197} 3198 3199static int 3200comparam(tp, t) 3201 struct tty *tp; 3202 struct termios *t; 3203{ 3204 u_int cfcr; 3205 int cflag; 3206 struct com_s *com; 3207 u_int divisor; 3208 u_char dlbh; 3209 u_char dlbl; 3210 int s; 3211 int unit; 3212#ifdef PC98 3213 u_char param = 0; 3214#endif 3215 3216 unit = DEV_TO_UNIT(tp->t_dev); 3217 com = com_addr(unit); 3218 if (com == NULL) 3219 return (ENODEV); 3220 3221#ifdef PC98 3222 cfcr = 0; 3223 3224 if (IS_8251(com->pc98_if_type)) { 3225 if (pc98_ttspeedtab(com, t->c_ospeed, &divisor) != 0) 3226 return (EINVAL); 3227 } else { 3228#endif 3229 /* do historical conversions */ 3230 if (t->c_ispeed == 0) 3231 t->c_ispeed = t->c_ospeed; 3232 3233 /* check requested parameters */ 3234 if (t->c_ospeed == 0) 3235 divisor = 0; 3236 else { 3237 if (t->c_ispeed != t->c_ospeed) 3238 return (EINVAL); 3239 divisor = siodivisor(com->rclk, t->c_ispeed); 3240 if (divisor == 0) 3241 return (EINVAL); 3242 } 3243#ifdef PC98 3244 } 3245#endif 3246 3247 /* parameters are OK, convert them to the com struct and the device */ 3248 s = spltty(); 3249#ifdef PC98 3250 if (IS_8251(com->pc98_if_type)) { 3251 if (divisor == 0) 3252 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 3253 else 3254 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 3255 } else 3256#endif 3257 if (divisor == 0) 3258 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */ 3259 else 3260 (void)commctl(com, TIOCM_DTR, DMBIS); 3261 cflag = t->c_cflag; 3262#ifdef PC98 3263 if (!IS_8251(com->pc98_if_type)) { 3264#endif 3265 switch (cflag & CSIZE) { 3266 case CS5: 3267 cfcr = CFCR_5BITS; 3268 break; 3269 case CS6: 3270 cfcr = CFCR_6BITS; 3271 break; 3272 case CS7: 3273 cfcr = CFCR_7BITS; 3274 break; 3275 default: 3276 cfcr = CFCR_8BITS; 3277 break; 3278 } 3279 if (cflag & PARENB) { 3280 cfcr |= CFCR_PENAB; 3281 if (!(cflag & PARODD)) 3282 cfcr |= CFCR_PEVEN; 3283 } 3284 if (cflag & CSTOPB) 3285 cfcr |= CFCR_STOPB; 3286 3287 if (com->hasfifo && divisor != 0) { 3288 /* 3289 * Use a fifo trigger level low enough so that the input 3290 * latency from the fifo is less than about 16 msec and 3291 * the total latency is less than about 30 msec. These 3292 * latencies are reasonable for humans. Serial comms 3293 * protocols shouldn't expect anything better since modem 3294 * latencies are larger. 3295 * 3296 * We have to set the FIFO trigger point such that we 3297 * don't overflow it accidently if a serial interrupt 3298 * is delayed. At high speeds, FIFO_RX_HIGH does not 3299 * leave enough slots free. 3300 */ 3301 com->fifo_image = t->c_ospeed <= 4800 3302 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_MEDH; 3303#ifdef COM_ESP 3304 /* 3305 * The Hayes ESP card needs the fifo DMA mode bit set 3306 * in compatibility mode. If not, it will interrupt 3307 * for each character received. 3308 */ 3309 if (com->esp) 3310 com->fifo_image |= FIFO_DMA_MODE; 3311#endif 3312 sio_setreg(com, com_fifo, com->fifo_image); 3313 } 3314#ifdef PC98 3315 } 3316#endif 3317 3318 /* 3319 * This returns with interrupts disabled so that we can complete 3320 * the speed change atomically. Keeping interrupts disabled is 3321 * especially important while com_data is hidden. 3322 */ 3323 (void) siosetwater(com, t->c_ispeed); 3324 3325#ifdef PC98 3326 if (IS_8251(com->pc98_if_type)) 3327 com_cflag_and_speed_set(com, cflag, t->c_ospeed); 3328 else { 3329#endif 3330 if (divisor != 0) { 3331 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB); 3332 /* 3333 * Only set the divisor registers if they would change, 3334 * since on some 16550 incompatibles (UMC8669F), setting 3335 * them while input is arriving them loses sync until 3336 * data stops arriving. 3337 */ 3338 dlbl = divisor & 0xFF; 3339 if (sio_getreg(com, com_dlbl) != dlbl) 3340 sio_setreg(com, com_dlbl, dlbl); 3341 dlbh = divisor >> 8; 3342 if (sio_getreg(com, com_dlbh) != dlbh) 3343 sio_setreg(com, com_dlbh, dlbh); 3344 } 3345 3346 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr); 3347#ifdef PC98 3348 } 3349#endif 3350 3351 if (!(tp->t_state & TS_TTSTOP)) 3352 com->state |= CS_TTGO; 3353 3354 if (cflag & CRTS_IFLOW) { 3355#ifndef PC98 3356 if (com->st16650a) { 3357 sio_setreg(com, com_cfcr, 0xbf); 3358 sio_setreg(com, com_fifo, 3359 sio_getreg(com, com_fifo) | 0x40); 3360 } 3361#endif 3362 com->state |= CS_RTS_IFLOW; 3363 /* 3364 * If CS_RTS_IFLOW just changed from off to on, the change 3365 * needs to be propagated to MCR_RTS. This isn't urgent, 3366 * so do it later by calling comstart() instead of repeating 3367 * a lot of code from comstart() here. 3368 */ 3369 } else if (com->state & CS_RTS_IFLOW) { 3370 com->state &= ~CS_RTS_IFLOW; 3371 /* 3372 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS 3373 * on here, since comstart() won't do it later. 3374 */ 3375#ifdef PC98 3376 if (IS_8251(com->pc98_if_type)) 3377 com_tiocm_bis(com, TIOCM_RTS); 3378 else 3379 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3380#else 3381 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3382 if (com->st16650a) { 3383 sio_setreg(com, com_cfcr, 0xbf); 3384 sio_setreg(com, com_fifo, 3385 sio_getreg(com, com_fifo) & ~0x40); 3386 } 3387#endif 3388 } 3389 3390 3391 /* 3392 * Set up state to handle output flow control. 3393 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level? 3394 * Now has 10+ msec latency, while CTS flow has 50- usec latency. 3395 */ 3396 com->state |= CS_ODEVREADY; 3397 com->state &= ~CS_CTS_OFLOW; 3398#ifdef PC98 3399 if (com->pc98_if_type == COM_IF_RSA98III) { 3400 param = inb(com->rsabase + rsa_msr); 3401 outb(com->rsabase + rsa_msr, param & 0x14); 3402 } 3403#endif 3404 if (cflag & CCTS_OFLOW) { 3405 com->state |= CS_CTS_OFLOW; 3406#ifdef PC98 3407 if (IS_8251(com->pc98_if_type)) { 3408 if (!(pc98_get_modem_status(com) & TIOCM_CTS)) 3409 com->state &= ~CS_ODEVREADY; 3410 } else { 3411 if (com->pc98_if_type == COM_IF_RSA98III) { 3412 /* Set automatic flow control mode */ 3413 outb(com->rsabase + rsa_msr, param | 0x08); 3414 } else 3415#endif 3416 if (!(com->last_modem_status & MSR_CTS)) 3417 com->state &= ~CS_ODEVREADY; 3418#ifdef PC98 3419 } 3420#else 3421 if (com->st16650a) { 3422 sio_setreg(com, com_cfcr, 0xbf); 3423 sio_setreg(com, com_fifo, 3424 sio_getreg(com, com_fifo) | 0x80); 3425 } 3426 } else { 3427 if (com->st16650a) { 3428 sio_setreg(com, com_cfcr, 0xbf); 3429 sio_setreg(com, com_fifo, 3430 sio_getreg(com, com_fifo) & ~0x80); 3431 } 3432#endif 3433 } 3434 3435#ifdef PC98 3436 if (!IS_8251(com->pc98_if_type)) 3437#endif 3438 sio_setreg(com, com_cfcr, com->cfcr_image); 3439 3440 /* XXX shouldn't call functions while intrs are disabled. */ 3441 disc_optim(tp, t, com); 3442 /* 3443 * Recover from fiddling with CS_TTGO. We used to call siointr1() 3444 * unconditionally, but that defeated the careful discarding of 3445 * stale input in sioopen(). 3446 */ 3447 if (com->state >= (CS_BUSY | CS_TTGO)) 3448 siointr1(com); 3449 3450 mtx_unlock_spin(&sio_lock); 3451 splx(s); 3452 comstart(tp); 3453 if (com->ibufold != NULL) { 3454 free(com->ibufold, M_DEVBUF); 3455 com->ibufold = NULL; 3456 } 3457 return (0); 3458} 3459 3460/* 3461 * This function must be called with the sio_lock mutex released and will 3462 * return with it obtained. 3463 */ 3464static int 3465siosetwater(com, speed) 3466 struct com_s *com; 3467 speed_t speed; 3468{ 3469 int cp4ticks; 3470 u_char *ibuf; 3471 int ibufsize; 3472 struct tty *tp; 3473 3474 /* 3475 * Make the buffer size large enough to handle a softtty interrupt 3476 * latency of about 2 ticks without loss of throughput or data 3477 * (about 3 ticks if input flow control is not used or not honoured, 3478 * but a bit less for CS5-CS7 modes). 3479 */ 3480 cp4ticks = speed / 10 / hz * 4; 3481 for (ibufsize = 128; ibufsize < cp4ticks;) 3482 ibufsize <<= 1; 3483#ifdef PC98 3484 if (com->pc98_if_type == COM_IF_RSA98III) 3485 ibufsize = 2048; 3486#endif 3487 if (ibufsize == com->ibufsize) { 3488 mtx_lock_spin(&sio_lock); 3489 return (0); 3490 } 3491 3492 /* 3493 * Allocate input buffer. The extra factor of 2 in the size is 3494 * to allow for an error byte for each input byte. 3495 */ 3496 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT); 3497 if (ibuf == NULL) { 3498 mtx_lock_spin(&sio_lock); 3499 return (ENOMEM); 3500 } 3501 3502 /* Initialize non-critical variables. */ 3503 com->ibufold = com->ibuf; 3504 com->ibufsize = ibufsize; 3505 tp = com->tp; 3506 if (tp != NULL) { 3507 tp->t_ififosize = 2 * ibufsize; 3508 tp->t_ispeedwat = (speed_t)-1; 3509 tp->t_ospeedwat = (speed_t)-1; 3510 } 3511 3512 /* 3513 * Read current input buffer, if any. Continue with interrupts 3514 * disabled. 3515 */ 3516 mtx_lock_spin(&sio_lock); 3517 if (com->iptr != com->ibuf) 3518 sioinput(com); 3519 3520 /*- 3521 * Initialize critical variables, including input buffer watermarks. 3522 * The external device is asked to stop sending when the buffer 3523 * exactly reaches high water, or when the high level requests it. 3524 * The high level is notified immediately (rather than at a later 3525 * clock tick) when this watermark is reached. 3526 * The buffer size is chosen so the watermark should almost never 3527 * be reached. 3528 * The low watermark is invisibly 0 since the buffer is always 3529 * emptied all at once. 3530 */ 3531 com->iptr = com->ibuf = ibuf; 3532 com->ibufend = ibuf + ibufsize; 3533 com->ierroff = ibufsize; 3534 com->ihighwater = ibuf + 3 * ibufsize / 4; 3535 return (0); 3536} 3537 3538static void 3539comstart(tp) 3540 struct tty *tp; 3541{ 3542 struct com_s *com; 3543 int s; 3544 int unit; 3545 3546 unit = DEV_TO_UNIT(tp->t_dev); 3547 com = com_addr(unit); 3548 if (com == NULL) 3549 return; 3550 s = spltty(); 3551 mtx_lock_spin(&sio_lock); 3552 if (tp->t_state & TS_TTSTOP) 3553 com->state &= ~CS_TTGO; 3554 else 3555 com->state |= CS_TTGO; 3556 if (tp->t_state & TS_TBLOCK) { 3557#ifdef PC98 3558 if (IS_8251(com->pc98_if_type)) { 3559 if ((com_tiocm_get(com) & TIOCM_RTS) && 3560 (com->state & CS_RTS_IFLOW)) 3561 com_tiocm_bic(com, TIOCM_RTS); 3562 } else { 3563 if ((com->mcr_image & MCR_RTS) && 3564 (com->state & CS_RTS_IFLOW)) 3565 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3566 } 3567#else 3568 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW) 3569 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3570#endif 3571 } else { 3572#ifdef PC98 3573 if (IS_8251(com->pc98_if_type)) { 3574 if (!(com_tiocm_get(com) & TIOCM_RTS) && 3575 com->iptr < com->ihighwater && 3576 com->state & CS_RTS_IFLOW) 3577 com_tiocm_bis(com, TIOCM_RTS); 3578 } else { 3579 if (!(com->mcr_image & MCR_RTS) && 3580 com->iptr < com->ihighwater && 3581 com->state & CS_RTS_IFLOW) 3582 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3583 } 3584#else 3585 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater 3586 && com->state & CS_RTS_IFLOW) 3587 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3588#endif 3589 } 3590 mtx_unlock_spin(&sio_lock); 3591 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) { 3592 ttwwakeup(tp); 3593 splx(s); 3594 return; 3595 } 3596 if (tp->t_outq.c_cc != 0) { 3597 struct lbq *qp; 3598 struct lbq *next; 3599 3600 if (!com->obufs[0].l_queued) { 3601 com->obufs[0].l_tail 3602 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1, 3603#ifdef PC98 3604 com->obufsize); 3605#else 3606 sizeof com->obuf1); 3607#endif 3608 com->obufs[0].l_next = NULL; 3609 com->obufs[0].l_queued = TRUE; 3610 mtx_lock_spin(&sio_lock); 3611 if (com->state & CS_BUSY) { 3612 qp = com->obufq.l_next; 3613 while ((next = qp->l_next) != NULL) 3614 qp = next; 3615 qp->l_next = &com->obufs[0]; 3616 } else { 3617 com->obufq.l_head = com->obufs[0].l_head; 3618 com->obufq.l_tail = com->obufs[0].l_tail; 3619 com->obufq.l_next = &com->obufs[0]; 3620 com->state |= CS_BUSY; 3621 } 3622 mtx_unlock_spin(&sio_lock); 3623 } 3624 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) { 3625 com->obufs[1].l_tail 3626 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2, 3627#ifdef PC98 3628 com->obufsize); 3629#else 3630 sizeof com->obuf2); 3631#endif 3632 com->obufs[1].l_next = NULL; 3633 com->obufs[1].l_queued = TRUE; 3634 mtx_lock_spin(&sio_lock); 3635 if (com->state & CS_BUSY) { 3636 qp = com->obufq.l_next; 3637 while ((next = qp->l_next) != NULL) 3638 qp = next; 3639 qp->l_next = &com->obufs[1]; 3640 } else { 3641 com->obufq.l_head = com->obufs[1].l_head; 3642 com->obufq.l_tail = com->obufs[1].l_tail; 3643 com->obufq.l_next = &com->obufs[1]; 3644 com->state |= CS_BUSY; 3645 } 3646 mtx_unlock_spin(&sio_lock); 3647 } 3648 tp->t_state |= TS_BUSY; 3649 } 3650 mtx_lock_spin(&sio_lock); 3651 if (com->state >= (CS_BUSY | CS_TTGO)) 3652 siointr1(com); /* fake interrupt to start output */ 3653 mtx_unlock_spin(&sio_lock); 3654 ttwwakeup(tp); 3655 splx(s); 3656} 3657 3658static void 3659comstop(tp, rw) 3660 struct tty *tp; 3661 int rw; 3662{ 3663 struct com_s *com; 3664#ifdef PC98 3665 int rsa98_tmp = 0; 3666#endif 3667 3668 com = com_addr(DEV_TO_UNIT(tp->t_dev)); 3669 if (com == NULL || com->gone) 3670 return; 3671 mtx_lock_spin(&sio_lock); 3672 if (rw & FWRITE) { 3673#ifdef PC98 3674 if (!IS_8251(com->pc98_if_type)) { 3675#endif 3676 if (com->hasfifo) 3677#ifdef COM_ESP 3678 /* XXX avoid h/w bug. */ 3679 if (!com->esp) 3680#endif 3681 sio_setreg(com, com_fifo, 3682 FIFO_XMT_RST | com->fifo_image); 3683#ifdef PC98 3684 if (com->pc98_if_type == COM_IF_RSA98III) 3685 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3686 sio_setreg(com, com_fifo, 3687 FIFO_XMT_RST | com->fifo_image); 3688 } 3689#endif 3690 com->obufs[0].l_queued = FALSE; 3691 com->obufs[1].l_queued = FALSE; 3692 if (com->state & CS_ODONE) 3693 com_events -= LOTS_OF_EVENTS; 3694 com->state &= ~(CS_ODONE | CS_BUSY); 3695 com->tp->t_state &= ~TS_BUSY; 3696 } 3697 if (rw & FREAD) { 3698#ifdef PC98 3699 if (!IS_8251(com->pc98_if_type)) { 3700 if (com->pc98_if_type == COM_IF_RSA98III) 3701 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3702 sio_getreg(com, com_data); 3703#endif 3704 if (com->hasfifo) 3705#ifdef COM_ESP 3706 /* XXX avoid h/w bug. */ 3707 if (!com->esp) 3708#endif 3709 sio_setreg(com, com_fifo, 3710 FIFO_RCV_RST | com->fifo_image); 3711#ifdef PC98 3712 } 3713#endif 3714 com_events -= (com->iptr - com->ibuf); 3715 com->iptr = com->ibuf; 3716 } 3717 mtx_unlock_spin(&sio_lock); 3718 comstart(tp); 3719} 3720 3721static int 3722commctl(com, bits, how) 3723 struct com_s *com; 3724 int bits; 3725 int how; 3726{ 3727 int mcr; 3728 int msr; 3729 3730 if (how == DMGET) { 3731 bits = TIOCM_LE; /* XXX - always enabled while open */ 3732 mcr = com->mcr_image; 3733 if (mcr & MCR_DTR) 3734 bits |= TIOCM_DTR; 3735 if (mcr & MCR_RTS) 3736 bits |= TIOCM_RTS; 3737 msr = com->prev_modem_status; 3738 if (msr & MSR_CTS) 3739 bits |= TIOCM_CTS; 3740 if (msr & MSR_DCD) 3741 bits |= TIOCM_CD; 3742 if (msr & MSR_DSR) 3743 bits |= TIOCM_DSR; 3744 /* 3745 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI 3746 * more volatile by reading the modem status a lot. Perhaps 3747 * we should latch both bits until the status is read here. 3748 */ 3749 if (msr & (MSR_RI | MSR_TERI)) 3750 bits |= TIOCM_RI; 3751 return (bits); 3752 } 3753 mcr = 0; 3754 if (bits & TIOCM_DTR) 3755 mcr |= MCR_DTR; 3756 if (bits & TIOCM_RTS) 3757 mcr |= MCR_RTS; 3758 if (com->gone) 3759 return(0); 3760 mtx_lock_spin(&sio_lock); 3761 switch (how) { 3762 case DMSET: 3763 outb(com->modem_ctl_port, 3764 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE)); 3765 break; 3766 case DMBIS: 3767 outb(com->modem_ctl_port, com->mcr_image |= mcr); 3768 break; 3769 case DMBIC: 3770 outb(com->modem_ctl_port, com->mcr_image &= ~mcr); 3771 break; 3772 } 3773 mtx_unlock_spin(&sio_lock); 3774 return (0); 3775} 3776 3777static void 3778siosettimeout() 3779{ 3780 struct com_s *com; 3781 bool_t someopen; 3782 int unit; 3783 3784 /* 3785 * Set our timeout period to 1 second if no polled devices are open. 3786 * Otherwise set it to max(1/200, 1/hz). 3787 * Enable timeouts iff some device is open. 3788 */ 3789 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 3790 sio_timeout = hz; 3791 someopen = FALSE; 3792 for (unit = 0; unit < sio_numunits; ++unit) { 3793 com = com_addr(unit); 3794 if (com != NULL && com->tp != NULL 3795 && com->tp->t_state & TS_ISOPEN && !com->gone) { 3796 someopen = TRUE; 3797 if (com->poll || com->poll_output) { 3798 sio_timeout = hz > 200 ? hz / 200 : 1; 3799 break; 3800 } 3801 } 3802 } 3803 if (someopen) { 3804 sio_timeouts_until_log = hz / sio_timeout; 3805 sio_timeout_handle = timeout(comwakeup, (void *)NULL, 3806 sio_timeout); 3807 } else { 3808 /* Flush error messages, if any. */ 3809 sio_timeouts_until_log = 1; 3810 comwakeup((void *)NULL); 3811 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 3812 } 3813} 3814 3815static void 3816comwakeup(chan) 3817 void *chan; 3818{ 3819 struct com_s *com; 3820 int unit; 3821 3822 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout); 3823 3824 /* 3825 * Recover from lost output interrupts. 3826 * Poll any lines that don't use interrupts. 3827 */ 3828 for (unit = 0; unit < sio_numunits; ++unit) { 3829 com = com_addr(unit); 3830 if (com != NULL && !com->gone 3831 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) { 3832 mtx_lock_spin(&sio_lock); 3833 siointr1(com); 3834 mtx_unlock_spin(&sio_lock); 3835 } 3836 } 3837 3838 /* 3839 * Check for and log errors, but not too often. 3840 */ 3841 if (--sio_timeouts_until_log > 0) 3842 return; 3843 sio_timeouts_until_log = hz / sio_timeout; 3844 for (unit = 0; unit < sio_numunits; ++unit) { 3845 int errnum; 3846 3847 com = com_addr(unit); 3848 if (com == NULL) 3849 continue; 3850 if (com->gone) 3851 continue; 3852 for (errnum = 0; errnum < CE_NTYPES; ++errnum) { 3853 u_int delta; 3854 u_long total; 3855 3856 mtx_lock_spin(&sio_lock); 3857 delta = com->delta_error_counts[errnum]; 3858 com->delta_error_counts[errnum] = 0; 3859 mtx_unlock_spin(&sio_lock); 3860 if (delta == 0) 3861 continue; 3862 total = com->error_counts[errnum] += delta; 3863 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n", 3864 unit, delta, error_desc[errnum], 3865 delta == 1 ? "" : "s", total); 3866 } 3867 } 3868} 3869 3870#ifdef PC98 3871/* commint is called when modem control line changes */ 3872static void 3873commint(dev_t dev) 3874{ 3875 register struct tty *tp; 3876 int stat,delta; 3877 struct com_s *com; 3878 int mynor,unit; 3879 3880 mynor = minor(dev); 3881 unit = MINOR_TO_UNIT(mynor); 3882 com = com_addr(unit); 3883 tp = com->tp; 3884 3885 stat = com_tiocm_get(com); 3886 delta = com_tiocm_get_delta(com); 3887 3888 if (com->state & CS_CTS_OFLOW) { 3889 if (stat & TIOCM_CTS) 3890 com->state |= CS_ODEVREADY; 3891 else 3892 com->state &= ~CS_ODEVREADY; 3893 } 3894 if ((delta & TIOCM_CAR) && (mynor & CALLOUT_MASK) == 0) { 3895 if (stat & TIOCM_CAR ) 3896 (void)(*linesw[tp->t_line].l_modem)(tp, 1); 3897 else if ((*linesw[tp->t_line].l_modem)(tp, 0) == 0) { 3898 /* negate DTR, RTS */ 3899 com_tiocm_bic(com, (tp->t_cflag & HUPCL) ? 3900 TIOCM_DTR|TIOCM_RTS|TIOCM_LE : TIOCM_LE ); 3901 /* disable IENABLE */ 3902 com_int_TxRx_disable( com ); 3903 } 3904 } 3905} 3906#endif 3907 3908static void 3909disc_optim(tp, t, com) 3910 struct tty *tp; 3911 struct termios *t; 3912 struct com_s *com; 3913{ 3914 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 3915 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 3916 && (!(t->c_iflag & PARMRK) 3917 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 3918 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 3919 && linesw[tp->t_line].l_rint == ttyinput) 3920 tp->t_state |= TS_CAN_BYPASS_L_RINT; 3921 else 3922 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 3923 com->hotchar = linesw[tp->t_line].l_hotchar; 3924} 3925 3926/* 3927 * Following are all routines needed for SIO to act as console 3928 */ 3929#include <sys/cons.h> 3930 3931struct siocnstate { 3932 u_char dlbl; 3933 u_char dlbh; 3934 u_char ier; 3935 u_char cfcr; 3936 u_char mcr; 3937}; 3938 3939#ifndef __alpha__ 3940static speed_t siocngetspeed(Port_t, u_long rclk); 3941#endif 3942static void siocnclose(struct siocnstate *sp, Port_t iobase); 3943static void siocnopen(struct siocnstate *sp, Port_t iobase, int speed); 3944static void siocntxwait(Port_t iobase); 3945 3946#ifdef __alpha__ 3947int siocnattach(int port, int speed); 3948int siogdbattach(int port, int speed); 3949int siogdbgetc(void); 3950void siogdbputc(int c); 3951#else 3952static cn_probe_t siocnprobe; 3953static cn_init_t siocninit; 3954static cn_term_t siocnterm; 3955#endif 3956static cn_checkc_t siocncheckc; 3957static cn_getc_t siocngetc; 3958static cn_putc_t siocnputc; 3959 3960#ifndef __alpha__ 3961CONS_DRIVER(sio, siocnprobe, siocninit, siocnterm, siocngetc, siocncheckc, 3962 siocnputc, NULL); 3963#endif 3964 3965/* To get the GDB related variables */ 3966#if DDB > 0 3967#include <ddb/ddb.h> 3968#endif 3969 3970static void 3971siocntxwait(iobase) 3972 Port_t iobase; 3973{ 3974 int timo; 3975 3976 /* 3977 * Wait for any pending transmission to finish. Required to avoid 3978 * the UART lockup bug when the speed is changed, and for normal 3979 * transmits. 3980 */ 3981 timo = 100000; 3982 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY)) 3983 != (LSR_TSRE | LSR_TXRDY) && --timo != 0) 3984 ; 3985} 3986 3987#ifndef __alpha__ 3988 3989/* 3990 * Read the serial port specified and try to figure out what speed 3991 * it's currently running at. We're assuming the serial port has 3992 * been initialized and is basicly idle. This routine is only intended 3993 * to be run at system startup. 3994 * 3995 * If the value read from the serial port doesn't make sense, return 0. 3996 */ 3997 3998static speed_t 3999siocngetspeed(iobase, rclk) 4000 Port_t iobase; 4001 u_long rclk; 4002{ 4003 u_int divisor; 4004 u_char dlbh; 4005 u_char dlbl; 4006 u_char cfcr; 4007 4008 cfcr = inb(iobase + com_cfcr); 4009 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 4010 4011 dlbl = inb(iobase + com_dlbl); 4012 dlbh = inb(iobase + com_dlbh); 4013 4014 outb(iobase + com_cfcr, cfcr); 4015 4016 divisor = dlbh << 8 | dlbl; 4017 4018 /* XXX there should be more sanity checking. */ 4019 if (divisor == 0) 4020 return (CONSPEED); 4021 return (rclk / (16UL * divisor)); 4022} 4023 4024#endif 4025 4026static void 4027siocnopen(sp, iobase, speed) 4028 struct siocnstate *sp; 4029 Port_t iobase; 4030 int speed; 4031{ 4032 u_int divisor; 4033 u_char dlbh; 4034 u_char dlbl; 4035 4036 /* 4037 * Save all the device control registers except the fifo register 4038 * and set our default ones (cs8 -parenb speed=comdefaultrate). 4039 * We can't save the fifo register since it is read-only. 4040 */ 4041 sp->ier = inb(iobase + com_ier); 4042 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */ 4043 siocntxwait(iobase); 4044 sp->cfcr = inb(iobase + com_cfcr); 4045 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 4046 sp->dlbl = inb(iobase + com_dlbl); 4047 sp->dlbh = inb(iobase + com_dlbh); 4048 /* 4049 * Only set the divisor registers if they would change, since on 4050 * some 16550 incompatibles (Startech), setting them clears the 4051 * data input register. This also reduces the effects of the 4052 * UMC8669F bug. 4053 */ 4054 divisor = siodivisor(comdefaultrclk, speed); 4055 dlbl = divisor & 0xFF; 4056 if (sp->dlbl != dlbl) 4057 outb(iobase + com_dlbl, dlbl); 4058 dlbh = divisor >> 8; 4059 if (sp->dlbh != dlbh) 4060 outb(iobase + com_dlbh, dlbh); 4061 outb(iobase + com_cfcr, CFCR_8BITS); 4062 sp->mcr = inb(iobase + com_mcr); 4063 /* 4064 * We don't want interrupts, but must be careful not to "disable" 4065 * them by clearing the MCR_IENABLE bit, since that might cause 4066 * an interrupt by floating the IRQ line. 4067 */ 4068 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS); 4069} 4070 4071static void 4072siocnclose(sp, iobase) 4073 struct siocnstate *sp; 4074 Port_t iobase; 4075{ 4076 /* 4077 * Restore the device control registers. 4078 */ 4079 siocntxwait(iobase); 4080 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 4081 if (sp->dlbl != inb(iobase + com_dlbl)) 4082 outb(iobase + com_dlbl, sp->dlbl); 4083 if (sp->dlbh != inb(iobase + com_dlbh)) 4084 outb(iobase + com_dlbh, sp->dlbh); 4085 outb(iobase + com_cfcr, sp->cfcr); 4086 /* 4087 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them. 4088 */ 4089 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS); 4090 outb(iobase + com_ier, sp->ier); 4091} 4092 4093#ifndef __alpha__ 4094 4095static void 4096siocnprobe(cp) 4097 struct consdev *cp; 4098{ 4099 speed_t boot_speed; 4100 u_char cfcr; 4101 u_int divisor; 4102 int s, unit; 4103 struct siocnstate sp; 4104 4105 /* 4106 * Find our first enabled console, if any. If it is a high-level 4107 * console device, then initialize it and return successfully. 4108 * If it is a low-level console device, then initialize it and 4109 * return unsuccessfully. It must be initialized in both cases 4110 * for early use by console drivers and debuggers. Initializing 4111 * the hardware is not necessary in all cases, since the i/o 4112 * routines initialize it on the fly, but it is necessary if 4113 * input might arrive while the hardware is switched back to an 4114 * uninitialized state. We can't handle multiple console devices 4115 * yet because our low-level routines don't take a device arg. 4116 * We trust the user to set the console flags properly so that we 4117 * don't need to probe. 4118 */ 4119 cp->cn_pri = CN_DEAD; 4120 4121 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */ 4122 int flags; 4123 int disabled; 4124 if (resource_int_value("sio", unit, "disabled", &disabled) == 0) { 4125 if (disabled) 4126 continue; 4127 } 4128 if (resource_int_value("sio", unit, "flags", &flags)) 4129 continue; 4130 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) { 4131 int port; 4132 Port_t iobase; 4133 4134 if (resource_int_value("sio", unit, "port", &port)) 4135 continue; 4136 iobase = port; 4137 s = spltty(); 4138 if (boothowto & RB_SERIAL) { 4139 boot_speed = 4140 siocngetspeed(iobase, comdefaultrclk); 4141 if (boot_speed) 4142 comdefaultrate = boot_speed; 4143 } 4144 4145 /* 4146 * Initialize the divisor latch. We can't rely on 4147 * siocnopen() to do this the first time, since it 4148 * avoids writing to the latch if the latch appears 4149 * to have the correct value. Also, if we didn't 4150 * just read the speed from the hardware, then we 4151 * need to set the speed in hardware so that 4152 * switching it later is null. 4153 */ 4154 cfcr = inb(iobase + com_cfcr); 4155 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 4156 divisor = siodivisor(comdefaultrclk, comdefaultrate); 4157 outb(iobase + com_dlbl, divisor & 0xff); 4158 outb(iobase + com_dlbh, divisor >> 8); 4159 outb(iobase + com_cfcr, cfcr); 4160 4161 siocnopen(&sp, iobase, comdefaultrate); 4162 4163 splx(s); 4164 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) { 4165 cp->cn_dev = makedev(CDEV_MAJOR, unit); 4166 cp->cn_pri = COM_FORCECONSOLE(flags) 4167 || boothowto & RB_SERIAL 4168 ? CN_REMOTE : CN_NORMAL; 4169 siocniobase = iobase; 4170 siocnunit = unit; 4171 } 4172 if (COM_DEBUGGER(flags)) { 4173 printf("sio%d: gdb debugging port\n", unit); 4174 siogdbiobase = iobase; 4175 siogdbunit = unit; 4176#if DDB > 0 4177 gdbdev = makedev(CDEV_MAJOR, unit); 4178 gdb_getc = siocngetc; 4179 gdb_putc = siocnputc; 4180#endif 4181 } 4182 } 4183 } 4184#ifdef __i386__ 4185#if DDB > 0 4186 /* 4187 * XXX Ugly Compatability. 4188 * If no gdb port has been specified, set it to be the console 4189 * as some configuration files don't specify the gdb port. 4190 */ 4191 if (gdbdev == NODEV && (boothowto & RB_GDB)) { 4192 printf("Warning: no GDB port specified. Defaulting to sio%d.\n", 4193 siocnunit); 4194 printf("Set flag 0x80 on desired GDB port in your\n"); 4195 printf("configuration file (currently sio only).\n"); 4196 siogdbiobase = siocniobase; 4197 siogdbunit = siocnunit; 4198 gdbdev = makedev(CDEV_MAJOR, siocnunit); 4199 gdb_getc = siocngetc; 4200 gdb_putc = siocnputc; 4201 } 4202#endif 4203#endif 4204} 4205 4206static void 4207siocninit(cp) 4208 struct consdev *cp; 4209{ 4210 comconsole = DEV_TO_UNIT(cp->cn_dev); 4211} 4212 4213static void 4214siocnterm(cp) 4215 struct consdev *cp; 4216{ 4217 comconsole = -1; 4218} 4219 4220#endif 4221 4222#ifdef __alpha__ 4223 4224CONS_DRIVER(sio, NULL, NULL, NULL, siocngetc, siocncheckc, siocnputc, NULL); 4225 4226int 4227siocnattach(port, speed) 4228 int port; 4229 int speed; 4230{ 4231 int s; 4232 u_char cfcr; 4233 u_int divisor; 4234 struct siocnstate sp; 4235 4236 siocniobase = port; 4237 comdefaultrate = speed; 4238 sio_consdev.cn_pri = CN_NORMAL; 4239 sio_consdev.cn_dev = makedev(CDEV_MAJOR, 0); 4240 4241 s = spltty(); 4242 4243 /* 4244 * Initialize the divisor latch. We can't rely on 4245 * siocnopen() to do this the first time, since it 4246 * avoids writing to the latch if the latch appears 4247 * to have the correct value. Also, if we didn't 4248 * just read the speed from the hardware, then we 4249 * need to set the speed in hardware so that 4250 * switching it later is null. 4251 */ 4252 cfcr = inb(siocniobase + com_cfcr); 4253 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr); 4254 divisor = siodivisor(comdefaultrclk, comdefaultrate); 4255 outb(siocniobase + com_dlbl, divisor & 0xff); 4256 outb(siocniobase + com_dlbh, divisor >> 8); 4257 outb(siocniobase + com_cfcr, cfcr); 4258 4259 siocnopen(&sp, siocniobase, comdefaultrate); 4260 splx(s); 4261 4262 cnadd(&sio_consdev); 4263 return (0); 4264} 4265 4266int 4267siogdbattach(port, speed) 4268 int port; 4269 int speed; 4270{ 4271 int s; 4272 u_char cfcr; 4273 u_int divisor; 4274 struct siocnstate sp; 4275 int unit = 1; /* XXX !!! */ 4276 4277 siogdbiobase = port; 4278 gdbdefaultrate = speed; 4279 4280 printf("sio%d: gdb debugging port\n", unit); 4281 siogdbunit = unit; 4282#if DDB > 0 4283 gdbdev = makedev(CDEV_MAJOR, unit); 4284 gdb_getc = siocngetc; 4285 gdb_putc = siocnputc; 4286#endif 4287 4288 s = spltty(); 4289 4290 /* 4291 * Initialize the divisor latch. We can't rely on 4292 * siocnopen() to do this the first time, since it 4293 * avoids writing to the latch if the latch appears 4294 * to have the correct value. Also, if we didn't 4295 * just read the speed from the hardware, then we 4296 * need to set the speed in hardware so that 4297 * switching it later is null. 4298 */ 4299 cfcr = inb(siogdbiobase + com_cfcr); 4300 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr); 4301 divisor = siodivisor(comdefaultrclk, gdbdefaultrate); 4302 outb(siogdbiobase + com_dlbl, divisor & 0xff); 4303 outb(siogdbiobase + com_dlbh, divisor >> 8); 4304 outb(siogdbiobase + com_cfcr, cfcr); 4305 4306 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 4307 splx(s); 4308 4309 return (0); 4310} 4311 4312#endif 4313 4314static int 4315siocncheckc(dev) 4316 dev_t dev; 4317{ 4318 int c; 4319 Port_t iobase; 4320 int s; 4321 struct siocnstate sp; 4322 4323 if (minor(dev) == siogdbunit) 4324 iobase = siogdbiobase; 4325 else 4326 iobase = siocniobase; 4327 s = spltty(); 4328 siocnopen(&sp, iobase, comdefaultrate); 4329 if (inb(iobase + com_lsr) & LSR_RXRDY) 4330 c = inb(iobase + com_data); 4331 else 4332 c = -1; 4333 siocnclose(&sp, iobase); 4334 splx(s); 4335 return (c); 4336} 4337 4338 4339int 4340siocngetc(dev) 4341 dev_t dev; 4342{ 4343 int c; 4344 Port_t iobase; 4345 int s; 4346 struct siocnstate sp; 4347 4348 if (minor(dev) == siogdbunit) 4349 iobase = siogdbiobase; 4350 else 4351 iobase = siocniobase; 4352 s = spltty(); 4353 siocnopen(&sp, iobase, comdefaultrate); 4354 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 4355 ; 4356 c = inb(iobase + com_data); 4357 siocnclose(&sp, iobase); 4358 splx(s); 4359 return (c); 4360} 4361 4362void 4363siocnputc(dev, c) 4364 dev_t dev; 4365 int c; 4366{ 4367 int need_unlock; 4368 int s; 4369 struct siocnstate sp; 4370 Port_t iobase; 4371 4372 if (minor(dev) == siogdbunit) 4373 iobase = siogdbiobase; 4374 else 4375 iobase = siocniobase; 4376 s = spltty(); 4377 need_unlock = 0; 4378 if (sio_inited == 2 && !mtx_owned(&sio_lock)) { 4379 mtx_lock_spin(&sio_lock); 4380 need_unlock = 1; 4381 } 4382 siocnopen(&sp, iobase, comdefaultrate); 4383 siocntxwait(iobase); 4384 outb(iobase + com_data, c); 4385 siocnclose(&sp, iobase); 4386 if (need_unlock) 4387 mtx_unlock_spin(&sio_lock); 4388 splx(s); 4389} 4390 4391#ifdef __alpha__ 4392int 4393siogdbgetc() 4394{ 4395 int c; 4396 Port_t iobase; 4397 int s; 4398 struct siocnstate sp; 4399 4400 iobase = siogdbiobase; 4401 s = spltty(); 4402 siocnopen(&sp, iobase, gdbdefaultrate); 4403 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 4404 ; 4405 c = inb(iobase + com_data); 4406 siocnclose(&sp, iobase); 4407 splx(s); 4408 return (c); 4409} 4410 4411void 4412siogdbputc(c) 4413 int c; 4414{ 4415 int s; 4416 struct siocnstate sp; 4417 4418 s = spltty(); 4419 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 4420 siocntxwait(siogdbiobase); 4421 outb(siogdbiobase + com_data, c); 4422 siocnclose(&sp, siogdbiobase); 4423 splx(s); 4424} 4425#endif 4426 4427#ifdef PC98 4428/* 4429 * pc98 local function 4430 */ 4431 4432static void 4433com_tiocm_set(struct com_s *com, int msr) 4434{ 4435 int s; 4436 int tmp = 0; 4437 int mask = CMD8251_TxEN|CMD8251_RxEN|CMD8251_DTR|CMD8251_RTS; 4438 4439 s=spltty(); 4440 com->pc98_prev_modem_status = ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ) 4441 | ( com->pc98_prev_modem_status & ~(TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4442 tmp |= (CMD8251_TxEN|CMD8251_RxEN); 4443 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4444 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4445 pc98_i8251_clear_or_cmd( com, mask, tmp ); 4446 splx(s); 4447} 4448 4449static void 4450com_tiocm_bis(struct com_s *com, int msr) 4451{ 4452 int s; 4453 int tmp = 0; 4454 4455 s=spltty(); 4456 com->pc98_prev_modem_status |= ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4457 tmp |= CMD8251_TxEN|CMD8251_RxEN; 4458 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4459 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4460 4461 pc98_i8251_or_cmd( com, tmp ); 4462 splx(s); 4463} 4464 4465static void 4466com_tiocm_bic(struct com_s *com, int msr) 4467{ 4468 int s; 4469 int tmp = msr; 4470 4471 s=spltty(); 4472 com->pc98_prev_modem_status &= ~( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4473 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4474 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4475 4476 pc98_i8251_clear_cmd( com, tmp ); 4477 splx(s); 4478} 4479 4480static int 4481com_tiocm_get(struct com_s *com) 4482{ 4483 return( com->pc98_prev_modem_status ); 4484} 4485 4486static int 4487com_tiocm_get_delta(struct com_s *com) 4488{ 4489 int tmp; 4490 4491 tmp = com->pc98_modem_delta; 4492 com->pc98_modem_delta = 0; 4493 return( tmp ); 4494} 4495 4496/* convert to TIOCM_?? ( ioctl.h ) */ 4497static int 4498pc98_get_modem_status(struct com_s *com) 4499{ 4500 register int msr; 4501 4502 msr = com->pc98_prev_modem_status 4503 & ~(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 4504 if (com->pc98_8251fifo_enable) { 4505 int stat2; 4506 4507 stat2 = inb(I8251F_msr); 4508 if ( stat2 & CICSCDF_CD ) msr |= TIOCM_CAR; 4509 if ( stat2 & CICSCDF_CI ) msr |= TIOCM_RI; 4510 if ( stat2 & CICSCDF_DR ) msr |= TIOCM_DSR; 4511 if ( stat2 & CICSCDF_CS ) msr |= TIOCM_CTS; 4512#if COM_CARRIER_DETECT_EMULATE 4513 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 4514 msr |= TIOCM_CAR; 4515 } 4516#endif 4517 } else { 4518 int stat, stat2; 4519 4520 stat = inb(com->sts_port); 4521 stat2 = inb(com->in_modem_port); 4522 if ( !(stat2 & CICSCD_CD) ) msr |= TIOCM_CAR; 4523 if ( !(stat2 & CICSCD_CI) ) msr |= TIOCM_RI; 4524 if ( stat & STS8251_DSR ) msr |= TIOCM_DSR; 4525 if ( !(stat2 & CICSCD_CS) ) msr |= TIOCM_CTS; 4526#if COM_CARRIER_DETECT_EMULATE 4527 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 4528 msr |= TIOCM_CAR; 4529 } 4530#endif 4531 } 4532 return(msr); 4533} 4534 4535static void 4536pc98_check_msr(void* chan) 4537{ 4538 int msr, delta; 4539 int s; 4540 register struct tty *tp; 4541 struct com_s *com; 4542 int mynor; 4543 int unit; 4544 dev_t dev; 4545 4546 dev=(dev_t)chan; 4547 mynor = minor(dev); 4548 unit = MINOR_TO_UNIT(mynor); 4549 com = com_addr(unit); 4550 tp = com->tp; 4551 4552 s = spltty(); 4553 msr = pc98_get_modem_status(com); 4554 /* make change flag */ 4555 delta = msr ^ com->pc98_prev_modem_status; 4556 if ( delta & TIOCM_CAR ) { 4557 if ( com->modem_car_chg_timer ) { 4558 if ( -- com->modem_car_chg_timer ) 4559 msr ^= TIOCM_CAR; 4560 } else { 4561 if ((com->modem_car_chg_timer = (msr & TIOCM_CAR) ? 4562 DCD_ON_RECOGNITION : DCD_OFF_TOLERANCE) != 0) 4563 msr ^= TIOCM_CAR; 4564 } 4565 } else 4566 com->modem_car_chg_timer = 0; 4567 delta = ( msr ^ com->pc98_prev_modem_status ) & 4568 (TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 4569 com->pc98_prev_modem_status = msr; 4570 delta = ( com->pc98_modem_delta |= delta ); 4571 splx(s); 4572 if ( com->modem_checking || (tp->t_state & (TS_ISOPEN)) ) { 4573 if ( delta ) { 4574 commint(dev); 4575 } 4576 timeout(pc98_check_msr, (caddr_t)dev, 4577 PC98_CHECK_MODEM_INTERVAL); 4578 } else { 4579 com->modem_checking = 0; 4580 } 4581} 4582 4583static void 4584pc98_msrint_start(dev_t dev) 4585{ 4586 struct com_s *com; 4587 int mynor; 4588 int unit; 4589 int s = spltty(); 4590 4591 mynor = minor(dev); 4592 unit = MINOR_TO_UNIT(mynor); 4593 com = com_addr(unit); 4594 /* modem control line check routine envoke interval is 1/10 sec */ 4595 if ( com->modem_checking == 0 ) { 4596 com->pc98_prev_modem_status = pc98_get_modem_status(com); 4597 com->pc98_modem_delta = 0; 4598 timeout(pc98_check_msr, (caddr_t)dev, 4599 PC98_CHECK_MODEM_INTERVAL); 4600 com->modem_checking = 1; 4601 } 4602 splx(s); 4603} 4604 4605static void 4606pc98_disable_i8251_interrupt(struct com_s *com, int mod) 4607{ 4608 /* disable interrupt */ 4609 register int tmp; 4610 4611 mod |= ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4612 COM_INT_DISABLE 4613 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4614 outb( com->intr_ctrl_port, (com->intr_enable&=~mod) | tmp ); 4615 COM_INT_ENABLE 4616} 4617 4618static void 4619pc98_enable_i8251_interrupt(struct com_s *com, int mod) 4620{ 4621 register int tmp; 4622 4623 COM_INT_DISABLE 4624 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4625 outb( com->intr_ctrl_port, (com->intr_enable|=mod) | tmp ); 4626 COM_INT_ENABLE 4627} 4628 4629static int 4630pc98_check_i8251_interrupt(struct com_s *com) 4631{ 4632 return ( com->intr_enable & 0x07 ); 4633} 4634 4635static void 4636pc98_i8251_clear_cmd(struct com_s *com, int x) 4637{ 4638 int tmp; 4639 4640 COM_INT_DISABLE 4641 tmp = com->pc98_prev_siocmd & ~(x); 4642 if (com->pc98_8251fifo_enable) 4643 outb(I8251F_fcr, 0); 4644 outb(com->cmd_port, tmp); 4645 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4646 if (com->pc98_8251fifo_enable) 4647 outb(I8251F_fcr, CTRL8251F_ENABLE); 4648 COM_INT_ENABLE 4649} 4650 4651static void 4652pc98_i8251_or_cmd(struct com_s *com, int x) 4653{ 4654 int tmp; 4655 4656 COM_INT_DISABLE 4657 if (com->pc98_8251fifo_enable) 4658 outb(I8251F_fcr, 0); 4659 tmp = com->pc98_prev_siocmd | (x); 4660 outb(com->cmd_port, tmp); 4661 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4662 if (com->pc98_8251fifo_enable) 4663 outb(I8251F_fcr, CTRL8251F_ENABLE); 4664 COM_INT_ENABLE 4665} 4666 4667static void 4668pc98_i8251_set_cmd(struct com_s *com, int x) 4669{ 4670 int tmp; 4671 4672 COM_INT_DISABLE 4673 if (com->pc98_8251fifo_enable) 4674 outb(I8251F_fcr, 0); 4675 tmp = (x); 4676 outb(com->cmd_port, tmp); 4677 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4678 if (com->pc98_8251fifo_enable) 4679 outb(I8251F_fcr, CTRL8251F_ENABLE); 4680 COM_INT_ENABLE 4681} 4682 4683static void 4684pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x) 4685{ 4686 int tmp; 4687 COM_INT_DISABLE 4688 if (com->pc98_8251fifo_enable) 4689 outb(I8251F_fcr, 0); 4690 tmp = com->pc98_prev_siocmd & ~(clr); 4691 tmp |= (x); 4692 outb(com->cmd_port, tmp); 4693 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4694 if (com->pc98_8251fifo_enable) 4695 outb(I8251F_fcr, CTRL8251F_ENABLE); 4696 COM_INT_ENABLE 4697} 4698 4699static int 4700pc98_i8251_get_cmd(struct com_s *com) 4701{ 4702 return com->pc98_prev_siocmd; 4703} 4704 4705static int 4706pc98_i8251_get_mod(struct com_s *com) 4707{ 4708 return com->pc98_prev_siomod; 4709} 4710 4711static void 4712pc98_i8251_reset(struct com_s *com, int mode, int command) 4713{ 4714 if (com->pc98_8251fifo_enable) 4715 outb(I8251F_fcr, 0); 4716 outb(com->cmd_port, 0); /* dummy */ 4717 DELAY(2); 4718 outb(com->cmd_port, 0); /* dummy */ 4719 DELAY(2); 4720 outb(com->cmd_port, 0); /* dummy */ 4721 DELAY(2); 4722 outb(com->cmd_port, CMD8251_RESET); /* internal reset */ 4723 DELAY(2); 4724 outb(com->cmd_port, mode ); /* mode register */ 4725 com->pc98_prev_siomod = mode; 4726 DELAY(2); 4727 pc98_i8251_set_cmd( com, (command|CMD8251_ER) ); 4728 DELAY(10); 4729 if (com->pc98_8251fifo_enable) 4730 outb(I8251F_fcr, CTRL8251F_ENABLE | 4731 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 4732} 4733 4734static void 4735pc98_check_sysclock(void) 4736{ 4737 /* get system clock from port */ 4738 if ( pc98_machine_type & M_8M ) { 4739 /* 8 MHz system & H98 */ 4740 sysclock = 8; 4741 } else { 4742 /* 5 MHz system */ 4743 sysclock = 5; 4744 } 4745} 4746 4747static void 4748com_cflag_and_speed_set( struct com_s *com, int cflag, int speed) 4749{ 4750 int cfcr=0; 4751 int previnterrupt; 4752 u_int count; 4753 4754 if (pc98_ttspeedtab(com, speed, &count) != 0) 4755 return; 4756 4757 previnterrupt = pc98_check_i8251_interrupt(com); 4758 pc98_disable_i8251_interrupt( com, IEN_Tx|IEN_TxEMP|IEN_Rx ); 4759 4760 switch ( cflag&CSIZE ) { 4761 case CS5: 4762 cfcr = MOD8251_5BITS; break; 4763 case CS6: 4764 cfcr = MOD8251_6BITS; break; 4765 case CS7: 4766 cfcr = MOD8251_7BITS; break; 4767 case CS8: 4768 cfcr = MOD8251_8BITS; break; 4769 } 4770 if ( cflag&PARENB ) { 4771 if ( cflag&PARODD ) 4772 cfcr |= MOD8251_PODD; 4773 else 4774 cfcr |= MOD8251_PEVEN; 4775 } else 4776 cfcr |= MOD8251_PDISAB; 4777 4778 if ( cflag&CSTOPB ) 4779 cfcr |= MOD8251_STOP2; 4780 else 4781 cfcr |= MOD8251_STOP1; 4782 4783 if ( count & 0x10000 ) 4784 cfcr |= MOD8251_CLKX1; 4785 else 4786 cfcr |= MOD8251_CLKX16; 4787 4788 if (epson_machine_id != 0x20) { /* XXX */ 4789 int tmp; 4790 while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP)) 4791 ; 4792 } 4793 /* set baud rate from ospeed */ 4794 pc98_set_baud_rate( com, count ); 4795 4796 if ( cfcr != pc98_i8251_get_mod(com) ) 4797 pc98_i8251_reset(com, cfcr, pc98_i8251_get_cmd(com) ); 4798 4799 pc98_enable_i8251_interrupt( com, previnterrupt ); 4800} 4801 4802static int 4803pc98_ttspeedtab(struct com_s *com, int speed, u_int *divisor) 4804{ 4805 int if_type, effect_sp, count = -1, mod; 4806 4807 if_type = com->pc98_if_type & 0x0f; 4808 4809 switch (com->pc98_if_type) { 4810 case COM_IF_INTERNAL: 4811 if (PC98SIO_baud_rate_port(if_type) != -1) { 4812 count = ttspeedtab(speed, if_8251_type[if_type].speedtab); 4813 if (count > 0) { 4814 count |= COM1_EXT_CLOCK; 4815 break; 4816 } 4817 } 4818 4819 /* for *1CLK asynchronous! mode, TEFUTEFU */ 4820 mod = (sysclock == 5) ? 2457600 : 1996800; 4821 effect_sp = ttspeedtab( speed, pc98speedtab ); 4822 if ( effect_sp < 0 ) /* XXX */ 4823 effect_sp = ttspeedtab( (speed - 1), pc98speedtab ); 4824 if ( effect_sp <= 0 ) 4825 return effect_sp; 4826 if ( effect_sp == speed ) 4827 mod /= 16; 4828 if ( mod % effect_sp ) 4829 return(-1); 4830 count = mod / effect_sp; 4831 if ( count > 65535 ) 4832 return(-1); 4833 if ( effect_sp != speed ) 4834 count |= 0x10000; 4835 break; 4836 case COM_IF_PC9861K_1: 4837 case COM_IF_PC9861K_2: 4838 count = 1; 4839 break; 4840 case COM_IF_IND_SS_1: 4841 case COM_IF_IND_SS_2: 4842 case COM_IF_PIO9032B_1: 4843 case COM_IF_PIO9032B_2: 4844 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 4845 break; 4846 case COM_IF_B98_01_1: 4847 case COM_IF_B98_01_2: 4848 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 4849#ifdef B98_01_OLD 4850 if (count == 0 || count == 1) { 4851 count += 4; 4852 count |= 0x20000; /* x1 mode for 76800 and 153600 */ 4853 } 4854#endif 4855 break; 4856 } 4857 4858 if (count < 0) 4859 return count; 4860 4861 *divisor = (u_int) count; 4862 return 0; 4863} 4864 4865static void 4866pc98_set_baud_rate( struct com_s *com, u_int count ) 4867{ 4868 int if_type, io, s; 4869 4870 if_type = com->pc98_if_type & 0x0f; 4871 io = rman_get_start(com->ioportres) & 0xff00; 4872 4873 switch (com->pc98_if_type) { 4874 case COM_IF_INTERNAL: 4875 if (PC98SIO_baud_rate_port(if_type) != -1) { 4876 if (count & COM1_EXT_CLOCK) { 4877 outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff); 4878 break; 4879 } else { 4880 outb((Port_t)PC98SIO_baud_rate_port(if_type), 0x09); 4881 } 4882 } 4883 4884 if (count == 0) 4885 return; 4886 4887 /* set i8253 */ 4888 s = splclock(); 4889 if (count != 3) 4890 outb( 0x77, 0xb6 ); 4891 else 4892 outb( 0x77, 0xb4 ); 4893 outb( 0x5f, 0); 4894 outb( 0x75, count & 0xff ); 4895 outb( 0x5f, 0); 4896 outb( 0x75, (count >> 8) & 0xff ); 4897 splx(s); 4898 break; 4899 case COM_IF_IND_SS_1: 4900 case COM_IF_IND_SS_2: 4901 outb(io | PC98SIO_intr_ctrl_port(if_type), 0); 4902 outb(io | PC98SIO_baud_rate_port(if_type), 0); 4903 outb(io | PC98SIO_baud_rate_port(if_type), 0xc0); 4904 outb(io | PC98SIO_baud_rate_port(if_type), (count >> 8) | 0x80); 4905 outb(io | PC98SIO_baud_rate_port(if_type), count & 0xff); 4906 break; 4907 case COM_IF_PIO9032B_1: 4908 case COM_IF_PIO9032B_2: 4909 outb(io | PC98SIO_baud_rate_port(if_type), count); 4910 break; 4911 case COM_IF_B98_01_1: 4912 case COM_IF_B98_01_2: 4913 outb(io | PC98SIO_baud_rate_port(if_type), count & 0x0f); 4914#ifdef B98_01_OLD 4915 /* 4916 * Some old B98_01 board should be controlled 4917 * in different way, but this hasn't been tested yet. 4918 */ 4919 outb(io | PC98SIO_func_port(if_type), 4920 (count & 0x20000) ? 0xf0 : 0xf2); 4921#endif 4922 break; 4923 } 4924} 4925static int 4926pc98_check_if_type(device_t dev, struct siodev *iod) 4927{ 4928 int irr, io, if_type, tmp; 4929 static short irq_tab[2][8] = { 4930 { 3, 5, 6, 9, 10, 12, 13, -1}, 4931 { 3, 10, 12, 13, 5, 6, 9, -1} 4932 }; 4933 4934 if_type = iod->if_type & 0x0f; 4935 iod->irq = 0; 4936 io = isa_get_port(dev) & 0xff00; 4937 4938 if (IS_8251(iod->if_type)) { 4939 if (PC98SIO_func_port(if_type) != -1) { 4940 outb(io | PC98SIO_func_port(if_type), 0xf2); 4941 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab); 4942 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1) 4943 outb(io | PC98SIO_baud_rate_port(if_type), tmp); 4944 } 4945 4946 iod->cmd = io | PC98SIO_cmd_port(if_type); 4947 iod->sts = io | PC98SIO_sts_port(if_type); 4948 iod->mod = io | PC98SIO_in_modem_port(if_type); 4949 iod->ctrl = io | PC98SIO_intr_ctrl_port(if_type); 4950 4951 if (iod->if_type == COM_IF_INTERNAL) { 4952 iod->irq = 4; 4953 4954 if (pc98_check_8251vfast()) { 4955 PC98SIO_baud_rate_port(if_type) = I8251F_div; 4956 if_8251_type[if_type].speedtab = pc98fast_speedtab; 4957 } 4958 } else { 4959 tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask; 4960 if ((isa_get_port(dev) & 0xff) == IO_COM2) 4961 iod->irq = irq_tab[0][tmp]; 4962 else 4963 iod->irq = irq_tab[1][tmp]; 4964 } 4965 } else { 4966 irr = if_16550a_type[if_type].irr_read; 4967#ifdef COM_MULTIPORT 4968 if (!COM_ISMULTIPORT(device_get_flags(dev)) || 4969 device_get_unit(dev) == COM_MPMASTER(device_get_flags(dev))) 4970#endif 4971 if (irr != -1) { 4972 tmp = inb(io | irr); 4973 if (isa_get_port(dev) & 0x01) /* XXX depend on RSB-384 */ 4974 iod->irq = irq_tab[1][tmp >> 3]; 4975 else 4976 iod->irq = irq_tab[0][tmp & 0x07]; 4977 } 4978 } 4979 if ( iod->irq == -1 ) return -1; 4980 4981 return 0; 4982} 4983static void 4984pc98_set_ioport(struct com_s *com) 4985{ 4986 int if_type = com->pc98_if_type & 0x0f; 4987 Port_t io = rman_get_start(com->ioportres) & 0xff00; 4988 4989 pc98_check_sysclock(); 4990 com->data_port = io | PC98SIO_data_port(if_type); 4991 com->cmd_port = io | PC98SIO_cmd_port(if_type); 4992 com->sts_port = io | PC98SIO_sts_port(if_type); 4993 com->in_modem_port = io | PC98SIO_in_modem_port(if_type); 4994 com->intr_ctrl_port = io | PC98SIO_intr_ctrl_port(if_type); 4995} 4996static int 4997pc98_check_8251vfast(void) 4998{ 4999 int i; 5000 5001 outb(I8251F_div, 0x8c); 5002 DELAY(10); 5003 for (i = 0; i < 100; i++) { 5004 if ((inb(I8251F_div) & 0x80) != 0) { 5005 i = 0; 5006 break; 5007 } 5008 DELAY(1); 5009 } 5010 outb(I8251F_div, 0); 5011 DELAY(10); 5012 for (; i < 100; i++) { 5013 if ((inb(I8251F_div) & 0x80) == 0) 5014 return 1; 5015 DELAY(1); 5016 } 5017 5018 return 0; 5019} 5020static int 5021pc98_check_8251fifo(void) 5022{ 5023 u_char tmp1, tmp2; 5024 5025 tmp1 = inb(I8251F_iir); 5026 DELAY(10); 5027 tmp2 = inb(I8251F_iir); 5028 if (((tmp1 ^ tmp2) & 0x40) != 0 && ((tmp1 | tmp2) & 0x20) == 0) 5029 return 1; 5030 5031 return 0; 5032} 5033#endif /* PC98 defined */ 5034