sio.c revision 67551
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Berkeley and its contributors. 17 * 4. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/pc98/cbus/sio.c 67551 2000-10-25 05:19:40Z jhb $ 34 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 35 * from: i386/isa sio.c,v 1.234 36 */ 37 38#include "opt_comconsole.h" 39#include "opt_compat.h" 40#include "opt_ddb.h" 41#include "opt_sio.h" 42#include "card.h" 43#include "pci.h" 44#include "sio.h" 45 46/* 47 * Serial driver, based on 386BSD-0.1 com driver. 48 * Mostly rewritten to use pseudo-DMA. 49 * Works for National Semiconductor NS8250-NS16550AF UARTs. 50 * COM driver, based on HP dca driver. 51 * 52 * Changes for PC-Card integration: 53 * - Added PC-Card driver table and handlers 54 */ 55/*=============================================================== 56 * 386BSD(98),FreeBSD-1.1x(98) com driver. 57 * ----- 58 * modified for PC9801 by M.Ishii 59 * Kyoto University Microcomputer Club (KMC) 60 * Chou "TEFUTEFU" Hirotomi 61 * Kyoto Univ. the faculty of medicine 62 *=============================================================== 63 * FreeBSD-2.0.1(98) sio driver. 64 * ----- 65 * modified for pc98 Internal i8251 and MICRO CORE MC16550II 66 * T.Koike(hfc01340@niftyserve.or.jp) 67 * implement kernel device configuration 68 * aizu@orient.center.nitech.ac.jp 69 * 70 * Notes. 71 * ----- 72 * PC98 localization based on 386BSD(98) com driver. Using its PC98 local 73 * functions. 74 * This driver is under debugging,has bugs. 75 * 76 * 1) config 77 * options COM_MULTIPORT #if using MC16550II 78 * device sio0 at nec? port 0x30 tty irq 4 #internal 79 * device sio1 at nec? port 0xd2 tty irq 5 flags 0x101 #mc1 80 * device sio2 at nec? port 0x8d2 tty flags 0x101 #mc2 81 * # ~~~~~iobase ~~multi port flag 82 * # ~ master device is sio1 83 * 2) device 84 * cd /dev; MAKEDEV ttyd0 ttyd1 .. 85 * 3) /etc/rc.serial 86 * 57600bps is too fast for sio0(internal8251) 87 * my ex. 88 * #set default speed 9600 89 * modem() 90 * : 91 * stty </dev/ttyid$i crtscts 9600 92 * : # ~~~~ default speed(can change after init.) 93 * modem 0 1 2 94 * 4) COMCONSOLE 95 * not changed. 96 * 5) PC9861K,PIO9032B,B98_01 97 * not tested. 98 */ 99/* 100 * modified for AIWA B98-01 101 * by T.Hatanou <hatanou@yasuda.comm.waseda.ac.jp> last update: 15 Sep.1995 102 * 103 * How to configure... 104 * # options COM_MULTIPORT # support for MICROCORE MC16550II 105 * ... comment-out this line, which will conflict with B98_01. 106 * options "B98_01" # support for AIWA B98-01 107 * device sio1 at nec? port 0x00d1 tty irq ? 108 * device sio2 at nec? port 0x00d5 tty irq ? 109 * ... you can leave these lines `irq ?', irq will be autodetected. 110 */ 111/* 112 * Modified by Y.Takahashi of Kogakuin University. 113 */ 114/* 115 * modified for 8251(FIFO) by Seigo TANIMURA <tanimura@FreeBSD.org> 116 */ 117 118#ifdef PC98 119#define COM_IF_INTERNAL 0x00 120#define COM_IF_PC9861K_1 0x01 121#define COM_IF_PC9861K_2 0x02 122#define COM_IF_IND_SS_1 0x03 123#define COM_IF_IND_SS_2 0x04 124#define COM_IF_PIO9032B_1 0x05 125#define COM_IF_PIO9032B_2 0x06 126#define COM_IF_B98_01_1 0x07 127#define COM_IF_B98_01_2 0x08 128#define COM_IF_END1 COM_IF_B98_01_2 129#define COM_IF_RSA98 0x10 /* same as COM_IF_NS16550 */ 130#define COM_IF_NS16550 0x11 131#define COM_IF_SECOND_CCU 0x12 /* same as COM_IF_NS16550 */ 132#define COM_IF_MC16550II 0x13 133#define COM_IF_MCRS98 0x14 /* same as COM_IF_MC16550II */ 134#define COM_IF_RSB3000 0x15 135#define COM_IF_RSB384 0x16 136#define COM_IF_MODEM_CARD 0x17 /* same as COM_IF_NS16550 */ 137#define COM_IF_RSA98III 0x18 138#define COM_IF_ESP98 0x19 139#define COM_IF_END2 COM_IF_ESP98 140#endif /* PC98 */ 141 142#include <sys/param.h> 143#include <sys/bus.h> 144#include <sys/systm.h> 145#include <sys/reboot.h> 146#include <sys/malloc.h> 147#include <sys/tty.h> 148#include <sys/proc.h> 149#include <sys/module.h> 150#include <sys/conf.h> 151#include <sys/dkstat.h> 152#include <sys/fcntl.h> 153#include <sys/interrupt.h> 154#include <sys/ipl.h> 155#include <sys/kernel.h> 156#include <sys/syslog.h> 157#include <sys/sysctl.h> 158#include <sys/bus.h> 159#include <machine/bus.h> 160#include <sys/rman.h> 161#include <sys/timetc.h> 162#include <sys/timepps.h> 163 164#ifdef PC98 165#include <pc98/pc98/pc98.h> 166#include <pc98/pc98/pc98_machdep.h> 167#include <i386/isa/ic/i8251.h> 168#else 169#include <isa/isareg.h> 170#endif 171#include <isa/isavar.h> 172#if NPCI > 0 173#include <pci/pcireg.h> 174#include <pci/pcivar.h> 175#endif 176#include <machine/lock.h> 177 178#ifndef SMP 179#include <machine/lock.h> 180#endif 181#include <machine/resource.h> 182 183#include <isa/sioreg.h> 184 185#ifdef COM_ESP 186#include <i386/isa/ic/esp.h> 187#endif 188#include <i386/isa/ic/ns16550.h> 189#ifdef PC98 190#include <i386/isa/ic/rsa.h> 191#endif 192 193/* XXX - this is ok because we only do sio fast interrupts on i386 */ 194#ifndef __i386__ 195#define disable_intr() 196#define enable_intr() 197#endif 198 199#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */ 200 201#define CALLOUT_MASK 0x80 202#define CONTROL_MASK 0x60 203#define CONTROL_INIT_STATE 0x20 204#define CONTROL_LOCK_STATE 0x40 205#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev))) 206#define MINOR_MAGIC_MASK (CALLOUT_MASK | CONTROL_MASK) 207#define MINOR_TO_UNIT(mynor) ((mynor) & ~MINOR_MAGIC_MASK) 208 209#ifdef COM_MULTIPORT 210/* checks in flags for multiport and which is multiport "master chip" 211 * for a given card 212 */ 213#define COM_ISMULTIPORT(flags) ((flags) & 0x01) 214#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff) 215#define COM_NOTAST4(flags) ((flags) & 0x04) 216#endif /* COM_MULTIPORT */ 217 218#define COM_CONSOLE(flags) ((flags) & 0x10) 219#define COM_FORCECONSOLE(flags) ((flags) & 0x20) 220#define COM_LLCONSOLE(flags) ((flags) & 0x40) 221#define COM_DEBUGGER(flags) ((flags) & 0x80) 222#define COM_LOSESOUTINTS(flags) ((flags) & 0x08) 223#define COM_NOFIFO(flags) ((flags) & 0x02) 224#define COM_ST16650A(flags) ((flags) & 0x20000) 225#define COM_C_NOPROBE (0x40000) 226#define COM_NOPROBE(flags) ((flags) & COM_C_NOPROBE) 227#define COM_C_IIR_TXRDYBUG (0x80000) 228#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG) 229#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24) 230 231#ifdef PC98 232#define com_emr com_msr /* Extension mode register for RSB-2000/3000 */ 233#endif 234#define com_scr 7 /* scratch register for 16450-16550 (R/W) */ 235 236#define sio_getreg(com, off) \ 237 (bus_space_read_1((com)->bst, (com)->bsh, (off))) 238#define sio_setreg(com, off, value) \ 239 (bus_space_write_1((com)->bst, (com)->bsh, (off), (value))) 240 241/* 242 * com state bits. 243 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher 244 * than the other bits so that they can be tested as a group without masking 245 * off the low bits. 246 * 247 * The following com and tty flags correspond closely: 248 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and 249 * comstop()) 250 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart()) 251 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam()) 252 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam()) 253 * TS_FLUSH is not used. 254 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON. 255 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state). 256 */ 257#define CS_BUSY 0x80 /* output in progress */ 258#define CS_TTGO 0x40 /* output not stopped by XOFF */ 259#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */ 260#define CS_CHECKMSR 1 /* check of MSR scheduled */ 261#define CS_CTS_OFLOW 2 /* use CTS output flow control */ 262#define CS_DTR_OFF 0x10 /* DTR held off */ 263#define CS_ODONE 4 /* output completed */ 264#define CS_RTS_IFLOW 8 /* use RTS input flow control */ 265#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */ 266 267static char const * const error_desc[] = { 268#define CE_OVERRUN 0 269 "silo overflow", 270#define CE_INTERRUPT_BUF_OVERFLOW 1 271 "interrupt-level buffer overflow", 272#define CE_TTY_BUF_OVERFLOW 2 273 "tty-level buffer overflow", 274}; 275 276#define CE_NTYPES 3 277#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum]) 278 279/* types. XXX - should be elsewhere */ 280typedef u_int Port_t; /* hardware port */ 281typedef u_char bool_t; /* boolean */ 282 283/* queue of linear buffers */ 284struct lbq { 285 u_char *l_head; /* next char to process */ 286 u_char *l_tail; /* one past the last char to process */ 287 struct lbq *l_next; /* next in queue */ 288 bool_t l_queued; /* nonzero if queued */ 289}; 290 291/* com device structure */ 292struct com_s { 293 u_int flags; /* Copy isa device flags */ 294 u_char state; /* miscellaneous flag bits */ 295 bool_t active_out; /* nonzero if the callout device is open */ 296 u_char cfcr_image; /* copy of value written to CFCR */ 297#ifdef COM_ESP 298 bool_t esp; /* is this unit a hayes esp board? */ 299#endif 300 u_char extra_state; /* more flag bits, separate for order trick */ 301 u_char fifo_image; /* copy of value written to FIFO */ 302 bool_t hasfifo; /* nonzero for 16550 UARTs */ 303 bool_t st16650a; /* Is a Startech 16650A or RTS/CTS compat */ 304 bool_t loses_outints; /* nonzero if device loses output interrupts */ 305 u_char mcr_image; /* copy of value written to MCR */ 306#ifdef COM_MULTIPORT 307 bool_t multiport; /* is this unit part of a multiport device? */ 308#endif /* COM_MULTIPORT */ 309 bool_t no_irq; /* nonzero if irq is not attached */ 310 bool_t gone; /* hardware disappeared */ 311 bool_t poll; /* nonzero if polling is required */ 312 bool_t poll_output; /* nonzero if polling for output is required */ 313 int unit; /* unit number */ 314 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */ 315 u_int tx_fifo_size; 316 u_int wopeners; /* # processes waiting for DCD in open() */ 317 318 /* 319 * The high level of the driver never reads status registers directly 320 * because there would be too many side effects to handle conveniently. 321 * Instead, it reads copies of the registers stored here by the 322 * interrupt handler. 323 */ 324 u_char last_modem_status; /* last MSR read by intr handler */ 325 u_char prev_modem_status; /* last MSR handled by high level */ 326 327 u_char hotchar; /* ldisc-specific char to be handled ASAP */ 328 u_char *ibuf; /* start of input buffer */ 329 u_char *ibufend; /* end of input buffer */ 330 u_char *ibufold; /* old input buffer, to be freed */ 331 u_char *ihighwater; /* threshold in input buffer */ 332 u_char *iptr; /* next free spot in input buffer */ 333 int ibufsize; /* size of ibuf (not include error bytes) */ 334 int ierroff; /* offset of error bytes in ibuf */ 335 336 struct lbq obufq; /* head of queue of output buffers */ 337 struct lbq obufs[2]; /* output buffers */ 338 339 bus_space_tag_t bst; 340 bus_space_handle_t bsh; 341 342#ifdef PC98 343 Port_t cmd_port; 344 Port_t sts_port; 345 Port_t in_modem_port; 346 Port_t intr_ctrl_port; 347 Port_t rsabase; /* iobase address of a I/O-DATA RSA board */ 348 int intr_enable; 349 int pc98_prev_modem_status; 350 int pc98_modem_delta; 351 int modem_car_chg_timer; 352 int pc98_prev_siocmd; 353 int pc98_prev_siomod; 354 int modem_checking; 355 int pc98_if_type; 356 357 bool_t pc98_8251fifo; 358 bool_t pc98_8251fifo_enable; 359#endif /* PC98 */ 360 Port_t data_port; /* i/o ports */ 361#ifdef COM_ESP 362 Port_t esp_port; 363#endif 364 Port_t int_id_port; 365 Port_t modem_ctl_port; 366 Port_t line_status_port; 367 Port_t modem_status_port; 368 Port_t intr_ctl_port; /* Ports of IIR register */ 369 370 struct tty *tp; /* cross reference */ 371 372 /* Initial state. */ 373 struct termios it_in; /* should be in struct tty */ 374 struct termios it_out; 375 376 /* Lock state. */ 377 struct termios lt_in; /* should be in struct tty */ 378 struct termios lt_out; 379 380 bool_t do_timestamp; 381 bool_t do_dcd_timestamp; 382 struct timeval timestamp; 383 struct timeval dcd_timestamp; 384 struct pps_state pps; 385 386 u_long bytes_in; /* statistics */ 387 u_long bytes_out; 388 u_int delta_error_counts[CE_NTYPES]; 389 u_long error_counts[CE_NTYPES]; 390 391 struct resource *irqres; 392 struct resource *ioportres; 393 void *cookie; 394 395 /* 396 * Data area for output buffers. Someday we should build the output 397 * buffer queue without copying data. 398 */ 399#ifdef PC98 400 int obufsize; 401 u_char *obuf1; 402 u_char *obuf2; 403#else 404 u_char obuf1[256]; 405 u_char obuf2[256]; 406#endif 407}; 408 409#ifdef COM_ESP 410static int espattach __P((struct com_s *com, Port_t esp_port)); 411#endif 412static int sioattach __P((device_t dev, int rid)); 413static int sio_isa_attach __P((device_t dev)); 414 415static timeout_t siobusycheck; 416static timeout_t siodtrwakeup; 417static void comhardclose __P((struct com_s *com)); 418static void sioinput __P((struct com_s *com)); 419static void siointr1 __P((struct com_s *com)); 420static void siointr __P((void *arg)); 421static int commctl __P((struct com_s *com, int bits, int how)); 422static int comparam __P((struct tty *tp, struct termios *t)); 423static swihand_t siopoll; 424static int sioprobe __P((device_t dev, int xrid)); 425static int sio_isa_probe __P((device_t dev)); 426static void siosettimeout __P((void)); 427static int siosetwater __P((struct com_s *com, speed_t speed)); 428static void comstart __P((struct tty *tp)); 429static void comstop __P((struct tty *tp, int rw)); 430static timeout_t comwakeup; 431static void disc_optim __P((struct tty *tp, struct termios *t, 432 struct com_s *com)); 433 434#if NCARD > 0 435static int sio_pccard_attach __P((device_t dev)); 436static int sio_pccard_detach __P((device_t dev)); 437static int sio_pccard_probe __P((device_t dev)); 438#endif /* NCARD > 0 */ 439 440#if NPCI > 0 441static int sio_pci_attach __P((device_t dev)); 442static void sio_pci_kludge_unit __P((device_t dev)); 443static int sio_pci_probe __P((device_t dev)); 444#endif /* NPCI > 0 */ 445 446static char driver_name[] = "sio"; 447 448/* table and macro for fast conversion from a unit number to its com struct */ 449static devclass_t sio_devclass; 450#define com_addr(unit) ((struct com_s *) \ 451 devclass_get_softc(sio_devclass, unit)) 452 453static device_method_t sio_isa_methods[] = { 454 /* Device interface */ 455 DEVMETHOD(device_probe, sio_isa_probe), 456 DEVMETHOD(device_attach, sio_isa_attach), 457 458 { 0, 0 } 459}; 460 461static driver_t sio_isa_driver = { 462 driver_name, 463 sio_isa_methods, 464 sizeof(struct com_s), 465}; 466 467#if NCARD > 0 468static device_method_t sio_pccard_methods[] = { 469 /* Device interface */ 470 DEVMETHOD(device_probe, sio_pccard_probe), 471 DEVMETHOD(device_attach, sio_pccard_attach), 472 DEVMETHOD(device_detach, sio_pccard_detach), 473 474 { 0, 0 } 475}; 476 477static driver_t sio_pccard_driver = { 478 driver_name, 479 sio_pccard_methods, 480 sizeof(struct com_s), 481}; 482#endif /* NCARD > 0 */ 483 484#if NPCI > 0 485static device_method_t sio_pci_methods[] = { 486 /* Device interface */ 487 DEVMETHOD(device_probe, sio_pci_probe), 488 DEVMETHOD(device_attach, sio_pci_attach), 489 490 { 0, 0 } 491}; 492 493static driver_t sio_pci_driver = { 494 driver_name, 495 sio_pci_methods, 496 sizeof(struct com_s), 497}; 498#endif /* NPCI > 0 */ 499 500static d_open_t sioopen; 501static d_close_t sioclose; 502static d_read_t sioread; 503static d_write_t siowrite; 504static d_ioctl_t sioioctl; 505 506#define CDEV_MAJOR 28 507static struct cdevsw sio_cdevsw = { 508 /* open */ sioopen, 509 /* close */ sioclose, 510 /* read */ sioread, 511 /* write */ siowrite, 512 /* ioctl */ sioioctl, 513 /* poll */ ttypoll, 514 /* mmap */ nommap, 515 /* strategy */ nostrategy, 516 /* name */ driver_name, 517 /* maj */ CDEV_MAJOR, 518 /* dump */ nodump, 519 /* psize */ nopsize, 520 /* flags */ D_TTY, 521 /* bmaj */ -1 522}; 523 524int comconsole = -1; 525static volatile speed_t comdefaultrate = CONSPEED; 526#ifdef __alpha__ 527static volatile speed_t gdbdefaultrate = CONSPEED; 528#endif 529static u_int com_events; /* input chars + weighted output completions */ 530static Port_t siocniobase; 531#ifndef __alpha__ 532static int siocnunit; 533#endif 534static Port_t siogdbiobase; 535static int siogdbunit = -1; 536static struct intrhand *sio_slow_ih; 537static struct intrhand *sio_fast_ih; 538static int sio_timeout; 539static int sio_timeouts_until_log; 540static struct callout_handle sio_timeout_handle 541 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle); 542static int sio_numunits; 543 544#ifdef PC98 545struct siodev { 546 short if_type; 547 short irq; 548 Port_t cmd, sts, ctrl, mod; 549}; 550static int sysclock; 551 552#define COM_INT_DISABLE {int previpri; previpri=spltty(); 553#define COM_INT_ENABLE splx(previpri);} 554#define IEN_TxFLAG IEN_Tx 555 556#define COM_CARRIER_DETECT_EMULATE 0 557#define PC98_CHECK_MODEM_INTERVAL (hz/10) 558#define DCD_OFF_TOLERANCE 2 559#define DCD_ON_RECOGNITION 2 560#define GET_IFTYPE(flags) ((flags >> 24) & 0x1f) 561#define SET_IFTYPE(type) (type << 24) 562#define IS_8251(if_type) (!(if_type & 0x10)) 563#define COM1_EXT_CLOCK 0x40000 564 565static void commint __P((dev_t dev)); 566static void com_tiocm_set __P((struct com_s *com, int msr)); 567static void com_tiocm_bis __P((struct com_s *com, int msr)); 568static void com_tiocm_bic __P((struct com_s *com, int msr)); 569static int com_tiocm_get __P((struct com_s *com)); 570static int com_tiocm_get_delta __P((struct com_s *com)); 571static void pc98_msrint_start __P((dev_t dev)); 572static void com_cflag_and_speed_set __P((struct com_s *com, int cflag, int speed)); 573static int pc98_ttspeedtab __P((struct com_s *com, int speed)); 574static int pc98_get_modem_status __P((struct com_s *com)); 575static timeout_t pc98_check_msr; 576static void pc98_set_baud_rate __P((struct com_s *com, int count)); 577static void pc98_i8251_reset __P((struct com_s *com, int mode, int command)); 578static void pc98_disable_i8251_interrupt __P((struct com_s *com, int mod)); 579static void pc98_enable_i8251_interrupt __P((struct com_s *com, int mod)); 580static int pc98_check_i8251_interrupt __P((struct com_s *com)); 581static int pc98_i8251_get_cmd __P((struct com_s *com)); 582static int pc98_i8251_get_mod __P((struct com_s *com)); 583static void pc98_i8251_set_cmd __P((struct com_s *com, int x)); 584static void pc98_i8251_or_cmd __P((struct com_s *com, int x)); 585static void pc98_i8251_clear_cmd __P((struct com_s *com, int x)); 586static void pc98_i8251_clear_or_cmd __P((struct com_s *com, int clr, int x)); 587static int pc98_check_if_type __P((device_t dev, struct siodev *iod)); 588static int pc98_check_8251vfast __P((void)); 589static int pc98_check_8251fifo __P((void)); 590static void pc98_check_sysclock __P((void)); 591static void pc98_set_ioport __P((struct com_s *com)); 592 593#define com_int_Tx_disable(com) \ 594 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP) 595#define com_int_Tx_enable(com) \ 596 pc98_enable_i8251_interrupt(com,IEN_TxFLAG) 597#define com_int_Rx_disable(com) \ 598 pc98_disable_i8251_interrupt(com,IEN_Rx) 599#define com_int_Rx_enable(com) \ 600 pc98_enable_i8251_interrupt(com,IEN_Rx) 601#define com_int_TxRx_disable(com) \ 602 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP|IEN_Rx) 603#define com_int_TxRx_enable(com) \ 604 pc98_enable_i8251_interrupt(com,IEN_TxFLAG|IEN_Rx) 605#define com_send_break_on(com) \ 606 pc98_i8251_or_cmd(com,CMD8251_SBRK) 607#define com_send_break_off(com) \ 608 pc98_i8251_clear_cmd(com,CMD8251_SBRK) 609 610static struct speedtab pc98speedtab[] = { /* internal RS232C interface */ 611 { 0, 0, }, 612 { 50, 50, }, 613 { 75, 75, }, 614 { 150, 150, }, 615 { 200, 200, }, 616 { 300, 300, }, 617 { 600, 600, }, 618 { 1200, 1200, }, 619 { 2400, 2400, }, 620 { 4800, 4800, }, 621 { 9600, 9600, }, 622 { 19200, 19200, }, 623 { 38400, 38400, }, 624 { 51200, 51200, }, 625 { 76800, 76800, }, 626 { 20800, 20800, }, 627 { 31200, 31200, }, 628 { 41600, 41600, }, 629 { 62400, 62400, }, 630 { -1, -1 } 631}; 632static struct speedtab pc98fast_speedtab[] = { 633 { 9600, 0x80 | COMBRD(9600), }, 634 { 19200, 0x80 | COMBRD(19200), }, 635 { 38400, 0x80 | COMBRD(38400), }, 636 { 57600, 0x80 | COMBRD(57600), }, 637 { 115200, 0x80 | COMBRD(115200), }, 638 { -1, -1 } 639}; 640static struct speedtab comspeedtab_pio9032b[] = { 641 { 300, 6, }, 642 { 600, 5, }, 643 { 1200, 4, }, 644 { 2400, 3, }, 645 { 4800, 2, }, 646 { 9600, 1, }, 647 { 19200, 0, }, 648 { 38400, 7, }, 649 { -1, -1 } 650}; 651static struct speedtab comspeedtab_b98_01[] = { 652 { 75, 11, }, 653 { 150, 10, }, 654 { 300, 9, }, 655 { 600, 8, }, 656 { 1200, 7, }, 657 { 2400, 6, }, 658 { 4800, 5, }, 659 { 9600, 4, }, 660 { 19200, 3, }, 661 { 38400, 2, }, 662 { 76800, 1, }, 663 { 153600, 0, }, 664 { -1, -1 } 665}; 666static struct speedtab comspeedtab_mc16550[] = { 667 { 300, 1536, }, 668 { 600, 768, }, 669 { 1200, 384, }, 670 { 2400, 192, }, 671 { 4800, 96, }, 672 { 9600, 48, }, 673 { 19200, 24, }, 674 { 38400, 12, }, 675 { 57600, 8, }, 676 { 115200, 4, }, 677 { 153600, 3, }, 678 { 230400, 2, }, 679 { 460800, 1, }, 680 { -1, -1 } 681}; 682static struct speedtab comspeedtab_rsb384[] = { 683 { 300, 3840, }, 684 { 600, 1920, }, 685 { 1200, 960, }, 686 { 2400, 480, }, 687 { 4800, 240, }, 688 { 9600, 120, }, 689 { 19200, 60, }, 690 { 38400, 30, }, 691 { 57600, 20, }, 692 { 115200, 10, }, 693 { 128000, 9, }, 694 { 144000, 8, }, 695 { 192000, 6, }, 696 { 230400, 5, }, 697 { 288000, 4, }, 698 { 384000, 3, }, 699 { 576000, 2, }, 700 { 1152000, 1, }, 701 { -1, -1 } 702}; 703static struct speedtab comspeedtab_rsa[] = { 704 { 0, 0 }, 705 { 50, COMBRD_RSA(50) }, 706 { 75, COMBRD_RSA(75) }, 707 { 110, COMBRD_RSA(110) }, 708 { 134, COMBRD_RSA(134) }, 709 { 150, COMBRD_RSA(150) }, 710 { 200, COMBRD_RSA(200) }, 711 { 300, COMBRD_RSA(300) }, 712 { 600, COMBRD_RSA(600) }, 713 { 1200, COMBRD_RSA(1200) }, 714 { 1800, COMBRD_RSA(1800) }, 715 { 2400, COMBRD_RSA(2400) }, 716 { 4800, COMBRD_RSA(4800) }, 717 { 9600, COMBRD_RSA(9600) }, 718 { 19200, COMBRD_RSA(19200) }, 719 { 38400, COMBRD_RSA(38400) }, 720 { 57600, COMBRD_RSA(57600) }, 721 { 115200, COMBRD_RSA(115200) }, 722 { 230400, COMBRD_RSA(230400) }, 723 { 460800, COMBRD_RSA(460800) }, 724 { 921600, COMBRD_RSA(921600) }, 725 { -1, -1 } 726}; 727#endif /* PC98 */ 728 729static struct speedtab comspeedtab[] = { 730 { 0, 0 }, 731 { 50, COMBRD(50) }, 732 { 75, COMBRD(75) }, 733 { 110, COMBRD(110) }, 734 { 134, COMBRD(134) }, 735 { 150, COMBRD(150) }, 736 { 200, COMBRD(200) }, 737 { 300, COMBRD(300) }, 738 { 600, COMBRD(600) }, 739 { 1200, COMBRD(1200) }, 740 { 1800, COMBRD(1800) }, 741 { 2400, COMBRD(2400) }, 742 { 4800, COMBRD(4800) }, 743 { 9600, COMBRD(9600) }, 744 { 19200, COMBRD(19200) }, 745 { 38400, COMBRD(38400) }, 746 { 57600, COMBRD(57600) }, 747 { 115200, COMBRD(115200) }, 748 { -1, -1 } 749}; 750 751#ifdef PC98 752struct { 753 char *name; 754 short port_table[7]; 755 short irr_mask; 756 struct speedtab *speedtab; 757 short check_irq; 758} if_8251_type[] = { 759 /* COM_IF_INTERNAL */ 760 { " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1}, 761 -1, pc98speedtab, 1 }, 762 /* COM_IF_PC9861K_1 */ 763 { " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1}, 764 3, NULL, 1 }, 765 /* COM_IF_PC9861K_2 */ 766 { " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1}, 767 3, NULL, 1 }, 768 /* COM_IF_IND_SS_1 */ 769 { " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1}, 770 3, comspeedtab_mc16550, 1 }, 771 /* COM_IF_IND_SS_2 */ 772 { " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1}, 773 3, comspeedtab_mc16550, 1 }, 774 /* COM_IF_PIO9032B_1 */ 775 { " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1}, 776 7, comspeedtab_pio9032b, 1 }, 777 /* COM_IF_PIO9032B_2 */ 778 { " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1}, 779 7, comspeedtab_pio9032b, 1 }, 780 /* COM_IF_B98_01_1 */ 781 { " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3}, 782 7, comspeedtab_b98_01, 0 }, 783 /* COM_IF_B98_01_2 */ 784 { " (B98-01)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xd5, 0xd7}, 785 7, comspeedtab_b98_01, 0 }, 786}; 787#define PC98SIO_data_port(type) (if_8251_type[type].port_table[0]) 788#define PC98SIO_cmd_port(type) (if_8251_type[type].port_table[1]) 789#define PC98SIO_sts_port(type) (if_8251_type[type].port_table[2]) 790#define PC98SIO_in_modem_port(type) (if_8251_type[type].port_table[3]) 791#define PC98SIO_intr_ctrl_port(type) (if_8251_type[type].port_table[4]) 792#define PC98SIO_baud_rate_port(type) (if_8251_type[type].port_table[5]) 793#define PC98SIO_func_port(type) (if_8251_type[type].port_table[6]) 794 795#define I8251F_data 0x130 796#define I8251F_lsr 0x132 797#define I8251F_msr 0x134 798#define I8251F_iir 0x136 799#define I8251F_fcr 0x138 800#define I8251F_div 0x13a 801 802 803static bus_addr_t port_table_0[] = 804 {0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007}; 805static bus_addr_t port_table_1[] = 806 {0x000, 0x002, 0x004, 0x006, 0x008, 0x00a, 0x00c, 0x00e}; 807static bus_addr_t port_table_8[] = 808 {0x000, 0x100, 0x200, 0x300, 0x400, 0x500, 0x600, 0x700}; 809static bus_addr_t port_table_rsa[] = { 810 0x008, 0x009, 0x00a, 0x00b, 0x00c, 0x00d, 0x00e, 0x00f, 811 0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007 812}; 813 814struct { 815 char *name; 816 short irr_read; 817 short irr_write; 818 bus_addr_t *iat; 819 bus_size_t iatsz; 820 struct speedtab *speedtab; 821} if_16550a_type[] = { 822 /* COM_IF_RSA98 */ 823 {" (RSA-98)", -1, -1, port_table_0, IO_COMSIZE, comspeedtab}, 824 /* COM_IF_NS16550 */ 825 {"", -1, -1, port_table_0, IO_COMSIZE, comspeedtab}, 826 /* COM_IF_SECOND_CCU */ 827 {"", -1, -1, port_table_0, IO_COMSIZE, comspeedtab}, 828 /* COM_IF_MC16550II */ 829 {" (MC16550II)", -1, 0x1000, port_table_8, IO_COMSIZE, 830 comspeedtab_mc16550}, 831 /* COM_IF_MCRS98 */ 832 {" (MC-RS98)", -1, 0x1000, port_table_8, IO_COMSIZE, 833 comspeedtab_mc16550}, 834 /* COM_IF_RSB3000 */ 835 {" (RSB-3000)", 0xbf, -1, port_table_1, IO_COMSIZE, 836 comspeedtab_rsb384}, 837 /* COM_IF_RSB384 */ 838 {" (RSB-384)", 0xbf, -1, port_table_1, IO_COMSIZE, comspeedtab_rsb384}, 839 /* COM_IF_MODEM_CARD */ 840 {"", -1, -1, port_table_0, IO_COMSIZE, comspeedtab}, 841 /* COM_IF_RSA98III */ 842 {" (RSA-98III)", -1, -1, port_table_rsa, 16, comspeedtab_rsa}, 843 /* COM_IF_ESP98 */ 844 {" (ESP98)", -1, -1, port_table_1, IO_COMSIZE, comspeedtab_mc16550}, 845}; 846#endif /* PC98 */ 847 848#ifdef COM_ESP 849#ifdef PC98 850 851/* XXX configure this properly. */ 852static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 }; 853static Port_t likely_esp_ports[] = { 0xc0d0, 0 }; 854 855#define ESP98_CMD1 (ESP_CMD1 * 0x100) 856#define ESP98_CMD2 (ESP_CMD2 * 0x100) 857#define ESP98_STATUS1 (ESP_STATUS1 * 0x100) 858#define ESP98_STATUS2 (ESP_STATUS2 * 0x100) 859 860#else /* PC98 */ 861 862/* XXX configure this properly. */ 863static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, }; 864static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 }; 865 866#endif /* PC98 */ 867#endif 868 869/* 870 * handle sysctl read/write requests for console speed 871 * 872 * In addition to setting comdefaultrate for I/O through /dev/console, 873 * also set the initial and lock values for the /dev/ttyXX device 874 * if there is one associated with the console. Finally, if the /dev/tty 875 * device has already been open, change the speed on the open running port 876 * itself. 877 */ 878 879static int 880sysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS) 881{ 882 int error, s; 883 speed_t newspeed; 884 struct com_s *com; 885 struct tty *tp; 886 887 newspeed = comdefaultrate; 888 889 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req); 890 if (error || !req->newptr) 891 return (error); 892 893 comdefaultrate = newspeed; 894 895 if (comconsole < 0) /* serial console not selected? */ 896 return (0); 897 898 com = com_addr(comconsole); 899 if (com == NULL) 900 return (ENXIO); 901 902 /* 903 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX 904 * (note, the lock rates really are boolean -- if non-zero, disallow 905 * speed changes) 906 */ 907 com->it_in.c_ispeed = com->it_in.c_ospeed = 908 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 909 com->it_out.c_ispeed = com->it_out.c_ospeed = 910 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate; 911 912 /* 913 * if we're open, change the running rate too 914 */ 915 tp = com->tp; 916 if (tp && (tp->t_state & TS_ISOPEN)) { 917 tp->t_termios.c_ispeed = 918 tp->t_termios.c_ospeed = comdefaultrate; 919 s = spltty(); 920 error = comparam(tp, &tp->t_termios); 921 splx(s); 922 } 923 return error; 924} 925 926SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW, 927 0, 0, sysctl_machdep_comdefaultrate, "I", ""); 928 929#define SET_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) | (bit)) 930#define CLR_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) & ~(bit)) 931 932#if NCARD > 0 933static int 934sio_pccard_probe(dev) 935 device_t dev; 936{ 937 /* Do not probe IRQ - pccard doesn't turn on the interrupt line */ 938 /* until bus_setup_intr */ 939 SET_FLAG(dev, COM_C_NOPROBE); 940 941 return (sioprobe(dev, 0)); 942} 943 944static int 945sio_pccard_attach(dev) 946 device_t dev; 947{ 948 return (sioattach(dev, 0)); 949} 950 951/* 952 * sio_detach - unload the driver and clear the table. 953 * XXX TODO: 954 * This is usually called when the card is ejected, but 955 * can be caused by a modunload of a controller driver. 956 * The idea is to reset the driver's view of the device 957 * and ensure that any driver entry points such as 958 * read and write do not hang. 959 */ 960static int 961sio_pccard_detach(dev) 962 device_t dev; 963{ 964 struct com_s *com; 965 966 com = (struct com_s *) device_get_softc(dev); 967 if (com == NULL) { 968 device_printf(dev, "NULL com in siounload\n"); 969 return (0); 970 } 971 com->gone = 1; 972 if (com->irqres) { 973 bus_teardown_intr(dev, com->irqres, com->cookie); 974 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres); 975 } 976 if (com->ioportres) 977 bus_release_resource(dev, SYS_RES_IOPORT, 0, com->ioportres); 978 if (com->tp && (com->tp->t_state & TS_ISOPEN)) { 979 device_printf(dev, "still open, forcing close\n"); 980 com->tp->t_gen++; 981 ttyclose(com->tp); 982 ttwakeup(com->tp); 983 ttwwakeup(com->tp); 984 } else { 985 if (com->ibuf != NULL) 986 free(com->ibuf, M_DEVBUF); 987 } 988 device_printf(dev, "unloaded\n"); 989 return (0); 990} 991#endif /* NCARD > 0 */ 992 993#if NPCI > 0 994struct pci_ids { 995 u_int32_t type; 996 const char *desc; 997 int rid; 998}; 999 1000static struct pci_ids pci_ids[] = { 1001 { 0x100812b9, "3COM PCI FaxModem", 0x10 }, 1002 { 0x048011c1, "ActionTec 56k FAX PCI Modem", 0x14 }, 1003 { 0x00000000, NULL, 0 } 1004}; 1005 1006static int 1007sio_pci_attach(dev) 1008 device_t dev; 1009{ 1010 u_int32_t type; 1011 struct pci_ids *id; 1012 1013 type = pci_get_devid(dev); 1014 id = pci_ids; 1015 while (id->type && id->type != type) 1016 id++; 1017 if (id->desc == NULL) 1018 return (ENXIO); 1019 sio_pci_kludge_unit(dev); 1020 return (sioattach(dev, id->rid)); 1021} 1022 1023/* 1024 * Don't cut and paste this to other drivers. It is a horrible kludge 1025 * which will fail to work and also be unnecessary in future versions. 1026 */ 1027static void 1028sio_pci_kludge_unit(dev) 1029 device_t dev; 1030{ 1031 devclass_t dc; 1032 int err; 1033 int start; 1034 int unit; 1035 1036 unit = 0; 1037 start = 0; 1038 while (resource_int_value("sio", unit, "port", &start) == 0 && 1039 start > 0) 1040 unit++; 1041 if (device_get_unit(dev) < unit) { 1042 dc = device_get_devclass(dev); 1043 while (devclass_get_device(dc, unit)) 1044 unit++; 1045 device_printf(dev, "moving to sio%d\n", unit); 1046 err = device_set_unit(dev, unit); /* EVIL DO NOT COPY */ 1047 if (err) 1048 device_printf(dev, "error moving device %d\n", err); 1049 } 1050} 1051 1052static int 1053sio_pci_probe(dev) 1054 device_t dev; 1055{ 1056 u_int32_t type; 1057 struct pci_ids *id; 1058 1059 type = pci_get_devid(dev); 1060 id = pci_ids; 1061 while (id->type && id->type != type) 1062 id++; 1063 if (id->desc == NULL) 1064 return (ENXIO); 1065 device_set_desc(dev, id->desc); 1066 return (sioprobe(dev, id->rid)); 1067} 1068#endif /* NPCI > 0 */ 1069 1070static struct isa_pnp_id sio_ids[] = { 1071 {0x0005d041, "Standard PC COM port"}, /* PNP0500 */ 1072 {0x0105d041, "16550A-compatible COM port"}, /* PNP0501 */ 1073 {0x0205d041, "Multiport serial device (non-intelligent 16550)"}, /* PNP0502 */ 1074 {0x1005d041, "Generic IRDA-compatible device"}, /* PNP0510 */ 1075 {0x1105d041, "Generic IRDA-compatible device"}, /* PNP0511 */ 1076 /* Devices that do not have a compatid */ 1077 {0x7602a904, NULL}, /* AEI0276 - 56K v.90 Fax Modem (LKT) */ 1078 {0x00007905, NULL}, /* AKY0000 - 56K Plug&Play Modem */ 1079 {0x01405407, NULL}, /* AZT4001 - AZT3000 PnP SOUND DEVICE, MODEM */ 1080 {0x56039008, NULL}, /* BDP0356 - Best Data 56x2 */ 1081 {0x36339008, NULL}, /* BDP3336 - Best Data Prods. 336F */ 1082 {0x0014490a, NULL}, /* BRI1400 - Boca 33.6 PnP */ 1083 {0x0015490a, NULL}, /* BRI1500 - Internal Fax Data */ 1084 {0x0034490a, NULL}, /* BRI3400 - Internal ACF Modem */ 1085 {0x0094490a, NULL}, /* BRI9400 - Boca K56Flex PnP */ 1086 {0x00b4490a, NULL}, /* BRIB400 - Boca 56k PnP */ 1087 {0x0030320d, NULL}, /* CIR3000 - Cirrus Logic V43 */ 1088 {0x0100440e, NULL}, /* CRD0001 - Cardinal MVP288IV ? */ 1089 {0x1200c31e, NULL}, /* GVC0012 - VF1128HV-R9 (win modem?) */ 1090 {0x0303c31e, NULL}, /* GVC0303 - MaxTech 33.6 PnP D/F/V */ 1091 {0x0505c31e, NULL}, /* GVC0505 - GVC 56k Faxmodem */ 1092 {0x0050c31e, NULL}, /* GVC5000 - some GVC modem */ 1093 {0x3800f91e, NULL}, /* GWY0038 - Telepath with v.90 */ 1094 {0x9062f91e, NULL}, /* GWY6290 - Telepath with x2 Technology */ 1095 {0x0000f435, NULL}, /* MOT0000 - Motorola ModemSURFR 33.6 Intern */ 1096 {0x5015f435, NULL}, /* MOT1550 - Motorola ModemSURFR 56K Modem */ 1097 {0xf015f435, NULL}, /* MOT15F0 - Motorola VoiceSURFR 56K Modem */ 1098 {0x6045f435, NULL}, /* MOT4560 - Motorola ? */ 1099 {0x61e7a338, NULL}, /* NECE761 - 33.6Modem */ 1100 {0x39804f3f, NULL}, /* OZO8039 - Zoom 56k flex */ 1101 {0x3024a341, NULL}, /* PMC2430 - Pace 56 Voice Internal Modem */ 1102 {0x1000eb49, NULL}, /* ROK0010 - Rockwell ? */ 1103 {0x5002734a, NULL}, /* RSS0250 - 5614Jx3(G) Internal Modem */ 1104 {0xc100ad4d, NULL}, /* SMM00C1 - Leopard 56k PnP */ 1105 {0x9012b04e, NULL}, /* SUP1290 - Supra ? */ 1106 {0x1013b04e, NULL}, /* SUP1310 - SupraExpress 336i PnP */ 1107 {0x8013b04e, NULL}, /* SUP1380 - SupraExpress 288i PnP Voice */ 1108 {0x8113b04e, NULL}, /* SUP1381 - SupraExpress 336i PnP Voice */ 1109 {0x5016b04e, NULL}, /* SUP1650 - Supra 336i Sp Intl */ 1110 {0x7420b04e, NULL}, /* SUP2070 - Supra ? */ 1111 {0x8020b04e, NULL}, /* SUP2080 - Supra ? */ 1112 {0x8420b04e, NULL}, /* SUP2084 - SupraExpress 56i PnP */ 1113 {0x7121b04e, NULL}, /* SUP2171 - SupraExpress 56i Sp? */ 1114 {0x8024b04e, NULL}, /* SUP2480 - Supra ? */ 1115 {0x01007256, NULL}, /* USR0001 - U.S. Robotics Inc., Sportster W */ 1116 {0x02007256, NULL}, /* USR0002 - U.S. Robotics Inc. Sportster 33. */ 1117 {0x04007256, NULL}, /* USR0004 - USR Sportster 14.4k */ 1118 {0x06007256, NULL}, /* USR0006 - USR Sportster 33.6k */ 1119 {0x11007256, NULL}, /* USR0011 - USR ? */ 1120 {0x01017256, NULL}, /* USR0101 - USR ? */ 1121 {0x30207256, NULL}, /* USR2030 - U.S.Robotics Inc. Sportster 560 */ 1122 {0x50207256, NULL}, /* USR2050 - U.S.Robotics Inc. Sportster 33. */ 1123 {0x70207256, NULL}, /* USR2070 - U.S.Robotics Inc. Sportster 560 */ 1124 {0x30307256, NULL}, /* USR3030 - U.S. Robotics 56K FAX INT */ 1125 {0x31307256, NULL}, /* USR3031 - U.S. Robotics 56K FAX INT */ 1126 {0x50307256, NULL}, /* USR3050 - U.S. Robotics 56K FAX INT */ 1127 {0x70307256, NULL}, /* USR3070 - U.S. Robotics 56K Voice INT */ 1128 {0x90307256, NULL}, /* USR3090 - USR ? */ 1129 {0x90917256, NULL}, /* USR9190 - USR 56k Voice INT */ 1130 {0x0300695c, NULL}, /* WCI0003 - Fax/Voice/Modem/Speakphone/Asvd */ 1131 {0x01a0896a, NULL}, /* ZTIA001 - Zoom Internal V90 Faxmodem */ 1132 {0x61f7896a, NULL}, /* ZTIF761 - Zoom ComStar 33.6 */ 1133#ifdef PC98 1134 {0x0100e4a5, "RSA-98III"}, 1135#endif 1136 {0} 1137}; 1138 1139 1140 1141static int 1142sio_isa_probe(dev) 1143 device_t dev; 1144{ 1145#ifdef PC98 1146 int logical_id; 1147#endif 1148 /* Check isapnp ids */ 1149 if (ISA_PNP_PROBE(device_get_parent(dev), dev, sio_ids) == ENXIO) 1150 return (ENXIO); 1151#ifdef PC98 1152 logical_id = isa_get_logicalid(dev); 1153 if (logical_id == 0x0100e4a5) /* RSA-98III */ 1154 device_set_flags(dev, SET_IFTYPE(COM_IF_RSA98III)); 1155#endif 1156 return (sioprobe(dev, 0)); 1157} 1158 1159static int 1160sioprobe(dev, xrid) 1161 device_t dev; 1162 int xrid; 1163{ 1164#if 0 1165 static bool_t already_init; 1166 device_t xdev; 1167#endif 1168 struct com_s *com; 1169 bool_t failures[10]; 1170 int fn; 1171 device_t idev; 1172 Port_t iobase; 1173 intrmask_t irqmap[4]; 1174 intrmask_t irqs; 1175 u_char mcr_image; 1176 int result; 1177 u_long xirq; 1178 u_int flags = device_get_flags(dev); 1179 int rid; 1180 struct resource *port; 1181 int intrsave; 1182#ifdef PC98 1183 int tmp; 1184 struct siodev iod; 1185#endif 1186 1187#ifdef PC98 1188 iod.if_type = GET_IFTYPE(flags); 1189 if ((iod.if_type < 0 || iod.if_type > COM_IF_END1) && 1190 (iod.if_type < 0x10 || iod.if_type > COM_IF_END2)) 1191 return ENXIO; 1192#endif 1193 1194 rid = xrid; 1195#ifdef PC98 1196 if (IS_8251(iod.if_type)) { 1197 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1198 0, ~0, 1, RF_ACTIVE); 1199 } else if (iod.if_type == COM_IF_RSA98III || 1200 isa_get_vendorid(dev)) { 1201 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 1202 if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE); 1203 } else { 1204 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, 1205 if_16550a_type[iod.if_type & 0x0f].iat, 1206 if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE); 1207 } 1208#else 1209 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1210 0, ~0, IO_COMSIZE, RF_ACTIVE); 1211#endif 1212 if (!port) 1213 return (ENXIO); 1214#ifdef PC98 1215 if (!IS_8251(iod.if_type)) { 1216 if (isa_load_resourcev(port, 1217 if_16550a_type[iod.if_type & 0x0f].iat, 1218 if_16550a_type[iod.if_type & 0x0f].iatsz) != 0) { 1219 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1220 return ENXIO; 1221 } 1222 } 1223#endif 1224 1225 com = device_get_softc(dev); 1226 com->bst = rman_get_bustag(port); 1227 com->bsh = rman_get_bushandle(port); 1228 1229#if 0 1230 /* 1231 * XXX this is broken - when we are first called, there are no 1232 * previously configured IO ports. We could hard code 1233 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse. 1234 * This code has been doing nothing since the conversion since 1235 * "count" is zero the first time around. 1236 */ 1237 if (!already_init) { 1238 /* 1239 * Turn off MCR_IENABLE for all likely serial ports. An unused 1240 * port with its MCR_IENABLE gate open will inhibit interrupts 1241 * from any used port that shares the interrupt vector. 1242 * XXX the gate enable is elsewhere for some multiports. 1243 */ 1244 device_t *devs; 1245 int count, i, xioport; 1246#ifdef PC98 1247 int xiftype; 1248#endif 1249 1250 devclass_get_devices(sio_devclass, &devs, &count); 1251#ifdef PC98 1252 for (i = 0; i < count; i++) { 1253 xdev = devs[i]; 1254 xioport = bus_get_resource_start(xdev, SYS_RES_IOPORT, 0); 1255 xiftype = GET_IFTYPE(device_get_flags(xdev)); 1256 if (device_is_enabled(xdev) && xioport > 0) { 1257 if (IS_8251(xiftype)) 1258 outb((xioport & 0xff00) | PC98SIO_cmd_port(xiftype & 0x0f), 0xf2); 1259 else 1260 outb(xioport + if_16550a_type[xiftype & 0x0f].iat[com_mcr], 0); 1261 } 1262 } 1263#else 1264 for (i = 0; i < count; i++) { 1265 xdev = devs[i]; 1266 if (device_is_enabled(xdev) && 1267 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport, 1268 NULL) == 0) 1269 outb(xioport + com_mcr, 0); 1270 } 1271#endif 1272 free(devs, M_TEMP); 1273 already_init = TRUE; 1274 } 1275#endif 1276 1277 if (COM_LLCONSOLE(flags)) { 1278 printf("sio%d: reserved for low-level i/o\n", 1279 device_get_unit(dev)); 1280 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1281 return (ENXIO); 1282 } 1283 1284#ifdef PC98 1285 DELAY(10); 1286 1287 /* 1288 * If the port is i8251 UART (internal, B98_01) 1289 */ 1290 if (pc98_check_if_type(dev, &iod) == -1) { 1291 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1292 return (ENXIO); 1293 } 1294 if (iod.irq > 0) 1295 bus_set_resource(dev, SYS_RES_IRQ, 0, iod.irq, 1); 1296 if (IS_8251(iod.if_type)) { 1297 outb(iod.cmd, 0); 1298 DELAY(10); 1299 outb(iod.cmd, 0); 1300 DELAY(10); 1301 outb(iod.cmd, 0); 1302 DELAY(10); 1303 outb(iod.cmd, CMD8251_RESET); 1304 DELAY(1000); /* for a while...*/ 1305 outb(iod.cmd, 0xf2); /* MODE (dummy) */ 1306 DELAY(10); 1307 outb(iod.cmd, 0x01); /* CMD (dummy) */ 1308 DELAY(1000); /* for a while...*/ 1309 if (( inb(iod.sts) & STS8251_TxEMP ) == 0 ) { 1310 result = (ENXIO); 1311 } 1312 if (if_8251_type[iod.if_type & 0x0f].check_irq) { 1313 COM_INT_DISABLE 1314 tmp = ( inb( iod.ctrl ) & ~(IEN_Rx|IEN_TxEMP|IEN_Tx)); 1315 outb( iod.ctrl, tmp|IEN_TxEMP ); 1316 DELAY(10); 1317 result = isa_irq_pending() ? 0 : ENXIO; 1318 outb( iod.ctrl, tmp ); 1319 COM_INT_ENABLE 1320 } else { 1321 /* 1322 * B98_01 doesn't activate TxEMP interrupt line 1323 * when being reset, so we can't check irq pending. 1324 */ 1325 result = 0; 1326 } 1327 if (epson_machine_id==0x20) { /* XXX */ 1328 result = 0; 1329 } 1330 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1331 return result; 1332 } 1333#endif /* PC98 */ 1334 /* 1335 * If the device is on a multiport card and has an AST/4 1336 * compatible interrupt control register, initialize this 1337 * register and prepare to leave MCR_IENABLE clear in the mcr. 1338 * Otherwise, prepare to set MCR_IENABLE in the mcr. 1339 * Point idev to the device struct giving the correct id_irq. 1340 * This is the struct for the master device if there is one. 1341 */ 1342 idev = dev; 1343 mcr_image = MCR_IENABLE; 1344#ifdef COM_MULTIPORT 1345 if (COM_ISMULTIPORT(flags)) { 1346#ifndef PC98 1347 Port_t xiobase; 1348 u_long io; 1349#endif 1350 1351 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags)); 1352 if (idev == NULL) { 1353 printf("sio%d: master device %d not configured\n", 1354 device_get_unit(dev), COM_MPMASTER(flags)); 1355 idev = dev; 1356 } 1357#ifndef PC98 1358 if (!COM_NOTAST4(flags)) { 1359 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io, 1360 NULL) == 0) { 1361 xiobase = io; 1362 if (bus_get_resource(idev, SYS_RES_IRQ, 0, 1363 NULL, NULL) == 0) 1364 outb(xiobase + com_scr, 0x80); 1365 else 1366 outb(xiobase + com_scr, 0); 1367 } 1368 mcr_image = 0; 1369 } 1370#endif 1371 } 1372#endif /* COM_MULTIPORT */ 1373 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0) 1374 mcr_image = 0; 1375 1376 bzero(failures, sizeof failures); 1377 iobase = rman_get_start(port); 1378 1379#ifdef PC98 1380 if (iod.if_type == COM_IF_RSA98III) { 1381 mcr_image = 0; 1382 1383 outb(iobase + rsa_msr, 0x04); 1384 outb(iobase + rsa_frr, 0x00); 1385 if ((inb(iobase + rsa_srr) & 0x36) != 0x36) { 1386 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1387 return (ENXIO); 1388 } 1389 outb(iobase + rsa_ier, 0x00); 1390 outb(iobase + rsa_frr, 0x00); 1391 outb(iobase + rsa_tivsr, 0x00); 1392 outb(iobase + rsa_tcr, 0x00); 1393 } 1394 1395 tmp = if_16550a_type[iod.if_type & 0x0f].irr_write; 1396 if (tmp != -1) { 1397 /* MC16550II */ 1398 int irqout; 1399 switch (isa_get_irq(idev)) { 1400 case 3: irqout = 4; break; 1401 case 5: irqout = 5; break; 1402 case 6: irqout = 6; break; 1403 case 12: irqout = 7; break; 1404 default: 1405 printf("sio%d: irq configuration error\n", 1406 device_get_unit(dev)); 1407 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1408 return (ENXIO); 1409 } 1410 outb((iobase & 0x00ff) | tmp, irqout); 1411 } 1412#endif 1413 1414 /* 1415 * We don't want to get actual interrupts, just masked ones. 1416 * Interrupts from this line should already be masked in the ICU, 1417 * but mask them in the processor as well in case there are some 1418 * (misconfigured) shared interrupts. 1419 */ 1420 intrsave = save_intr(); 1421 disable_intr(); 1422 COM_LOCK(); 1423/* EXTRA DELAY? */ 1424 1425 /* 1426 * Initialize the speed and the word size and wait long enough to 1427 * drain the maximum of 16 bytes of junk in device output queues. 1428 * The speed is undefined after a master reset and must be set 1429 * before relying on anything related to output. There may be 1430 * junk after a (very fast) soft reboot and (apparently) after 1431 * master reset. 1432 * XXX what about the UART bug avoided by waiting in comparam()? 1433 * We don't want to to wait long enough to drain at 2 bps. 1434 */ 1435 if (iobase == siocniobase) 1436 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10)); 1437 else { 1438#ifdef PC98 1439 tmp = ttspeedtab(SIO_TEST_SPEED, 1440 if_16550a_type[iod.if_type & 0x0f].speedtab); 1441 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS); 1442 sio_setreg(com, com_dlbl, tmp & 0xff); 1443 sio_setreg(com, com_dlbh, (tmp >> 8) & 0xff); 1444 sio_setreg(com, com_cfcr, CFCR_8BITS); 1445#else 1446 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS); 1447 sio_setreg(com, com_dlbl, COMBRD(SIO_TEST_SPEED) & 0xff); 1448 sio_setreg(com, com_dlbh, (u_int) COMBRD(SIO_TEST_SPEED) >> 8); 1449 sio_setreg(com, com_cfcr, CFCR_8BITS); 1450#endif 1451 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10)); 1452 } 1453 1454 /* 1455 * Enable the interrupt gate and disable device interupts. This 1456 * should leave the device driving the interrupt line low and 1457 * guarantee an edge trigger if an interrupt can be generated. 1458 */ 1459/* EXTRA DELAY? */ 1460 sio_setreg(com, com_mcr, mcr_image); 1461 sio_setreg(com, com_ier, 0); 1462 DELAY(1000); /* XXX */ 1463 irqmap[0] = isa_irq_pending(); 1464 1465 /* 1466 * Attempt to set loopback mode so that we can send a null byte 1467 * without annoying any external device. 1468 */ 1469/* EXTRA DELAY? */ 1470 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK); 1471 1472 /* 1473 * Attempt to generate an output interrupt. On 8250's, setting 1474 * IER_ETXRDY generates an interrupt independent of the current 1475 * setting and independent of whether the THR is empty. On 16450's, 1476 * setting IER_ETXRDY generates an interrupt independent of the 1477 * current setting. On 16550A's, setting IER_ETXRDY only 1478 * generates an interrupt when IER_ETXRDY is not already set. 1479 */ 1480 sio_setreg(com, com_ier, IER_ETXRDY); 1481#ifdef PC98 1482 if (iod.if_type == COM_IF_RSA98III) 1483 outb(iobase + rsa_ier, 0x04); 1484#endif 1485 1486 /* 1487 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate 1488 * an interrupt. They'd better generate one for actually doing 1489 * output. Loopback may be broken on the same incompatibles but 1490 * it's unlikely to do more than allow the null byte out. 1491 */ 1492 sio_setreg(com, com_data, 0); 1493 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10)); 1494 1495 /* 1496 * Turn off loopback mode so that the interrupt gate works again 1497 * (MCR_IENABLE was hidden). This should leave the device driving 1498 * an interrupt line high. It doesn't matter if the interrupt 1499 * line oscillates while we are not looking at it, since interrupts 1500 * are disabled. 1501 */ 1502/* EXTRA DELAY? */ 1503 sio_setreg(com, com_mcr, mcr_image); 1504 1505 /* 1506 * Some pcmcia cards have the "TXRDY bug", so we check everyone 1507 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... ) 1508 */ 1509 if (COM_NOPROBE(flags)) { 1510 /* Reading IIR register twice */ 1511 for (fn = 0; fn < 2; fn ++) { 1512 DELAY(10000); 1513 failures[6] = sio_getreg(com, com_iir); 1514 } 1515 /* Check IIR_TXRDY clear ? */ 1516 result = 0; 1517 if (failures[6] & IIR_TXRDY) { 1518 /* Nop, Double check with clearing IER */ 1519 sio_setreg(com, com_ier, 0); 1520 if (sio_getreg(com, com_iir) & IIR_NOPEND) { 1521 /* Ok. we're familia this gang */ 1522 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); 1523 } else { 1524 /* Unknown, Just omit this chip.. XXX */ 1525 result = ENXIO; 1526 } 1527 } else { 1528 /* OK. this is well-known guys */ 1529 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); 1530 } 1531 sio_setreg(com, com_cfcr, CFCR_8BITS); 1532 COM_UNLOCK(); 1533 restore_intr(intrsave); 1534 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1535 return (iobase == siocniobase ? 0 : result); 1536 } 1537 1538 /* 1539 * Check that 1540 * o the CFCR, IER and MCR in UART hold the values written to them 1541 * (the values happen to be all distinct - this is good for 1542 * avoiding false positive tests from bus echoes). 1543 * o an output interrupt is generated and its vector is correct. 1544 * o the interrupt goes away when the IIR in the UART is read. 1545 */ 1546/* EXTRA DELAY? */ 1547 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS; 1548 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY; 1549 failures[2] = sio_getreg(com, com_mcr) - mcr_image; 1550 DELAY(10000); /* Some internal modems need this time */ 1551 irqmap[1] = isa_irq_pending(); 1552 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY; 1553#ifdef PC98 1554 if (iod.if_type == COM_IF_RSA98III) 1555 inb(iobase + rsa_srr); 1556#endif 1557 DELAY(1000); /* XXX */ 1558 irqmap[2] = isa_irq_pending(); 1559 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 1560#ifdef PC98 1561 if (iod.if_type == COM_IF_RSA98III) 1562 inb(iobase + rsa_srr); 1563#endif 1564 1565 /* 1566 * Turn off all device interrupts and check that they go off properly. 1567 * Leave MCR_IENABLE alone. For ports without a master port, it gates 1568 * the OUT2 output of the UART to 1569 * the ICU input. Closing the gate would give a floating ICU input 1570 * (unless there is another device driving it) and spurious interrupts. 1571 * (On the system that this was first tested on, the input floats high 1572 * and gives a (masked) interrupt as soon as the gate is closed.) 1573 */ 1574 sio_setreg(com, com_ier, 0); 1575 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */ 1576 failures[7] = sio_getreg(com, com_ier); 1577#ifdef PC98 1578 if (iod.if_type == COM_IF_RSA98III) 1579 outb(iobase + rsa_ier, 0x00); 1580#endif 1581 DELAY(1000); /* XXX */ 1582 irqmap[3] = isa_irq_pending(); 1583 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 1584#ifdef PC98 1585 if (iod.if_type == COM_IF_RSA98III) { 1586 inb(iobase + rsa_srr); 1587 outb(iobase + rsa_frr, 0x00); 1588 } 1589#endif 1590 1591 COM_UNLOCK(); 1592 restore_intr(intrsave); 1593 1594 irqs = irqmap[1] & ~irqmap[0]; 1595 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 && 1596 ((1 << xirq) & irqs) == 0) 1597 printf( 1598 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n", 1599 device_get_unit(dev), xirq, irqs); 1600 if (bootverbose) 1601 printf("sio%d: irq maps: %#x %#x %#x %#x\n", 1602 device_get_unit(dev), 1603 irqmap[0], irqmap[1], irqmap[2], irqmap[3]); 1604 1605 result = 0; 1606 for (fn = 0; fn < sizeof failures; ++fn) 1607 if (failures[fn]) { 1608 sio_setreg(com, com_mcr, 0); 1609 result = ENXIO; 1610 if (bootverbose) { 1611 printf("sio%d: probe failed test(s):", 1612 device_get_unit(dev)); 1613 for (fn = 0; fn < sizeof failures; ++fn) 1614 if (failures[fn]) 1615 printf(" %d", fn); 1616 printf("\n"); 1617 } 1618 break; 1619 } 1620 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1621 return (iobase == siocniobase ? 0 : result); 1622} 1623 1624#ifdef COM_ESP 1625static int 1626espattach(com, esp_port) 1627 struct com_s *com; 1628 Port_t esp_port; 1629{ 1630 u_char dips; 1631 u_char val; 1632 1633 /* 1634 * Check the ESP-specific I/O port to see if we're an ESP 1635 * card. If not, return failure immediately. 1636 */ 1637 if ((inb(esp_port) & 0xf3) == 0) { 1638 printf(" port 0x%x is not an ESP board?\n", esp_port); 1639 return (0); 1640 } 1641 1642 /* 1643 * We've got something that claims to be a Hayes ESP card. 1644 * Let's hope so. 1645 */ 1646 1647 /* Get the dip-switch configuration */ 1648#ifdef PC98 1649 outb(esp_port + ESP98_CMD1, ESP_GETDIPS); 1650 dips = inb(esp_port + ESP98_STATUS1); 1651#else 1652 outb(esp_port + ESP_CMD1, ESP_GETDIPS); 1653 dips = inb(esp_port + ESP_STATUS1); 1654#endif 1655 1656 /* 1657 * Bits 0,1 of dips say which COM port we are. 1658 */ 1659#ifdef PC98 1660 if ((rman_get_start(com->ioportres) & 0xff) == 1661 likely_com_ports[dips & 0x03]) 1662#else 1663 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03]) 1664#endif 1665 printf(" : ESP"); 1666 else { 1667 printf(" esp_port has com %d\n", dips & 0x03); 1668 return (0); 1669 } 1670 1671 /* 1672 * Check for ESP version 2.0 or later: bits 4,5,6 = 010. 1673 */ 1674#ifdef PC98 1675 outb(esp_port + ESP98_CMD1, ESP_GETTEST); 1676 val = inb(esp_port + ESP98_STATUS1); /* clear reg 1 */ 1677 val = inb(esp_port + ESP98_STATUS2); 1678#else 1679 outb(esp_port + ESP_CMD1, ESP_GETTEST); 1680 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */ 1681 val = inb(esp_port + ESP_STATUS2); 1682#endif 1683 if ((val & 0x70) < 0x20) { 1684 printf("-old (%o)", val & 0x70); 1685 return (0); 1686 } 1687 1688 /* 1689 * Check for ability to emulate 16550: bit 7 == 1 1690 */ 1691 if ((dips & 0x80) == 0) { 1692 printf(" slave"); 1693 return (0); 1694 } 1695 1696 /* 1697 * Okay, we seem to be a Hayes ESP card. Whee. 1698 */ 1699 com->esp = TRUE; 1700 com->esp_port = esp_port; 1701 return (1); 1702} 1703#endif /* COM_ESP */ 1704 1705static int 1706sio_isa_attach(dev) 1707 device_t dev; 1708{ 1709 return (sioattach(dev, 0)); 1710} 1711 1712static int 1713sioattach(dev, xrid) 1714 device_t dev; 1715 int xrid; 1716{ 1717 struct com_s *com; 1718#ifdef COM_ESP 1719 Port_t *espp; 1720#endif 1721 Port_t iobase; 1722 int unit; 1723 u_int flags; 1724 int rid; 1725 struct resource *port; 1726 int ret; 1727 int intrstate; 1728#ifdef PC98 1729 u_char *obuf; 1730 u_long obufsize; 1731 int if_type = GET_IFTYPE(device_get_flags(dev)); 1732#endif 1733 1734 rid = xrid; 1735#ifdef PC98 1736 if (IS_8251(if_type)) { 1737 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1738 0, ~0, 1, RF_ACTIVE); 1739 } else if (if_type == COM_IF_RSA98III || 1740 isa_get_vendorid(dev)) { 1741 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 1742 if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE); 1743 } else { 1744 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, 1745 if_16550a_type[if_type & 0x0f].iat, 1746 if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE); 1747 } 1748#else 1749 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1750 0, ~0, IO_COMSIZE, RF_ACTIVE); 1751#endif 1752 if (!port) 1753 return (ENXIO); 1754#ifdef PC98 1755 if (!IS_8251(if_type)) { 1756 if (isa_load_resourcev(port, 1757 if_16550a_type[if_type & 0x0f].iat, 1758 if_16550a_type[if_type & 0x0f].iatsz) != 0) { 1759 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1760 return ENXIO; 1761 } 1762 } 1763#endif 1764 1765 iobase = rman_get_start(port); 1766 unit = device_get_unit(dev); 1767 com = device_get_softc(dev); 1768 flags = device_get_flags(dev); 1769 1770 if (unit >= sio_numunits) 1771 sio_numunits = unit + 1; 1772 1773#ifdef PC98 1774 obufsize = 256; 1775 if (if_type == COM_IF_RSA98III) 1776 obufsize = 2048; 1777 if ((obuf = malloc(obufsize * 2, M_DEVBUF, M_NOWAIT)) == NULL) { 1778 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1779 return ENXIO; 1780 } 1781 bzero(obuf, obufsize * 2); 1782#endif 1783 1784 /* 1785 * sioprobe() has initialized the device registers as follows: 1786 * o cfcr = CFCR_8BITS. 1787 * It is most important that CFCR_DLAB is off, so that the 1788 * data port is not hidden when we enable interrupts. 1789 * o ier = 0. 1790 * Interrupts are only enabled when the line is open. 1791 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible 1792 * interrupt control register or the config specifies no irq. 1793 * Keeping MCR_DTR and MCR_RTS off might stop the external 1794 * device from sending before we are ready. 1795 */ 1796 bzero(com, sizeof *com); 1797 com->unit = unit; 1798 com->ioportres = port; 1799 com->bst = rman_get_bustag(port); 1800 com->bsh = rman_get_bushandle(port); 1801 com->cfcr_image = CFCR_8BITS; 1802 com->dtr_wait = 3 * hz; 1803 com->loses_outints = COM_LOSESOUTINTS(flags) != 0; 1804 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0; 1805 com->tx_fifo_size = 1; 1806#ifdef PC98 1807 com->obufsize = obufsize; 1808 com->obuf1 = obuf; 1809 com->obuf2 = obuf + obufsize; 1810#endif 1811 com->obufs[0].l_head = com->obuf1; 1812 com->obufs[1].l_head = com->obuf2; 1813 1814#ifdef PC98 1815 com->pc98_if_type = if_type; 1816 1817 if (IS_8251(if_type)) { 1818 pc98_set_ioport(com); 1819 1820 if (if_type == COM_IF_INTERNAL && pc98_check_8251fifo()) { 1821 com->pc98_8251fifo = 1; 1822 com->pc98_8251fifo_enable = 0; 1823 } 1824 } else { 1825 bus_addr_t *iat = if_16550a_type[if_type & 0x0f].iat; 1826 1827 com->data_port = iobase + iat[com_data]; 1828 com->int_id_port = iobase + iat[com_iir]; 1829 com->modem_ctl_port = iobase + iat[com_mcr]; 1830 com->mcr_image = inb(com->modem_ctl_port); 1831 com->line_status_port = iobase + iat[com_lsr]; 1832 com->modem_status_port = iobase + iat[com_msr]; 1833 com->intr_ctl_port = iobase + iat[com_ier]; 1834 } 1835#else /* not PC98 */ 1836 com->data_port = iobase + com_data; 1837 com->int_id_port = iobase + com_iir; 1838 com->modem_ctl_port = iobase + com_mcr; 1839 com->mcr_image = inb(com->modem_ctl_port); 1840 com->line_status_port = iobase + com_lsr; 1841 com->modem_status_port = iobase + com_msr; 1842 com->intr_ctl_port = iobase + com_ier; 1843#endif 1844 1845 /* 1846 * We don't use all the flags from <sys/ttydefaults.h> since they 1847 * are only relevant for logins. It's important to have echo off 1848 * initially so that the line doesn't start blathering before the 1849 * echo flag can be turned off. 1850 */ 1851 com->it_in.c_iflag = 0; 1852 com->it_in.c_oflag = 0; 1853 com->it_in.c_cflag = TTYDEF_CFLAG; 1854 com->it_in.c_lflag = 0; 1855 if (unit == comconsole) { 1856#ifdef PC98 1857 if (IS_8251(com->pc98_if_type)) 1858 DELAY(100000); 1859#endif 1860 com->it_in.c_iflag = TTYDEF_IFLAG; 1861 com->it_in.c_oflag = TTYDEF_OFLAG; 1862 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL; 1863 com->it_in.c_lflag = TTYDEF_LFLAG; 1864 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL; 1865 com->lt_out.c_ispeed = com->lt_out.c_ospeed = 1866 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 1867 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate; 1868 } else 1869 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED; 1870 intrstate = save_intr(); 1871 if (siosetwater(com, com->it_in.c_ispeed) != 0) { 1872 COM_UNLOCK(); 1873 restore_intr(intrstate); 1874 /* 1875 * Leave i/o resources allocated if this is a `cn'-level 1876 * console, so that other devices can't snarf them. 1877 */ 1878 if (iobase != siocniobase) 1879 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1880 return (ENOMEM); 1881 } 1882 COM_UNLOCK(); 1883 restore_intr(intrstate); 1884 termioschars(&com->it_in); 1885 com->it_out = com->it_in; 1886 1887 /* attempt to determine UART type */ 1888 printf("sio%d: type", unit); 1889 1890 1891#ifndef PC98 1892#ifdef COM_MULTIPORT 1893 if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags)) 1894#else 1895 if (!COM_IIR_TXRDYBUG(flags)) 1896#endif 1897 { 1898 u_char scr; 1899 u_char scr1; 1900 u_char scr2; 1901 1902 scr = sio_getreg(com, com_scr); 1903 sio_setreg(com, com_scr, 0xa5); 1904 scr1 = sio_getreg(com, com_scr); 1905 sio_setreg(com, com_scr, 0x5a); 1906 scr2 = sio_getreg(com, com_scr); 1907 sio_setreg(com, com_scr, scr); 1908 if (scr1 != 0xa5 || scr2 != 0x5a) { 1909 printf(" 8250"); 1910 goto determined_type; 1911 } 1912 } 1913#endif /* !PC98 */ 1914#ifdef PC98 1915 if (IS_8251(com->pc98_if_type)) { 1916 if (com->pc98_8251fifo && !COM_NOFIFO(flags)) 1917 com->tx_fifo_size = 16; 1918 com_int_TxRx_disable( com ); 1919 com_cflag_and_speed_set( com, com->it_in.c_cflag, comdefaultrate ); 1920 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE ); 1921 com_send_break_off( com ); 1922 1923 if (com->pc98_if_type == COM_IF_INTERNAL) { 1924 printf(" (internal%s%s)", 1925 com->pc98_8251fifo ? " fifo" : "", 1926 PC98SIO_baud_rate_port(com->pc98_if_type) != -1 ? 1927 " v-fast" : ""); 1928 } else { 1929 printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name); 1930 } 1931 } else { 1932#endif /* PC98 */ 1933 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH); 1934 DELAY(100); 1935 com->st16650a = 0; 1936 switch (inb(com->int_id_port) & IIR_FIFO_MASK) { 1937 case FIFO_RX_LOW: 1938 printf(" 16450"); 1939 break; 1940 case FIFO_RX_MEDL: 1941 printf(" 16450?"); 1942 break; 1943 case FIFO_RX_MEDH: 1944 printf(" 16550?"); 1945 break; 1946 case FIFO_RX_HIGH: 1947 if (COM_NOFIFO(flags)) { 1948 printf(" 16550A fifo disabled"); 1949 } else { 1950 com->hasfifo = TRUE; 1951#ifdef PC98 1952 com->tx_fifo_size = 0; /* XXX flag conflicts. */ 1953 printf(" 16550A"); 1954#else 1955 if (COM_ST16650A(flags)) { 1956 com->st16650a = 1; 1957 com->tx_fifo_size = 32; 1958 printf(" ST16650A"); 1959 } else { 1960 com->tx_fifo_size = COM_FIFOSIZE(flags); 1961 printf(" 16550A"); 1962 } 1963#endif 1964 } 1965#ifdef PC98 1966 if (com->pc98_if_type == COM_IF_RSA98III) { 1967 com->tx_fifo_size = 2048; 1968 com->rsabase = iobase; 1969 outb(com->rsabase + rsa_ier, 0x00); 1970 outb(com->rsabase + rsa_frr, 0x00); 1971 } 1972#endif 1973 1974#ifdef COM_ESP 1975#ifdef PC98 1976 if (com->pc98_if_type == COM_IF_ESP98) 1977#endif 1978 for (espp = likely_esp_ports; *espp != 0; espp++) 1979 if (espattach(com, *espp)) { 1980 com->tx_fifo_size = 1024; 1981 break; 1982 } 1983#endif 1984 if (!com->st16650a) { 1985 if (!com->tx_fifo_size) 1986 com->tx_fifo_size = 16; 1987 else 1988 printf(" lookalike with %d bytes FIFO", 1989 com->tx_fifo_size); 1990 } 1991 1992 break; 1993 } 1994 1995#ifdef PC98 1996 if (com->pc98_if_type == COM_IF_RSB3000) { 1997 /* Set RSB-2000/3000 Extended Buffer mode. */ 1998 u_char lcr; 1999 lcr = sio_getreg(com, com_cfcr); 2000 sio_setreg(com, com_cfcr, lcr | CFCR_DLAB); 2001 sio_setreg(com, com_emr, EMR_EXBUFF | EMR_EFMODE); 2002 sio_setreg(com, com_cfcr, lcr); 2003 } 2004#endif 2005 2006#ifdef COM_ESP 2007 if (com->esp) { 2008 /* 2009 * Set 16550 compatibility mode. 2010 * We don't use the ESP_MODE_SCALE bit to increase the 2011 * fifo trigger levels because we can't handle large 2012 * bursts of input. 2013 * XXX flow control should be set in comparam(), not here. 2014 */ 2015#ifdef PC98 2016 outb(com->esp_port + ESP98_CMD1, ESP_SETMODE); 2017 outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 2018#else 2019 outb(com->esp_port + ESP_CMD1, ESP_SETMODE); 2020 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 2021#endif 2022 2023 /* Set RTS/CTS flow control. */ 2024#ifdef PC98 2025 outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE); 2026 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS); 2027 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS); 2028#else 2029 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE); 2030 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS); 2031 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS); 2032#endif 2033 2034 /* Set flow-control levels. */ 2035#ifdef PC98 2036 outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW); 2037 outb(com->esp_port + ESP98_CMD2, HIBYTE(768)); 2038 outb(com->esp_port + ESP98_CMD2, LOBYTE(768)); 2039 outb(com->esp_port + ESP98_CMD2, HIBYTE(512)); 2040 outb(com->esp_port + ESP98_CMD2, LOBYTE(512)); 2041#else 2042 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW); 2043 outb(com->esp_port + ESP_CMD2, HIBYTE(768)); 2044 outb(com->esp_port + ESP_CMD2, LOBYTE(768)); 2045 outb(com->esp_port + ESP_CMD2, HIBYTE(512)); 2046 outb(com->esp_port + ESP_CMD2, LOBYTE(512)); 2047#endif 2048 2049#ifdef PC98 2050 /* Set UART clock prescaler. */ 2051 outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK); 2052 outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */ 2053#endif 2054 } 2055#endif /* COM_ESP */ 2056 sio_setreg(com, com_fifo, 0); 2057#ifdef PC98 2058 printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name); 2059#else 2060determined_type: ; 2061#endif 2062 2063#ifdef COM_MULTIPORT 2064 if (COM_ISMULTIPORT(flags)) { 2065 device_t masterdev; 2066 2067 com->multiport = TRUE; 2068 printf(" (multiport"); 2069 if (unit == COM_MPMASTER(flags)) 2070 printf(" master"); 2071 printf(")"); 2072 masterdev = devclass_get_device(sio_devclass, 2073 COM_MPMASTER(flags)); 2074 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev, 2075 SYS_RES_IRQ, 0, NULL, NULL) != 0); 2076 } 2077#endif /* COM_MULTIPORT */ 2078#ifdef PC98 2079 } 2080#endif 2081 if (unit == comconsole) 2082 printf(", console"); 2083 if (COM_IIR_TXRDYBUG(flags)) 2084 printf(" with a bogus IIR_TXRDY register"); 2085 printf("\n"); 2086 2087 if (sio_fast_ih == NULL) { 2088 sio_fast_ih = sinthand_add("tty:sio", &tty_ithd, siopoll, 2089 NULL, SWI_TTY, 0); 2090 sio_slow_ih = sinthand_add("tty:sio", &clk_ithd, siopoll, 2091 NULL, SWI_TTY, 0); 2092 } 2093 make_dev(&sio_cdevsw, unit, 2094 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit); 2095 make_dev(&sio_cdevsw, unit | CONTROL_INIT_STATE, 2096 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit); 2097 make_dev(&sio_cdevsw, unit | CONTROL_LOCK_STATE, 2098 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit); 2099 make_dev(&sio_cdevsw, unit | CALLOUT_MASK, 2100 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit); 2101 make_dev(&sio_cdevsw, unit | CALLOUT_MASK | CONTROL_INIT_STATE, 2102 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit); 2103 make_dev(&sio_cdevsw, unit | CALLOUT_MASK | CONTROL_LOCK_STATE, 2104 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit); 2105 com->flags = flags; 2106 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 2107 pps_init(&com->pps); 2108 2109 rid = 0; 2110 com->irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1, 2111 RF_ACTIVE); 2112 if (com->irqres) { 2113 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres, 2114 INTR_TYPE_TTY | INTR_FAST, 2115 siointr, com, &com->cookie); 2116 if (ret) { 2117 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, 2118 com->irqres, INTR_TYPE_TTY, 2119 siointr, com, &com->cookie); 2120 if (ret == 0) 2121 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode"); 2122 } 2123 if (ret) 2124 device_printf(dev, "could not activate interrupt\n"); 2125 } 2126 2127 return (0); 2128} 2129 2130static int 2131sioopen(dev, flag, mode, p) 2132 dev_t dev; 2133 int flag; 2134 int mode; 2135 struct proc *p; 2136{ 2137 struct com_s *com; 2138 int error; 2139 int mynor; 2140 int s; 2141 struct tty *tp; 2142 int unit; 2143 2144 mynor = minor(dev); 2145 unit = MINOR_TO_UNIT(mynor); 2146 com = com_addr(unit); 2147 if (com == NULL) 2148 return (ENXIO); 2149 if (com->gone) 2150 return (ENXIO); 2151 if (mynor & CONTROL_MASK) 2152 return (0); 2153 tp = dev->si_tty = com->tp = ttymalloc(com->tp); 2154 s = spltty(); 2155 /* 2156 * We jump to this label after all non-interrupted sleeps to pick 2157 * up any changes of the device state. 2158 */ 2159open_top: 2160 while (com->state & CS_DTR_OFF) { 2161 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0); 2162 if (com_addr(unit) == NULL) 2163 return (ENXIO); 2164 if (error != 0 || com->gone) 2165 goto out; 2166 } 2167 if (tp->t_state & TS_ISOPEN) { 2168 /* 2169 * The device is open, so everything has been initialized. 2170 * Handle conflicts. 2171 */ 2172 if (mynor & CALLOUT_MASK) { 2173 if (!com->active_out) { 2174 error = EBUSY; 2175 goto out; 2176 } 2177 } else { 2178 if (com->active_out) { 2179 if (flag & O_NONBLOCK) { 2180 error = EBUSY; 2181 goto out; 2182 } 2183 error = tsleep(&com->active_out, 2184 TTIPRI | PCATCH, "siobi", 0); 2185 if (com_addr(unit) == NULL) 2186 return (ENXIO); 2187 if (error != 0 || com->gone) 2188 goto out; 2189 goto open_top; 2190 } 2191 } 2192 if (tp->t_state & TS_XCLUDE && 2193 suser(p)) { 2194 error = EBUSY; 2195 goto out; 2196 } 2197 } else { 2198 int intrsave; 2199 2200 /* 2201 * The device isn't open, so there are no conflicts. 2202 * Initialize it. Initialization is done twice in many 2203 * cases: to preempt sleeping callin opens if we are 2204 * callout, and to complete a callin open after DCD rises. 2205 */ 2206 tp->t_oproc = comstart; 2207 tp->t_param = comparam; 2208 tp->t_stop = comstop; 2209 tp->t_dev = dev; 2210 tp->t_termios = mynor & CALLOUT_MASK 2211 ? com->it_out : com->it_in; 2212#ifdef PC98 2213 if (!IS_8251(com->pc98_if_type)) 2214#endif 2215 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET); 2216 com->poll = com->no_irq; 2217 com->poll_output = com->loses_outints; 2218 ++com->wopeners; 2219 error = comparam(tp, &tp->t_termios); 2220 --com->wopeners; 2221 if (error != 0) 2222 goto out; 2223#ifdef PC98 2224 if (IS_8251(com->pc98_if_type)) { 2225 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS); 2226 pc98_msrint_start(dev); 2227 if (com->pc98_8251fifo) { 2228 com->pc98_8251fifo_enable = 1; 2229 outb(I8251F_fcr, CTRL8251F_ENABLE | 2230 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 2231 } 2232 } 2233#endif 2234 /* 2235 * XXX we should goto open_top if comparam() slept. 2236 */ 2237 if (com->hasfifo) { 2238 /* 2239 * (Re)enable and drain fifos. 2240 * 2241 * Certain SMC chips cause problems if the fifos 2242 * are enabled while input is ready. Turn off the 2243 * fifo if necessary to clear the input. We test 2244 * the input ready bit after enabling the fifos 2245 * since we've already enabled them in comparam() 2246 * and to handle races between enabling and fresh 2247 * input. 2248 */ 2249 while (TRUE) { 2250 sio_setreg(com, com_fifo, 2251 FIFO_RCV_RST | FIFO_XMT_RST 2252 | com->fifo_image); 2253#ifdef PC98 2254 if (com->pc98_if_type == COM_IF_RSA98III) 2255 outb(com->rsabase + rsa_frr , 0x00); 2256#endif 2257 /* 2258 * XXX the delays are for superstitious 2259 * historical reasons. It must be less than 2260 * the character time at the maximum 2261 * supported speed (87 usec at 115200 bps 2262 * 8N1). Otherwise we might loop endlessly 2263 * if data is streaming in. We used to use 2264 * delays of 100. That usually worked 2265 * because DELAY(100) used to usually delay 2266 * for about 85 usec instead of 100. 2267 */ 2268 DELAY(50); 2269#ifdef PC98 2270 if (com->pc98_if_type == COM_IF_RSA98III ? 2271 !(inb(com->rsabase + rsa_srr) & 0x08) : 2272 !(inb(com->line_status_port) & LSR_RXRDY)) 2273 break; 2274#else 2275 if (!(inb(com->line_status_port) & LSR_RXRDY)) 2276 break; 2277#endif 2278 sio_setreg(com, com_fifo, 0); 2279 DELAY(50); 2280 (void) inb(com->data_port); 2281 } 2282 } 2283 2284 intrsave = save_intr(); 2285 disable_intr(); 2286 COM_LOCK(); 2287#ifdef PC98 2288 if (IS_8251(com->pc98_if_type)) { 2289 com_tiocm_bis(com, TIOCM_LE); 2290 com->pc98_prev_modem_status = pc98_get_modem_status(com); 2291 com_int_Rx_enable(com); 2292 } else { 2293#endif 2294 (void) inb(com->line_status_port); 2295 (void) inb(com->data_port); 2296 com->prev_modem_status = com->last_modem_status 2297 = inb(com->modem_status_port); 2298 if (COM_IIR_TXRDYBUG(com->flags)) { 2299 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS 2300 | IER_EMSC); 2301 } else { 2302 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY 2303 | IER_ERLS | IER_EMSC); 2304 } 2305#ifdef PC98 2306 if (com->pc98_if_type == COM_IF_RSA98III) { 2307 outb(com->rsabase + rsa_ier, 0x1d); 2308 outb(com->intr_ctl_port, IER_ERLS | IER_EMSC); 2309 } 2310#endif 2311#ifdef PC98 2312 } 2313#endif 2314 COM_UNLOCK(); 2315 restore_intr(intrsave); 2316 /* 2317 * Handle initial DCD. Callout devices get a fake initial 2318 * DCD (trapdoor DCD). If we are callout, then any sleeping 2319 * callin opens get woken up and resume sleeping on "siobi" 2320 * instead of "siodcd". 2321 */ 2322 /* 2323 * XXX `mynor & CALLOUT_MASK' should be 2324 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where 2325 * TRAPDOOR_CARRIER is the default initial state for callout 2326 * devices and SOFT_CARRIER is like CLOCAL except it hides 2327 * the true carrier. 2328 */ 2329#ifdef PC98 2330 if ((IS_8251(com->pc98_if_type) && 2331 (pc98_get_modem_status(com) & TIOCM_CAR)) || 2332 (!IS_8251(com->pc98_if_type) && 2333 (com->prev_modem_status & MSR_DCD)) || 2334 mynor & CALLOUT_MASK) 2335 (*linesw[tp->t_line].l_modem)(tp, 1); 2336#else 2337 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK) 2338 (*linesw[tp->t_line].l_modem)(tp, 1); 2339#endif 2340 } 2341 /* 2342 * Wait for DCD if necessary. 2343 */ 2344 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK) 2345 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 2346 ++com->wopeners; 2347 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0); 2348 if (com_addr(unit) == NULL) 2349 return (ENXIO); 2350 --com->wopeners; 2351 if (error != 0 || com->gone) 2352 goto out; 2353 goto open_top; 2354 } 2355 error = (*linesw[tp->t_line].l_open)(dev, tp); 2356 disc_optim(tp, &tp->t_termios, com); 2357 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK) 2358 com->active_out = TRUE; 2359 siosettimeout(); 2360out: 2361 splx(s); 2362 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0) 2363 comhardclose(com); 2364 return (error); 2365} 2366 2367static int 2368sioclose(dev, flag, mode, p) 2369 dev_t dev; 2370 int flag; 2371 int mode; 2372 struct proc *p; 2373{ 2374 struct com_s *com; 2375 int mynor; 2376 int s; 2377 struct tty *tp; 2378 2379 mynor = minor(dev); 2380 if (mynor & CONTROL_MASK) 2381 return (0); 2382 com = com_addr(MINOR_TO_UNIT(mynor)); 2383 if (com == NULL) 2384 return (ENODEV); 2385 tp = com->tp; 2386 s = spltty(); 2387 (*linesw[tp->t_line].l_close)(tp, flag); 2388#ifdef PC98 2389 com->modem_checking = 0; 2390#endif 2391 disc_optim(tp, &tp->t_termios, com); 2392 comstop(tp, FREAD | FWRITE); 2393 comhardclose(com); 2394 ttyclose(tp); 2395 siosettimeout(); 2396 splx(s); 2397 if (com->gone) { 2398 printf("sio%d: gone\n", com->unit); 2399 s = spltty(); 2400 if (com->ibuf != NULL) 2401 free(com->ibuf, M_DEVBUF); 2402 bzero(tp, sizeof *tp); 2403 splx(s); 2404 } 2405 return (0); 2406} 2407 2408static void 2409comhardclose(com) 2410 struct com_s *com; 2411{ 2412 int s; 2413 struct tty *tp; 2414 int unit; 2415 2416 unit = com->unit; 2417 s = spltty(); 2418 com->poll = FALSE; 2419 com->poll_output = FALSE; 2420 com->do_timestamp = FALSE; 2421 com->do_dcd_timestamp = FALSE; 2422 com->pps.ppsparam.mode = 0; 2423#ifdef PC98 2424 if (IS_8251(com->pc98_if_type)) 2425 com_send_break_off(com); 2426 else 2427#endif 2428 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 2429 { 2430#ifdef PC98 2431 int tmp; 2432 if (IS_8251(com->pc98_if_type)) 2433 com_int_TxRx_disable(com); 2434 else 2435 sio_setreg(com, com_ier, 0); 2436 if (com->pc98_if_type == COM_IF_RSA98III) 2437 outb(com->rsabase + rsa_ier, 0x00); 2438#else 2439 sio_setreg(com, com_ier, 0); 2440#endif 2441 tp = com->tp; 2442#ifdef PC98 2443 if (IS_8251(com->pc98_if_type)) 2444 tmp = pc98_get_modem_status(com) & TIOCM_CAR; 2445 else 2446 tmp = com->prev_modem_status & MSR_DCD; 2447#endif 2448 if (tp->t_cflag & HUPCL 2449 /* 2450 * XXX we will miss any carrier drop between here and the 2451 * next open. Perhaps we should watch DCD even when the 2452 * port is closed; it is not sufficient to check it at 2453 * the next open because it might go up and down while 2454 * we're not watching. 2455 */ 2456 || (!com->active_out 2457#ifdef PC98 2458 && !(tmp) 2459#else 2460 && !(com->prev_modem_status & MSR_DCD) 2461#endif 2462 && !(com->it_in.c_cflag & CLOCAL)) 2463 || !(tp->t_state & TS_ISOPEN)) { 2464#ifdef PC98 2465 if (IS_8251(com->pc98_if_type)) 2466 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 2467 else 2468#endif 2469 (void)commctl(com, TIOCM_DTR, DMBIC); 2470 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) { 2471 timeout(siodtrwakeup, com, com->dtr_wait); 2472 com->state |= CS_DTR_OFF; 2473 } 2474 } 2475#ifdef PC98 2476 else { 2477 if (IS_8251(com->pc98_if_type)) 2478 com_tiocm_bic(com, TIOCM_LE); 2479 } 2480#endif 2481 } 2482#ifdef PC98 2483 if (com->pc98_8251fifo) { 2484 if (com->pc98_8251fifo_enable) 2485 outb(I8251F_fcr, CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 2486 com->pc98_8251fifo_enable = 0; 2487 } 2488#endif 2489 if (com->hasfifo) { 2490 /* 2491 * Disable fifos so that they are off after controlled 2492 * reboots. Some BIOSes fail to detect 16550s when the 2493 * fifos are enabled. 2494 */ 2495 sio_setreg(com, com_fifo, 0); 2496 } 2497 com->active_out = FALSE; 2498 wakeup(&com->active_out); 2499 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */ 2500 splx(s); 2501} 2502 2503static int 2504sioread(dev, uio, flag) 2505 dev_t dev; 2506 struct uio *uio; 2507 int flag; 2508{ 2509 int mynor; 2510 struct com_s *com; 2511 2512 mynor = minor(dev); 2513 if (mynor & CONTROL_MASK) 2514 return (ENODEV); 2515 com = com_addr(MINOR_TO_UNIT(mynor)); 2516 if (com == NULL || com->gone) 2517 return (ENODEV); 2518 return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag)); 2519} 2520 2521static int 2522siowrite(dev, uio, flag) 2523 dev_t dev; 2524 struct uio *uio; 2525 int flag; 2526{ 2527 int mynor; 2528 struct com_s *com; 2529 int unit; 2530 2531 mynor = minor(dev); 2532 if (mynor & CONTROL_MASK) 2533 return (ENODEV); 2534 2535 unit = MINOR_TO_UNIT(mynor); 2536 com = com_addr(unit); 2537 if (com == NULL || com->gone) 2538 return (ENODEV); 2539 /* 2540 * (XXX) We disallow virtual consoles if the physical console is 2541 * a serial port. This is in case there is a display attached that 2542 * is not the console. In that situation we don't need/want the X 2543 * server taking over the console. 2544 */ 2545 if (constty != NULL && unit == comconsole) 2546 constty = NULL; 2547 return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag)); 2548} 2549 2550static void 2551siobusycheck(chan) 2552 void *chan; 2553{ 2554 struct com_s *com; 2555 int s; 2556 2557 com = (struct com_s *)chan; 2558 2559 /* 2560 * Clear TS_BUSY if low-level output is complete. 2561 * spl locking is sufficient because siointr1() does not set CS_BUSY. 2562 * If siointr1() clears CS_BUSY after we look at it, then we'll get 2563 * called again. Reading the line status port outside of siointr1() 2564 * is safe because CS_BUSY is clear so there are no output interrupts 2565 * to lose. 2566 */ 2567 s = spltty(); 2568 if (com->state & CS_BUSY) 2569 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */ 2570#ifdef PC98 2571 else if ((IS_8251(com->pc98_if_type) && 2572 ((com->pc98_8251fifo_enable && 2573 (inb(I8251F_lsr) & (STS8251F_TxRDY | STS8251F_TxEMP)) 2574 == (STS8251F_TxRDY | STS8251F_TxEMP)) || 2575 (!com->pc98_8251fifo_enable && 2576 (inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP)) 2577 == (STS8251_TxRDY | STS8251_TxEMP)))) || 2578 ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2579 == (LSR_TSRE | LSR_TXRDY))) { 2580#else 2581 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2582 == (LSR_TSRE | LSR_TXRDY)) { 2583#endif 2584 com->tp->t_state &= ~TS_BUSY; 2585 ttwwakeup(com->tp); 2586 com->extra_state &= ~CSE_BUSYCHECK; 2587 } else 2588 timeout(siobusycheck, com, hz / 100); 2589 splx(s); 2590} 2591 2592static void 2593siodtrwakeup(chan) 2594 void *chan; 2595{ 2596 struct com_s *com; 2597 2598 com = (struct com_s *)chan; 2599 com->state &= ~CS_DTR_OFF; 2600 wakeup(&com->dtr_wait); 2601} 2602 2603/* 2604 * Call this function with COM_LOCK. It will return with the lock still held. 2605 */ 2606static void 2607sioinput(com) 2608 struct com_s *com; 2609{ 2610 u_char *buf; 2611 int incc; 2612 u_char line_status; 2613 int recv_data; 2614 struct tty *tp; 2615 int intrsave; 2616 2617 buf = com->ibuf; 2618 tp = com->tp; 2619 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) { 2620 com_events -= (com->iptr - com->ibuf); 2621 com->iptr = com->ibuf; 2622 return; 2623 } 2624 if (tp->t_state & TS_CAN_BYPASS_L_RINT) { 2625 /* 2626 * Avoid the grotesquely inefficient lineswitch routine 2627 * (ttyinput) in "raw" mode. It usually takes about 450 2628 * instructions (that's without canonical processing or echo!). 2629 * slinput is reasonably fast (usually 40 instructions plus 2630 * call overhead). 2631 */ 2632 do { 2633 /* 2634 * This may look odd, but it is using save-and-enable 2635 * semantics instead of the save-and-disable semantics 2636 * that are used everywhere else. 2637 */ 2638 intrsave = save_intr(); 2639 COM_UNLOCK(); 2640 enable_intr(); 2641 incc = com->iptr - buf; 2642 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat 2643 && (com->state & CS_RTS_IFLOW 2644 || tp->t_iflag & IXOFF) 2645 && !(tp->t_state & TS_TBLOCK)) 2646 ttyblock(tp); 2647 com->delta_error_counts[CE_TTY_BUF_OVERFLOW] 2648 += b_to_q((char *)buf, incc, &tp->t_rawq); 2649 buf += incc; 2650 tk_nin += incc; 2651 tk_rawcc += incc; 2652 tp->t_rawcc += incc; 2653 ttwakeup(tp); 2654 if (tp->t_state & TS_TTSTOP 2655 && (tp->t_iflag & IXANY 2656 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) { 2657 tp->t_state &= ~TS_TTSTOP; 2658 tp->t_lflag &= ~FLUSHO; 2659 comstart(tp); 2660 } 2661 restore_intr(intrsave); 2662 COM_LOCK(); 2663 } while (buf < com->iptr); 2664 } else { 2665 do { 2666 /* 2667 * This may look odd, but it is using save-and-enable 2668 * semantics instead of the save-and-disable semantics 2669 * that are used everywhere else. 2670 */ 2671 intrsave = save_intr(); 2672 COM_UNLOCK(); 2673 enable_intr(); 2674 line_status = buf[com->ierroff]; 2675 recv_data = *buf++; 2676 if (line_status 2677 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) { 2678 if (line_status & LSR_BI) 2679 recv_data |= TTY_BI; 2680 if (line_status & LSR_FE) 2681 recv_data |= TTY_FE; 2682 if (line_status & LSR_OE) 2683 recv_data |= TTY_OE; 2684 if (line_status & LSR_PE) 2685 recv_data |= TTY_PE; 2686 } 2687 (*linesw[tp->t_line].l_rint)(recv_data, tp); 2688 restore_intr(intrsave); 2689 COM_LOCK(); 2690 } while (buf < com->iptr); 2691 } 2692 com_events -= (com->iptr - com->ibuf); 2693 com->iptr = com->ibuf; 2694 2695 /* 2696 * There is now room for another low-level buffer full of input, 2697 * so enable RTS if it is now disabled and there is room in the 2698 * high-level buffer. 2699 */ 2700#ifdef PC98 2701 if (IS_8251(com->pc98_if_type)) { 2702 if ((com->state & CS_RTS_IFLOW) && 2703 !(com_tiocm_get(com) & TIOCM_RTS) && 2704 !(tp->t_state & TS_TBLOCK)) 2705 com_tiocm_bis(com, TIOCM_RTS); 2706 } else { 2707 if ((com->state & CS_RTS_IFLOW) && 2708 !(com->mcr_image & MCR_RTS) && 2709 !(tp->t_state & TS_TBLOCK)) 2710 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2711 } 2712#else 2713 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) && 2714 !(tp->t_state & TS_TBLOCK)) 2715 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2716#endif 2717} 2718 2719void 2720siointr(arg) 2721 void *arg; 2722{ 2723#ifndef COM_MULTIPORT 2724 COM_LOCK(); 2725 siointr1((struct com_s *) arg); 2726 COM_UNLOCK(); 2727#else /* COM_MULTIPORT */ 2728 bool_t possibly_more_intrs; 2729 int unit; 2730 struct com_s *com; 2731#ifdef PC98 2732 u_char rsa_buf_status; 2733#endif 2734 2735 /* 2736 * Loop until there is no activity on any port. This is necessary 2737 * to get an interrupt edge more than to avoid another interrupt. 2738 * If the IRQ signal is just an OR of the IRQ signals from several 2739 * devices, then the edge from one may be lost because another is 2740 * on. 2741 */ 2742 COM_LOCK(); 2743 do { 2744 possibly_more_intrs = FALSE; 2745 for (unit = 0; unit < sio_numunits; ++unit) { 2746 com = com_addr(unit); 2747 /* 2748 * XXX COM_LOCK(); 2749 * would it work here, or be counter-productive? 2750 */ 2751#ifdef PC98 2752 if (com != NULL 2753 && !com->gone 2754 && IS_8251(com->pc98_if_type)) { 2755 siointr1(com); 2756 } else if (com != NULL 2757 && !com->gone 2758 && com->pc98_if_type == COM_IF_RSA98III) { 2759 rsa_buf_status = 2760 inb(com->rsabase + rsa_srr) & 0xc9; 2761 if ((rsa_buf_status & 0xc8) 2762 || !(rsa_buf_status & 0x01)) { 2763 siointr1(com); 2764 if (rsa_buf_status != 2765 (inb(com->rsabase + rsa_srr) & 0xc9)) 2766 possibly_more_intrs = TRUE; 2767 } 2768 } else 2769#endif 2770 if (com != NULL 2771 && !com->gone 2772 && (inb(com->int_id_port) & IIR_IMASK) 2773 != IIR_NOPEND) { 2774 siointr1(com); 2775 possibly_more_intrs = TRUE; 2776 } 2777 /* XXX COM_UNLOCK(); */ 2778 } 2779 } while (possibly_more_intrs); 2780 COM_UNLOCK(); 2781#endif /* COM_MULTIPORT */ 2782} 2783 2784static void 2785siointr1(com) 2786 struct com_s *com; 2787{ 2788 u_char line_status; 2789 u_char modem_status; 2790 u_char *ioptr; 2791 u_char recv_data; 2792 u_char int_ctl; 2793 u_char int_ctl_new; 2794 struct timecounter *tc; 2795 u_int count; 2796 2797#ifdef PC98 2798 u_char tmp = 0; 2799 u_char rsa_buf_status = 0; 2800 int rsa_tx_fifo_size = 0; 2801#endif /* PC98 */ 2802 2803 int_ctl = inb(com->intr_ctl_port); 2804 int_ctl_new = int_ctl; 2805 2806 while (!com->gone) { 2807#ifdef PC98 2808status_read:; 2809 if (IS_8251(com->pc98_if_type)) { 2810 if (com->pc98_8251fifo_enable) 2811 tmp = inb(I8251F_lsr); 2812 else 2813 tmp = inb(com->sts_port); 2814more_intr: 2815 line_status = 0; 2816 if (com->pc98_8251fifo_enable) { 2817 if (tmp & STS8251F_TxRDY) line_status |= LSR_TXRDY; 2818 if (tmp & STS8251F_RxRDY) line_status |= LSR_RXRDY; 2819 if (tmp & STS8251F_TxEMP) line_status |= LSR_TSRE; 2820 if (tmp & STS8251F_PE) line_status |= LSR_PE; 2821 if (tmp & STS8251F_OE) line_status |= LSR_OE; 2822 if (tmp & STS8251F_BD_SD) line_status |= LSR_BI; 2823 } else { 2824 if (tmp & STS8251_TxRDY) line_status |= LSR_TXRDY; 2825 if (tmp & STS8251_RxRDY) line_status |= LSR_RXRDY; 2826 if (tmp & STS8251_TxEMP) line_status |= LSR_TSRE; 2827 if (tmp & STS8251_PE) line_status |= LSR_PE; 2828 if (tmp & STS8251_OE) line_status |= LSR_OE; 2829 if (tmp & STS8251_FE) line_status |= LSR_FE; 2830 if (tmp & STS8251_BD_SD) line_status |= LSR_BI; 2831 } 2832 } else { 2833#endif /* PC98 */ 2834 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) { 2835 modem_status = inb(com->modem_status_port); 2836 if ((modem_status ^ com->last_modem_status) & MSR_DCD) { 2837 tc = timecounter; 2838 count = tc->tc_get_timecount(tc); 2839 pps_event(&com->pps, tc, count, 2840 (modem_status & MSR_DCD) ? 2841 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR); 2842 } 2843 } 2844 line_status = inb(com->line_status_port); 2845#ifdef PC98 2846 } 2847 if (com->pc98_if_type == COM_IF_RSA98III) 2848 rsa_buf_status = inb(com->rsabase + rsa_srr); 2849#endif /* PC98 */ 2850 2851 /* input event? (check first to help avoid overruns) */ 2852#ifndef PC98 2853 while (line_status & LSR_RCV_MASK) { 2854#else 2855 while ((line_status & LSR_RCV_MASK) 2856 || (com->pc98_if_type == COM_IF_RSA98III 2857 && (rsa_buf_status & 0x08))) { 2858#endif /* PC98 */ 2859 /* break/unnattached error bits or real input? */ 2860#ifdef PC98 2861 if (IS_8251(com->pc98_if_type)) { 2862 if (com->pc98_8251fifo_enable) { 2863 recv_data = inb(I8251F_data); 2864 if (tmp & (STS8251F_PE | STS8251F_OE | 2865 STS8251F_BD_SD)) { 2866 pc98_i8251_or_cmd(com, CMD8251_ER); 2867 recv_data = 0; 2868 } 2869 } else { 2870 recv_data = inb(com->data_port); 2871 if (tmp & (STS8251_PE | STS8251_OE | 2872 STS8251_FE | STS8251_BD_SD)) { 2873 pc98_i8251_or_cmd(com, CMD8251_ER); 2874 recv_data = 0; 2875 } 2876 } 2877 } else if (com->pc98_if_type == COM_IF_RSA98III) { 2878 if (!(rsa_buf_status & 0x08)) 2879 recv_data = 0; 2880 else 2881 recv_data = inb(com->data_port); 2882 } else 2883#endif 2884 if (!(line_status & LSR_RXRDY)) 2885 recv_data = 0; 2886 else 2887 recv_data = inb(com->data_port); 2888 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) { 2889 /* 2890 * Don't store BI if IGNBRK or FE/PE if IGNPAR. 2891 * Otherwise, push the work to a higher level 2892 * (to handle PARMRK) if we're bypassing. 2893 * Otherwise, convert BI/FE and PE+INPCK to 0. 2894 * 2895 * This makes bypassing work right in the 2896 * usual "raw" case (IGNBRK set, and IGNPAR 2897 * and INPCK clear). 2898 * 2899 * Note: BI together with FE/PE means just BI. 2900 */ 2901 if (line_status & LSR_BI) { 2902#if defined(DDB) && defined(BREAK_TO_DEBUGGER) 2903 if (com->unit == comconsole) { 2904 breakpoint(); 2905 goto cont; 2906 } 2907#endif 2908 if (com->tp == NULL 2909 || com->tp->t_iflag & IGNBRK) 2910 goto cont; 2911 } else { 2912 if (com->tp == NULL 2913 || com->tp->t_iflag & IGNPAR) 2914 goto cont; 2915 } 2916 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT 2917 && (line_status & (LSR_BI | LSR_FE) 2918 || com->tp->t_iflag & INPCK)) 2919 recv_data = 0; 2920 } 2921 ++com->bytes_in; 2922 if (com->hotchar != 0 && recv_data == com->hotchar) 2923 sched_swi(sio_fast_ih, SWI_NOSWITCH); 2924 ioptr = com->iptr; 2925 if (ioptr >= com->ibufend) 2926 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW); 2927 else { 2928 if (com->do_timestamp) 2929 microtime(&com->timestamp); 2930 ++com_events; 2931/* XXX - needs to go away when alpha gets ithreads */ 2932 sched_swi(sio_slow_ih, SWI_DELAY); 2933#if 0 /* for testing input latency vs efficiency */ 2934if (com->iptr - com->ibuf == 8) 2935 sched_swi(sio_fast_ih, SWI_NOSWITCH); 2936#endif 2937 ioptr[0] = recv_data; 2938 ioptr[com->ierroff] = line_status; 2939 com->iptr = ++ioptr; 2940 if (ioptr == com->ihighwater 2941 && com->state & CS_RTS_IFLOW) 2942#ifdef PC98 2943 IS_8251(com->pc98_if_type) ? 2944 com_tiocm_bic(com, TIOCM_RTS) : 2945#endif 2946 outb(com->modem_ctl_port, 2947 com->mcr_image &= ~MCR_RTS); 2948 if (line_status & LSR_OE) 2949 CE_RECORD(com, CE_OVERRUN); 2950 } 2951cont: 2952 /* 2953 * "& 0x7F" is to avoid the gcc-1.40 generating a slow 2954 * jump from the top of the loop to here 2955 */ 2956#ifdef PC98 2957 if (IS_8251(com->pc98_if_type)) 2958 goto status_read; 2959 else 2960#endif 2961 line_status = inb(com->line_status_port) & 0x7F; 2962#ifdef PC98 2963 if (com->pc98_if_type == COM_IF_RSA98III) 2964 rsa_buf_status = inb(com->rsabase + rsa_srr); 2965#endif /* PC98 */ 2966 } 2967 2968 /* modem status change? (always check before doing output) */ 2969#ifdef PC98 2970 if (!IS_8251(com->pc98_if_type)) { 2971#endif 2972 modem_status = inb(com->modem_status_port); 2973 if (modem_status != com->last_modem_status) { 2974 if (com->do_dcd_timestamp 2975 && !(com->last_modem_status & MSR_DCD) 2976 && modem_status & MSR_DCD) 2977 microtime(&com->dcd_timestamp); 2978 2979 /* 2980 * Schedule high level to handle DCD changes. Note 2981 * that we don't use the delta bits anywhere. Some 2982 * UARTs mess them up, and it's easy to remember the 2983 * previous bits and calculate the delta. 2984 */ 2985 com->last_modem_status = modem_status; 2986 if (!(com->state & CS_CHECKMSR)) { 2987 com_events += LOTS_OF_EVENTS; 2988 com->state |= CS_CHECKMSR; 2989 sched_swi(sio_fast_ih, SWI_NOSWITCH); 2990 } 2991 2992 /* handle CTS change immediately for crisp flow ctl */ 2993 if (com->state & CS_CTS_OFLOW) { 2994 if (modem_status & MSR_CTS) 2995 com->state |= CS_ODEVREADY; 2996 else 2997 com->state &= ~CS_ODEVREADY; 2998 } 2999 } 3000#ifdef PC98 3001 } 3002#endif 3003 3004 /* output queued and everything ready? */ 3005#ifndef PC98 3006 if (line_status & LSR_TXRDY 3007 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 3008#else 3009 if (((com->pc98_if_type == COM_IF_RSA98III) 3010 ? (rsa_buf_status & 0x02) 3011 : (line_status & LSR_TXRDY)) 3012 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 3013#endif 3014#ifdef PC98 3015 Port_t tmp_data_port; 3016 3017 if (IS_8251(com->pc98_if_type) && 3018 com->pc98_8251fifo_enable) 3019 tmp_data_port = I8251F_data; 3020 else 3021 tmp_data_port = com->data_port; 3022#endif 3023 3024 ioptr = com->obufq.l_head; 3025 if (com->tx_fifo_size > 1) { 3026 u_int ocount; 3027 3028 ocount = com->obufq.l_tail - ioptr; 3029#ifdef PC98 3030 if (com->pc98_if_type == COM_IF_RSA98III) { 3031 rsa_buf_status = inb(com->rsabase + rsa_srr); 3032 rsa_tx_fifo_size = 1024; 3033 if (!(rsa_buf_status & 0x01)) 3034 rsa_tx_fifo_size = 2048; 3035 if (ocount > rsa_tx_fifo_size) 3036 ocount = rsa_tx_fifo_size; 3037 } else 3038#endif 3039 if (ocount > com->tx_fifo_size) 3040 ocount = com->tx_fifo_size; 3041 com->bytes_out += ocount; 3042 do 3043#ifdef PC98 3044 outb(tmp_data_port, *ioptr++); 3045#else 3046 outb(com->data_port, *ioptr++); 3047#endif 3048 while (--ocount != 0); 3049 } else { 3050#ifdef PC98 3051 outb(tmp_data_port, *ioptr++); 3052#else 3053 outb(com->data_port, *ioptr++); 3054#endif 3055 ++com->bytes_out; 3056 } 3057#ifdef PC98 3058 if (IS_8251(com->pc98_if_type)) 3059 if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG)) 3060 com_int_Tx_enable(com); 3061#endif 3062 com->obufq.l_head = ioptr; 3063 if (COM_IIR_TXRDYBUG(com->flags)) { 3064 int_ctl_new = int_ctl | IER_ETXRDY; 3065 } 3066 if (ioptr >= com->obufq.l_tail) { 3067 struct lbq *qp; 3068 3069 qp = com->obufq.l_next; 3070 qp->l_queued = FALSE; 3071 qp = qp->l_next; 3072 if (qp != NULL) { 3073 com->obufq.l_head = qp->l_head; 3074 com->obufq.l_tail = qp->l_tail; 3075 com->obufq.l_next = qp; 3076 } else { 3077 /* output just completed */ 3078 if (COM_IIR_TXRDYBUG(com->flags)) { 3079 int_ctl_new = int_ctl & ~IER_ETXRDY; 3080 } 3081 com->state &= ~CS_BUSY; 3082#if defined(PC98) 3083 if (IS_8251(com->pc98_if_type) && 3084 pc98_check_i8251_interrupt(com) & IEN_TxFLAG) 3085 com_int_Tx_disable(com); 3086#endif 3087 } 3088 if (!(com->state & CS_ODONE)) { 3089 com_events += LOTS_OF_EVENTS; 3090 com->state |= CS_ODONE; 3091 /* handle at high level ASAP */ 3092 sched_swi(sio_fast_ih, SWI_NOSWITCH); 3093 } 3094 } 3095 if (COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) { 3096#ifdef PC98 3097 if (com->pc98_if_type == COM_IF_RSA98III) { 3098 int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY); 3099 outb(com->intr_ctl_port, int_ctl_new); 3100 outb(com->rsabase + rsa_ier, 0x1d); 3101 } else 3102#endif 3103 outb(com->intr_ctl_port, int_ctl_new); 3104 } 3105 } 3106#ifdef PC98 3107 else if (line_status & LSR_TXRDY) { 3108 if (IS_8251(com->pc98_if_type)) 3109 if (pc98_check_i8251_interrupt(com) & IEN_TxFLAG) 3110 com_int_Tx_disable(com); 3111 } 3112 if (IS_8251(com->pc98_if_type)) { 3113 if (com->pc98_8251fifo_enable) { 3114 if ((tmp = inb(I8251F_lsr)) & STS8251F_RxRDY) 3115 goto more_intr; 3116 } else { 3117 if ((tmp = inb(com->sts_port)) & STS8251_RxRDY) 3118 goto more_intr; 3119 } 3120 } 3121#endif 3122 3123 /* finished? */ 3124#ifndef COM_MULTIPORT 3125#ifdef PC98 3126 if (IS_8251(com->pc98_if_type)) 3127 return; 3128#endif 3129 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND) 3130#endif /* COM_MULTIPORT */ 3131 return; 3132 } 3133} 3134 3135static int 3136sioioctl(dev, cmd, data, flag, p) 3137 dev_t dev; 3138 u_long cmd; 3139 caddr_t data; 3140 int flag; 3141 struct proc *p; 3142{ 3143 struct com_s *com; 3144 int error; 3145 int mynor; 3146 int s; 3147 struct tty *tp; 3148#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 3149 u_long oldcmd; 3150 struct termios term; 3151#endif 3152 3153 mynor = minor(dev); 3154 com = com_addr(MINOR_TO_UNIT(mynor)); 3155 if (com == NULL || com->gone) 3156 return (ENODEV); 3157 if (mynor & CONTROL_MASK) { 3158 struct termios *ct; 3159 3160 switch (mynor & CONTROL_MASK) { 3161 case CONTROL_INIT_STATE: 3162 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in; 3163 break; 3164 case CONTROL_LOCK_STATE: 3165 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in; 3166 break; 3167 default: 3168 return (ENODEV); /* /dev/nodev */ 3169 } 3170 switch (cmd) { 3171 case TIOCSETA: 3172 error = suser(p); 3173 if (error != 0) 3174 return (error); 3175 *ct = *(struct termios *)data; 3176 return (0); 3177 case TIOCGETA: 3178 *(struct termios *)data = *ct; 3179 return (0); 3180 case TIOCGETD: 3181 *(int *)data = TTYDISC; 3182 return (0); 3183 case TIOCGWINSZ: 3184 bzero(data, sizeof(struct winsize)); 3185 return (0); 3186 default: 3187 return (ENOTTY); 3188 } 3189 } 3190 tp = com->tp; 3191#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 3192 term = tp->t_termios; 3193 oldcmd = cmd; 3194 error = ttsetcompat(tp, &cmd, data, &term); 3195 if (error != 0) 3196 return (error); 3197 if (cmd != oldcmd) 3198 data = (caddr_t)&term; 3199#endif 3200 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) { 3201 int cc; 3202 struct termios *dt = (struct termios *)data; 3203 struct termios *lt = mynor & CALLOUT_MASK 3204 ? &com->lt_out : &com->lt_in; 3205 3206 dt->c_iflag = (tp->t_iflag & lt->c_iflag) 3207 | (dt->c_iflag & ~lt->c_iflag); 3208 dt->c_oflag = (tp->t_oflag & lt->c_oflag) 3209 | (dt->c_oflag & ~lt->c_oflag); 3210 dt->c_cflag = (tp->t_cflag & lt->c_cflag) 3211 | (dt->c_cflag & ~lt->c_cflag); 3212 dt->c_lflag = (tp->t_lflag & lt->c_lflag) 3213 | (dt->c_lflag & ~lt->c_lflag); 3214 for (cc = 0; cc < NCCS; ++cc) 3215 if (lt->c_cc[cc] != 0) 3216 dt->c_cc[cc] = tp->t_cc[cc]; 3217 if (lt->c_ispeed != 0) 3218 dt->c_ispeed = tp->t_ispeed; 3219 if (lt->c_ospeed != 0) 3220 dt->c_ospeed = tp->t_ospeed; 3221 } 3222 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 3223 if (error != ENOIOCTL) 3224 return (error); 3225 s = spltty(); 3226 error = ttioctl(tp, cmd, data, flag); 3227 disc_optim(tp, &tp->t_termios, com); 3228 if (error != ENOIOCTL) { 3229 splx(s); 3230 return (error); 3231 } 3232#ifdef PC98 3233 if (IS_8251(com->pc98_if_type)) { 3234 switch (cmd) { 3235 case TIOCSBRK: 3236 com_send_break_on(com); 3237 break; 3238 case TIOCCBRK: 3239 com_send_break_off(com); 3240 break; 3241 case TIOCSDTR: 3242 com_tiocm_bis(com, TIOCM_DTR | TIOCM_RTS); 3243 break; 3244 case TIOCCDTR: 3245 com_tiocm_bic(com, TIOCM_DTR); 3246 break; 3247 /* 3248 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 3249 * changes get undone on the next call to comparam(). 3250 */ 3251 case TIOCMSET: 3252 com_tiocm_set(com, *(int *)data); 3253 break; 3254 case TIOCMBIS: 3255 com_tiocm_bis(com, *(int *)data); 3256 break; 3257 case TIOCMBIC: 3258 com_tiocm_bic(com, *(int *)data); 3259 break; 3260 case TIOCMGET: 3261 *(int *)data = com_tiocm_get(com); 3262 break; 3263 case TIOCMSDTRWAIT: 3264 /* must be root since the wait applies to following logins */ 3265 error = suser(p); 3266 if (error != 0) { 3267 splx(s); 3268 return (error); 3269 } 3270 com->dtr_wait = *(int *)data * hz / 100; 3271 break; 3272 case TIOCMGDTRWAIT: 3273 *(int *)data = com->dtr_wait * 100 / hz; 3274 break; 3275 case TIOCTIMESTAMP: 3276 com->do_timestamp = TRUE; 3277 *(struct timeval *)data = com->timestamp; 3278 break; 3279 case TIOCDCDTIMESTAMP: 3280 com->do_dcd_timestamp = TRUE; 3281 *(struct timeval *)data = com->dcd_timestamp; 3282 break; 3283 default: 3284 splx(s); 3285 error = pps_ioctl(cmd, data, &com->pps); 3286 if (error == ENODEV) 3287 error = ENOTTY; 3288 return (error); 3289 } 3290 } else { 3291#endif 3292 switch (cmd) { 3293 case TIOCSBRK: 3294 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK); 3295 break; 3296 case TIOCCBRK: 3297 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 3298 break; 3299 case TIOCSDTR: 3300 (void)commctl(com, TIOCM_DTR, DMBIS); 3301 break; 3302 case TIOCCDTR: 3303 (void)commctl(com, TIOCM_DTR, DMBIC); 3304 break; 3305 /* 3306 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 3307 * changes get undone on the next call to comparam(). 3308 */ 3309 case TIOCMSET: 3310 (void)commctl(com, *(int *)data, DMSET); 3311 break; 3312 case TIOCMBIS: 3313 (void)commctl(com, *(int *)data, DMBIS); 3314 break; 3315 case TIOCMBIC: 3316 (void)commctl(com, *(int *)data, DMBIC); 3317 break; 3318 case TIOCMGET: 3319 *(int *)data = commctl(com, 0, DMGET); 3320 break; 3321 case TIOCMSDTRWAIT: 3322 /* must be root since the wait applies to following logins */ 3323 error = suser(p); 3324 if (error != 0) { 3325 splx(s); 3326 return (error); 3327 } 3328 com->dtr_wait = *(int *)data * hz / 100; 3329 break; 3330 case TIOCMGDTRWAIT: 3331 *(int *)data = com->dtr_wait * 100 / hz; 3332 break; 3333 case TIOCTIMESTAMP: 3334 com->do_timestamp = TRUE; 3335 *(struct timeval *)data = com->timestamp; 3336 break; 3337 case TIOCDCDTIMESTAMP: 3338 com->do_dcd_timestamp = TRUE; 3339 *(struct timeval *)data = com->dcd_timestamp; 3340 break; 3341 default: 3342 splx(s); 3343 error = pps_ioctl(cmd, data, &com->pps); 3344 if (error == ENODEV) 3345 error = ENOTTY; 3346 return (error); 3347 } 3348#ifdef PC98 3349 } 3350#endif 3351 splx(s); 3352 return (0); 3353} 3354 3355/* software interrupt handler for SWI_TTY */ 3356static void 3357siopoll() 3358{ 3359 int unit; 3360 int intrsave; 3361 3362 if (com_events == 0) 3363 return; 3364repeat: 3365 for (unit = 0; unit < sio_numunits; ++unit) { 3366 struct com_s *com; 3367 int incc; 3368 struct tty *tp; 3369 3370 com = com_addr(unit); 3371 if (com == NULL) 3372 continue; 3373 tp = com->tp; 3374 if (tp == NULL || com->gone) { 3375 /* 3376 * Discard any events related to never-opened or 3377 * going-away devices. 3378 */ 3379 intrsave = save_intr(); 3380 disable_intr(); 3381 COM_LOCK(); 3382 incc = com->iptr - com->ibuf; 3383 com->iptr = com->ibuf; 3384 if (com->state & CS_CHECKMSR) { 3385 incc += LOTS_OF_EVENTS; 3386 com->state &= ~CS_CHECKMSR; 3387 } 3388 com_events -= incc; 3389 COM_UNLOCK(); 3390 restore_intr(intrsave); 3391 continue; 3392 } 3393 if (com->iptr != com->ibuf) { 3394 intrsave = save_intr(); 3395 disable_intr(); 3396 COM_LOCK(); 3397 sioinput(com); 3398 COM_UNLOCK(); 3399 restore_intr(intrsave); 3400 } 3401 if (com->state & CS_CHECKMSR) { 3402 u_char delta_modem_status; 3403 3404#ifdef PC98 3405 if (!IS_8251(com->pc98_if_type)) { 3406#endif 3407 intrsave = save_intr(); 3408 disable_intr(); 3409 COM_LOCK(); 3410 delta_modem_status = com->last_modem_status 3411 ^ com->prev_modem_status; 3412 com->prev_modem_status = com->last_modem_status; 3413 com_events -= LOTS_OF_EVENTS; 3414 com->state &= ~CS_CHECKMSR; 3415 COM_UNLOCK(); 3416 restore_intr(intrsave); 3417 if (delta_modem_status & MSR_DCD) 3418 (*linesw[tp->t_line].l_modem) 3419 (tp, com->prev_modem_status & MSR_DCD); 3420#ifdef PC98 3421 } 3422#endif 3423 } 3424 if (com->state & CS_ODONE) { 3425 intrsave = save_intr(); 3426 disable_intr(); 3427 COM_LOCK(); 3428 com_events -= LOTS_OF_EVENTS; 3429 com->state &= ~CS_ODONE; 3430 COM_UNLOCK(); 3431 restore_intr(intrsave); 3432 if (!(com->state & CS_BUSY) 3433 && !(com->extra_state & CSE_BUSYCHECK)) { 3434 timeout(siobusycheck, com, hz / 100); 3435 com->extra_state |= CSE_BUSYCHECK; 3436 } 3437 (*linesw[tp->t_line].l_start)(tp); 3438 } 3439 if (com_events == 0) 3440 break; 3441 } 3442 if (com_events >= LOTS_OF_EVENTS) 3443 goto repeat; 3444} 3445 3446static int 3447comparam(tp, t) 3448 struct tty *tp; 3449 struct termios *t; 3450{ 3451 u_int cfcr; 3452 int cflag; 3453 struct com_s *com; 3454 int divisor; 3455 u_char dlbh; 3456 u_char dlbl; 3457 int s; 3458 int unit; 3459 int intrsave; 3460#ifdef PC98 3461 u_char param = 0; 3462#endif 3463 3464#ifdef PC98 3465 unit = DEV_TO_UNIT(tp->t_dev); 3466 com = com_addr(unit); 3467 3468 cfcr = 0; 3469 if (IS_8251(com->pc98_if_type)) { 3470 divisor = pc98_ttspeedtab(com, t->c_ospeed); 3471 } else { 3472 /* do historical conversions */ 3473 if (t->c_ispeed == 0) 3474 t->c_ispeed = t->c_ospeed; 3475 3476 /* check requested parameters */ 3477 divisor = ttspeedtab(t->c_ospeed, 3478 if_16550a_type[com->pc98_if_type & 0x0f].speedtab); 3479 } 3480#else 3481 /* do historical conversions */ 3482 if (t->c_ispeed == 0) 3483 t->c_ispeed = t->c_ospeed; 3484 3485 /* check requested parameters */ 3486 divisor = ttspeedtab(t->c_ospeed, comspeedtab); 3487#endif 3488 if (divisor < 0 || (divisor > 0 && t->c_ispeed != t->c_ospeed)) 3489 return (EINVAL); 3490 3491#ifndef PC98 3492 /* parameters are OK, convert them to the com struct and the device */ 3493 unit = DEV_TO_UNIT(tp->t_dev); 3494 com = com_addr(unit); 3495 if (com == NULL) 3496 return (ENODEV); 3497#endif 3498 s = spltty(); 3499#ifdef PC98 3500 if (IS_8251(com->pc98_if_type)) { 3501 if (divisor == 0) 3502 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 3503 else 3504 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 3505 } else 3506#endif 3507 if (divisor == 0) 3508 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */ 3509 else 3510 (void)commctl(com, TIOCM_DTR, DMBIS); 3511 cflag = t->c_cflag; 3512#ifdef PC98 3513 if (!IS_8251(com->pc98_if_type)) { 3514#endif 3515 switch (cflag & CSIZE) { 3516 case CS5: 3517 cfcr = CFCR_5BITS; 3518 break; 3519 case CS6: 3520 cfcr = CFCR_6BITS; 3521 break; 3522 case CS7: 3523 cfcr = CFCR_7BITS; 3524 break; 3525 default: 3526 cfcr = CFCR_8BITS; 3527 break; 3528 } 3529 if (cflag & PARENB) { 3530 cfcr |= CFCR_PENAB; 3531 if (!(cflag & PARODD)) 3532 cfcr |= CFCR_PEVEN; 3533 } 3534 if (cflag & CSTOPB) 3535 cfcr |= CFCR_STOPB; 3536 3537 if (com->hasfifo && divisor != 0) { 3538 /* 3539 * Use a fifo trigger level low enough so that the input 3540 * latency from the fifo is less than about 16 msec and 3541 * the total latency is less than about 30 msec. These 3542 * latencies are reasonable for humans. Serial comms 3543 * protocols shouldn't expect anything better since modem 3544 * latencies are larger. 3545 */ 3546 com->fifo_image = t->c_ospeed <= 4800 3547 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_HIGH; 3548#ifdef COM_ESP 3549 /* 3550 * The Hayes ESP card needs the fifo DMA mode bit set 3551 * in compatibility mode. If not, it will interrupt 3552 * for each character received. 3553 */ 3554 if (com->esp) 3555 com->fifo_image |= FIFO_DMA_MODE; 3556#endif 3557 sio_setreg(com, com_fifo, com->fifo_image); 3558 } 3559#ifdef PC98 3560 } 3561#endif 3562 3563 /* 3564 * This returns with interrupts disabled so that we can complete 3565 * the speed change atomically. Keeping interrupts disabled is 3566 * especially important while com_data is hidden. 3567 */ 3568 intrsave = save_intr(); 3569 (void) siosetwater(com, t->c_ispeed); 3570 3571#ifdef PC98 3572 if (IS_8251(com->pc98_if_type)) 3573 com_cflag_and_speed_set(com, cflag, t->c_ospeed); 3574 else { 3575#endif 3576 if (divisor != 0) { 3577 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB); 3578 /* 3579 * Only set the divisor registers if they would change, 3580 * since on some 16550 incompatibles (UMC8669F), setting 3581 * them while input is arriving them loses sync until 3582 * data stops arriving. 3583 */ 3584 dlbl = divisor & 0xFF; 3585 if (sio_getreg(com, com_dlbl) != dlbl) 3586 sio_setreg(com, com_dlbl, dlbl); 3587 dlbh = (u_int) divisor >> 8; 3588 if (sio_getreg(com, com_dlbh) != dlbh) 3589 sio_setreg(com, com_dlbh, dlbh); 3590 } 3591 3592 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr); 3593#ifdef PC98 3594 } 3595#endif 3596 3597 if (!(tp->t_state & TS_TTSTOP)) 3598 com->state |= CS_TTGO; 3599 3600 if (cflag & CRTS_IFLOW) { 3601#ifndef PC98 3602 if (com->st16650a) { 3603 sio_setreg(com, com_cfcr, 0xbf); 3604 sio_setreg(com, com_fifo, 3605 sio_getreg(com, com_fifo) | 0x40); 3606 } 3607#endif 3608 com->state |= CS_RTS_IFLOW; 3609 /* 3610 * If CS_RTS_IFLOW just changed from off to on, the change 3611 * needs to be propagated to MCR_RTS. This isn't urgent, 3612 * so do it later by calling comstart() instead of repeating 3613 * a lot of code from comstart() here. 3614 */ 3615 } else if (com->state & CS_RTS_IFLOW) { 3616 com->state &= ~CS_RTS_IFLOW; 3617 /* 3618 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS 3619 * on here, since comstart() won't do it later. 3620 */ 3621#ifdef PC98 3622 if (IS_8251(com->pc98_if_type)) 3623 com_tiocm_bis(com, TIOCM_RTS); 3624 else 3625 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3626#else 3627 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3628 if (com->st16650a) { 3629 sio_setreg(com, com_cfcr, 0xbf); 3630 sio_setreg(com, com_fifo, 3631 sio_getreg(com, com_fifo) & ~0x40); 3632 } 3633#endif 3634 } 3635 3636 3637 /* 3638 * Set up state to handle output flow control. 3639 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level? 3640 * Now has 10+ msec latency, while CTS flow has 50- usec latency. 3641 */ 3642 com->state |= CS_ODEVREADY; 3643 com->state &= ~CS_CTS_OFLOW; 3644#ifdef PC98 3645 if (com->pc98_if_type == COM_IF_RSA98III) { 3646 param = inb(com->rsabase + rsa_msr); 3647 outb(com->rsabase + rsa_msr, param & 0x14); 3648 } 3649#endif 3650 if (cflag & CCTS_OFLOW) { 3651 com->state |= CS_CTS_OFLOW; 3652#ifdef PC98 3653 if (IS_8251(com->pc98_if_type)) { 3654 if (!(pc98_get_modem_status(com) & TIOCM_CTS)) 3655 com->state &= ~CS_ODEVREADY; 3656 } else { 3657 if (com->pc98_if_type == COM_IF_RSA98III) { 3658 /* Set automatic flow control mode */ 3659 outb(com->rsabase + rsa_msr, param | 0x08); 3660 } else 3661#endif 3662 if (!(com->last_modem_status & MSR_CTS)) 3663 com->state &= ~CS_ODEVREADY; 3664#ifdef PC98 3665 } 3666#else 3667 if (com->st16650a) { 3668 sio_setreg(com, com_cfcr, 0xbf); 3669 sio_setreg(com, com_fifo, 3670 sio_getreg(com, com_fifo) | 0x80); 3671 } 3672 } else { 3673 if (com->st16650a) { 3674 sio_setreg(com, com_cfcr, 0xbf); 3675 sio_setreg(com, com_fifo, 3676 sio_getreg(com, com_fifo) & ~0x80); 3677 } 3678#endif 3679 } 3680 3681#ifdef PC98 3682 if (!IS_8251(com->pc98_if_type)) 3683#endif 3684 sio_setreg(com, com_cfcr, com->cfcr_image); 3685 3686 /* XXX shouldn't call functions while intrs are disabled. */ 3687 disc_optim(tp, t, com); 3688 /* 3689 * Recover from fiddling with CS_TTGO. We used to call siointr1() 3690 * unconditionally, but that defeated the careful discarding of 3691 * stale input in sioopen(). 3692 */ 3693 if (com->state >= (CS_BUSY | CS_TTGO)) 3694 siointr1(com); 3695 3696 COM_UNLOCK(); 3697 restore_intr(intrsave); 3698 splx(s); 3699 comstart(tp); 3700 if (com->ibufold != NULL) { 3701 free(com->ibufold, M_DEVBUF); 3702 com->ibufold = NULL; 3703 } 3704 return (0); 3705} 3706 3707/* 3708 * This function must be called with interrupts enabled and the com_lock 3709 * unlocked. It will return with interrupts disabled and the com_lock locked. 3710 */ 3711static int 3712siosetwater(com, speed) 3713 struct com_s *com; 3714 speed_t speed; 3715{ 3716 int cp4ticks; 3717 u_char *ibuf; 3718 int ibufsize; 3719 struct tty *tp; 3720 3721 /* 3722 * Make the buffer size large enough to handle a softtty interrupt 3723 * latency of about 2 ticks without loss of throughput or data 3724 * (about 3 ticks if input flow control is not used or not honoured, 3725 * but a bit less for CS5-CS7 modes). 3726 */ 3727 cp4ticks = speed / 10 / hz * 4; 3728 for (ibufsize = 128; ibufsize < cp4ticks;) 3729 ibufsize <<= 1; 3730#ifdef PC98 3731 if (com->pc98_if_type == COM_IF_RSA98III) 3732 ibufsize = 2048; 3733#endif 3734 if (ibufsize == com->ibufsize) { 3735 disable_intr(); 3736 COM_LOCK(); 3737 return (0); 3738 } 3739 3740 /* 3741 * Allocate input buffer. The extra factor of 2 in the size is 3742 * to allow for an error byte for each input byte. 3743 */ 3744 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT); 3745 if (ibuf == NULL) { 3746 disable_intr(); 3747 COM_LOCK(); 3748 return (ENOMEM); 3749 } 3750 3751 /* Initialize non-critical variables. */ 3752 com->ibufold = com->ibuf; 3753 com->ibufsize = ibufsize; 3754 tp = com->tp; 3755 if (tp != NULL) { 3756 tp->t_ififosize = 2 * ibufsize; 3757 tp->t_ispeedwat = (speed_t)-1; 3758 tp->t_ospeedwat = (speed_t)-1; 3759 } 3760 3761 /* 3762 * Read current input buffer, if any. Continue with interrupts 3763 * disabled. 3764 */ 3765 disable_intr(); 3766 COM_LOCK(); 3767 if (com->iptr != com->ibuf) 3768 sioinput(com); 3769 3770 /*- 3771 * Initialize critical variables, including input buffer watermarks. 3772 * The external device is asked to stop sending when the buffer 3773 * exactly reaches high water, or when the high level requests it. 3774 * The high level is notified immediately (rather than at a later 3775 * clock tick) when this watermark is reached. 3776 * The buffer size is chosen so the watermark should almost never 3777 * be reached. 3778 * The low watermark is invisibly 0 since the buffer is always 3779 * emptied all at once. 3780 */ 3781 com->iptr = com->ibuf = ibuf; 3782 com->ibufend = ibuf + ibufsize; 3783 com->ierroff = ibufsize; 3784 com->ihighwater = ibuf + 3 * ibufsize / 4; 3785 return (0); 3786} 3787 3788static void 3789comstart(tp) 3790 struct tty *tp; 3791{ 3792 struct com_s *com; 3793 int s; 3794 int unit; 3795 int intrsave; 3796 3797 unit = DEV_TO_UNIT(tp->t_dev); 3798 com = com_addr(unit); 3799 if (com == NULL) 3800 return; 3801 s = spltty(); 3802 intrsave = save_intr(); 3803 disable_intr(); 3804 COM_LOCK(); 3805 if (tp->t_state & TS_TTSTOP) 3806 com->state &= ~CS_TTGO; 3807 else 3808 com->state |= CS_TTGO; 3809 if (tp->t_state & TS_TBLOCK) { 3810#ifdef PC98 3811 if (IS_8251(com->pc98_if_type)) { 3812 if ((com_tiocm_get(com) & TIOCM_RTS) && 3813 (com->state & CS_RTS_IFLOW)) 3814 com_tiocm_bic(com, TIOCM_RTS); 3815 } else { 3816 if ((com->mcr_image & MCR_RTS) && 3817 (com->state & CS_RTS_IFLOW)) 3818 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3819 } 3820#else 3821 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW) 3822 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3823#endif 3824 } else { 3825#ifdef PC98 3826 if (IS_8251(com->pc98_if_type)) { 3827 if (!(com_tiocm_get(com) & TIOCM_RTS) && 3828 com->iptr < com->ihighwater && 3829 com->state & CS_RTS_IFLOW) 3830 com_tiocm_bis(com, TIOCM_RTS); 3831 } else { 3832 if (!(com->mcr_image & MCR_RTS) && 3833 com->iptr < com->ihighwater && 3834 com->state & CS_RTS_IFLOW) 3835 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3836 } 3837#else 3838 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater 3839 && com->state & CS_RTS_IFLOW) 3840 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3841#endif 3842 } 3843 COM_UNLOCK(); 3844 restore_intr(intrsave); 3845 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) { 3846 ttwwakeup(tp); 3847 splx(s); 3848 return; 3849 } 3850 if (tp->t_outq.c_cc != 0) { 3851 struct lbq *qp; 3852 struct lbq *next; 3853 3854 if (!com->obufs[0].l_queued) { 3855 com->obufs[0].l_tail 3856 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1, 3857#ifdef PC98 3858 com->obufsize); 3859#else 3860 sizeof com->obuf1); 3861#endif 3862 com->obufs[0].l_next = NULL; 3863 com->obufs[0].l_queued = TRUE; 3864 intrsave = save_intr(); 3865 disable_intr(); 3866 COM_LOCK(); 3867 if (com->state & CS_BUSY) { 3868 qp = com->obufq.l_next; 3869 while ((next = qp->l_next) != NULL) 3870 qp = next; 3871 qp->l_next = &com->obufs[0]; 3872 } else { 3873 com->obufq.l_head = com->obufs[0].l_head; 3874 com->obufq.l_tail = com->obufs[0].l_tail; 3875 com->obufq.l_next = &com->obufs[0]; 3876 com->state |= CS_BUSY; 3877 } 3878 COM_UNLOCK(); 3879 restore_intr(intrsave); 3880 } 3881 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) { 3882 com->obufs[1].l_tail 3883 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2, 3884#ifdef PC98 3885 com->obufsize); 3886#else 3887 sizeof com->obuf2); 3888#endif 3889 com->obufs[1].l_next = NULL; 3890 com->obufs[1].l_queued = TRUE; 3891 intrsave = save_intr(); 3892 disable_intr(); 3893 COM_LOCK(); 3894 if (com->state & CS_BUSY) { 3895 qp = com->obufq.l_next; 3896 while ((next = qp->l_next) != NULL) 3897 qp = next; 3898 qp->l_next = &com->obufs[1]; 3899 } else { 3900 com->obufq.l_head = com->obufs[1].l_head; 3901 com->obufq.l_tail = com->obufs[1].l_tail; 3902 com->obufq.l_next = &com->obufs[1]; 3903 com->state |= CS_BUSY; 3904 } 3905 COM_UNLOCK(); 3906 restore_intr(intrsave); 3907 } 3908 tp->t_state |= TS_BUSY; 3909 } 3910 intrsave = save_intr(); 3911 disable_intr(); 3912 COM_LOCK(); 3913 if (com->state >= (CS_BUSY | CS_TTGO)) 3914 siointr1(com); /* fake interrupt to start output */ 3915 COM_UNLOCK(); 3916 restore_intr(intrsave); 3917 ttwwakeup(tp); 3918 splx(s); 3919} 3920 3921static void 3922comstop(tp, rw) 3923 struct tty *tp; 3924 int rw; 3925{ 3926 struct com_s *com; 3927 int intrsave; 3928#ifdef PC98 3929 int rsa98_tmp = 0; 3930#endif 3931 3932 com = com_addr(DEV_TO_UNIT(tp->t_dev)); 3933 if (com == NULL || com->gone) 3934 return; 3935 intrsave = save_intr(); 3936 disable_intr(); 3937 COM_LOCK(); 3938 if (rw & FWRITE) { 3939#ifdef PC98 3940 if (!IS_8251(com->pc98_if_type)) { 3941#endif 3942 if (com->hasfifo) 3943#ifdef COM_ESP 3944 /* XXX avoid h/w bug. */ 3945 if (!com->esp) 3946#endif 3947 sio_setreg(com, com_fifo, 3948 FIFO_XMT_RST | com->fifo_image); 3949#ifdef PC98 3950 if (com->pc98_if_type == COM_IF_RSA98III) 3951 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3952 sio_setreg(com, com_fifo, 3953 FIFO_XMT_RST | com->fifo_image); 3954 } 3955#endif 3956 com->obufs[0].l_queued = FALSE; 3957 com->obufs[1].l_queued = FALSE; 3958 if (com->state & CS_ODONE) 3959 com_events -= LOTS_OF_EVENTS; 3960 com->state &= ~(CS_ODONE | CS_BUSY); 3961 com->tp->t_state &= ~TS_BUSY; 3962 } 3963 if (rw & FREAD) { 3964#ifdef PC98 3965 if (!IS_8251(com->pc98_if_type)) { 3966 if (com->pc98_if_type == COM_IF_RSA98III) 3967 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3968 sio_getreg(com, com_data); 3969#endif 3970 if (com->hasfifo) 3971#ifdef COM_ESP 3972 /* XXX avoid h/w bug. */ 3973 if (!com->esp) 3974#endif 3975 sio_setreg(com, com_fifo, 3976 FIFO_RCV_RST | com->fifo_image); 3977#ifdef PC98 3978 } 3979#endif 3980 com_events -= (com->iptr - com->ibuf); 3981 com->iptr = com->ibuf; 3982 } 3983 COM_UNLOCK(); 3984 restore_intr(intrsave); 3985 comstart(tp); 3986} 3987 3988static int 3989commctl(com, bits, how) 3990 struct com_s *com; 3991 int bits; 3992 int how; 3993{ 3994 int mcr; 3995 int msr; 3996 int intrsave; 3997 3998 if (how == DMGET) { 3999 bits = TIOCM_LE; /* XXX - always enabled while open */ 4000 mcr = com->mcr_image; 4001 if (mcr & MCR_DTR) 4002 bits |= TIOCM_DTR; 4003 if (mcr & MCR_RTS) 4004 bits |= TIOCM_RTS; 4005 msr = com->prev_modem_status; 4006 if (msr & MSR_CTS) 4007 bits |= TIOCM_CTS; 4008 if (msr & MSR_DCD) 4009 bits |= TIOCM_CD; 4010 if (msr & MSR_DSR) 4011 bits |= TIOCM_DSR; 4012 /* 4013 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI 4014 * more volatile by reading the modem status a lot. Perhaps 4015 * we should latch both bits until the status is read here. 4016 */ 4017 if (msr & (MSR_RI | MSR_TERI)) 4018 bits |= TIOCM_RI; 4019 return (bits); 4020 } 4021 mcr = 0; 4022 if (bits & TIOCM_DTR) 4023 mcr |= MCR_DTR; 4024 if (bits & TIOCM_RTS) 4025 mcr |= MCR_RTS; 4026 if (com->gone) 4027 return(0); 4028 intrsave = save_intr(); 4029 disable_intr(); 4030 COM_LOCK(); 4031 switch (how) { 4032 case DMSET: 4033 outb(com->modem_ctl_port, 4034 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE)); 4035 break; 4036 case DMBIS: 4037 outb(com->modem_ctl_port, com->mcr_image |= mcr); 4038 break; 4039 case DMBIC: 4040 outb(com->modem_ctl_port, com->mcr_image &= ~mcr); 4041 break; 4042 } 4043 COM_UNLOCK(); 4044 restore_intr(intrsave); 4045 return (0); 4046} 4047 4048static void 4049siosettimeout() 4050{ 4051 struct com_s *com; 4052 bool_t someopen; 4053 int unit; 4054 4055 /* 4056 * Set our timeout period to 1 second if no polled devices are open. 4057 * Otherwise set it to max(1/200, 1/hz). 4058 * Enable timeouts iff some device is open. 4059 */ 4060 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 4061 sio_timeout = hz; 4062 someopen = FALSE; 4063 for (unit = 0; unit < sio_numunits; ++unit) { 4064 com = com_addr(unit); 4065 if (com != NULL && com->tp != NULL 4066 && com->tp->t_state & TS_ISOPEN && !com->gone) { 4067 someopen = TRUE; 4068 if (com->poll || com->poll_output) { 4069 sio_timeout = hz > 200 ? hz / 200 : 1; 4070 break; 4071 } 4072 } 4073 } 4074 if (someopen) { 4075 sio_timeouts_until_log = hz / sio_timeout; 4076 sio_timeout_handle = timeout(comwakeup, (void *)NULL, 4077 sio_timeout); 4078 } else { 4079 /* Flush error messages, if any. */ 4080 sio_timeouts_until_log = 1; 4081 comwakeup((void *)NULL); 4082 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 4083 } 4084} 4085 4086static void 4087comwakeup(chan) 4088 void *chan; 4089{ 4090 struct com_s *com; 4091 int unit; 4092 int intrsave; 4093 4094 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout); 4095 4096 /* 4097 * Recover from lost output interrupts. 4098 * Poll any lines that don't use interrupts. 4099 */ 4100 for (unit = 0; unit < sio_numunits; ++unit) { 4101 com = com_addr(unit); 4102 if (com != NULL && !com->gone 4103 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) { 4104 intrsave = save_intr(); 4105 disable_intr(); 4106 COM_LOCK(); 4107 siointr1(com); 4108 COM_UNLOCK(); 4109 restore_intr(intrsave); 4110 } 4111 } 4112 4113 /* 4114 * Check for and log errors, but not too often. 4115 */ 4116 if (--sio_timeouts_until_log > 0) 4117 return; 4118 sio_timeouts_until_log = hz / sio_timeout; 4119 for (unit = 0; unit < sio_numunits; ++unit) { 4120 int errnum; 4121 4122 com = com_addr(unit); 4123 if (com == NULL) 4124 continue; 4125 if (com->gone) 4126 continue; 4127 for (errnum = 0; errnum < CE_NTYPES; ++errnum) { 4128 u_int delta; 4129 u_long total; 4130 4131 intrsave = save_intr(); 4132 disable_intr(); 4133 COM_LOCK(); 4134 delta = com->delta_error_counts[errnum]; 4135 com->delta_error_counts[errnum] = 0; 4136 COM_UNLOCK(); 4137 restore_intr(intrsave); 4138 if (delta == 0) 4139 continue; 4140 total = com->error_counts[errnum] += delta; 4141 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n", 4142 unit, delta, error_desc[errnum], 4143 delta == 1 ? "" : "s", total); 4144 } 4145 } 4146} 4147 4148#ifdef PC98 4149/* commint is called when modem control line changes */ 4150static void 4151commint(dev_t dev) 4152{ 4153 register struct tty *tp; 4154 int stat,delta; 4155 struct com_s *com; 4156 int mynor,unit; 4157 4158 mynor = minor(dev); 4159 unit = MINOR_TO_UNIT(mynor); 4160 com = com_addr(unit); 4161 tp = com->tp; 4162 4163 stat = com_tiocm_get(com); 4164 delta = com_tiocm_get_delta(com); 4165 4166 if (com->state & CS_CTS_OFLOW) { 4167 if (stat & TIOCM_CTS) 4168 com->state |= CS_ODEVREADY; 4169 else 4170 com->state &= ~CS_ODEVREADY; 4171 } 4172 if ((delta & TIOCM_CAR) && (mynor & CALLOUT_MASK) == 0) { 4173 if (stat & TIOCM_CAR ) 4174 (void)(*linesw[tp->t_line].l_modem)(tp, 1); 4175 else if ((*linesw[tp->t_line].l_modem)(tp, 0) == 0) { 4176 /* negate DTR, RTS */ 4177 com_tiocm_bic(com, (tp->t_cflag & HUPCL) ? 4178 TIOCM_DTR|TIOCM_RTS|TIOCM_LE : TIOCM_LE ); 4179 /* disable IENABLE */ 4180 com_int_TxRx_disable( com ); 4181 } 4182 } 4183} 4184#endif 4185 4186static void 4187disc_optim(tp, t, com) 4188 struct tty *tp; 4189 struct termios *t; 4190 struct com_s *com; 4191{ 4192 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 4193 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 4194 && (!(t->c_iflag & PARMRK) 4195 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 4196 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 4197 && linesw[tp->t_line].l_rint == ttyinput) 4198 tp->t_state |= TS_CAN_BYPASS_L_RINT; 4199 else 4200 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 4201 com->hotchar = linesw[tp->t_line].l_hotchar; 4202} 4203 4204/* 4205 * Following are all routines needed for SIO to act as console 4206 */ 4207#include <sys/cons.h> 4208 4209struct siocnstate { 4210 u_char dlbl; 4211 u_char dlbh; 4212 u_char ier; 4213 u_char cfcr; 4214 u_char mcr; 4215}; 4216 4217#ifndef __alpha__ 4218static speed_t siocngetspeed __P((Port_t, struct speedtab *)); 4219#endif 4220static void siocnclose __P((struct siocnstate *sp, Port_t iobase)); 4221static void siocnopen __P((struct siocnstate *sp, Port_t iobase, int speed)); 4222static void siocntxwait __P((Port_t iobase)); 4223 4224#ifdef __alpha__ 4225int siocnattach __P((int port, int speed)); 4226int siogdbattach __P((int port, int speed)); 4227int siogdbgetc __P((void)); 4228void siogdbputc __P((int c)); 4229#else 4230static cn_probe_t siocnprobe; 4231static cn_init_t siocninit; 4232#endif 4233static cn_checkc_t siocncheckc; 4234static cn_getc_t siocngetc; 4235static cn_putc_t siocnputc; 4236 4237#ifdef __i386__ 4238CONS_DRIVER(sio, siocnprobe, siocninit, NULL, siocngetc, siocncheckc, 4239 siocnputc, NULL); 4240#endif 4241 4242/* To get the GDB related variables */ 4243#if DDB > 0 4244#include <ddb/ddb.h> 4245#endif 4246 4247static void 4248siocntxwait(iobase) 4249 Port_t iobase; 4250{ 4251 int timo; 4252 4253 /* 4254 * Wait for any pending transmission to finish. Required to avoid 4255 * the UART lockup bug when the speed is changed, and for normal 4256 * transmits. 4257 */ 4258 timo = 100000; 4259 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY)) 4260 != (LSR_TSRE | LSR_TXRDY) && --timo != 0) 4261 ; 4262} 4263 4264#ifndef __alpha__ 4265 4266/* 4267 * Read the serial port specified and try to figure out what speed 4268 * it's currently running at. We're assuming the serial port has 4269 * been initialized and is basicly idle. This routine is only intended 4270 * to be run at system startup. 4271 * 4272 * If the value read from the serial port doesn't make sense, return 0. 4273 */ 4274 4275static speed_t 4276siocngetspeed(iobase, table) 4277 Port_t iobase; 4278 struct speedtab *table; 4279{ 4280 int code; 4281 u_char dlbh; 4282 u_char dlbl; 4283 u_char cfcr; 4284 4285 cfcr = inb(iobase + com_cfcr); 4286 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 4287 4288 dlbl = inb(iobase + com_dlbl); 4289 dlbh = inb(iobase + com_dlbh); 4290 4291 outb(iobase + com_cfcr, cfcr); 4292 4293 code = dlbh << 8 | dlbl; 4294 4295 for (; table->sp_speed != -1; table++) 4296 if (table->sp_code == code) 4297 return (table->sp_speed); 4298 4299 return (0); /* didn't match anything sane */ 4300} 4301 4302#endif 4303 4304static void 4305siocnopen(sp, iobase, speed) 4306 struct siocnstate *sp; 4307 Port_t iobase; 4308 int speed; 4309{ 4310 int divisor; 4311 u_char dlbh; 4312 u_char dlbl; 4313 4314 /* 4315 * Save all the device control registers except the fifo register 4316 * and set our default ones (cs8 -parenb speed=comdefaultrate). 4317 * We can't save the fifo register since it is read-only. 4318 */ 4319 sp->ier = inb(iobase + com_ier); 4320 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */ 4321 siocntxwait(iobase); 4322 sp->cfcr = inb(iobase + com_cfcr); 4323 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 4324 sp->dlbl = inb(iobase + com_dlbl); 4325 sp->dlbh = inb(iobase + com_dlbh); 4326 /* 4327 * Only set the divisor registers if they would change, since on 4328 * some 16550 incompatibles (Startech), setting them clears the 4329 * data input register. This also reduces the effects of the 4330 * UMC8669F bug. 4331 */ 4332 divisor = ttspeedtab(speed, comspeedtab); 4333 dlbl = divisor & 0xFF; 4334 if (sp->dlbl != dlbl) 4335 outb(iobase + com_dlbl, dlbl); 4336 dlbh = (u_int) divisor >> 8; 4337 if (sp->dlbh != dlbh) 4338 outb(iobase + com_dlbh, dlbh); 4339 outb(iobase + com_cfcr, CFCR_8BITS); 4340 sp->mcr = inb(iobase + com_mcr); 4341 /* 4342 * We don't want interrupts, but must be careful not to "disable" 4343 * them by clearing the MCR_IENABLE bit, since that might cause 4344 * an interrupt by floating the IRQ line. 4345 */ 4346 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS); 4347} 4348 4349static void 4350siocnclose(sp, iobase) 4351 struct siocnstate *sp; 4352 Port_t iobase; 4353{ 4354 /* 4355 * Restore the device control registers. 4356 */ 4357 siocntxwait(iobase); 4358 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 4359 if (sp->dlbl != inb(iobase + com_dlbl)) 4360 outb(iobase + com_dlbl, sp->dlbl); 4361 if (sp->dlbh != inb(iobase + com_dlbh)) 4362 outb(iobase + com_dlbh, sp->dlbh); 4363 outb(iobase + com_cfcr, sp->cfcr); 4364 /* 4365 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them. 4366 */ 4367 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS); 4368 outb(iobase + com_ier, sp->ier); 4369} 4370 4371#ifndef __alpha__ 4372 4373static void 4374siocnprobe(cp) 4375 struct consdev *cp; 4376{ 4377 speed_t boot_speed; 4378 u_char cfcr; 4379 int s, unit; 4380 struct siocnstate sp; 4381 4382 /* 4383 * Find our first enabled console, if any. If it is a high-level 4384 * console device, then initialize it and return successfully. 4385 * If it is a low-level console device, then initialize it and 4386 * return unsuccessfully. It must be initialized in both cases 4387 * for early use by console drivers and debuggers. Initializing 4388 * the hardware is not necessary in all cases, since the i/o 4389 * routines initialize it on the fly, but it is necessary if 4390 * input might arrive while the hardware is switched back to an 4391 * uninitialized state. We can't handle multiple console devices 4392 * yet because our low-level routines don't take a device arg. 4393 * We trust the user to set the console flags properly so that we 4394 * don't need to probe. 4395 */ 4396 cp->cn_pri = CN_DEAD; 4397 4398 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */ 4399 int flags; 4400 int disabled; 4401 if (resource_int_value("sio", unit, "disabled", &disabled) == 0) { 4402 if (disabled) 4403 continue; 4404 } 4405 if (resource_int_value("sio", unit, "flags", &flags)) 4406 continue; 4407 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) { 4408 int port; 4409 Port_t iobase; 4410 4411 if (resource_int_value("sio", unit, "port", &port)) 4412 continue; 4413 iobase = port; 4414 s = spltty(); 4415 if (boothowto & RB_SERIAL) { 4416 boot_speed = siocngetspeed(iobase, comspeedtab); 4417 if (boot_speed) 4418 comdefaultrate = boot_speed; 4419 } 4420 4421 /* 4422 * Initialize the divisor latch. We can't rely on 4423 * siocnopen() to do this the first time, since it 4424 * avoids writing to the latch if the latch appears 4425 * to have the correct value. Also, if we didn't 4426 * just read the speed from the hardware, then we 4427 * need to set the speed in hardware so that 4428 * switching it later is null. 4429 */ 4430 cfcr = inb(iobase + com_cfcr); 4431 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 4432 outb(iobase + com_dlbl, 4433 COMBRD(comdefaultrate) & 0xff); 4434 outb(iobase + com_dlbh, 4435 (u_int) COMBRD(comdefaultrate) >> 8); 4436 outb(iobase + com_cfcr, cfcr); 4437 4438 siocnopen(&sp, iobase, comdefaultrate); 4439 4440 splx(s); 4441 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) { 4442 cp->cn_dev = makedev(CDEV_MAJOR, unit); 4443 cp->cn_pri = COM_FORCECONSOLE(flags) 4444 || boothowto & RB_SERIAL 4445 ? CN_REMOTE : CN_NORMAL; 4446 siocniobase = iobase; 4447 siocnunit = unit; 4448 } 4449 if (COM_DEBUGGER(flags)) { 4450 printf("sio%d: gdb debugging port\n", unit); 4451 siogdbiobase = iobase; 4452 siogdbunit = unit; 4453#if DDB > 0 4454 gdbdev = makedev(CDEV_MAJOR, unit); 4455 gdb_getc = siocngetc; 4456 gdb_putc = siocnputc; 4457#endif 4458 } 4459 } 4460 } 4461#ifdef __i386__ 4462#if DDB > 0 4463 /* 4464 * XXX Ugly Compatability. 4465 * If no gdb port has been specified, set it to be the console 4466 * as some configuration files don't specify the gdb port. 4467 */ 4468 if (gdbdev == NODEV && (boothowto & RB_GDB)) { 4469 printf("Warning: no GDB port specified. Defaulting to sio%d.\n", 4470 siocnunit); 4471 printf("Set flag 0x80 on desired GDB port in your\n"); 4472 printf("configuration file (currently sio only).\n"); 4473 siogdbiobase = siocniobase; 4474 siogdbunit = siocnunit; 4475 gdbdev = makedev(CDEV_MAJOR, siocnunit); 4476 gdb_getc = siocngetc; 4477 gdb_putc = siocnputc; 4478 } 4479#endif 4480#endif 4481} 4482 4483static void 4484siocninit(cp) 4485 struct consdev *cp; 4486{ 4487 comconsole = DEV_TO_UNIT(cp->cn_dev); 4488} 4489 4490#endif 4491 4492#ifdef __alpha__ 4493 4494CONS_DRIVER(sio, NULL, NULL, NULL, siocngetc, siocncheckc, siocnputc, NULL); 4495 4496int 4497siocnattach(port, speed) 4498 int port; 4499 int speed; 4500{ 4501 int s; 4502 u_char cfcr; 4503 struct siocnstate sp; 4504 4505 siocniobase = port; 4506 comdefaultrate = speed; 4507 sio_consdev.cn_pri = CN_NORMAL; 4508 sio_consdev.cn_dev = makedev(CDEV_MAJOR, 0); 4509 4510 s = spltty(); 4511 4512 /* 4513 * Initialize the divisor latch. We can't rely on 4514 * siocnopen() to do this the first time, since it 4515 * avoids writing to the latch if the latch appears 4516 * to have the correct value. Also, if we didn't 4517 * just read the speed from the hardware, then we 4518 * need to set the speed in hardware so that 4519 * switching it later is null. 4520 */ 4521 cfcr = inb(siocniobase + com_cfcr); 4522 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr); 4523 outb(siocniobase + com_dlbl, 4524 COMBRD(comdefaultrate) & 0xff); 4525 outb(siocniobase + com_dlbh, 4526 (u_int) COMBRD(comdefaultrate) >> 8); 4527 outb(siocniobase + com_cfcr, cfcr); 4528 4529 siocnopen(&sp, siocniobase, comdefaultrate); 4530 splx(s); 4531 4532 cn_tab = &sio_consdev; 4533 return (0); 4534} 4535 4536int 4537siogdbattach(port, speed) 4538 int port; 4539 int speed; 4540{ 4541 int s; 4542 u_char cfcr; 4543 struct siocnstate sp; 4544 int unit = 1; /* XXX !!! */ 4545 4546 siogdbiobase = port; 4547 gdbdefaultrate = speed; 4548 4549 printf("sio%d: gdb debugging port\n", unit); 4550 siogdbunit = unit; 4551#if DDB > 0 4552 gdbdev = makedev(CDEV_MAJOR, unit); 4553 gdb_getc = siocngetc; 4554 gdb_putc = siocnputc; 4555#endif 4556 4557 s = spltty(); 4558 4559 /* 4560 * Initialize the divisor latch. We can't rely on 4561 * siocnopen() to do this the first time, since it 4562 * avoids writing to the latch if the latch appears 4563 * to have the correct value. Also, if we didn't 4564 * just read the speed from the hardware, then we 4565 * need to set the speed in hardware so that 4566 * switching it later is null. 4567 */ 4568 cfcr = inb(siogdbiobase + com_cfcr); 4569 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr); 4570 outb(siogdbiobase + com_dlbl, 4571 COMBRD(gdbdefaultrate) & 0xff); 4572 outb(siogdbiobase + com_dlbh, 4573 (u_int) COMBRD(gdbdefaultrate) >> 8); 4574 outb(siogdbiobase + com_cfcr, cfcr); 4575 4576 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 4577 splx(s); 4578 4579 return (0); 4580} 4581 4582#endif 4583 4584static int 4585siocncheckc(dev) 4586 dev_t dev; 4587{ 4588 int c; 4589 Port_t iobase; 4590 int s; 4591 struct siocnstate sp; 4592 4593 if (minor(dev) == siogdbunit) 4594 iobase = siogdbiobase; 4595 else 4596 iobase = siocniobase; 4597 s = spltty(); 4598 siocnopen(&sp, iobase, comdefaultrate); 4599 if (inb(iobase + com_lsr) & LSR_RXRDY) 4600 c = inb(iobase + com_data); 4601 else 4602 c = -1; 4603 siocnclose(&sp, iobase); 4604 splx(s); 4605 return (c); 4606} 4607 4608 4609int 4610siocngetc(dev) 4611 dev_t dev; 4612{ 4613 int c; 4614 Port_t iobase; 4615 int s; 4616 struct siocnstate sp; 4617 4618 if (minor(dev) == siogdbunit) 4619 iobase = siogdbiobase; 4620 else 4621 iobase = siocniobase; 4622 s = spltty(); 4623 siocnopen(&sp, iobase, comdefaultrate); 4624 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 4625 ; 4626 c = inb(iobase + com_data); 4627 siocnclose(&sp, iobase); 4628 splx(s); 4629 return (c); 4630} 4631 4632void 4633siocnputc(dev, c) 4634 dev_t dev; 4635 int c; 4636{ 4637 int s; 4638 struct siocnstate sp; 4639 Port_t iobase; 4640 4641 if (minor(dev) == siogdbunit) 4642 iobase = siogdbiobase; 4643 else 4644 iobase = siocniobase; 4645 s = spltty(); 4646 siocnopen(&sp, iobase, comdefaultrate); 4647 siocntxwait(iobase); 4648 outb(iobase + com_data, c); 4649 siocnclose(&sp, iobase); 4650 splx(s); 4651} 4652 4653#ifdef __alpha__ 4654int 4655siogdbgetc() 4656{ 4657 int c; 4658 Port_t iobase; 4659 int s; 4660 struct siocnstate sp; 4661 4662 iobase = siogdbiobase; 4663 s = spltty(); 4664 siocnopen(&sp, iobase, gdbdefaultrate); 4665 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 4666 ; 4667 c = inb(iobase + com_data); 4668 siocnclose(&sp, iobase); 4669 splx(s); 4670 return (c); 4671} 4672 4673void 4674siogdbputc(c) 4675 int c; 4676{ 4677 int s; 4678 struct siocnstate sp; 4679 4680 s = spltty(); 4681 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 4682 siocntxwait(siogdbiobase); 4683 outb(siogdbiobase + com_data, c); 4684 siocnclose(&sp, siogdbiobase); 4685 splx(s); 4686} 4687#endif 4688 4689DRIVER_MODULE(sio, isa, sio_isa_driver, sio_devclass, 0, 0); 4690#if NCARD > 0 4691DRIVER_MODULE(sio, pccard, sio_pccard_driver, sio_devclass, 0, 0); 4692#endif 4693#if NPCI > 0 4694DRIVER_MODULE(sio, pci, sio_pci_driver, sio_devclass, 0, 0); 4695#endif 4696 4697#ifdef PC98 4698/* 4699 * pc98 local function 4700 */ 4701 4702static void 4703com_tiocm_set(struct com_s *com, int msr) 4704{ 4705 int s; 4706 int tmp = 0; 4707 int mask = CMD8251_TxEN|CMD8251_RxEN|CMD8251_DTR|CMD8251_RTS; 4708 4709 s=spltty(); 4710 com->pc98_prev_modem_status = ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ) 4711 | ( com->pc98_prev_modem_status & ~(TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4712 tmp |= (CMD8251_TxEN|CMD8251_RxEN); 4713 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4714 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4715 pc98_i8251_clear_or_cmd( com, mask, tmp ); 4716 splx(s); 4717} 4718 4719static void 4720com_tiocm_bis(struct com_s *com, int msr) 4721{ 4722 int s; 4723 int tmp = 0; 4724 4725 s=spltty(); 4726 com->pc98_prev_modem_status |= ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4727 tmp |= CMD8251_TxEN|CMD8251_RxEN; 4728 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4729 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4730 4731 pc98_i8251_or_cmd( com, tmp ); 4732 splx(s); 4733} 4734 4735static void 4736com_tiocm_bic(struct com_s *com, int msr) 4737{ 4738 int s; 4739 int tmp = msr; 4740 4741 s=spltty(); 4742 com->pc98_prev_modem_status &= ~( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4743 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4744 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4745 4746 pc98_i8251_clear_cmd( com, tmp ); 4747 splx(s); 4748} 4749 4750static int 4751com_tiocm_get(struct com_s *com) 4752{ 4753 return( com->pc98_prev_modem_status ); 4754} 4755 4756static int 4757com_tiocm_get_delta(struct com_s *com) 4758{ 4759 int tmp; 4760 4761 tmp = com->pc98_modem_delta; 4762 com->pc98_modem_delta = 0; 4763 return( tmp ); 4764} 4765 4766/* convert to TIOCM_?? ( ioctl.h ) */ 4767static int 4768pc98_get_modem_status(struct com_s *com) 4769{ 4770 register int msr; 4771 4772 msr = com->pc98_prev_modem_status 4773 & ~(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 4774 if (com->pc98_8251fifo_enable) { 4775 int stat2; 4776 4777 stat2 = inb(I8251F_msr); 4778 if ( stat2 & CICSCDF_CD ) msr |= TIOCM_CAR; 4779 if ( stat2 & CICSCDF_CI ) msr |= TIOCM_RI; 4780 if ( stat2 & CICSCDF_DR ) msr |= TIOCM_DSR; 4781 if ( stat2 & CICSCDF_CS ) msr |= TIOCM_CTS; 4782#if COM_CARRIER_DETECT_EMULATE 4783 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 4784 msr |= TIOCM_CAR; 4785 } 4786#endif 4787 } else { 4788 int stat, stat2; 4789 4790 stat = inb(com->sts_port); 4791 stat2 = inb(com->in_modem_port); 4792 if ( !(stat2 & CICSCD_CD) ) msr |= TIOCM_CAR; 4793 if ( !(stat2 & CICSCD_CI) ) msr |= TIOCM_RI; 4794 if ( stat & STS8251_DSR ) msr |= TIOCM_DSR; 4795 if ( !(stat2 & CICSCD_CS) ) msr |= TIOCM_CTS; 4796#if COM_CARRIER_DETECT_EMULATE 4797 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 4798 msr |= TIOCM_CAR; 4799 } 4800#endif 4801 } 4802 return(msr); 4803} 4804 4805static void 4806pc98_check_msr(void* chan) 4807{ 4808 int msr, delta; 4809 int s; 4810 register struct tty *tp; 4811 struct com_s *com; 4812 int mynor; 4813 int unit; 4814 dev_t dev; 4815 4816 dev=(dev_t)chan; 4817 mynor = minor(dev); 4818 unit = MINOR_TO_UNIT(mynor); 4819 com = com_addr(unit); 4820 tp = com->tp; 4821 4822 s = spltty(); 4823 msr = pc98_get_modem_status(com); 4824 /* make change flag */ 4825 delta = msr ^ com->pc98_prev_modem_status; 4826 if ( delta & TIOCM_CAR ) { 4827 if ( com->modem_car_chg_timer ) { 4828 if ( -- com->modem_car_chg_timer ) 4829 msr ^= TIOCM_CAR; 4830 } else { 4831 if ((com->modem_car_chg_timer = (msr & TIOCM_CAR) ? 4832 DCD_ON_RECOGNITION : DCD_OFF_TOLERANCE) != 0) 4833 msr ^= TIOCM_CAR; 4834 } 4835 } else 4836 com->modem_car_chg_timer = 0; 4837 delta = ( msr ^ com->pc98_prev_modem_status ) & 4838 (TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 4839 com->pc98_prev_modem_status = msr; 4840 delta = ( com->pc98_modem_delta |= delta ); 4841 splx(s); 4842 if ( com->modem_checking || (tp->t_state & (TS_ISOPEN)) ) { 4843 if ( delta ) { 4844 commint(dev); 4845 } 4846 timeout(pc98_check_msr, (caddr_t)dev, 4847 PC98_CHECK_MODEM_INTERVAL); 4848 } else { 4849 com->modem_checking = 0; 4850 } 4851} 4852 4853static void 4854pc98_msrint_start(dev_t dev) 4855{ 4856 struct com_s *com; 4857 int mynor; 4858 int unit; 4859 int s = spltty(); 4860 4861 mynor = minor(dev); 4862 unit = MINOR_TO_UNIT(mynor); 4863 com = com_addr(unit); 4864 /* modem control line check routine envoke interval is 1/10 sec */ 4865 if ( com->modem_checking == 0 ) { 4866 com->pc98_prev_modem_status = pc98_get_modem_status(com); 4867 com->pc98_modem_delta = 0; 4868 timeout(pc98_check_msr, (caddr_t)dev, 4869 PC98_CHECK_MODEM_INTERVAL); 4870 com->modem_checking = 1; 4871 } 4872 splx(s); 4873} 4874 4875static void 4876pc98_disable_i8251_interrupt(struct com_s *com, int mod) 4877{ 4878 /* disable interrupt */ 4879 register int tmp; 4880 4881 mod |= ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4882 COM_INT_DISABLE 4883 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4884 outb( com->intr_ctrl_port, (com->intr_enable&=~mod) | tmp ); 4885 COM_INT_ENABLE 4886} 4887 4888static void 4889pc98_enable_i8251_interrupt(struct com_s *com, int mod) 4890{ 4891 register int tmp; 4892 4893 COM_INT_DISABLE 4894 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4895 outb( com->intr_ctrl_port, (com->intr_enable|=mod) | tmp ); 4896 COM_INT_ENABLE 4897} 4898 4899static int 4900pc98_check_i8251_interrupt(struct com_s *com) 4901{ 4902 return ( com->intr_enable & 0x07 ); 4903} 4904 4905static void 4906pc98_i8251_clear_cmd(struct com_s *com, int x) 4907{ 4908 int tmp; 4909 4910 COM_INT_DISABLE 4911 tmp = com->pc98_prev_siocmd & ~(x); 4912 if (com->pc98_8251fifo_enable) 4913 outb(I8251F_fcr, 0); 4914 outb(com->cmd_port, tmp); 4915 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4916 if (com->pc98_8251fifo_enable) 4917 outb(I8251F_fcr, CTRL8251F_ENABLE); 4918 COM_INT_ENABLE 4919} 4920 4921static void 4922pc98_i8251_or_cmd(struct com_s *com, int x) 4923{ 4924 int tmp; 4925 4926 COM_INT_DISABLE 4927 if (com->pc98_8251fifo_enable) 4928 outb(I8251F_fcr, 0); 4929 tmp = com->pc98_prev_siocmd | (x); 4930 outb(com->cmd_port, tmp); 4931 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4932 if (com->pc98_8251fifo_enable) 4933 outb(I8251F_fcr, CTRL8251F_ENABLE); 4934 COM_INT_ENABLE 4935} 4936 4937static void 4938pc98_i8251_set_cmd(struct com_s *com, int x) 4939{ 4940 int tmp; 4941 4942 COM_INT_DISABLE 4943 if (com->pc98_8251fifo_enable) 4944 outb(I8251F_fcr, 0); 4945 tmp = (x); 4946 outb(com->cmd_port, tmp); 4947 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4948 if (com->pc98_8251fifo_enable) 4949 outb(I8251F_fcr, CTRL8251F_ENABLE); 4950 COM_INT_ENABLE 4951} 4952 4953static void 4954pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x) 4955{ 4956 int tmp; 4957 COM_INT_DISABLE 4958 if (com->pc98_8251fifo_enable) 4959 outb(I8251F_fcr, 0); 4960 tmp = com->pc98_prev_siocmd & ~(clr); 4961 tmp |= (x); 4962 outb(com->cmd_port, tmp); 4963 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4964 if (com->pc98_8251fifo_enable) 4965 outb(I8251F_fcr, CTRL8251F_ENABLE); 4966 COM_INT_ENABLE 4967} 4968 4969static int 4970pc98_i8251_get_cmd(struct com_s *com) 4971{ 4972 return com->pc98_prev_siocmd; 4973} 4974 4975static int 4976pc98_i8251_get_mod(struct com_s *com) 4977{ 4978 return com->pc98_prev_siomod; 4979} 4980 4981static void 4982pc98_i8251_reset(struct com_s *com, int mode, int command) 4983{ 4984 if (com->pc98_8251fifo_enable) 4985 outb(I8251F_fcr, 0); 4986 outb(com->cmd_port, 0); /* dummy */ 4987 DELAY(2); 4988 outb(com->cmd_port, 0); /* dummy */ 4989 DELAY(2); 4990 outb(com->cmd_port, 0); /* dummy */ 4991 DELAY(2); 4992 outb(com->cmd_port, CMD8251_RESET); /* internal reset */ 4993 DELAY(2); 4994 outb(com->cmd_port, mode ); /* mode register */ 4995 com->pc98_prev_siomod = mode; 4996 DELAY(2); 4997 pc98_i8251_set_cmd( com, (command|CMD8251_ER) ); 4998 DELAY(10); 4999 if (com->pc98_8251fifo_enable) 5000 outb(I8251F_fcr, CTRL8251F_ENABLE | 5001 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 5002} 5003 5004static void 5005pc98_check_sysclock(void) 5006{ 5007 /* get system clock from port */ 5008 if ( pc98_machine_type & M_8M ) { 5009 /* 8 MHz system & H98 */ 5010 sysclock = 8; 5011 } else { 5012 /* 5 MHz system */ 5013 sysclock = 5; 5014 } 5015} 5016 5017static void 5018com_cflag_and_speed_set( struct com_s *com, int cflag, int speed) 5019{ 5020 int cfcr=0, count; 5021 int previnterrupt; 5022 5023 count = pc98_ttspeedtab( com, speed ); 5024 if ( count < 0 ) return; 5025 5026 previnterrupt = pc98_check_i8251_interrupt(com); 5027 pc98_disable_i8251_interrupt( com, IEN_Tx|IEN_TxEMP|IEN_Rx ); 5028 5029 switch ( cflag&CSIZE ) { 5030 case CS5: 5031 cfcr = MOD8251_5BITS; break; 5032 case CS6: 5033 cfcr = MOD8251_6BITS; break; 5034 case CS7: 5035 cfcr = MOD8251_7BITS; break; 5036 case CS8: 5037 cfcr = MOD8251_8BITS; break; 5038 } 5039 if ( cflag&PARENB ) { 5040 if ( cflag&PARODD ) 5041 cfcr |= MOD8251_PODD; 5042 else 5043 cfcr |= MOD8251_PEVEN; 5044 } else 5045 cfcr |= MOD8251_PDISAB; 5046 5047 if ( cflag&CSTOPB ) 5048 cfcr |= MOD8251_STOP2; 5049 else 5050 cfcr |= MOD8251_STOP1; 5051 5052 if ( count & 0x10000 ) 5053 cfcr |= MOD8251_CLKX1; 5054 else 5055 cfcr |= MOD8251_CLKX16; 5056 5057 if (epson_machine_id != 0x20) { /* XXX */ 5058 int tmp; 5059 while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP)) 5060 ; 5061 } 5062 /* set baud rate from ospeed */ 5063 pc98_set_baud_rate( com, count ); 5064 5065 if ( cfcr != pc98_i8251_get_mod(com) ) 5066 pc98_i8251_reset(com, cfcr, pc98_i8251_get_cmd(com) ); 5067 5068 pc98_enable_i8251_interrupt( com, previnterrupt ); 5069} 5070 5071static int 5072pc98_ttspeedtab(struct com_s *com, int speed) 5073{ 5074 int if_type, effect_sp, count = -1, mod; 5075 5076 if_type = com->pc98_if_type & 0x0f; 5077 5078 switch (com->pc98_if_type) { 5079 case COM_IF_INTERNAL: 5080 if (PC98SIO_baud_rate_port(if_type) != -1) { 5081 count = ttspeedtab(speed, if_8251_type[if_type].speedtab); 5082 if (count > 0) { 5083 count |= COM1_EXT_CLOCK; 5084 break; 5085 } 5086 } 5087 5088 /* for *1CLK asynchronous! mode, TEFUTEFU */ 5089 mod = (sysclock == 5) ? 2457600 : 1996800; 5090 effect_sp = ttspeedtab( speed, pc98speedtab ); 5091 if ( effect_sp < 0 ) /* XXX */ 5092 effect_sp = ttspeedtab( (speed - 1), pc98speedtab ); 5093 if ( effect_sp <= 0 ) 5094 return effect_sp; 5095 if ( effect_sp == speed ) 5096 mod /= 16; 5097 if ( mod % effect_sp ) 5098 return(-1); 5099 count = mod / effect_sp; 5100 if ( count > 65535 ) 5101 return(-1); 5102 if ( effect_sp != speed ) 5103 count |= 0x10000; 5104 break; 5105 case COM_IF_PC9861K_1: 5106 case COM_IF_PC9861K_2: 5107 count = 1; 5108 break; 5109 case COM_IF_IND_SS_1: 5110 case COM_IF_IND_SS_2: 5111 case COM_IF_PIO9032B_1: 5112 case COM_IF_PIO9032B_2: 5113 if ( speed == 0 ) return 0; 5114 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 5115 break; 5116 case COM_IF_B98_01_1: 5117 case COM_IF_B98_01_2: 5118 if ( speed == 0 ) return 0; 5119 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 5120#ifdef B98_01_OLD 5121 if (count == 0 || count == 1) { 5122 count += 4; 5123 count |= 0x20000; /* x1 mode for 76800 and 153600 */ 5124 } 5125#endif 5126 break; 5127 } 5128 5129 return count; 5130} 5131 5132static void 5133pc98_set_baud_rate( struct com_s *com, int count ) 5134{ 5135 int if_type, io, s; 5136 5137 if_type = com->pc98_if_type & 0x0f; 5138 io = rman_get_start(com->ioportres) & 0xff00; 5139 5140 switch (com->pc98_if_type) { 5141 case COM_IF_INTERNAL: 5142 if (PC98SIO_baud_rate_port(if_type) != -1) { 5143 if (count & COM1_EXT_CLOCK) { 5144 outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff); 5145 break; 5146 } else { 5147 outb((Port_t)PC98SIO_baud_rate_port(if_type), 0x09); 5148 } 5149 } 5150 5151 if ( count < 0 ) { 5152 printf( "[ Illegal count : %d ]", count ); 5153 return; 5154 } else if ( count == 0 ) 5155 return; 5156 /* set i8253 */ 5157 s = splclock(); 5158 if (count != 3) 5159 outb( 0x77, 0xb6 ); 5160 else 5161 outb( 0x77, 0xb4 ); 5162 outb( 0x5f, 0); 5163 outb( 0x75, count & 0xff ); 5164 outb( 0x5f, 0); 5165 outb( 0x75, (count >> 8) & 0xff ); 5166 splx(s); 5167 break; 5168 case COM_IF_IND_SS_1: 5169 case COM_IF_IND_SS_2: 5170 outb(io | PC98SIO_intr_ctrl_port(if_type), 0); 5171 outb(io | PC98SIO_baud_rate_port(if_type), 0); 5172 outb(io | PC98SIO_baud_rate_port(if_type), 0xc0); 5173 outb(io | PC98SIO_baud_rate_port(if_type), (count >> 8) | 0x80); 5174 outb(io | PC98SIO_baud_rate_port(if_type), count & 0xff); 5175 break; 5176 case COM_IF_PIO9032B_1: 5177 case COM_IF_PIO9032B_2: 5178 outb(io | PC98SIO_baud_rate_port(if_type), count); 5179 break; 5180 case COM_IF_B98_01_1: 5181 case COM_IF_B98_01_2: 5182 outb(io | PC98SIO_baud_rate_port(if_type), count & 0x0f); 5183#ifdef B98_01_OLD 5184 /* 5185 * Some old B98_01 board should be controlled 5186 * in different way, but this hasn't been tested yet. 5187 */ 5188 outb(io | PC98SIO_func_port(if_type), 5189 (count & 0x20000) ? 0xf0 : 0xf2); 5190#endif 5191 break; 5192 } 5193} 5194static int 5195pc98_check_if_type(device_t dev, struct siodev *iod) 5196{ 5197 int irr, io, if_type, tmp; 5198 static short irq_tab[2][8] = { 5199 { 3, 5, 6, 9, 10, 12, 13, -1}, 5200 { 3, 10, 12, 13, 5, 6, 9, -1} 5201 }; 5202 5203 if_type = iod->if_type & 0x0f; 5204 iod->irq = 0; 5205 io = isa_get_port(dev) & 0xff00; 5206 5207 if (IS_8251(iod->if_type)) { 5208 if (PC98SIO_func_port(if_type) != -1) { 5209 outb(io | PC98SIO_func_port(if_type), 0xf2); 5210 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab); 5211 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1) 5212 outb(io | PC98SIO_baud_rate_port(if_type), tmp); 5213 } 5214 5215 iod->cmd = io | PC98SIO_cmd_port(if_type); 5216 iod->sts = io | PC98SIO_sts_port(if_type); 5217 iod->mod = io | PC98SIO_in_modem_port(if_type); 5218 iod->ctrl = io | PC98SIO_intr_ctrl_port(if_type); 5219 5220 if (iod->if_type == COM_IF_INTERNAL) { 5221 iod->irq = 4; 5222 5223 if (pc98_check_8251vfast()) { 5224 PC98SIO_baud_rate_port(if_type) = I8251F_div; 5225 if_8251_type[if_type].speedtab = pc98fast_speedtab; 5226 } 5227 } else { 5228 tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask; 5229 if ((isa_get_port(dev) & 0xff) == IO_COM2) 5230 iod->irq = irq_tab[0][tmp]; 5231 else 5232 iod->irq = irq_tab[1][tmp]; 5233 } 5234 } else { 5235 irr = if_16550a_type[if_type].irr_read; 5236#ifdef COM_MULTIPORT 5237 if (!COM_ISMULTIPORT(device_get_flags(dev)) || 5238 device_get_unit(dev) == COM_MPMASTER(device_get_flags(dev))) 5239#endif 5240 if (irr != -1) { 5241 tmp = inb(io | irr); 5242 if (isa_get_port(dev) & 0x01) /* XXX depend on RSB-384 */ 5243 iod->irq = irq_tab[1][tmp >> 3]; 5244 else 5245 iod->irq = irq_tab[0][tmp & 0x07]; 5246 } 5247 } 5248 if ( iod->irq == -1 ) return -1; 5249 5250 return 0; 5251} 5252static void 5253pc98_set_ioport(struct com_s *com) 5254{ 5255 int if_type = com->pc98_if_type & 0x0f; 5256 Port_t io = rman_get_start(com->ioportres) & 0xff00; 5257 5258 pc98_check_sysclock(); 5259 com->data_port = io | PC98SIO_data_port(if_type); 5260 com->cmd_port = io | PC98SIO_cmd_port(if_type); 5261 com->sts_port = io | PC98SIO_sts_port(if_type); 5262 com->in_modem_port = io | PC98SIO_in_modem_port(if_type); 5263 com->intr_ctrl_port = io | PC98SIO_intr_ctrl_port(if_type); 5264} 5265static int 5266pc98_check_8251vfast(void) 5267{ 5268 int i; 5269 5270 outb(I8251F_div, 0x8c); 5271 DELAY(10); 5272 for (i = 0; i < 100; i++) { 5273 if ((inb(I8251F_div) & 0x80) != 0) { 5274 i = 0; 5275 break; 5276 } 5277 DELAY(1); 5278 } 5279 outb(I8251F_div, 0); 5280 DELAY(10); 5281 for (; i < 100; i++) { 5282 if ((inb(I8251F_div) & 0x80) == 0) 5283 return 1; 5284 DELAY(1); 5285 } 5286 5287 return 0; 5288} 5289static int 5290pc98_check_8251fifo(void) 5291{ 5292 u_char tmp1, tmp2; 5293 5294 tmp1 = inb(I8251F_iir); 5295 DELAY(10); 5296 tmp2 = inb(I8251F_iir); 5297 if (((tmp1 ^ tmp2) & 0x40) != 0 && ((tmp1 | tmp2) & 0x20) == 0) 5298 return 1; 5299 5300 return 0; 5301} 5302#endif /* PC98 defined */ 5303