sio.c revision 57885
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Berkeley and its contributors. 17 * 4. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/pc98/cbus/sio.c 57885 2000-03-10 10:34:36Z kato $ 34 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 35 * from: i386/isa sio.c,v 1.234 36 */ 37 38#include "opt_comconsole.h" 39#include "opt_compat.h" 40#include "opt_ddb.h" 41#include "opt_sio.h" 42#include "card.h" 43#include "sio.h" 44 45/* 46 * Serial driver, based on 386BSD-0.1 com driver. 47 * Mostly rewritten to use pseudo-DMA. 48 * Works for National Semiconductor NS8250-NS16550AF UARTs. 49 * COM driver, based on HP dca driver. 50 * 51 * Changes for PC-Card integration: 52 * - Added PC-Card driver table and handlers 53 */ 54/*=============================================================== 55 * 386BSD(98),FreeBSD-1.1x(98) com driver. 56 * ----- 57 * modified for PC9801 by M.Ishii 58 * Kyoto University Microcomputer Club (KMC) 59 * Chou "TEFUTEFU" Hirotomi 60 * Kyoto Univ. the faculty of medicine 61 *=============================================================== 62 * FreeBSD-2.0.1(98) sio driver. 63 * ----- 64 * modified for pc98 Internal i8251 and MICRO CORE MC16550II 65 * T.Koike(hfc01340@niftyserve.or.jp) 66 * implement kernel device configuration 67 * aizu@orient.center.nitech.ac.jp 68 * 69 * Notes. 70 * ----- 71 * PC98 localization based on 386BSD(98) com driver. Using its PC98 local 72 * functions. 73 * This driver is under debugging,has bugs. 74 * 75 * 1) config 76 * options COM_MULTIPORT #if using MC16550II 77 * device sio0 at nec? port 0x30 tty irq 4 #internal 78 * device sio1 at nec? port 0xd2 tty irq 5 flags 0x101 #mc1 79 * device sio2 at nec? port 0x8d2 tty flags 0x101 #mc2 80 * # ~~~~~iobase ~~multi port flag 81 * # ~ master device is sio1 82 * 2) device 83 * cd /dev; MAKEDEV ttyd0 ttyd1 .. 84 * 3) /etc/rc.serial 85 * 57600bps is too fast for sio0(internal8251) 86 * my ex. 87 * #set default speed 9600 88 * modem() 89 * : 90 * stty </dev/ttyid$i crtscts 9600 91 * : # ~~~~ default speed(can change after init.) 92 * modem 0 1 2 93 * 4) COMCONSOLE 94 * not changed. 95 * 5) PC9861K,PIO9032B,B98_01 96 * not tested. 97 */ 98/* 99 * modified for AIWA B98-01 100 * by T.Hatanou <hatanou@yasuda.comm.waseda.ac.jp> last update: 15 Sep.1995 101 * 102 * How to configure... 103 * # options COM_MULTIPORT # support for MICROCORE MC16550II 104 * ... comment-out this line, which will conflict with B98_01. 105 * options "B98_01" # support for AIWA B98-01 106 * device sio1 at nec? port 0x00d1 tty irq ? 107 * device sio2 at nec? port 0x00d5 tty irq ? 108 * ... you can leave these lines `irq ?', irq will be autodetected. 109 */ 110/* 111 * Modified by Y.Takahashi of Kogakuin University. 112 */ 113/* 114 * modified for 8251(FIFO) by Seigo TANIMURA <tanimura@FreeBSD.org> 115 */ 116 117#ifdef PC98 118#define COM_IF_INTERNAL 0x00 119#define COM_IF_PC9861K_1 0x01 120#define COM_IF_PC9861K_2 0x02 121#define COM_IF_IND_SS_1 0x03 122#define COM_IF_IND_SS_2 0x04 123#define COM_IF_PIO9032B_1 0x05 124#define COM_IF_PIO9032B_2 0x06 125#define COM_IF_B98_01_1 0x07 126#define COM_IF_B98_01_2 0x08 127#define COM_IF_END1 COM_IF_B98_01_2 128#define COM_IF_RSA98 0x10 /* same as COM_IF_NS16550 */ 129#define COM_IF_NS16550 0x11 130#define COM_IF_SECOND_CCU 0x12 /* same as COM_IF_NS16550 */ 131#define COM_IF_MC16550II 0x13 132#define COM_IF_MCRS98 0x14 /* same as COM_IF_MC16550II */ 133#define COM_IF_RSB3000 0x15 134#define COM_IF_RSB384 0x16 135#define COM_IF_MODEM_CARD 0x17 /* same as COM_IF_NS16550 */ 136#define COM_IF_RSA98III 0x18 137#define COM_IF_ESP98 0x19 138#define COM_IF_END2 COM_IF_ESP98 139#endif /* PC98 */ 140 141#include <sys/param.h> 142#include <sys/systm.h> 143#include <sys/reboot.h> 144#include <sys/malloc.h> 145#include <sys/tty.h> 146#include <sys/proc.h> 147#include <sys/module.h> 148#include <sys/conf.h> 149#include <sys/dkstat.h> 150#include <sys/fcntl.h> 151#include <sys/interrupt.h> 152#include <sys/kernel.h> 153#include <sys/syslog.h> 154#include <sys/sysctl.h> 155#include <sys/bus.h> 156#include <machine/bus.h> 157#include <sys/rman.h> 158#include <sys/timepps.h> 159 160#ifdef PC98 161#include <pc98/pc98/pc98.h> 162#include <pc98/pc98/pc98_machdep.h> 163#include <i386/isa/ic/i8251.h> 164#else 165#include <isa/isareg.h> 166#endif 167#include <isa/isavar.h> 168#include <machine/lock.h> 169 170#include <machine/clock.h> 171#include <machine/ipl.h> 172#ifndef SMP 173#include <machine/lock.h> 174#endif 175#include <machine/resource.h> 176 177#include <isa/sioreg.h> 178 179#ifdef COM_ESP 180#include <i386/isa/ic/esp.h> 181#endif 182#include <i386/isa/ic/ns16550.h> 183#ifdef PC98 184#include <i386/isa/ic/rsa.h> 185#endif 186 187#ifndef __i386__ 188#define disable_intr() 189#define enable_intr() 190#endif 191 192#ifdef SMP 193#define disable_intr() COM_DISABLE_INTR() 194#define enable_intr() COM_ENABLE_INTR() 195#endif /* SMP */ 196 197#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */ 198 199#define CALLOUT_MASK 0x80 200#define CONTROL_MASK 0x60 201#define CONTROL_INIT_STATE 0x20 202#define CONTROL_LOCK_STATE 0x40 203#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev))) 204#define MINOR_MAGIC_MASK (CALLOUT_MASK | CONTROL_MASK) 205#define MINOR_TO_UNIT(mynor) ((mynor) & ~MINOR_MAGIC_MASK) 206 207#ifdef COM_MULTIPORT 208/* checks in flags for multiport and which is multiport "master chip" 209 * for a given card 210 */ 211#define COM_ISMULTIPORT(flags) ((flags) & 0x01) 212#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff) 213#define COM_NOTAST4(flags) ((flags) & 0x04) 214#endif /* COM_MULTIPORT */ 215 216#define COM_CONSOLE(flags) ((flags) & 0x10) 217#define COM_FORCECONSOLE(flags) ((flags) & 0x20) 218#define COM_LLCONSOLE(flags) ((flags) & 0x40) 219#define COM_DEBUGGER(flags) ((flags) & 0x80) 220#define COM_LOSESOUTINTS(flags) ((flags) & 0x08) 221#define COM_NOFIFO(flags) ((flags) & 0x02) 222#define COM_ST16650A(flags) ((flags) & 0x20000) 223#define COM_C_NOPROBE (0x40000) 224#define COM_NOPROBE(flags) ((flags) & COM_C_NOPROBE) 225#define COM_C_IIR_TXRDYBUG (0x80000) 226#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG) 227#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24) 228 229#ifdef PC98 230#define com_emr com_msr /* Extension mode register for RSB-2000/3000 */ 231#else 232#define com_scr 7 /* scratch register for 16450-16550 (R/W) */ 233#endif 234 235/* 236 * com state bits. 237 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher 238 * than the other bits so that they can be tested as a group without masking 239 * off the low bits. 240 * 241 * The following com and tty flags correspond closely: 242 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and 243 * comstop()) 244 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart()) 245 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam()) 246 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam()) 247 * TS_FLUSH is not used. 248 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON. 249 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state). 250 */ 251#define CS_BUSY 0x80 /* output in progress */ 252#define CS_TTGO 0x40 /* output not stopped by XOFF */ 253#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */ 254#define CS_CHECKMSR 1 /* check of MSR scheduled */ 255#define CS_CTS_OFLOW 2 /* use CTS output flow control */ 256#define CS_DTR_OFF 0x10 /* DTR held off */ 257#define CS_ODONE 4 /* output completed */ 258#define CS_RTS_IFLOW 8 /* use RTS input flow control */ 259#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */ 260 261static char const * const error_desc[] = { 262#define CE_OVERRUN 0 263 "silo overflow", 264#define CE_INTERRUPT_BUF_OVERFLOW 1 265 "interrupt-level buffer overflow", 266#define CE_TTY_BUF_OVERFLOW 2 267 "tty-level buffer overflow", 268}; 269 270#define CE_NTYPES 3 271#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum]) 272 273/* types. XXX - should be elsewhere */ 274typedef u_int Port_t; /* hardware port */ 275typedef u_char bool_t; /* boolean */ 276 277/* queue of linear buffers */ 278struct lbq { 279 u_char *l_head; /* next char to process */ 280 u_char *l_tail; /* one past the last char to process */ 281 struct lbq *l_next; /* next in queue */ 282 bool_t l_queued; /* nonzero if queued */ 283}; 284 285/* com device structure */ 286struct com_s { 287 u_int flags; /* Copy isa device flags */ 288 u_char state; /* miscellaneous flag bits */ 289 bool_t active_out; /* nonzero if the callout device is open */ 290 u_char cfcr_image; /* copy of value written to CFCR */ 291#ifdef COM_ESP 292 bool_t esp; /* is this unit a hayes esp board? */ 293#endif 294 u_char extra_state; /* more flag bits, separate for order trick */ 295 u_char fifo_image; /* copy of value written to FIFO */ 296 bool_t hasfifo; /* nonzero for 16550 UARTs */ 297 bool_t st16650a; /* Is a Startech 16650A or RTS/CTS compat */ 298 bool_t loses_outints; /* nonzero if device loses output interrupts */ 299 u_char mcr_image; /* copy of value written to MCR */ 300#ifdef COM_MULTIPORT 301 bool_t multiport; /* is this unit part of a multiport device? */ 302#endif /* COM_MULTIPORT */ 303 bool_t no_irq; /* nonzero if irq is not attached */ 304 bool_t gone; /* hardware disappeared */ 305 bool_t poll; /* nonzero if polling is required */ 306 bool_t poll_output; /* nonzero if polling for output is required */ 307 int unit; /* unit number */ 308 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */ 309 u_int tx_fifo_size; 310 u_int wopeners; /* # processes waiting for DCD in open() */ 311 312 /* 313 * The high level of the driver never reads status registers directly 314 * because there would be too many side effects to handle conveniently. 315 * Instead, it reads copies of the registers stored here by the 316 * interrupt handler. 317 */ 318 u_char last_modem_status; /* last MSR read by intr handler */ 319 u_char prev_modem_status; /* last MSR handled by high level */ 320 321 u_char hotchar; /* ldisc-specific char to be handled ASAP */ 322 u_char *ibuf; /* start of input buffer */ 323 u_char *ibufend; /* end of input buffer */ 324 u_char *ibufold; /* old input buffer, to be freed */ 325 u_char *ihighwater; /* threshold in input buffer */ 326 u_char *iptr; /* next free spot in input buffer */ 327 int ibufsize; /* size of ibuf (not include error bytes) */ 328 int ierroff; /* offset of error bytes in ibuf */ 329 330 struct lbq obufq; /* head of queue of output buffers */ 331 struct lbq obufs[2]; /* output buffers */ 332 333#ifdef PC98 334 Port_t cmd_port; 335 Port_t sts_port; 336 Port_t in_modem_port; 337 Port_t intr_ctrl_port; 338 int intr_enable; 339 int pc98_prev_modem_status; 340 int pc98_modem_delta; 341 int modem_car_chg_timer; 342 int pc98_prev_siocmd; 343 int pc98_prev_siomod; 344 int modem_checking; 345 int pc98_if_type; 346 347 bool_t pc98_8251fifo; 348 bool_t pc98_8251fifo_enable; 349#endif /* PC98 */ 350 Port_t data_port; /* i/o ports */ 351#ifdef COM_ESP 352 Port_t esp_port; 353#endif 354 Port_t int_id_port; 355 Port_t iobase; 356#ifdef PC98 357 Port_t rsabase; /* iobase address of a I/O-DATA RSA board */ 358#endif 359 Port_t modem_ctl_port; 360 Port_t line_status_port; 361 Port_t modem_status_port; 362 Port_t intr_ctl_port; /* Ports of IIR register */ 363 364 struct tty *tp; /* cross reference */ 365 366 /* Initial state. */ 367 struct termios it_in; /* should be in struct tty */ 368 struct termios it_out; 369 370 /* Lock state. */ 371 struct termios lt_in; /* should be in struct tty */ 372 struct termios lt_out; 373 374 bool_t do_timestamp; 375 bool_t do_dcd_timestamp; 376 struct timeval timestamp; 377 struct timeval dcd_timestamp; 378 struct pps_state pps; 379 380 u_long bytes_in; /* statistics */ 381 u_long bytes_out; 382 u_int delta_error_counts[CE_NTYPES]; 383 u_long error_counts[CE_NTYPES]; 384 385 struct resource *irqres; 386 struct resource *ioportres; 387 void *cookie; 388 389 /* 390 * Data area for output buffers. Someday we should build the output 391 * buffer queue without copying data. 392 */ 393#ifdef PC98 394 int obufsize; 395 u_char *obuf1; 396 u_char *obuf2; 397#else 398 u_char obuf1[256]; 399 u_char obuf2[256]; 400#endif 401}; 402 403#ifdef COM_ESP 404static int espattach __P((struct com_s *com, Port_t esp_port)); 405#endif 406static int sioattach __P((device_t dev)); 407static int sio_isa_attach __P((device_t dev)); 408 409static timeout_t siobusycheck; 410static timeout_t siodtrwakeup; 411static void comhardclose __P((struct com_s *com)); 412static void sioinput __P((struct com_s *com)); 413static void siointr1 __P((struct com_s *com)); 414static void siointr __P((void *arg)); 415static int commctl __P((struct com_s *com, int bits, int how)); 416static int comparam __P((struct tty *tp, struct termios *t)); 417static swihand_t siopoll; 418static int sioprobe __P((device_t dev)); 419static int sio_isa_probe __P((device_t dev)); 420static void siosettimeout __P((void)); 421static int siosetwater __P((struct com_s *com, speed_t speed)); 422static void comstart __P((struct tty *tp)); 423static void comstop __P((struct tty *tp, int rw)); 424static timeout_t comwakeup; 425static void disc_optim __P((struct tty *tp, struct termios *t, 426 struct com_s *com)); 427 428#if NCARD > 0 429static int sio_pccard_attach __P((device_t dev)); 430static int sio_pccard_detach __P((device_t dev)); 431static int sio_pccard_probe __P((device_t dev)); 432#endif /* NCARD > 0 */ 433 434static char driver_name[] = "sio"; 435 436/* table and macro for fast conversion from a unit number to its com struct */ 437static devclass_t sio_devclass; 438#define com_addr(unit) ((struct com_s *) \ 439 devclass_get_softc(sio_devclass, unit)) 440 441static device_method_t sio_isa_methods[] = { 442 /* Device interface */ 443 DEVMETHOD(device_probe, sio_isa_probe), 444 DEVMETHOD(device_attach, sio_isa_attach), 445 446 { 0, 0 } 447}; 448 449static driver_t sio_isa_driver = { 450 driver_name, 451 sio_isa_methods, 452 sizeof(struct com_s), 453}; 454 455#if NCARD > 0 456static device_method_t sio_pccard_methods[] = { 457 /* Device interface */ 458 DEVMETHOD(device_probe, sio_pccard_probe), 459 DEVMETHOD(device_attach, sio_pccard_attach), 460 DEVMETHOD(device_detach, sio_pccard_detach), 461 462 { 0, 0 } 463}; 464 465static driver_t sio_pccard_driver = { 466 driver_name, 467 sio_pccard_methods, 468 sizeof(struct com_s), 469}; 470#endif (NCARD > 0) 471 472static d_open_t sioopen; 473static d_close_t sioclose; 474static d_read_t sioread; 475static d_write_t siowrite; 476static d_ioctl_t sioioctl; 477 478#define CDEV_MAJOR 28 479static struct cdevsw sio_cdevsw = { 480 /* open */ sioopen, 481 /* close */ sioclose, 482 /* read */ sioread, 483 /* write */ siowrite, 484 /* ioctl */ sioioctl, 485 /* poll */ ttypoll, 486 /* mmap */ nommap, 487 /* strategy */ nostrategy, 488 /* name */ driver_name, 489 /* maj */ CDEV_MAJOR, 490 /* dump */ nodump, 491 /* psize */ nopsize, 492 /* flags */ D_TTY, 493 /* bmaj */ -1 494}; 495 496int comconsole = -1; 497static volatile speed_t comdefaultrate = CONSPEED; 498#ifdef __alpha__ 499static volatile speed_t gdbdefaultrate = CONSPEED; 500#endif 501static u_int com_events; /* input chars + weighted output completions */ 502static Port_t siocniobase; 503static int siocnunit; 504static Port_t siogdbiobase; 505static int siogdbunit = -1; 506static bool_t sio_registered; 507static int sio_timeout; 508static int sio_timeouts_until_log; 509static struct callout_handle sio_timeout_handle 510 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle); 511static int sio_numunits; 512 513#ifdef PC98 514struct siodev { 515 short if_type; 516 short irq; 517 Port_t cmd, sts, ctrl, mod; 518}; 519static int sysclock; 520 521#define COM_INT_DISABLE {int previpri; previpri=spltty(); 522#define COM_INT_ENABLE splx(previpri);} 523#define IEN_TxFLAG IEN_Tx 524 525#define COM_CARRIER_DETECT_EMULATE 0 526#define PC98_CHECK_MODEM_INTERVAL (hz/10) 527#define DCD_OFF_TOLERANCE 2 528#define DCD_ON_RECOGNITION 2 529#define GET_IFTYPE(flags) ((flags >> 24) & 0x1f) 530#define IS_8251(if_type) (!(if_type & 0x10)) 531#define COM1_EXT_CLOCK 0x40000 532 533static void commint __P((dev_t dev)); 534static void com_tiocm_set __P((struct com_s *com, int msr)); 535static void com_tiocm_bis __P((struct com_s *com, int msr)); 536static void com_tiocm_bic __P((struct com_s *com, int msr)); 537static int com_tiocm_get __P((struct com_s *com)); 538static int com_tiocm_get_delta __P((struct com_s *com)); 539static void pc98_msrint_start __P((dev_t dev)); 540static void com_cflag_and_speed_set __P((struct com_s *com, int cflag, int speed)); 541static int pc98_ttspeedtab __P((struct com_s *com, int speed)); 542static int pc98_get_modem_status __P((struct com_s *com)); 543static timeout_t pc98_check_msr; 544static void pc98_set_baud_rate __P((struct com_s *com, int count)); 545static void pc98_i8251_reset __P((struct com_s *com, int mode, int command)); 546static void pc98_disable_i8251_interrupt __P((struct com_s *com, int mod)); 547static void pc98_enable_i8251_interrupt __P((struct com_s *com, int mod)); 548static int pc98_check_i8251_interrupt __P((struct com_s *com)); 549static int pc98_i8251_get_cmd __P((struct com_s *com)); 550static int pc98_i8251_get_mod __P((struct com_s *com)); 551static void pc98_i8251_set_cmd __P((struct com_s *com, int x)); 552static void pc98_i8251_or_cmd __P((struct com_s *com, int x)); 553static void pc98_i8251_clear_cmd __P((struct com_s *com, int x)); 554static void pc98_i8251_clear_or_cmd __P((struct com_s *com, int clr, int x)); 555static int pc98_check_if_type __P((device_t dev, struct siodev *iod)); 556static int pc98_check_8251vfast __P((void)); 557static int pc98_check_8251fifo __P((void)); 558static void pc98_check_sysclock __P((void)); 559static int pc98_set_ioport __P((struct com_s *com)); 560 561#define com_int_Tx_disable(com) \ 562 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP) 563#define com_int_Tx_enable(com) \ 564 pc98_enable_i8251_interrupt(com,IEN_TxFLAG) 565#define com_int_Rx_disable(com) \ 566 pc98_disable_i8251_interrupt(com,IEN_Rx) 567#define com_int_Rx_enable(com) \ 568 pc98_enable_i8251_interrupt(com,IEN_Rx) 569#define com_int_TxRx_disable(com) \ 570 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP|IEN_Rx) 571#define com_int_TxRx_enable(com) \ 572 pc98_enable_i8251_interrupt(com,IEN_TxFLAG|IEN_Rx) 573#define com_send_break_on(com) \ 574 pc98_i8251_or_cmd(com,CMD8251_SBRK) 575#define com_send_break_off(com) \ 576 pc98_i8251_clear_cmd(com,CMD8251_SBRK) 577 578static struct speedtab pc98speedtab[] = { /* internal RS232C interface */ 579 { 0, 0, }, 580 { 50, 50, }, 581 { 75, 75, }, 582 { 150, 150, }, 583 { 200, 200, }, 584 { 300, 300, }, 585 { 600, 600, }, 586 { 1200, 1200, }, 587 { 2400, 2400, }, 588 { 4800, 4800, }, 589 { 9600, 9600, }, 590 { 19200, 19200, }, 591 { 38400, 38400, }, 592 { 51200, 51200, }, 593 { 76800, 76800, }, 594 { 20800, 20800, }, 595 { 31200, 31200, }, 596 { 41600, 41600, }, 597 { 62400, 62400, }, 598 { -1, -1 } 599}; 600static struct speedtab pc98fast_speedtab[] = { 601 { 9600, 0x80 | COMBRD(9600), }, 602 { 19200, 0x80 | COMBRD(19200), }, 603 { 38400, 0x80 | COMBRD(38400), }, 604 { 57600, 0x80 | COMBRD(57600), }, 605 { 115200, 0x80 | COMBRD(115200), }, 606 { -1, -1 } 607}; 608static struct speedtab comspeedtab_pio9032b[] = { 609 { 300, 6, }, 610 { 600, 5, }, 611 { 1200, 4, }, 612 { 2400, 3, }, 613 { 4800, 2, }, 614 { 9600, 1, }, 615 { 19200, 0, }, 616 { 38400, 7, }, 617 { -1, -1 } 618}; 619static struct speedtab comspeedtab_b98_01[] = { 620 { 75, 11, }, 621 { 150, 10, }, 622 { 300, 9, }, 623 { 600, 8, }, 624 { 1200, 7, }, 625 { 2400, 6, }, 626 { 4800, 5, }, 627 { 9600, 4, }, 628 { 19200, 3, }, 629 { 38400, 2, }, 630 { 76800, 1, }, 631 { 153600, 0, }, 632 { -1, -1 } 633}; 634static struct speedtab comspeedtab_mc16550[] = { 635 { 300, 1536, }, 636 { 600, 768, }, 637 { 1200, 384, }, 638 { 2400, 192, }, 639 { 4800, 96, }, 640 { 9600, 48, }, 641 { 19200, 24, }, 642 { 38400, 12, }, 643 { 57600, 8, }, 644 { 115200, 4, }, 645 { 153600, 3, }, 646 { 230400, 2, }, 647 { 460800, 1, }, 648 { -1, -1 } 649}; 650static struct speedtab comspeedtab_rsb384[] = { 651 { 300, 3840, }, 652 { 600, 1920, }, 653 { 1200, 960, }, 654 { 2400, 480, }, 655 { 4800, 240, }, 656 { 9600, 120, }, 657 { 19200, 60, }, 658 { 38400, 30, }, 659 { 57600, 20, }, 660 { 115200, 10, }, 661 { 128000, 9, }, 662 { 144000, 8, }, 663 { 192000, 6, }, 664 { 230400, 5, }, 665 { 288000, 4, }, 666 { 384000, 3, }, 667 { 576000, 2, }, 668 { 1152000, 1, }, 669 { -1, -1 } 670}; 671static struct speedtab comspeedtab_rsa[] = { 672 { 0, 0 }, 673 { 50, COMBRD_RSA(50) }, 674 { 75, COMBRD_RSA(75) }, 675 { 110, COMBRD_RSA(110) }, 676 { 134, COMBRD_RSA(134) }, 677 { 150, COMBRD_RSA(150) }, 678 { 200, COMBRD_RSA(200) }, 679 { 300, COMBRD_RSA(300) }, 680 { 600, COMBRD_RSA(600) }, 681 { 1200, COMBRD_RSA(1200) }, 682 { 1800, COMBRD_RSA(1800) }, 683 { 2400, COMBRD_RSA(2400) }, 684 { 4800, COMBRD_RSA(4800) }, 685 { 9600, COMBRD_RSA(9600) }, 686 { 19200, COMBRD_RSA(19200) }, 687 { 38400, COMBRD_RSA(38400) }, 688 { 57600, COMBRD_RSA(57600) }, 689 { 115200, COMBRD_RSA(115200) }, 690 { 230400, COMBRD_RSA(230400) }, 691 { 460800, COMBRD_RSA(460800) }, 692 { 921600, COMBRD_RSA(921600) }, 693 { -1, -1 } 694}; 695#endif /* PC98 */ 696 697static struct speedtab comspeedtab[] = { 698 { 0, 0 }, 699 { 50, COMBRD(50) }, 700 { 75, COMBRD(75) }, 701 { 110, COMBRD(110) }, 702 { 134, COMBRD(134) }, 703 { 150, COMBRD(150) }, 704 { 200, COMBRD(200) }, 705 { 300, COMBRD(300) }, 706 { 600, COMBRD(600) }, 707 { 1200, COMBRD(1200) }, 708 { 1800, COMBRD(1800) }, 709 { 2400, COMBRD(2400) }, 710 { 4800, COMBRD(4800) }, 711 { 9600, COMBRD(9600) }, 712 { 19200, COMBRD(19200) }, 713 { 38400, COMBRD(38400) }, 714 { 57600, COMBRD(57600) }, 715 { 115200, COMBRD(115200) }, 716 { -1, -1 } 717}; 718 719#ifdef PC98 720struct { 721 char *name; 722 short port_table[7]; 723 short irr_mask; 724 struct speedtab *speedtab; 725 short check_irq; 726} if_8251_type[] = { 727 /* COM_IF_INTERNAL */ 728 { " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1}, 729 -1, pc98speedtab, 1 }, 730 /* COM_IF_PC9861K_1 */ 731 { " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1}, 732 3, NULL, 1 }, 733 /* COM_IF_PC9861K_2 */ 734 { " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1}, 735 3, NULL, 1 }, 736 /* COM_IF_IND_SS_1 */ 737 { " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1}, 738 3, comspeedtab_mc16550, 1 }, 739 /* COM_IF_IND_SS_2 */ 740 { " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1}, 741 3, comspeedtab_mc16550, 1 }, 742 /* COM_IF_PIO9032B_1 */ 743 { " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1}, 744 7, comspeedtab_pio9032b, 1 }, 745 /* COM_IF_PIO9032B_2 */ 746 { " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1}, 747 7, comspeedtab_pio9032b, 1 }, 748 /* COM_IF_B98_01_1 */ 749 { " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3}, 750 7, comspeedtab_b98_01, 0 }, 751 /* COM_IF_B98_01_2 */ 752 { " (B98-01)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xd5, 0xd7}, 753 7, comspeedtab_b98_01, 0 }, 754}; 755#define PC98SIO_data_port(type) (if_8251_type[type].port_table[0]) 756#define PC98SIO_cmd_port(type) (if_8251_type[type].port_table[1]) 757#define PC98SIO_sts_port(type) (if_8251_type[type].port_table[2]) 758#define PC98SIO_in_modem_port(type) (if_8251_type[type].port_table[3]) 759#define PC98SIO_intr_ctrl_port(type) (if_8251_type[type].port_table[4]) 760#define PC98SIO_baud_rate_port(type) (if_8251_type[type].port_table[5]) 761#define PC98SIO_func_port(type) (if_8251_type[type].port_table[6]) 762 763#define I8251F_data 0x130 764#define I8251F_lsr 0x132 765#define I8251F_msr 0x134 766#define I8251F_iir 0x136 767#define I8251F_fcr 0x138 768#define I8251F_div 0x13a 769 770 771struct { 772 char *name; 773 short irr_read; 774 short irr_write; 775 short port_shift; 776 short io_size; 777 struct speedtab *speedtab; 778} if_16550a_type[] = { 779 /* COM_IF_RSA98 */ 780 { " (RSA-98)", -1, -1, 0, IO_COMSIZE, comspeedtab }, 781 /* COM_IF_NS16550 */ 782 { "", -1, -1, 0, IO_COMSIZE, comspeedtab }, 783 /* COM_IF_SECOND_CCU */ 784 { "", -1, -1, 0, IO_COMSIZE, comspeedtab }, 785 /* COM_IF_MC16550II */ 786 { " (MC16550II)", -1, 0x1000, 8, 1, comspeedtab_mc16550 }, 787 /* COM_IF_MCRS98 */ 788 { " (MC-RS98)", -1, 0x1000, 8, 1, comspeedtab_mc16550 }, 789 /* COM_IF_RSB3000 */ 790 { " (RSB-3000)", 0xbf, -1, 1, 1, comspeedtab_rsb384 }, 791 /* COM_IF_RSB384 */ 792 { " (RSB-384)", 0xbf, -1, 1, 1, comspeedtab_rsb384 }, 793 /* COM_IF_MODEM_CARD */ 794 { "", -1, -1, 0, IO_COMSIZE, comspeedtab }, 795 /* COM_IF_RSA98III */ 796 { " (RSA-98III)", -1, -1, 0, 16, comspeedtab_rsa }, 797 /* COM_IF_ESP98 */ 798 { " (ESP98)", -1, -1, 1, 1, comspeedtab_mc16550 }, 799}; 800#endif /* PC98 */ 801 802#ifdef COM_ESP 803#ifdef PC98 804 805/* XXX configure this properly. */ 806static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 }; 807static Port_t likely_esp_ports[] = { 0xc0d0, 0 }; 808 809#define ESP98_CMD1 (ESP_CMD1 * 0x100) 810#define ESP98_CMD2 (ESP_CMD2 * 0x100) 811#define ESP98_STATUS1 (ESP_STATUS1 * 0x100) 812#define ESP98_STATUS2 (ESP_STATUS2 * 0x100) 813 814#else /* PC98 */ 815 816/* XXX configure this properly. */ 817static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, }; 818static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 }; 819 820#endif /* PC98 */ 821#endif 822 823/* 824 * handle sysctl read/write requests for console speed 825 * 826 * In addition to setting comdefaultrate for I/O through /dev/console, 827 * also set the initial and lock values for the /dev/ttyXX device 828 * if there is one associated with the console. Finally, if the /dev/tty 829 * device has already been open, change the speed on the open running port 830 * itself. 831 */ 832 833static int 834sysctl_machdep_comdefaultrate SYSCTL_HANDLER_ARGS 835{ 836 int error, s; 837 speed_t newspeed; 838 struct com_s *com; 839 struct tty *tp; 840 841 newspeed = comdefaultrate; 842 843 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req); 844 if (error || !req->newptr) 845 return (error); 846 847 comdefaultrate = newspeed; 848 849 if (comconsole < 0) /* serial console not selected? */ 850 return (0); 851 852 com = com_addr(comconsole); 853 if (!com) 854 return (ENXIO); 855 856 /* 857 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX 858 * (note, the lock rates really are boolean -- if non-zero, disallow 859 * speed changes) 860 */ 861 com->it_in.c_ispeed = com->it_in.c_ospeed = 862 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 863 com->it_out.c_ispeed = com->it_out.c_ospeed = 864 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate; 865 866 /* 867 * if we're open, change the running rate too 868 */ 869 tp = com->tp; 870 if (tp && (tp->t_state & TS_ISOPEN)) { 871 tp->t_termios.c_ispeed = 872 tp->t_termios.c_ospeed = comdefaultrate; 873 s = spltty(); 874 error = comparam(tp, &tp->t_termios); 875 splx(s); 876 } 877 return error; 878} 879 880SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW, 881 0, 0, sysctl_machdep_comdefaultrate, "I", ""); 882 883#define SET_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) | (bit)) 884#define CLR_FLAG(dev, bit) device_set_flags(dev, device_get_flags(dev) & ~(bit)) 885 886#if NCARD > 0 887static int 888sio_pccard_probe(dev) 889 device_t dev; 890{ 891 /* Do not probe IRQ - pccard doesn't turn on the interrupt line */ 892 /* until bus_setup_intr */ 893 SET_FLAG(dev, COM_C_NOPROBE); 894 895 return (sioprobe(dev)); 896} 897 898static int 899sio_pccard_attach(dev) 900 device_t dev; 901{ 902 return (sioattach(dev)); 903} 904 905/* 906 * sio_detach - unload the driver and clear the table. 907 * XXX TODO: 908 * This is usually called when the card is ejected, but 909 * can be caused by a modunload of a controller driver. 910 * The idea is to reset the driver's view of the device 911 * and ensure that any driver entry points such as 912 * read and write do not hang. 913 */ 914static int 915sio_pccard_detach(dev) 916 device_t dev; 917{ 918 struct com_s *com; 919 920 com = (struct com_s *) device_get_softc(dev); 921 if (!com) { 922 device_printf(dev, "NULL com in siounload\n"); 923 return (0); 924 } 925 if (!com->iobase) { 926 device_printf(dev, "already unloaded!\n"); 927 return (0); 928 } 929 com->gone = 1; 930 if (com->irqres) { 931 bus_teardown_intr(dev, com->irqres, com->cookie); 932 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres); 933 } 934 if (com->ioportres) 935 bus_release_resource(dev, SYS_RES_IOPORT, 0, com->ioportres); 936 if (com->tp && (com->tp->t_state & TS_ISOPEN)) { 937 device_printf(dev, "unload\n"); 938 com->tp->t_gen++; 939 ttyclose(com->tp); 940 ttwakeup(com->tp); 941 ttwwakeup(com->tp); 942 device_printf(dev, "Was busy, so crash likely\n"); 943 } else { 944 if (com->ibuf != NULL) 945 free(com->ibuf, M_DEVBUF); 946 device_printf(dev, "unload, gone\n"); 947 } 948 return (0); 949} 950#endif /* NCARD > 0 */ 951 952 953static struct isa_pnp_id sio_ids[] = { 954 {0x0005d041, "Standard PC COM port"}, /* PNP0500 */ 955 {0x0105d041, "16550A-compatible COM port"}, /* PNP0501 */ 956 {0x0205d041, "Multiport serial device (non-intelligent 16550)"}, /* PNP0502 */ 957 {0x1005d041, "Generic IRDA-compatible device"}, /* PNP0510 */ 958 {0x1105d041, "Generic IRDA-compatible device"}, /* PNP0511 */ 959 /* Devices that do not have a compatid */ 960 {0x7602a904, NULL}, /* AEI0276 - 56K v.90 Fax Modem (LKT) */ 961 {0x00007905, NULL}, /* AKY0000 - 56K Plug&Play Modem */ 962 {0x01405407, NULL}, /* AZT4001 - AZT3000 PnP SOUND DEVICE, MODEM */ 963 {0x56039008, NULL}, /* BDP0356 - Best Data 56x2 */ 964 {0x36339008, NULL}, /* BDP3336 - Best Data Prods. 336F */ 965 {0x0014490a, NULL}, /* BRI1400 - Boca 33.6 PnP */ 966 {0x0015490a, NULL}, /* BRI1500 - Internal Fax Data */ 967 {0x0034490a, NULL}, /* BRI3400 - Internal ACF Modem */ 968 {0x00b4490a, NULL}, /* BRIB400 - Boca 56k PnP */ 969 {0x0030320d, NULL}, /* CIR3000 - Cirrus Logic V43 */ 970 {0x0100440e, NULL}, /* CRD0001 - Cardinal MVP288IV ? */ 971 {0x1200c31e, NULL}, /* GVC0012 - VF1128HV-R9 (win modem?) */ 972 {0x0303c31e, NULL}, /* GVC0303 - MaxTech 33.6 PnP D/F/V */ 973 {0x0505c31e, NULL}, /* GVC0505 - GVC 56k Faxmodem */ 974 {0x0050c31e, NULL}, /* GVC5000 - some GVC modem */ 975 {0x3800f91e, NULL}, /* GWY0038 - Telepath with v.90 */ 976 {0x9062f91e, NULL}, /* GWY6290 - Telepath with x2 Technology */ 977 {0x0000f435, NULL}, /* MOT0000 - Motorola ModemSURFR 33.6 Intern */ 978 {0x5015f435, NULL}, /* MOT1550 - Motorola ModemSURFR 56K Modem */ 979 {0xf015f435, NULL}, /* MOT15F0 - Motorola VoiceSURFR 56K Modem */ 980 {0x6045f435, NULL}, /* MOT4560 - Motorola ? */ 981 {0x61e7a338, NULL}, /* NECE761 - 33.6Modem */ 982 {0x39804f3f, NULL}, /* OZO8039 - Zoom 56k flex */ 983 {0x3024a341, NULL}, /* PMC2430 - Pace 56 Voice Internal Modem */ 984 {0x1000eb49, NULL}, /* ROK0010 - Rockwell ? */ 985 {0x5002734a, NULL}, /* RSS0250 - 5614Jx3(G) Internal Modem */ 986 {0xc100ad4d, NULL}, /* SMM00C1 - Leopard 56k PnP */ 987 {0x9012b04e, NULL}, /* SUP1290 - Supra ? */ 988 {0x1013b04e, NULL}, /* SUP1310 - SupraExpress 336i PnP */ 989 {0x8013b04e, NULL}, /* SUP1380 - SupraExpress 288i PnP Voice */ 990 {0x8113b04e, NULL}, /* SUP1381 - SupraExpress 336i PnP Voice */ 991 {0x5016b04e, NULL}, /* SUP1650 - Supra 336i Sp Intl */ 992 {0x7420b04e, NULL}, /* SUP2070 - Supra ? */ 993 {0x8020b04e, NULL}, /* SUP2080 - Supra ? */ 994 {0x8420b04e, NULL}, /* SUP2084 - SupraExpress 56i PnP */ 995 {0x7121b04e, NULL}, /* SUP2171 - SupraExpress 56i Sp? */ 996 {0x8024b04e, NULL}, /* SUP2480 - Supra ? */ 997 {0x01007256, NULL}, /* USR0001 - U.S. Robotics Inc., Sportster W */ 998 {0x02007256, NULL}, /* USR0002 - U.S. Robotics Inc. Sportster 33. */ 999 {0x04007256, NULL}, /* USR0004 - USR Sportster 14.4k */ 1000 {0x06007256, NULL}, /* USR0006 - USR Sportster 33.6k */ 1001 {0x11007256, NULL}, /* USR0011 - USR ? */ 1002 {0x01017256, NULL}, /* USR0101 - USR ? */ 1003 {0x30207256, NULL}, /* USR2030 - U.S.Robotics Inc. Sportster 560 */ 1004 {0x50207256, NULL}, /* USR2050 - U.S.Robotics Inc. Sportster 33. */ 1005 {0x70207256, NULL}, /* USR2070 - U.S.Robotics Inc. Sportster 560 */ 1006 {0x30307256, NULL}, /* USR3030 - U.S. Robotics 56K FAX INT */ 1007 {0x31307256, NULL}, /* USR3031 - U.S. Robotics 56K FAX INT */ 1008 {0x70307256, NULL}, /* USR3070 - U.S. Robotics 56K Voice INT */ 1009 {0x90307256, NULL}, /* USR3090 - USR ? */ 1010 {0x90917256, NULL}, /* USR9190 - USR 56k Voice INT */ 1011 {0x0300695c, NULL}, /* WCI0003 - Fax/Voice/Modem/Speakphone/Asvd */ 1012 {0x61f7896a, NULL}, /* ZTIF761 - Zoom ComStar 33.6 */ 1013#ifdef PC98 1014 {0x0100e4a5, "RSA-98III"}, 1015#endif 1016 {0} 1017}; 1018 1019 1020 1021static int 1022sio_isa_probe(dev) 1023 device_t dev; 1024{ 1025#ifdef PC98 1026 int logical_id; 1027#endif 1028 /* Check isapnp ids */ 1029 if (ISA_PNP_PROBE(device_get_parent(dev), dev, sio_ids) == ENXIO) 1030 return (ENXIO); 1031#ifdef PC98 1032 logical_id = isa_get_logicalid(dev); 1033 if (logical_id == 0x0100e4a5) /* RSA-98III */ 1034 device_set_flags(dev, COM_IF_RSA98III << 24); 1035#endif 1036 return (sioprobe(dev)); 1037} 1038 1039static int 1040sioprobe(dev) 1041 device_t dev; 1042{ 1043#if 0 1044 static bool_t already_init; 1045 device_t xdev; 1046#endif 1047 bool_t failures[10]; 1048 int fn; 1049 device_t idev; 1050 Port_t iobase; 1051 intrmask_t irqmap[4]; 1052 intrmask_t irqs; 1053 u_char mcr_image; 1054 int result; 1055 u_long xirq; 1056 u_int flags = device_get_flags(dev); 1057 int rid; 1058 struct resource *port; 1059#ifdef PC98 1060 int irqout=0; 1061 int tmp; 1062 int port_shift = 0; 1063 struct siodev iod; 1064 Port_t rsabase; 1065#endif 1066 1067 rid = 0; 1068#ifdef PC98 1069 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1070 0, ~0, 1, RF_ACTIVE); /* XXX */ 1071#else 1072 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1073 0, ~0, IO_COMSIZE, RF_ACTIVE); 1074#endif 1075 if (!port) 1076 return ENXIO; 1077 1078#if 0 1079 /* 1080 * XXX this is broken - when we are first called, there are no 1081 * previously configured IO ports. We could hard code 1082 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse. 1083 * This code has been doing nothing since the conversion since 1084 * "count" is zero the first time around. 1085 */ 1086 if (!already_init) { 1087 /* 1088 * Turn off MCR_IENABLE for all likely serial ports. An unused 1089 * port with its MCR_IENABLE gate open will inhibit interrupts 1090 * from any used port that shares the interrupt vector. 1091 * XXX the gate enable is elsewhere for some multiports. 1092 */ 1093 device_t *devs; 1094 int count, i, xioport; 1095#ifdef PC98 1096 int xiftype; 1097#endif 1098 1099 devclass_get_devices(sio_devclass, &devs, &count); 1100#ifdef PC98 1101 for (i = 0; i < count; i++) { 1102 xdev = devs[i]; 1103 xioport = bus_get_resource_start(xdev, SYS_RES_IOPORT, 0); 1104 xiftype = GET_IFTYPE(device_get_flags(xdev)); 1105 if (device_is_enabled(xdev) && xioport > 0) { 1106 if (IS_8251(xiftype)) 1107 outb(xioport & 0xff00) | PC98SIO_cmd_port(xiftype & 0x0f), 0xf2); 1108 else { 1109 if (xiftype == COM_IF_RSA98III) 1110 xioport += 8; 1111 outb(xioport + (com_mcr << if_16550a_type[xiftype & 0x0f].port_shift), 0); 1112 } 1113 } 1114 } 1115#else 1116 for (i = 0; i < count; i++) { 1117 xdev = devs[i]; 1118 if (device_is_enabled(xdev) && 1119 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport, 1120 NULL) == 0) 1121 outb(xioport + com_mcr, 0); 1122 } 1123#endif 1124 free(devs, M_TEMP); 1125 already_init = TRUE; 1126 } 1127#endif 1128 1129 if (COM_LLCONSOLE(flags)) { 1130 printf("sio%d: reserved for low-level i/o\n", 1131 device_get_unit(dev)); 1132 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1133 return (ENXIO); 1134 } 1135 1136#ifdef PC98 1137 DELAY(10); 1138 1139 /* 1140 * If the port is i8251 UART (internal, B98_01) 1141 */ 1142 if (pc98_check_if_type(dev, &iod) == -1) 1143 return ENXIO; 1144 if (iod.irq > 0) 1145 bus_set_resource(dev, SYS_RES_IRQ, 0, iod.irq, 1); 1146 if (IS_8251(iod.if_type)) { 1147 outb(iod.cmd, 0); 1148 DELAY(10); 1149 outb(iod.cmd, 0); 1150 DELAY(10); 1151 outb(iod.cmd, 0); 1152 DELAY(10); 1153 outb(iod.cmd, CMD8251_RESET); 1154 DELAY(1000); /* for a while...*/ 1155 outb(iod.cmd, 0xf2); /* MODE (dummy) */ 1156 DELAY(10); 1157 outb(iod.cmd, 0x01); /* CMD (dummy) */ 1158 DELAY(1000); /* for a while...*/ 1159 if (( inb(iod.sts) & STS8251_TxEMP ) == 0 ) { 1160 result = ENXIO; 1161 } 1162 if (if_8251_type[iod.if_type & 0x0f].check_irq) { 1163 COM_INT_DISABLE 1164 tmp = ( inb( iod.ctrl ) & ~(IEN_Rx|IEN_TxEMP|IEN_Tx)); 1165 outb( iod.ctrl, tmp|IEN_TxEMP ); 1166 DELAY(10); 1167 result = isa_irq_pending() ? 0 : ENXIO; 1168 outb( iod.ctrl, tmp ); 1169 COM_INT_ENABLE 1170 } else { 1171 /* 1172 * B98_01 doesn't activate TxEMP interrupt line 1173 * when being reset, so we can't check irq pending. 1174 */ 1175 result = 0; 1176 } 1177 if (epson_machine_id==0x20) { /* XXX */ 1178 result = 0; 1179 } 1180 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1181 return result; 1182 } 1183#endif /* PC98 */ 1184 /* 1185 * If the device is on a multiport card and has an AST/4 1186 * compatible interrupt control register, initialize this 1187 * register and prepare to leave MCR_IENABLE clear in the mcr. 1188 * Otherwise, prepare to set MCR_IENABLE in the mcr. 1189 * Point idev to the device struct giving the correct id_irq. 1190 * This is the struct for the master device if there is one. 1191 */ 1192 idev = dev; 1193 mcr_image = MCR_IENABLE; 1194#ifdef COM_MULTIPORT 1195 if (COM_ISMULTIPORT(flags)) { 1196 Port_t xiobase; 1197 u_long io; 1198 1199 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags)); 1200 if (idev == NULL) { 1201 printf("sio%d: master device %d not configured\n", 1202 device_get_unit(dev), COM_MPMASTER(flags)); 1203 idev = dev; 1204 } 1205#ifndef PC98 1206 if (!COM_NOTAST4(flags)) { 1207 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io, 1208 NULL) == 0) { 1209 xiobase = io; 1210 if (bus_get_resource(idev, SYS_RES_IRQ, 0, 1211 NULL, NULL) == 0) 1212 outb(xiobase + com_scr, 0x80); 1213 else 1214 outb(xiobase + com_scr, 0); 1215 } 1216 mcr_image = 0; 1217 } 1218#endif 1219 } 1220#endif /* COM_MULTIPORT */ 1221 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0) 1222 mcr_image = 0; 1223 1224 bzero(failures, sizeof failures); 1225 iobase = rman_get_start(port); 1226 1227#ifdef PC98 1228 if (iod.if_type == COM_IF_RSA98III) { 1229 mcr_image = 0; 1230 1231 rsabase = iobase & 0xfff0; 1232 if (rsabase != iobase) 1233 return(0); 1234 iobase += 8; 1235 1236 outb(rsabase + rsa_msr, 0x04); 1237 outb(rsabase + rsa_frr, 0x00); 1238 if ((inb(rsabase + rsa_srr) & 0x36) != 0x36) 1239 return (0); 1240 outb(rsabase + rsa_ier, 0x00); 1241 outb(rsabase + rsa_frr, 0x00); 1242 outb(rsabase + rsa_tivsr, 0x00); 1243 outb(rsabase + rsa_tcr, 0x00); 1244 } 1245 1246 tmp = if_16550a_type[iod.if_type & 0x0f].irr_write; 1247 if (tmp != -1) { 1248 /* MC16550II */ 1249 switch (isa_get_irq(idev)) { 1250 case 3: irqout = 4; break; 1251 case 5: irqout = 5; break; 1252 case 6: irqout = 6; break; 1253 case 12: irqout = 7; break; 1254 default: 1255 printf("sio%d: irq configuration error\n", 1256 device_get_unit(dev)); 1257 return (0); 1258 } 1259 outb((isa_get_port(dev) & 0x00ff) | tmp, irqout); 1260 } 1261 port_shift = if_16550a_type[iod.if_type & 0x0f].port_shift; 1262#endif 1263 1264 /* 1265 * We don't want to get actual interrupts, just masked ones. 1266 * Interrupts from this line should already be masked in the ICU, 1267 * but mask them in the processor as well in case there are some 1268 * (misconfigured) shared interrupts. 1269 */ 1270 disable_intr(); 1271/* EXTRA DELAY? */ 1272 1273 /* 1274 * Initialize the speed and the word size and wait long enough to 1275 * drain the maximum of 16 bytes of junk in device output queues. 1276 * The speed is undefined after a master reset and must be set 1277 * before relying on anything related to output. There may be 1278 * junk after a (very fast) soft reboot and (apparently) after 1279 * master reset. 1280 * XXX what about the UART bug avoided by waiting in comparam()? 1281 * We don't want to to wait long enough to drain at 2 bps. 1282 */ 1283 if (iobase == siocniobase) 1284 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10)); 1285 else { 1286#ifdef PC98 1287 tmp = ttspeedtab(SIO_TEST_SPEED, 1288 if_16550a_type[iod.if_type & 0x0f].speedtab); 1289 outb(iobase + (com_cfcr << port_shift), CFCR_DLAB|CFCR_8BITS); 1290 outb(iobase + (com_dlbl << port_shift), tmp & 0xff); 1291 outb(iobase + (com_dlbh << port_shift), (tmp >> 8) & 0xff); 1292 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS); 1293#else 1294 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 1295 outb(iobase + com_dlbl, COMBRD(SIO_TEST_SPEED) & 0xff); 1296 outb(iobase + com_dlbh, (u_int) COMBRD(SIO_TEST_SPEED) >> 8); 1297 outb(iobase + com_cfcr, CFCR_8BITS); 1298#endif 1299 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10)); 1300 } 1301 1302 /* 1303 * Enable the interrupt gate and disable device interupts. This 1304 * should leave the device driving the interrupt line low and 1305 * guarantee an edge trigger if an interrupt can be generated. 1306 */ 1307/* EXTRA DELAY? */ 1308#ifdef PC98 1309 outb(iobase + (com_mcr << port_shift), mcr_image); 1310 outb(iobase + (com_ier << port_shift), 0); 1311#else 1312 outb(iobase + com_mcr, mcr_image); 1313 outb(iobase + com_ier, 0); 1314#endif 1315 DELAY(1000); /* XXX */ 1316 irqmap[0] = isa_irq_pending(); 1317 1318 /* 1319 * Attempt to set loopback mode so that we can send a null byte 1320 * without annoying any external device. 1321 */ 1322/* EXTRA DELAY? */ 1323#ifdef PC98 1324 outb(iobase + (com_mcr << port_shift), mcr_image | MCR_LOOPBACK); 1325#else 1326 outb(iobase + com_mcr, mcr_image | MCR_LOOPBACK); 1327#endif 1328 1329 /* 1330 * Attempt to generate an output interrupt. On 8250's, setting 1331 * IER_ETXRDY generates an interrupt independent of the current 1332 * setting and independent of whether the THR is empty. On 16450's, 1333 * setting IER_ETXRDY generates an interrupt independent of the 1334 * current setting. On 16550A's, setting IER_ETXRDY only 1335 * generates an interrupt when IER_ETXRDY is not already set. 1336 */ 1337#ifdef PC98 1338 outb(iobase + (com_ier << port_shift), IER_ETXRDY); 1339 if (iod.if_type == COM_IF_RSA98III) 1340 outb(rsabase + rsa_ier, 0x04); 1341#else 1342 outb(iobase + com_ier, IER_ETXRDY); 1343#endif /* PC98 */ 1344 1345 /* 1346 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate 1347 * an interrupt. They'd better generate one for actually doing 1348 * output. Loopback may be broken on the same incompatibles but 1349 * it's unlikely to do more than allow the null byte out. 1350 */ 1351#ifdef PC98 1352 outb(iobase + (com_data << port_shift), 0); 1353#else 1354 outb(iobase + com_data, 0); 1355#endif 1356 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10)); 1357 1358 /* 1359 * Turn off loopback mode so that the interrupt gate works again 1360 * (MCR_IENABLE was hidden). This should leave the device driving 1361 * an interrupt line high. It doesn't matter if the interrupt 1362 * line oscillates while we are not looking at it, since interrupts 1363 * are disabled. 1364 */ 1365/* EXTRA DELAY? */ 1366#ifdef PC98 1367 outb(iobase + (com_mcr << port_shift), mcr_image); 1368#else 1369 outb(iobase + com_mcr, mcr_image); 1370#endif /* PC98 */ 1371 1372 /* 1373 * Some pcmcia cards have the "TXRDY bug", so we check everyone 1374 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... ) 1375 */ 1376 if (COM_NOPROBE(flags)) { 1377 /* Reading IIR register twice */ 1378 for (fn = 0; fn < 2; fn ++) { 1379 DELAY(10000); 1380#ifdef PC98 1381 failures[6] = inb(iobase + (com_iir << port_shift)); 1382#else 1383 failures[6] = inb(iobase + com_iir); 1384#endif 1385 } 1386 /* Check IIR_TXRDY clear ? */ 1387 result = 0; 1388 if (failures[6] & IIR_TXRDY) { 1389 /* Nop, Double check with clearing IER */ 1390#ifdef PC98 1391 outb(iobase + (com_ier << port_shift), 0); 1392 if (inb(iobase + (com_iir << port_shift)) 1393 & IIR_NOPEND) { 1394#else 1395 outb(iobase + com_ier, 0); 1396 if (inb(iobase + com_iir) & IIR_NOPEND) { 1397#endif 1398 /* Ok. we're familia this gang */ 1399 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); 1400 } else { 1401 /* Unknown, Just omit this chip.. XXX */ 1402 result = ENXIO; 1403 } 1404 } else { 1405 /* OK. this is well-known guys */ 1406 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); 1407 } 1408#ifdef PC98 1409 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS); 1410#else 1411 outb(iobase + com_cfcr, CFCR_8BITS); 1412#endif 1413 enable_intr(); 1414 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1415 return (iobase == siocniobase ? 0 : result); 1416 } 1417 1418 /* 1419 * Check that 1420 * o the CFCR, IER and MCR in UART hold the values written to them 1421 * (the values happen to be all distinct - this is good for 1422 * avoiding false positive tests from bus echoes). 1423 * o an output interrupt is generated and its vector is correct. 1424 * o the interrupt goes away when the IIR in the UART is read. 1425 */ 1426/* EXTRA DELAY? */ 1427#ifdef PC98 1428 failures[0] = inb(iobase + (com_cfcr << port_shift)) - CFCR_8BITS; 1429 failures[1] = inb(iobase + (com_ier << port_shift)) - IER_ETXRDY; 1430 failures[2] = inb(iobase + (com_mcr << port_shift)) - mcr_image; 1431#else 1432 failures[0] = inb(iobase + com_cfcr) - CFCR_8BITS; 1433 failures[1] = inb(iobase + com_ier) - IER_ETXRDY; 1434 failures[2] = inb(iobase + com_mcr) - mcr_image; 1435#endif 1436 DELAY(10000); /* Some internal modems need this time */ 1437 irqmap[1] = isa_irq_pending(); 1438#ifdef PC98 1439 failures[4] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK) 1440 - IIR_TXRDY; 1441 if (iod.if_type == COM_IF_RSA98III) 1442 inb(rsabase + rsa_srr); 1443#else 1444 failures[4] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_TXRDY; 1445#endif 1446 DELAY(1000); /* XXX */ 1447 irqmap[2] = isa_irq_pending(); 1448#ifdef PC98 1449 failures[6] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK) 1450 - IIR_NOPEND; 1451 if (iod.if_type == COM_IF_RSA98III) 1452 inb(rsabase + rsa_srr); 1453#else 1454 failures[6] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND; 1455#endif 1456 1457 /* 1458 * Turn off all device interrupts and check that they go off properly. 1459 * Leave MCR_IENABLE alone. For ports without a master port, it gates 1460 * the OUT2 output of the UART to 1461 * the ICU input. Closing the gate would give a floating ICU input 1462 * (unless there is another device driving it) and spurious interrupts. 1463 * (On the system that this was first tested on, the input floats high 1464 * and gives a (masked) interrupt as soon as the gate is closed.) 1465 */ 1466#ifdef PC98 1467 outb(iobase + (com_ier << port_shift), 0); 1468 outb(iobase + (com_cfcr << port_shift), CFCR_8BITS); 1469 failures[7] = inb(iobase + (com_ier << port_shift)); 1470 if (iod.if_type == COM_IF_RSA98III) 1471 outb(rsabase + rsa_ier, 0x00); 1472#else 1473 outb(iobase + com_ier, 0); 1474 outb(iobase + com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */ 1475 failures[7] = inb(iobase + com_ier); 1476#endif 1477 DELAY(1000); /* XXX */ 1478 irqmap[3] = isa_irq_pending(); 1479#ifdef PC98 1480 failures[9] = (inb(iobase + (com_iir << port_shift)) & IIR_IMASK) 1481 - IIR_NOPEND; 1482 if (iod.if_type == COM_IF_RSA98III) { 1483 inb(rsabase + rsa_srr); 1484 outb(rsabase + rsa_frr, 0x00); 1485 } 1486#else 1487 failures[9] = (inb(iobase + com_iir) & IIR_IMASK) - IIR_NOPEND; 1488#endif 1489 1490 enable_intr(); 1491 1492 irqs = irqmap[1] & ~irqmap[0]; 1493 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 && 1494 ((1 << xirq) & irqs) == 0) 1495 printf( 1496 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n", 1497 device_get_unit(dev), xirq, irqs); 1498 if (bootverbose) 1499 printf("sio%d: irq maps: %#x %#x %#x %#x\n", 1500 device_get_unit(dev), 1501 irqmap[0], irqmap[1], irqmap[2], irqmap[3]); 1502 1503 result = 0; 1504 for (fn = 0; fn < sizeof failures; ++fn) 1505 if (failures[fn]) { 1506#ifdef PC98 1507 outb(iobase + (com_mcr << port_shift), 0); 1508#else 1509 outb(iobase + com_mcr, 0); 1510#endif 1511 result = ENXIO; 1512 if (bootverbose) { 1513 printf("sio%d: probe failed test(s):", 1514 device_get_unit(dev)); 1515 for (fn = 0; fn < sizeof failures; ++fn) 1516 if (failures[fn]) 1517 printf(" %d", fn); 1518 printf("\n"); 1519 } 1520 break; 1521 } 1522 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1523 return (iobase == siocniobase ? 0 : result); 1524} 1525 1526#ifdef COM_ESP 1527static int 1528espattach(com, esp_port) 1529 struct com_s *com; 1530 Port_t esp_port; 1531{ 1532 u_char dips; 1533 u_char val; 1534 1535 /* 1536 * Check the ESP-specific I/O port to see if we're an ESP 1537 * card. If not, return failure immediately. 1538 */ 1539 if ((inb(esp_port) & 0xf3) == 0) { 1540 printf(" port 0x%x is not an ESP board?\n", esp_port); 1541 return (0); 1542 } 1543 1544 /* 1545 * We've got something that claims to be a Hayes ESP card. 1546 * Let's hope so. 1547 */ 1548 1549 /* Get the dip-switch configuration */ 1550#ifdef PC98 1551 outb(esp_port + ESP98_CMD1, ESP_GETDIPS); 1552 dips = inb(esp_port + ESP98_STATUS1); 1553#else 1554 outb(esp_port + ESP_CMD1, ESP_GETDIPS); 1555 dips = inb(esp_port + ESP_STATUS1); 1556#endif 1557 1558 /* 1559 * Bits 0,1 of dips say which COM port we are. 1560 */ 1561#ifdef PC98 1562 if ((com->iobase & 0xff) == likely_com_ports[dips & 0x03]) 1563#else 1564 if (com->iobase == likely_com_ports[dips & 0x03]) 1565#endif 1566 printf(" : ESP"); 1567 else { 1568 printf(" esp_port has com %d\n", dips & 0x03); 1569 return (0); 1570 } 1571 1572 /* 1573 * Check for ESP version 2.0 or later: bits 4,5,6 = 010. 1574 */ 1575#ifdef PC98 1576 outb(esp_port + ESP98_CMD1, ESP_GETTEST); 1577 val = inb(esp_port + ESP98_STATUS1); /* clear reg 1 */ 1578 val = inb(esp_port + ESP98_STATUS2); 1579#else 1580 outb(esp_port + ESP_CMD1, ESP_GETTEST); 1581 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */ 1582 val = inb(esp_port + ESP_STATUS2); 1583#endif 1584 if ((val & 0x70) < 0x20) { 1585 printf("-old (%o)", val & 0x70); 1586 return (0); 1587 } 1588 1589 /* 1590 * Check for ability to emulate 16550: bit 7 == 1 1591 */ 1592 if ((dips & 0x80) == 0) { 1593 printf(" slave"); 1594 return (0); 1595 } 1596 1597 /* 1598 * Okay, we seem to be a Hayes ESP card. Whee. 1599 */ 1600 com->esp = TRUE; 1601 com->esp_port = esp_port; 1602 return (1); 1603} 1604#endif /* COM_ESP */ 1605 1606static int 1607sio_isa_attach(dev) 1608 device_t dev; 1609{ 1610 return (sioattach(dev)); 1611} 1612 1613static int 1614sioattach(dev) 1615 device_t dev; 1616{ 1617 struct com_s *com; 1618#ifdef COM_ESP 1619 Port_t *espp; 1620#endif 1621 Port_t iobase; 1622 int unit; 1623 u_int flags; 1624 int rid; 1625 struct resource *port; 1626 int ret; 1627#ifdef PC98 1628 int port_shift = 0; 1629 u_char *obuf; 1630 u_long obufsize; 1631#endif 1632 1633 rid = 0; 1634#ifdef PC98 1635 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1636 0, ~0, 1, RF_ACTIVE); /* XXX */ 1637#else 1638 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1639 0, ~0, IO_COMSIZE, RF_ACTIVE); 1640#endif 1641 if (!port) 1642 return ENXIO; 1643 1644 iobase = rman_get_start(port); 1645 unit = device_get_unit(dev); 1646 com = device_get_softc(dev); 1647 flags = device_get_flags(dev); 1648 1649 if (unit >= sio_numunits) 1650 sio_numunits = unit + 1; 1651 1652#ifdef PC98 1653 obufsize = 256; 1654 if (GET_IFTYPE(flags) == COM_IF_RSA98III) { 1655 iobase += 8; 1656 obufsize = 2048; 1657 } 1658 if ((obuf = malloc(obufsize * 2, M_DEVBUF, M_NOWAIT)) == NULL) 1659 return ENXIO; 1660 bzero(obuf, obufsize * 2); 1661#endif 1662 1663 /* 1664 * sioprobe() has initialized the device registers as follows: 1665 * o cfcr = CFCR_8BITS. 1666 * It is most important that CFCR_DLAB is off, so that the 1667 * data port is not hidden when we enable interrupts. 1668 * o ier = 0. 1669 * Interrupts are only enabled when the line is open. 1670 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible 1671 * interrupt control register or the config specifies no irq. 1672 * Keeping MCR_DTR and MCR_RTS off might stop the external 1673 * device from sending before we are ready. 1674 */ 1675 bzero(com, sizeof *com); 1676#ifdef PC98 1677 com->obufsize = obufsize; 1678 com->obuf1 = obuf; 1679 com->obuf2 = obuf + obufsize; 1680#endif 1681 com->unit = unit; 1682 com->ioportres = port; 1683 com->cfcr_image = CFCR_8BITS; 1684 com->dtr_wait = 3 * hz; 1685 com->loses_outints = COM_LOSESOUTINTS(flags) != 0; 1686 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0; 1687 com->tx_fifo_size = 1; 1688 com->obufs[0].l_head = com->obuf1; 1689 com->obufs[1].l_head = com->obuf2; 1690 1691 com->iobase = iobase; 1692#ifdef PC98 1693 com->pc98_if_type = GET_IFTYPE(flags); 1694 1695 if (pc98_set_ioport(com) == -1) { 1696 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift; 1697 1698 com->data_port = iobase + (com_data << port_shift); 1699 com->int_id_port = iobase + (com_iir << port_shift); 1700 com->modem_ctl_port = iobase + (com_mcr << port_shift); 1701 com->mcr_image = inb(com->modem_ctl_port); 1702 com->line_status_port = iobase + (com_lsr << port_shift); 1703 com->modem_status_port = iobase + (com_msr << port_shift); 1704 com->intr_ctl_port = iobase + (com_ier << port_shift); 1705 } 1706 if (com->pc98_if_type == COM_IF_INTERNAL && pc98_check_8251fifo()) { 1707 com->pc98_8251fifo = 1; 1708 com->pc98_8251fifo_enable = 0; 1709 } 1710#else /* not PC98 */ 1711 com->data_port = iobase + com_data; 1712 com->int_id_port = iobase + com_iir; 1713 com->modem_ctl_port = iobase + com_mcr; 1714 com->mcr_image = inb(com->modem_ctl_port); 1715 com->line_status_port = iobase + com_lsr; 1716 com->modem_status_port = iobase + com_msr; 1717 com->intr_ctl_port = iobase + com_ier; 1718#endif 1719 1720 /* 1721 * We don't use all the flags from <sys/ttydefaults.h> since they 1722 * are only relevant for logins. It's important to have echo off 1723 * initially so that the line doesn't start blathering before the 1724 * echo flag can be turned off. 1725 */ 1726 com->it_in.c_iflag = 0; 1727 com->it_in.c_oflag = 0; 1728 com->it_in.c_cflag = TTYDEF_CFLAG; 1729 com->it_in.c_lflag = 0; 1730 if (unit == comconsole) { 1731#ifdef PC98 1732 if (IS_8251(com->pc98_if_type)) 1733 DELAY(100000); 1734#endif 1735 com->it_in.c_iflag = TTYDEF_IFLAG; 1736 com->it_in.c_oflag = TTYDEF_OFLAG; 1737 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL; 1738 com->it_in.c_lflag = TTYDEF_LFLAG; 1739 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL; 1740 com->lt_out.c_ispeed = com->lt_out.c_ospeed = 1741 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 1742 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate; 1743 } else 1744 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED; 1745 if (siosetwater(com, com->it_in.c_ispeed) != 0) { 1746 enable_intr(); 1747 /* 1748 * Leave i/o resources allocated if this is a `cn'-level 1749 * console, so that other devices can't snarf them. 1750 */ 1751 if (iobase != siocniobase) 1752 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1753 return (ENOMEM); 1754 } 1755 enable_intr(); 1756 termioschars(&com->it_in); 1757 com->it_out = com->it_in; 1758 1759 /* attempt to determine UART type */ 1760 printf("sio%d: type", unit); 1761 1762 1763#ifndef PC98 1764#ifdef COM_MULTIPORT 1765 if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags)) 1766#else 1767 if (!COM_IIR_TXRDYBUG(flags)) 1768#endif 1769 { 1770 u_char scr; 1771 u_char scr1; 1772 u_char scr2; 1773 1774 scr = inb(iobase + com_scr); 1775 outb(iobase + com_scr, 0xa5); 1776 scr1 = inb(iobase + com_scr); 1777 outb(iobase + com_scr, 0x5a); 1778 scr2 = inb(iobase + com_scr); 1779 outb(iobase + com_scr, scr); 1780 if (scr1 != 0xa5 || scr2 != 0x5a) { 1781 printf(" 8250"); 1782 goto determined_type; 1783 } 1784 } 1785#endif /* !PC98 */ 1786#ifdef PC98 1787 if (IS_8251(com->pc98_if_type)) { 1788 if (com->pc98_8251fifo && !COM_NOFIFO(flags)) 1789 com->tx_fifo_size = 16; 1790 com_int_TxRx_disable( com ); 1791 com_cflag_and_speed_set( com, com->it_in.c_cflag, comdefaultrate ); 1792 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE ); 1793 com_send_break_off( com ); 1794 1795 if (com->pc98_if_type == COM_IF_INTERNAL) { 1796 printf(" (internal%s%s)", 1797 com->pc98_8251fifo ? " fifo" : "", 1798 PC98SIO_baud_rate_port(com->pc98_if_type) != -1 ? 1799 " v-fast" : ""); 1800 } else { 1801 printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name); 1802 } 1803 } else { 1804 outb(iobase + (com_fifo << port_shift), FIFO_ENABLE | FIFO_RX_HIGH); 1805#else 1806 outb(iobase + com_fifo, FIFO_ENABLE | FIFO_RX_HIGH); 1807#endif /* PC98 */ 1808 DELAY(100); 1809 com->st16650a = 0; 1810 switch (inb(com->int_id_port) & IIR_FIFO_MASK) { 1811 case FIFO_RX_LOW: 1812 printf(" 16450"); 1813 break; 1814 case FIFO_RX_MEDL: 1815 printf(" 16450?"); 1816 break; 1817 case FIFO_RX_MEDH: 1818 printf(" 16550?"); 1819 break; 1820 case FIFO_RX_HIGH: 1821 if (COM_NOFIFO(flags)) { 1822 printf(" 16550A fifo disabled"); 1823 } else { 1824 com->hasfifo = TRUE; 1825#ifdef PC98 1826 com->tx_fifo_size = 0; /* XXX flag conflicts. */ 1827 printf(" 16550A"); 1828#else 1829 if (COM_ST16650A(flags)) { 1830 com->st16650a = 1; 1831 com->tx_fifo_size = 32; 1832 printf(" ST16650A"); 1833 } else { 1834 com->tx_fifo_size = COM_FIFOSIZE(flags); 1835 printf(" 16550A"); 1836 } 1837#endif 1838 } 1839#ifdef PC98 1840 if (com->pc98_if_type == COM_IF_RSA98III) { 1841 com->tx_fifo_size = 2048; 1842 com->rsabase = isa_get_port(dev); 1843 outb(com->rsabase + rsa_ier, 0x00); 1844 outb(com->rsabase + rsa_frr, 0x00); 1845 } 1846#endif 1847 1848#ifdef COM_ESP 1849#ifdef PC98 1850 if (com->pc98_if_type == COM_IF_ESP98) 1851#endif 1852 for (espp = likely_esp_ports; *espp != 0; espp++) 1853 if (espattach(com, *espp)) { 1854 com->tx_fifo_size = 1024; 1855 break; 1856 } 1857#endif 1858 if (!com->st16650a) { 1859 if (!com->tx_fifo_size) 1860 com->tx_fifo_size = 16; 1861 else 1862 printf(" lookalike with %d bytes FIFO", 1863 com->tx_fifo_size); 1864 } 1865 1866 break; 1867 } 1868 1869#ifdef PC98 1870 if (com->pc98_if_type == COM_IF_RSB3000) { 1871 /* Set RSB-2000/3000 Extended Buffer mode. */ 1872 u_char lcr; 1873 lcr = inb(iobase + (com_cfcr << port_shift)); 1874 outb(iobase + (com_cfcr << port_shift), lcr | CFCR_DLAB); 1875 outb(iobase + (com_emr << port_shift), EMR_EXBUFF | EMR_EFMODE); 1876 outb(iobase + (com_cfcr << port_shift), lcr); 1877 } 1878#endif 1879 1880#ifdef COM_ESP 1881 if (com->esp) { 1882 /* 1883 * Set 16550 compatibility mode. 1884 * We don't use the ESP_MODE_SCALE bit to increase the 1885 * fifo trigger levels because we can't handle large 1886 * bursts of input. 1887 * XXX flow control should be set in comparam(), not here. 1888 */ 1889#ifdef PC98 1890 outb(com->esp_port + ESP98_CMD1, ESP_SETMODE); 1891 outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1892#else 1893 outb(com->esp_port + ESP_CMD1, ESP_SETMODE); 1894 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1895#endif 1896 1897 /* Set RTS/CTS flow control. */ 1898#ifdef PC98 1899 outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE); 1900 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS); 1901 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS); 1902#else 1903 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE); 1904 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS); 1905 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS); 1906#endif 1907 1908 /* Set flow-control levels. */ 1909#ifdef PC98 1910 outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW); 1911 outb(com->esp_port + ESP98_CMD2, HIBYTE(768)); 1912 outb(com->esp_port + ESP98_CMD2, LOBYTE(768)); 1913 outb(com->esp_port + ESP98_CMD2, HIBYTE(512)); 1914 outb(com->esp_port + ESP98_CMD2, LOBYTE(512)); 1915#else 1916 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW); 1917 outb(com->esp_port + ESP_CMD2, HIBYTE(768)); 1918 outb(com->esp_port + ESP_CMD2, LOBYTE(768)); 1919 outb(com->esp_port + ESP_CMD2, HIBYTE(512)); 1920 outb(com->esp_port + ESP_CMD2, LOBYTE(512)); 1921#endif 1922 1923#ifdef PC98 1924 /* Set UART clock prescaler. */ 1925 outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK); 1926 outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */ 1927#endif 1928 } 1929#endif /* COM_ESP */ 1930#ifdef PC98 1931 printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name); 1932 outb(iobase + (com_fifo << port_shift), 0); 1933#else 1934 outb(iobase + com_fifo, 0); 1935determined_type: ; 1936#endif 1937 1938#ifdef COM_MULTIPORT 1939 if (COM_ISMULTIPORT(flags)) { 1940 device_t masterdev; 1941 1942 com->multiport = TRUE; 1943 printf(" (multiport"); 1944 if (unit == COM_MPMASTER(flags)) 1945 printf(" master"); 1946 printf(")"); 1947 masterdev = devclass_get_device(sio_devclass, 1948 COM_MPMASTER(flags)); 1949 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev, 1950 SYS_RES_IRQ, 0, NULL, NULL) != 0); 1951 } 1952#endif /* COM_MULTIPORT */ 1953#ifdef PC98 1954 } 1955#endif 1956 if (unit == comconsole) 1957 printf(", console"); 1958 if (COM_IIR_TXRDYBUG(flags)) 1959 printf(" with a bogus IIR_TXRDY register"); 1960 printf("\n"); 1961 1962 if (!sio_registered) { 1963 register_swi(SWI_TTY, siopoll); 1964 sio_registered = TRUE; 1965 } 1966 make_dev(&sio_cdevsw, unit, 1967 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit); 1968 make_dev(&sio_cdevsw, unit | CONTROL_INIT_STATE, 1969 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit); 1970 make_dev(&sio_cdevsw, unit | CONTROL_LOCK_STATE, 1971 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit); 1972 make_dev(&sio_cdevsw, unit | CALLOUT_MASK, 1973 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit); 1974 make_dev(&sio_cdevsw, unit | CALLOUT_MASK | CONTROL_INIT_STATE, 1975 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit); 1976 make_dev(&sio_cdevsw, unit | CALLOUT_MASK | CONTROL_LOCK_STATE, 1977 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit); 1978 com->flags = flags; 1979 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1980 pps_init(&com->pps); 1981 1982 rid = 0; 1983 com->irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1, 1984 RF_ACTIVE); 1985 if (com->irqres) { 1986 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres, 1987 INTR_TYPE_TTY | INTR_TYPE_FAST, 1988 siointr, com, &com->cookie); 1989 if (ret) { 1990 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, 1991 com->irqres, INTR_TYPE_TTY, 1992 siointr, com, &com->cookie); 1993 if (ret == 0) 1994 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode"); 1995 } 1996 if (ret) 1997 device_printf(dev, "could not activate interrupt\n"); 1998 } 1999 2000 return (0); 2001} 2002 2003static int 2004sioopen(dev, flag, mode, p) 2005 dev_t dev; 2006 int flag; 2007 int mode; 2008 struct proc *p; 2009{ 2010 struct com_s *com; 2011 int error; 2012 Port_t iobase; 2013 int mynor; 2014 int s; 2015 struct tty *tp; 2016 int unit; 2017#ifdef PC98 2018 int port_shift = 0; 2019#endif 2020 2021 mynor = minor(dev); 2022 unit = MINOR_TO_UNIT(mynor); 2023 com = com_addr(unit); 2024 if (com == NULL) 2025 return (ENXIO); 2026 if (com->gone) 2027 return (ENXIO); 2028 if (mynor & CONTROL_MASK) 2029 return (0); 2030 tp = dev->si_tty = com->tp = ttymalloc(com->tp); 2031 s = spltty(); 2032 2033#ifdef PC98 2034 if (!IS_8251(com->pc98_if_type)) 2035 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift; 2036#endif 2037 /* 2038 * We jump to this label after all non-interrupted sleeps to pick 2039 * up any changes of the device state. 2040 */ 2041open_top: 2042 while (com->state & CS_DTR_OFF) { 2043 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0); 2044 if (com_addr(unit) == NULL) 2045 return (ENXIO); 2046 if (error != 0 || com->gone) 2047 goto out; 2048 } 2049 if (tp->t_state & TS_ISOPEN) { 2050 /* 2051 * The device is open, so everything has been initialized. 2052 * Handle conflicts. 2053 */ 2054 if (mynor & CALLOUT_MASK) { 2055 if (!com->active_out) { 2056 error = EBUSY; 2057 goto out; 2058 } 2059 } else { 2060 if (com->active_out) { 2061 if (flag & O_NONBLOCK) { 2062 error = EBUSY; 2063 goto out; 2064 } 2065 error = tsleep(&com->active_out, 2066 TTIPRI | PCATCH, "siobi", 0); 2067 if (com_addr(unit) == NULL) 2068 return (ENXIO); 2069 if (error != 0 || com->gone) 2070 goto out; 2071 goto open_top; 2072 } 2073 } 2074 if (tp->t_state & TS_XCLUDE && 2075 suser(p)) { 2076 error = EBUSY; 2077 goto out; 2078 } 2079 } else { 2080 /* 2081 * The device isn't open, so there are no conflicts. 2082 * Initialize it. Initialization is done twice in many 2083 * cases: to preempt sleeping callin opens if we are 2084 * callout, and to complete a callin open after DCD rises. 2085 */ 2086 tp->t_oproc = comstart; 2087 tp->t_param = comparam; 2088 tp->t_stop = comstop; 2089 tp->t_dev = dev; 2090 tp->t_termios = mynor & CALLOUT_MASK 2091 ? com->it_out : com->it_in; 2092#ifdef PC98 2093 if (!IS_8251(com->pc98_if_type)) 2094#endif 2095 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET); 2096 com->poll = com->no_irq; 2097 com->poll_output = com->loses_outints; 2098 ++com->wopeners; 2099 error = comparam(tp, &tp->t_termios); 2100 --com->wopeners; 2101 if (error != 0) 2102 goto out; 2103#ifdef PC98 2104 if (IS_8251(com->pc98_if_type)) { 2105 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS); 2106 pc98_msrint_start(dev); 2107 if (com->pc98_8251fifo) { 2108 com->pc98_8251fifo_enable = 1; 2109 outb(I8251F_fcr, CTRL8251F_ENABLE | 2110 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 2111 } 2112 } 2113#endif 2114 /* 2115 * XXX we should goto open_top if comparam() slept. 2116 */ 2117 iobase = com->iobase; 2118 if (com->hasfifo) { 2119 /* 2120 * (Re)enable and drain fifos. 2121 * 2122 * Certain SMC chips cause problems if the fifos 2123 * are enabled while input is ready. Turn off the 2124 * fifo if necessary to clear the input. We test 2125 * the input ready bit after enabling the fifos 2126 * since we've already enabled them in comparam() 2127 * and to handle races between enabling and fresh 2128 * input. 2129 */ 2130 while (TRUE) { 2131#ifdef PC98 2132 outb(iobase + (com_fifo << port_shift), 2133 FIFO_RCV_RST | FIFO_XMT_RST 2134 | com->fifo_image); 2135 if (com->pc98_if_type == COM_IF_RSA98III) 2136 outb(com->rsabase + rsa_frr , 0x00); 2137#else 2138 outb(iobase + com_fifo, 2139 FIFO_RCV_RST | FIFO_XMT_RST 2140 | com->fifo_image); 2141#endif 2142 /* 2143 * XXX the delays are for superstitious 2144 * historical reasons. It must be less than 2145 * the character time at the maximum 2146 * supported speed (87 usec at 115200 bps 2147 * 8N1). Otherwise we might loop endlessly 2148 * if data is streaming in. We used to use 2149 * delays of 100. That usually worked 2150 * because DELAY(100) used to usually delay 2151 * for about 85 usec instead of 100. 2152 */ 2153 DELAY(50); 2154#ifndef PC98 2155 if (!(inb(com->line_status_port) & LSR_RXRDY)) 2156#else 2157 if (com->pc98_if_type == COM_IF_RSA98III 2158 ? !(inb(com->rsabase + rsa_srr) & 0x08) 2159 : !(inb(com->line_status_port) & LSR_RXRDY)) 2160#endif 2161 break; 2162#ifdef PC98 2163 outb(iobase + (com_fifo << port_shift), 0); 2164#else 2165 outb(iobase + com_fifo, 0); 2166#endif 2167 DELAY(50); 2168 (void) inb(com->data_port); 2169 } 2170 } 2171 2172 disable_intr(); 2173#ifdef PC98 2174 if (IS_8251(com->pc98_if_type)) { 2175 com_tiocm_bis(com, TIOCM_LE); 2176 com->pc98_prev_modem_status = pc98_get_modem_status(com); 2177 com_int_Rx_enable(com); 2178 } else { 2179#endif 2180 (void) inb(com->line_status_port); 2181 (void) inb(com->data_port); 2182 com->prev_modem_status = com->last_modem_status 2183 = inb(com->modem_status_port); 2184 if (COM_IIR_TXRDYBUG(com->flags)) { 2185 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS 2186 | IER_EMSC); 2187 } else { 2188 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY 2189 | IER_ERLS | IER_EMSC); 2190 } 2191#ifdef PC98 2192 if (com->pc98_if_type == COM_IF_RSA98III) { 2193 outb(com->rsabase + rsa_ier, 0x1d); 2194 outb(com->intr_ctl_port, IER_ERLS | IER_EMSC); 2195 } 2196#endif 2197#ifdef PC98 2198 } 2199#endif 2200 enable_intr(); 2201 /* 2202 * Handle initial DCD. Callout devices get a fake initial 2203 * DCD (trapdoor DCD). If we are callout, then any sleeping 2204 * callin opens get woken up and resume sleeping on "siobi" 2205 * instead of "siodcd". 2206 */ 2207 /* 2208 * XXX `mynor & CALLOUT_MASK' should be 2209 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where 2210 * TRAPDOOR_CARRIER is the default initial state for callout 2211 * devices and SOFT_CARRIER is like CLOCAL except it hides 2212 * the true carrier. 2213 */ 2214#ifdef PC98 2215 if ((IS_8251(com->pc98_if_type) && 2216 (pc98_get_modem_status(com) & TIOCM_CAR)) || 2217 (!IS_8251(com->pc98_if_type) && 2218 (com->prev_modem_status & MSR_DCD)) || 2219 mynor & CALLOUT_MASK) 2220#else 2221 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK) 2222#endif 2223 (*linesw[tp->t_line].l_modem)(tp, 1); 2224 } 2225 /* 2226 * Wait for DCD if necessary. 2227 */ 2228 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK) 2229 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 2230 ++com->wopeners; 2231 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0); 2232 if (com_addr(unit) == NULL) 2233 return (ENXIO); 2234 --com->wopeners; 2235 if (error != 0 || com->gone) 2236 goto out; 2237 goto open_top; 2238 } 2239 error = (*linesw[tp->t_line].l_open)(dev, tp); 2240 disc_optim(tp, &tp->t_termios, com); 2241 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK) 2242 com->active_out = TRUE; 2243 siosettimeout(); 2244out: 2245 splx(s); 2246 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0) 2247 comhardclose(com); 2248 return (error); 2249} 2250 2251static int 2252sioclose(dev, flag, mode, p) 2253 dev_t dev; 2254 int flag; 2255 int mode; 2256 struct proc *p; 2257{ 2258 struct com_s *com; 2259 int mynor; 2260 int s; 2261 struct tty *tp; 2262 2263 mynor = minor(dev); 2264 if (mynor & CONTROL_MASK) 2265 return (0); 2266 com = com_addr(MINOR_TO_UNIT(mynor)); 2267 tp = com->tp; 2268 s = spltty(); 2269 (*linesw[tp->t_line].l_close)(tp, flag); 2270#ifdef PC98 2271 com->modem_checking = 0; 2272#endif 2273 disc_optim(tp, &tp->t_termios, com); 2274 comstop(tp, FREAD | FWRITE); 2275 comhardclose(com); 2276 ttyclose(tp); 2277 siosettimeout(); 2278 splx(s); 2279 if (com->gone) { 2280 printf("sio%d: gone\n", com->unit); 2281 s = spltty(); 2282 if (com->ibuf != NULL) 2283 free(com->ibuf, M_DEVBUF); 2284 bzero(tp, sizeof *tp); 2285 splx(s); 2286 } 2287 return (0); 2288} 2289 2290static void 2291comhardclose(com) 2292 struct com_s *com; 2293{ 2294 Port_t iobase; 2295 int s; 2296 struct tty *tp; 2297 int unit; 2298#ifdef PC98 2299 int port_shift = 0; 2300#endif 2301 2302 unit = com->unit; 2303 iobase = com->iobase; 2304 s = spltty(); 2305 com->poll = FALSE; 2306 com->poll_output = FALSE; 2307 com->do_timestamp = FALSE; 2308 com->do_dcd_timestamp = FALSE; 2309 com->pps.ppsparam.mode = 0; 2310#ifdef PC98 2311 if (IS_8251(com->pc98_if_type)) 2312 com_send_break_off(com); 2313 else { 2314 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift; 2315 outb(iobase + (com_cfcr << port_shift), 2316 com->cfcr_image &= ~CFCR_SBREAK); 2317 } 2318#else 2319 outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 2320#endif 2321 { 2322#ifdef PC98 2323 int tmp; 2324 if (IS_8251(com->pc98_if_type)) 2325 com_int_TxRx_disable(com); 2326 else 2327 outb(iobase + (com_ier << port_shift), 0); 2328 if (com->pc98_if_type == COM_IF_RSA98III) { 2329 outb(com->rsabase + rsa_ier, 0x00); 2330 } 2331#else 2332 outb(iobase + com_ier, 0); 2333#endif 2334 tp = com->tp; 2335#ifdef PC98 2336 if (IS_8251(com->pc98_if_type)) 2337 tmp = pc98_get_modem_status(com) & TIOCM_CAR; 2338 else 2339 tmp = com->prev_modem_status & MSR_DCD; 2340#endif 2341 if (tp->t_cflag & HUPCL 2342 /* 2343 * XXX we will miss any carrier drop between here and the 2344 * next open. Perhaps we should watch DCD even when the 2345 * port is closed; it is not sufficient to check it at 2346 * the next open because it might go up and down while 2347 * we're not watching. 2348 */ 2349 || (!com->active_out 2350#ifdef PC98 2351 && !(tmp) 2352#else 2353 && !(com->prev_modem_status & MSR_DCD) 2354#endif 2355 && !(com->it_in.c_cflag & CLOCAL)) 2356 || !(tp->t_state & TS_ISOPEN)) { 2357#ifdef PC98 2358 if (IS_8251(com->pc98_if_type)) 2359 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 2360 else 2361#endif 2362 (void)commctl(com, TIOCM_DTR, DMBIC); 2363 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) { 2364 timeout(siodtrwakeup, com, com->dtr_wait); 2365 com->state |= CS_DTR_OFF; 2366 } 2367 } 2368#ifdef PC98 2369 else { 2370 if (IS_8251(com->pc98_if_type)) 2371 com_tiocm_bic(com, TIOCM_LE ); 2372 } 2373#endif 2374 } 2375#ifdef PC98 2376 if (com->pc98_8251fifo) { 2377 if (com->pc98_8251fifo_enable) 2378 outb(I8251F_fcr, CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 2379 com->pc98_8251fifo_enable = 0; 2380 } 2381#endif 2382 if (com->hasfifo) { 2383 /* 2384 * Disable fifos so that they are off after controlled 2385 * reboots. Some BIOSes fail to detect 16550s when the 2386 * fifos are enabled. 2387 */ 2388#ifdef PC98 2389 outb(iobase + (com_fifo << port_shift), 0); 2390#else 2391 outb(iobase + com_fifo, 0); 2392#endif 2393 } 2394 com->active_out = FALSE; 2395 wakeup(&com->active_out); 2396 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */ 2397 splx(s); 2398} 2399 2400static int 2401sioread(dev, uio, flag) 2402 dev_t dev; 2403 struct uio *uio; 2404 int flag; 2405{ 2406 int mynor; 2407 struct com_s *com; 2408 2409 mynor = minor(dev); 2410 if (mynor & CONTROL_MASK) 2411 return (ENODEV); 2412 com = com_addr(MINOR_TO_UNIT(mynor)); 2413 if (com->gone) 2414 return (ENODEV); 2415 return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag)); 2416} 2417 2418static int 2419siowrite(dev, uio, flag) 2420 dev_t dev; 2421 struct uio *uio; 2422 int flag; 2423{ 2424 int mynor; 2425 struct com_s *com; 2426 int unit; 2427 2428 mynor = minor(dev); 2429 if (mynor & CONTROL_MASK) 2430 return (ENODEV); 2431 2432 unit = MINOR_TO_UNIT(mynor); 2433 com = com_addr(unit); 2434 if (com->gone) 2435 return (ENODEV); 2436 /* 2437 * (XXX) We disallow virtual consoles if the physical console is 2438 * a serial port. This is in case there is a display attached that 2439 * is not the console. In that situation we don't need/want the X 2440 * server taking over the console. 2441 */ 2442 if (constty != NULL && unit == comconsole) 2443 constty = NULL; 2444 return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag)); 2445} 2446 2447static void 2448siobusycheck(chan) 2449 void *chan; 2450{ 2451 struct com_s *com; 2452 int s; 2453 2454 com = (struct com_s *)chan; 2455 2456 /* 2457 * Clear TS_BUSY if low-level output is complete. 2458 * spl locking is sufficient because siointr1() does not set CS_BUSY. 2459 * If siointr1() clears CS_BUSY after we look at it, then we'll get 2460 * called again. Reading the line status port outside of siointr1() 2461 * is safe because CS_BUSY is clear so there are no output interrupts 2462 * to lose. 2463 */ 2464 s = spltty(); 2465 if (com->state & CS_BUSY) 2466 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */ 2467#ifdef PC98 2468 else if ((IS_8251(com->pc98_if_type) && 2469 ((com->pc98_8251fifo_enable && 2470 (inb(I8251F_lsr) & (STS8251F_TxRDY | STS8251F_TxEMP)) 2471 == (STS8251F_TxRDY | STS8251F_TxEMP)) || 2472 (!com->pc98_8251fifo_enable && 2473 (inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP)) 2474 == (STS8251_TxRDY | STS8251_TxEMP)))) || 2475 ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2476 == (LSR_TSRE | LSR_TXRDY))) { 2477#else 2478 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2479 == (LSR_TSRE | LSR_TXRDY)) { 2480#endif 2481 com->tp->t_state &= ~TS_BUSY; 2482 ttwwakeup(com->tp); 2483 com->extra_state &= ~CSE_BUSYCHECK; 2484 } else 2485 timeout(siobusycheck, com, hz / 100); 2486 splx(s); 2487} 2488 2489static void 2490siodtrwakeup(chan) 2491 void *chan; 2492{ 2493 struct com_s *com; 2494 2495 com = (struct com_s *)chan; 2496 com->state &= ~CS_DTR_OFF; 2497 wakeup(&com->dtr_wait); 2498} 2499 2500static void 2501sioinput(com) 2502 struct com_s *com; 2503{ 2504 u_char *buf; 2505 int incc; 2506 u_char line_status; 2507 int recv_data; 2508 struct tty *tp; 2509 2510 buf = com->ibuf; 2511 tp = com->tp; 2512 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) { 2513 com_events -= (com->iptr - com->ibuf); 2514 com->iptr = com->ibuf; 2515 return; 2516 } 2517 if (tp->t_state & TS_CAN_BYPASS_L_RINT) { 2518 /* 2519 * Avoid the grotesquely inefficient lineswitch routine 2520 * (ttyinput) in "raw" mode. It usually takes about 450 2521 * instructions (that's without canonical processing or echo!). 2522 * slinput is reasonably fast (usually 40 instructions plus 2523 * call overhead). 2524 */ 2525 do { 2526 enable_intr(); 2527 incc = com->iptr - buf; 2528 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat 2529 && (com->state & CS_RTS_IFLOW 2530 || tp->t_iflag & IXOFF) 2531 && !(tp->t_state & TS_TBLOCK)) 2532 ttyblock(tp); 2533 com->delta_error_counts[CE_TTY_BUF_OVERFLOW] 2534 += b_to_q((char *)buf, incc, &tp->t_rawq); 2535 buf += incc; 2536 tk_nin += incc; 2537 tk_rawcc += incc; 2538 tp->t_rawcc += incc; 2539 ttwakeup(tp); 2540 if (tp->t_state & TS_TTSTOP 2541 && (tp->t_iflag & IXANY 2542 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) { 2543 tp->t_state &= ~TS_TTSTOP; 2544 tp->t_lflag &= ~FLUSHO; 2545 comstart(tp); 2546 } 2547 disable_intr(); 2548 } while (buf < com->iptr); 2549 } else { 2550 do { 2551 enable_intr(); 2552 line_status = buf[com->ierroff]; 2553 recv_data = *buf++; 2554 if (line_status 2555 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) { 2556 if (line_status & LSR_BI) 2557 recv_data |= TTY_BI; 2558 if (line_status & LSR_FE) 2559 recv_data |= TTY_FE; 2560 if (line_status & LSR_OE) 2561 recv_data |= TTY_OE; 2562 if (line_status & LSR_PE) 2563 recv_data |= TTY_PE; 2564 } 2565 (*linesw[tp->t_line].l_rint)(recv_data, tp); 2566 disable_intr(); 2567 } while (buf < com->iptr); 2568 } 2569 com_events -= (com->iptr - com->ibuf); 2570 com->iptr = com->ibuf; 2571 2572 /* 2573 * There is now room for another low-level buffer full of input, 2574 * so enable RTS if it is now disabled and there is room in the 2575 * high-level buffer. 2576 */ 2577#ifdef PC98 2578 if (IS_8251(com->pc98_if_type)) { 2579 if ((com->state & CS_RTS_IFLOW) && 2580 !(com_tiocm_get(com) & TIOCM_RTS) && 2581 !(tp->t_state & TS_TBLOCK)) 2582 com_tiocm_bis(com, TIOCM_RTS); 2583 } else { 2584 if ((com->state & CS_RTS_IFLOW) && 2585 !(com->mcr_image & MCR_RTS) && 2586 !(tp->t_state & TS_TBLOCK)) 2587 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2588 } 2589#else 2590 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) && 2591 !(tp->t_state & TS_TBLOCK)) 2592 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2593#endif 2594} 2595 2596void 2597siointr(arg) 2598 void *arg; 2599{ 2600#ifndef COM_MULTIPORT 2601 COM_LOCK(); 2602 siointr1((struct com_s *) arg); 2603 COM_UNLOCK(); 2604#else /* COM_MULTIPORT */ 2605 bool_t possibly_more_intrs; 2606 int unit; 2607 struct com_s *com; 2608#ifdef PC98 2609 u_char rsa_buf_status; 2610#endif 2611 2612 /* 2613 * Loop until there is no activity on any port. This is necessary 2614 * to get an interrupt edge more than to avoid another interrupt. 2615 * If the IRQ signal is just an OR of the IRQ signals from several 2616 * devices, then the edge from one may be lost because another is 2617 * on. 2618 */ 2619 COM_LOCK(); 2620 do { 2621 possibly_more_intrs = FALSE; 2622 for (unit = 0; unit < sio_numunits; ++unit) { 2623 com = com_addr(unit); 2624 /* 2625 * XXX COM_LOCK(); 2626 * would it work here, or be counter-productive? 2627 */ 2628#ifdef PC98 2629 if (com != NULL 2630 && !com->gone 2631 && IS_8251(com->pc98_if_type)){ 2632 siointr1(com); 2633 } else 2634#endif /* PC98 */ 2635#ifdef PC98 2636 if (com != NULL 2637 && !com->gone 2638 && com->pc98_if_type == COM_IF_RSA98III) { 2639 rsa_buf_status = inb(com->rsabase + rsa_srr) & 0xc9; 2640 if ((rsa_buf_status & 0xc8) 2641 || !(rsa_buf_status & 0x01)) { 2642 siointr1(com); 2643 if(rsa_buf_status 2644 != (inb(com->rsabase + rsa_srr) & 0xc9)) 2645 possibly_more_intrs = TRUE; 2646 } 2647 } else 2648#endif 2649 if (com != NULL 2650 && !com->gone 2651 && (inb(com->int_id_port) & IIR_IMASK) 2652 != IIR_NOPEND) { 2653 siointr1(com); 2654 possibly_more_intrs = TRUE; 2655 } 2656 /* XXX COM_UNLOCK(); */ 2657 } 2658 } while (possibly_more_intrs); 2659 COM_UNLOCK(); 2660#endif /* COM_MULTIPORT */ 2661} 2662 2663static void 2664siointr1(com) 2665 struct com_s *com; 2666{ 2667 u_char line_status; 2668 u_char modem_status; 2669 u_char *ioptr; 2670 u_char recv_data; 2671 u_char int_ctl; 2672 u_char int_ctl_new; 2673 struct timecounter *tc; 2674 u_int count; 2675 2676#ifdef PC98 2677 u_char tmp=0; 2678 u_char rsa_buf_status = 0; 2679 int rsa_tx_fifo_size=0; 2680 recv_data=0; 2681#endif /* PC98 */ 2682 2683 int_ctl = inb(com->intr_ctl_port); 2684 int_ctl_new = int_ctl; 2685 2686 while (!com->gone) { 2687#ifdef PC98 2688status_read:; 2689 if (IS_8251(com->pc98_if_type)) { 2690 if (com->pc98_8251fifo_enable) 2691 tmp = inb(I8251F_lsr); 2692 else 2693 tmp = inb(com->sts_port); 2694more_intr: 2695 line_status = 0; 2696 if (com->pc98_8251fifo_enable) { 2697 if (tmp & STS8251F_TxRDY) line_status |= LSR_TXRDY; 2698 if (tmp & STS8251F_RxRDY) line_status |= LSR_RXRDY; 2699 if (tmp & STS8251F_TxEMP) line_status |= LSR_TSRE; 2700 if (tmp & STS8251F_PE) line_status |= LSR_PE; 2701 if (tmp & STS8251F_OE) line_status |= LSR_OE; 2702 if (tmp & STS8251F_BD_SD) line_status |= LSR_BI; 2703 } else { 2704 if (tmp & STS8251_TxRDY) line_status |= LSR_TXRDY; 2705 if (tmp & STS8251_RxRDY) line_status |= LSR_RXRDY; 2706 if (tmp & STS8251_TxEMP) line_status |= LSR_TSRE; 2707 if (tmp & STS8251_PE) line_status |= LSR_PE; 2708 if (tmp & STS8251_OE) line_status |= LSR_OE; 2709 if (tmp & STS8251_FE) line_status |= LSR_FE; 2710 if (tmp & STS8251_BD_SD) line_status |= LSR_BI; 2711 } 2712 } else { 2713#endif /* PC98 */ 2714 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) { 2715 modem_status = inb(com->modem_status_port); 2716 if ((modem_status ^ com->last_modem_status) & MSR_DCD) { 2717 tc = timecounter; 2718 count = tc->tc_get_timecount(tc); 2719 pps_event(&com->pps, tc, count, 2720 (modem_status & MSR_DCD) ? 2721 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR); 2722 } 2723 } 2724 line_status = inb(com->line_status_port); 2725#ifdef PC98 2726 } 2727 if (com->pc98_if_type == COM_IF_RSA98III) 2728 rsa_buf_status = inb(com->rsabase + rsa_srr); 2729#endif /* PC98 */ 2730 2731 /* input event? (check first to help avoid overruns) */ 2732#ifndef PC98 2733 while (line_status & LSR_RCV_MASK) { 2734#else 2735 while ((line_status & LSR_RCV_MASK) 2736 || (com->pc98_if_type == COM_IF_RSA98III 2737 && (rsa_buf_status & 0x08))) { 2738#endif /* PC98 */ 2739 /* break/unnattached error bits or real input? */ 2740#ifdef PC98 2741 if (IS_8251(com->pc98_if_type)) { 2742 if (com->pc98_8251fifo_enable) { 2743 recv_data = inb(I8251F_data); 2744 if (tmp & (STS8251F_PE | STS8251F_OE | 2745 STS8251F_BD_SD)) { 2746 pc98_i8251_or_cmd(com, CMD8251_ER); 2747 recv_data = 0; 2748 } 2749 } else { 2750 recv_data = inb(com->data_port); 2751 if (tmp & (STS8251_PE | STS8251_OE | 2752 STS8251_FE | STS8251_BD_SD)) { 2753 pc98_i8251_or_cmd(com, CMD8251_ER); 2754 recv_data = 0; 2755 } 2756 } 2757 } else { 2758#endif /* PC98 */ 2759#ifdef PC98 2760 if (com->pc98_if_type == COM_IF_RSA98III) { 2761 if (!(rsa_buf_status & 0x08)) 2762 recv_data = 0; 2763 else 2764 recv_data = inb(com->data_port); 2765 } else 2766#endif 2767 if (!(line_status & LSR_RXRDY)) 2768 recv_data = 0; 2769 else 2770 recv_data = inb(com->data_port); 2771#ifdef PC98 2772 } 2773#endif 2774 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) { 2775 /* 2776 * Don't store BI if IGNBRK or FE/PE if IGNPAR. 2777 * Otherwise, push the work to a higher level 2778 * (to handle PARMRK) if we're bypassing. 2779 * Otherwise, convert BI/FE and PE+INPCK to 0. 2780 * 2781 * This makes bypassing work right in the 2782 * usual "raw" case (IGNBRK set, and IGNPAR 2783 * and INPCK clear). 2784 * 2785 * Note: BI together with FE/PE means just BI. 2786 */ 2787 if (line_status & LSR_BI) { 2788#if defined(DDB) && defined(BREAK_TO_DEBUGGER) 2789 if (com->unit == comconsole) { 2790 breakpoint(); 2791 goto cont; 2792 } 2793#endif 2794 if (com->tp == NULL 2795 || com->tp->t_iflag & IGNBRK) 2796 goto cont; 2797 } else { 2798 if (com->tp == NULL 2799 || com->tp->t_iflag & IGNPAR) 2800 goto cont; 2801 } 2802 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT 2803 && (line_status & (LSR_BI | LSR_FE) 2804 || com->tp->t_iflag & INPCK)) 2805 recv_data = 0; 2806 } 2807 ++com->bytes_in; 2808 if (com->hotchar != 0 && recv_data == com->hotchar) 2809 setsofttty(); 2810 ioptr = com->iptr; 2811 if (ioptr >= com->ibufend) 2812 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW); 2813 else { 2814 if (com->do_timestamp) 2815 microtime(&com->timestamp); 2816 ++com_events; 2817 schedsofttty(); 2818#if 0 /* for testing input latency vs efficiency */ 2819if (com->iptr - com->ibuf == 8) 2820 setsofttty(); 2821#endif 2822 ioptr[0] = recv_data; 2823 ioptr[com->ierroff] = line_status; 2824 com->iptr = ++ioptr; 2825 if (ioptr == com->ihighwater 2826 && com->state & CS_RTS_IFLOW) 2827#ifdef PC98 2828 IS_8251(com->pc98_if_type) ? 2829 com_tiocm_bic(com, TIOCM_RTS) : 2830#endif 2831 outb(com->modem_ctl_port, 2832 com->mcr_image &= ~MCR_RTS); 2833 if (line_status & LSR_OE) 2834 CE_RECORD(com, CE_OVERRUN); 2835 } 2836cont: 2837 /* 2838 * "& 0x7F" is to avoid the gcc-1.40 generating a slow 2839 * jump from the top of the loop to here 2840 */ 2841#ifdef PC98 2842 if (IS_8251(com->pc98_if_type)) 2843 goto status_read; 2844 else 2845#endif 2846 line_status = inb(com->line_status_port) & 0x7F; 2847#ifdef PC98 2848 if (com->pc98_if_type == COM_IF_RSA98III) 2849 rsa_buf_status = inb(com->rsabase + rsa_srr); 2850#endif /* PC98 */ 2851 } 2852 2853 /* modem status change? (always check before doing output) */ 2854#ifdef PC98 2855 if (!IS_8251(com->pc98_if_type)) { 2856#endif 2857 modem_status = inb(com->modem_status_port); 2858 if (modem_status != com->last_modem_status) { 2859 if (com->do_dcd_timestamp 2860 && !(com->last_modem_status & MSR_DCD) 2861 && modem_status & MSR_DCD) 2862 microtime(&com->dcd_timestamp); 2863 2864 /* 2865 * Schedule high level to handle DCD changes. Note 2866 * that we don't use the delta bits anywhere. Some 2867 * UARTs mess them up, and it's easy to remember the 2868 * previous bits and calculate the delta. 2869 */ 2870 com->last_modem_status = modem_status; 2871 if (!(com->state & CS_CHECKMSR)) { 2872 com_events += LOTS_OF_EVENTS; 2873 com->state |= CS_CHECKMSR; 2874 setsofttty(); 2875 } 2876 2877 /* handle CTS change immediately for crisp flow ctl */ 2878 if (com->state & CS_CTS_OFLOW) { 2879 if (modem_status & MSR_CTS) 2880 com->state |= CS_ODEVREADY; 2881 else 2882 com->state &= ~CS_ODEVREADY; 2883 } 2884 } 2885#ifdef PC98 2886 } 2887#endif 2888 2889 /* output queued and everything ready? */ 2890#ifndef PC98 2891 if (line_status & LSR_TXRDY 2892 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 2893#else 2894 if (((com->pc98_if_type == COM_IF_RSA98III) 2895 ? (rsa_buf_status & 0x02) 2896 : (line_status & LSR_TXRDY)) 2897 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 2898#endif 2899#ifdef PC98 2900 Port_t tmp_data_port; 2901 2902 if (IS_8251(com->pc98_if_type) && 2903 com->pc98_8251fifo_enable) 2904 tmp_data_port = I8251F_data; 2905 else 2906 tmp_data_port = com->data_port; 2907#endif 2908 2909 ioptr = com->obufq.l_head; 2910 if (com->tx_fifo_size > 1) { 2911 u_int ocount; 2912 2913 ocount = com->obufq.l_tail - ioptr; 2914#ifdef PC98 2915 if (com->pc98_if_type == COM_IF_RSA98III) { 2916 rsa_buf_status = inb(com->rsabase + rsa_srr); 2917 rsa_tx_fifo_size = 1024; 2918 if (!(rsa_buf_status & 0x01)) 2919 rsa_tx_fifo_size = 2048; 2920 if (ocount > rsa_tx_fifo_size) 2921 ocount = rsa_tx_fifo_size; 2922 } else 2923#endif 2924 if (ocount > com->tx_fifo_size) 2925 ocount = com->tx_fifo_size; 2926 com->bytes_out += ocount; 2927 do 2928#ifdef PC98 2929 outb(tmp_data_port, *ioptr++); 2930#else 2931 outb(com->data_port, *ioptr++); 2932#endif 2933 while (--ocount != 0); 2934 } else { 2935#ifdef PC98 2936 outb(tmp_data_port, *ioptr++); 2937#else 2938 outb(com->data_port, *ioptr++); 2939#endif 2940 ++com->bytes_out; 2941 } 2942#ifdef PC98 2943 if (IS_8251(com->pc98_if_type)) 2944 if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG)) 2945 com_int_Tx_enable(com); 2946#endif 2947 com->obufq.l_head = ioptr; 2948 if (COM_IIR_TXRDYBUG(com->flags)) { 2949 int_ctl_new = int_ctl | IER_ETXRDY; 2950 } 2951 if (ioptr >= com->obufq.l_tail) { 2952 struct lbq *qp; 2953 2954 qp = com->obufq.l_next; 2955 qp->l_queued = FALSE; 2956 qp = qp->l_next; 2957 if (qp != NULL) { 2958 com->obufq.l_head = qp->l_head; 2959 com->obufq.l_tail = qp->l_tail; 2960 com->obufq.l_next = qp; 2961 } else { 2962 /* output just completed */ 2963 if (COM_IIR_TXRDYBUG(com->flags)) { 2964 int_ctl_new = int_ctl & ~IER_ETXRDY; 2965 } 2966 com->state &= ~CS_BUSY; 2967#if defined(PC98) 2968 if (IS_8251(com->pc98_if_type)) 2969 if ( pc98_check_i8251_interrupt(com) & IEN_TxFLAG ) 2970 com_int_Tx_disable(com); 2971#endif 2972 } 2973 if (!(com->state & CS_ODONE)) { 2974 com_events += LOTS_OF_EVENTS; 2975 com->state |= CS_ODONE; 2976 setsofttty(); /* handle at high level ASAP */ 2977 } 2978 } 2979 if (COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) { 2980#ifdef PC98 2981 if (com->pc98_if_type == COM_IF_RSA98III) { 2982 int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY); 2983 outb(com->intr_ctl_port, int_ctl_new); 2984 outb(com->rsabase + rsa_ier, 0x1d); 2985 } else 2986#endif 2987 outb(com->intr_ctl_port, int_ctl_new); 2988 } 2989 } 2990#ifdef PC98 2991 else if (line_status & LSR_TXRDY) { 2992 if (IS_8251(com->pc98_if_type)) 2993 if ( pc98_check_i8251_interrupt(com) & IEN_TxFLAG ) 2994 com_int_Tx_disable(com); 2995 } 2996 if (IS_8251(com->pc98_if_type)) { 2997 if (com->pc98_8251fifo_enable) { 2998 if ((tmp = inb(I8251F_lsr)) & STS8251F_RxRDY) 2999 goto more_intr; 3000 } else { 3001 if ((tmp = inb(com->sts_port)) & STS8251_RxRDY) 3002 goto more_intr; 3003 } 3004 } 3005#endif 3006 3007 /* finished? */ 3008#ifndef COM_MULTIPORT 3009#ifdef PC98 3010 if (IS_8251(com->pc98_if_type)) 3011 return; 3012#endif 3013 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND) 3014#endif /* COM_MULTIPORT */ 3015 return; 3016 } 3017} 3018 3019static int 3020sioioctl(dev, cmd, data, flag, p) 3021 dev_t dev; 3022 u_long cmd; 3023 caddr_t data; 3024 int flag; 3025 struct proc *p; 3026{ 3027 struct com_s *com; 3028 int error; 3029 Port_t iobase; 3030 int mynor; 3031 int s; 3032 struct tty *tp; 3033#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 3034 u_long oldcmd; 3035 struct termios term; 3036#endif 3037 3038 mynor = minor(dev); 3039 com = com_addr(MINOR_TO_UNIT(mynor)); 3040 if (com->gone) 3041 return (ENODEV); 3042 iobase = com->iobase; 3043 if (mynor & CONTROL_MASK) { 3044 struct termios *ct; 3045 3046 switch (mynor & CONTROL_MASK) { 3047 case CONTROL_INIT_STATE: 3048 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in; 3049 break; 3050 case CONTROL_LOCK_STATE: 3051 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in; 3052 break; 3053 default: 3054 return (ENODEV); /* /dev/nodev */ 3055 } 3056 switch (cmd) { 3057 case TIOCSETA: 3058 error = suser(p); 3059 if (error != 0) 3060 return (error); 3061 *ct = *(struct termios *)data; 3062 return (0); 3063 case TIOCGETA: 3064 *(struct termios *)data = *ct; 3065 return (0); 3066 case TIOCGETD: 3067 *(int *)data = TTYDISC; 3068 return (0); 3069 case TIOCGWINSZ: 3070 bzero(data, sizeof(struct winsize)); 3071 return (0); 3072 default: 3073 return (ENOTTY); 3074 } 3075 } 3076 tp = com->tp; 3077#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 3078 term = tp->t_termios; 3079 oldcmd = cmd; 3080 error = ttsetcompat(tp, &cmd, data, &term); 3081 if (error != 0) 3082 return (error); 3083 if (cmd != oldcmd) 3084 data = (caddr_t)&term; 3085#endif 3086 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) { 3087 int cc; 3088 struct termios *dt = (struct termios *)data; 3089 struct termios *lt = mynor & CALLOUT_MASK 3090 ? &com->lt_out : &com->lt_in; 3091 3092 dt->c_iflag = (tp->t_iflag & lt->c_iflag) 3093 | (dt->c_iflag & ~lt->c_iflag); 3094 dt->c_oflag = (tp->t_oflag & lt->c_oflag) 3095 | (dt->c_oflag & ~lt->c_oflag); 3096 dt->c_cflag = (tp->t_cflag & lt->c_cflag) 3097 | (dt->c_cflag & ~lt->c_cflag); 3098 dt->c_lflag = (tp->t_lflag & lt->c_lflag) 3099 | (dt->c_lflag & ~lt->c_lflag); 3100 for (cc = 0; cc < NCCS; ++cc) 3101 if (lt->c_cc[cc] != 0) 3102 dt->c_cc[cc] = tp->t_cc[cc]; 3103 if (lt->c_ispeed != 0) 3104 dt->c_ispeed = tp->t_ispeed; 3105 if (lt->c_ospeed != 0) 3106 dt->c_ospeed = tp->t_ospeed; 3107 } 3108 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 3109 if (error != ENOIOCTL) 3110 return (error); 3111 s = spltty(); 3112 error = ttioctl(tp, cmd, data, flag); 3113 disc_optim(tp, &tp->t_termios, com); 3114 if (error != ENOIOCTL) { 3115 splx(s); 3116 return (error); 3117 } 3118#ifdef PC98 3119 if (IS_8251(com->pc98_if_type)) { 3120 switch (cmd) { 3121 case TIOCSBRK: 3122 com_send_break_on( com ); 3123 break; 3124 case TIOCCBRK: 3125 com_send_break_off( com ); 3126 break; 3127 case TIOCSDTR: 3128 com_tiocm_bis(com, TIOCM_DTR | TIOCM_RTS ); 3129 break; 3130 case TIOCCDTR: 3131 com_tiocm_bic(com, TIOCM_DTR); 3132 break; 3133 /* 3134 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 3135 * changes get undone on the next call to comparam(). 3136 */ 3137 case TIOCMSET: 3138 com_tiocm_set( com, *(int *)data ); 3139 break; 3140 case TIOCMBIS: 3141 com_tiocm_bis( com, *(int *)data ); 3142 break; 3143 case TIOCMBIC: 3144 com_tiocm_bic( com, *(int *)data ); 3145 break; 3146 case TIOCMGET: 3147 *(int *)data = com_tiocm_get(com); 3148 break; 3149 case TIOCMSDTRWAIT: 3150 /* must be root since the wait applies to following logins */ 3151 error = suser(p); 3152 if (error != 0) { 3153 splx(s); 3154 return (error); 3155 } 3156 com->dtr_wait = *(int *)data * hz / 100; 3157 break; 3158 case TIOCMGDTRWAIT: 3159 *(int *)data = com->dtr_wait * 100 / hz; 3160 break; 3161 case TIOCTIMESTAMP: 3162 com->do_timestamp = TRUE; 3163 *(struct timeval *)data = com->timestamp; 3164 break; 3165 case TIOCDCDTIMESTAMP: 3166 com->do_dcd_timestamp = TRUE; 3167 *(struct timeval *)data = com->dcd_timestamp; 3168 break; 3169 default: 3170 splx(s); 3171 return (ENOTTY); 3172 } 3173 } else { 3174 int port_shift; 3175 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift; 3176#endif 3177 switch (cmd) { 3178 case TIOCSBRK: 3179#ifdef PC98 3180 outb(iobase + (com_cfcr << port_shift), 3181 com->cfcr_image |= CFCR_SBREAK); 3182#else 3183 outb(iobase + com_cfcr, com->cfcr_image |= CFCR_SBREAK); 3184#endif 3185 break; 3186 case TIOCCBRK: 3187#ifdef PC98 3188 outb(iobase + (com_cfcr << port_shift), 3189 com->cfcr_image &= ~CFCR_SBREAK); 3190#else 3191 outb(iobase + com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 3192#endif 3193 break; 3194 case TIOCSDTR: 3195 (void)commctl(com, TIOCM_DTR, DMBIS); 3196 break; 3197 case TIOCCDTR: 3198 (void)commctl(com, TIOCM_DTR, DMBIC); 3199 break; 3200 /* 3201 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 3202 * changes get undone on the next call to comparam(). 3203 */ 3204 case TIOCMSET: 3205 (void)commctl(com, *(int *)data, DMSET); 3206 break; 3207 case TIOCMBIS: 3208 (void)commctl(com, *(int *)data, DMBIS); 3209 break; 3210 case TIOCMBIC: 3211 (void)commctl(com, *(int *)data, DMBIC); 3212 break; 3213 case TIOCMGET: 3214 *(int *)data = commctl(com, 0, DMGET); 3215 break; 3216 case TIOCMSDTRWAIT: 3217 /* must be root since the wait applies to following logins */ 3218 error = suser(p); 3219 if (error != 0) { 3220 splx(s); 3221 return (error); 3222 } 3223 com->dtr_wait = *(int *)data * hz / 100; 3224 break; 3225 case TIOCMGDTRWAIT: 3226 *(int *)data = com->dtr_wait * 100 / hz; 3227 break; 3228 case TIOCTIMESTAMP: 3229 com->do_timestamp = TRUE; 3230 *(struct timeval *)data = com->timestamp; 3231 break; 3232 case TIOCDCDTIMESTAMP: 3233 com->do_dcd_timestamp = TRUE; 3234 *(struct timeval *)data = com->dcd_timestamp; 3235 break; 3236 default: 3237 splx(s); 3238 error = pps_ioctl(cmd, data, &com->pps); 3239 if (error == ENODEV) 3240 error = ENOTTY; 3241 return (error); 3242 } 3243#ifdef PC98 3244 } 3245#endif 3246 splx(s); 3247 return (0); 3248} 3249 3250static void 3251siopoll() 3252{ 3253 int unit; 3254 3255 if (com_events == 0) 3256 return; 3257repeat: 3258 for (unit = 0; unit < sio_numunits; ++unit) { 3259 struct com_s *com; 3260 int incc; 3261 struct tty *tp; 3262 3263 com = com_addr(unit); 3264 if (com == NULL) 3265 continue; 3266 tp = com->tp; 3267 if (tp == NULL || com->gone) { 3268 /* 3269 * Discard any events related to never-opened or 3270 * going-away devices. 3271 */ 3272 disable_intr(); 3273 incc = com->iptr - com->ibuf; 3274 com->iptr = com->ibuf; 3275 if (com->state & CS_CHECKMSR) { 3276 incc += LOTS_OF_EVENTS; 3277 com->state &= ~CS_CHECKMSR; 3278 } 3279 com_events -= incc; 3280 enable_intr(); 3281 continue; 3282 } 3283 if (com->iptr != com->ibuf) { 3284 disable_intr(); 3285 sioinput(com); 3286 enable_intr(); 3287 } 3288 if (com->state & CS_CHECKMSR) { 3289 u_char delta_modem_status; 3290 3291#ifdef PC98 3292 if (!IS_8251(com->pc98_if_type)) { 3293#endif 3294 disable_intr(); 3295 delta_modem_status = com->last_modem_status 3296 ^ com->prev_modem_status; 3297 com->prev_modem_status = com->last_modem_status; 3298 com_events -= LOTS_OF_EVENTS; 3299 com->state &= ~CS_CHECKMSR; 3300 enable_intr(); 3301 if (delta_modem_status & MSR_DCD) 3302 (*linesw[tp->t_line].l_modem) 3303 (tp, com->prev_modem_status & MSR_DCD); 3304#ifdef PC98 3305 } 3306#endif 3307 } 3308 if (com->state & CS_ODONE) { 3309 disable_intr(); 3310 com_events -= LOTS_OF_EVENTS; 3311 com->state &= ~CS_ODONE; 3312 enable_intr(); 3313 if (!(com->state & CS_BUSY) 3314 && !(com->extra_state & CSE_BUSYCHECK)) { 3315 timeout(siobusycheck, com, hz / 100); 3316 com->extra_state |= CSE_BUSYCHECK; 3317 } 3318 (*linesw[tp->t_line].l_start)(tp); 3319 } 3320 if (com_events == 0) 3321 break; 3322 } 3323 if (com_events >= LOTS_OF_EVENTS) 3324 goto repeat; 3325} 3326 3327static int 3328comparam(tp, t) 3329 struct tty *tp; 3330 struct termios *t; 3331{ 3332 u_int cfcr; 3333 int cflag; 3334 struct com_s *com; 3335 int divisor; 3336 u_char dlbh; 3337 u_char dlbl; 3338 Port_t iobase; 3339 int s; 3340 int unit; 3341#ifdef PC98 3342 int port_shift = 0; 3343 u_char param = 0; 3344#endif 3345 3346#ifdef PC98 3347 cfcr = 0; 3348 unit = DEV_TO_UNIT(tp->t_dev); 3349 com = com_addr(unit); 3350 iobase = com->iobase; 3351 if (IS_8251(com->pc98_if_type)) { 3352 divisor = pc98_ttspeedtab(com, t->c_ospeed); 3353 } else { 3354 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift; 3355 3356 /* do historical conversions */ 3357 if (t->c_ispeed == 0) 3358 t->c_ispeed = t->c_ospeed; 3359 3360 /* check requested parameters */ 3361 divisor = ttspeedtab(t->c_ospeed, 3362 if_16550a_type[com->pc98_if_type & 0x0f].speedtab); 3363 } 3364#else 3365 /* do historical conversions */ 3366 if (t->c_ispeed == 0) 3367 t->c_ispeed = t->c_ospeed; 3368 3369 /* check requested parameters */ 3370 divisor = ttspeedtab(t->c_ospeed, comspeedtab); 3371#endif 3372 if (divisor < 0 || (divisor > 0 && t->c_ispeed != t->c_ospeed)) 3373 return (EINVAL); 3374 3375 /* parameters are OK, convert them to the com struct and the device */ 3376#ifndef PC98 3377 unit = DEV_TO_UNIT(tp->t_dev); 3378 com = com_addr(unit); 3379 iobase = com->iobase; 3380#endif 3381 s = spltty(); 3382#ifdef PC98 3383 if (IS_8251(com->pc98_if_type)) { 3384 if (divisor == 0) 3385 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE ); 3386 else 3387 com_tiocm_bis( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE ); 3388 } else { 3389#endif 3390 if (divisor == 0) 3391 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */ 3392 else 3393 (void)commctl(com, TIOCM_DTR, DMBIS); 3394#ifdef PC98 3395 } 3396#endif 3397 cflag = t->c_cflag; 3398#ifdef PC98 3399 if (!IS_8251(com->pc98_if_type)) { 3400#endif 3401 switch (cflag & CSIZE) { 3402 case CS5: 3403 cfcr = CFCR_5BITS; 3404 break; 3405 case CS6: 3406 cfcr = CFCR_6BITS; 3407 break; 3408 case CS7: 3409 cfcr = CFCR_7BITS; 3410 break; 3411 default: 3412 cfcr = CFCR_8BITS; 3413 break; 3414 } 3415 if (cflag & PARENB) { 3416 cfcr |= CFCR_PENAB; 3417 if (!(cflag & PARODD)) 3418 cfcr |= CFCR_PEVEN; 3419 } 3420 if (cflag & CSTOPB) 3421 cfcr |= CFCR_STOPB; 3422 3423 if (com->hasfifo && divisor != 0) { 3424 /* 3425 * Use a fifo trigger level low enough so that the input 3426 * latency from the fifo is less than about 16 msec and 3427 * the total latency is less than about 30 msec. These 3428 * latencies are reasonable for humans. Serial comms 3429 * protocols shouldn't expect anything better since modem 3430 * latencies are larger. 3431 */ 3432 com->fifo_image = t->c_ospeed <= 4800 3433 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_HIGH; 3434#ifdef COM_ESP 3435 /* 3436 * The Hayes ESP card needs the fifo DMA mode bit set 3437 * in compatibility mode. If not, it will interrupt 3438 * for each character received. 3439 */ 3440 if (com->esp) 3441 com->fifo_image |= FIFO_DMA_MODE; 3442#endif 3443#ifdef PC98 3444 outb(iobase + (com_fifo << port_shift), com->fifo_image); 3445#else 3446 outb(iobase + com_fifo, com->fifo_image); 3447#endif 3448 } 3449#ifdef PC98 3450 } 3451#endif 3452 3453 /* 3454 * This returns with interrupts disabled so that we can complete 3455 * the speed change atomically. Keeping interrupts disabled is 3456 * especially important while com_data is hidden. 3457 */ 3458 (void) siosetwater(com, t->c_ispeed); 3459 3460#ifdef PC98 3461 if (IS_8251(com->pc98_if_type)) 3462 com_cflag_and_speed_set(com, cflag, t->c_ospeed); 3463 else { 3464#endif 3465 if (divisor != 0) { 3466#ifdef PC98 3467 outb(iobase + (com_cfcr << port_shift), cfcr | CFCR_DLAB); 3468#else 3469 outb(iobase + com_cfcr, cfcr | CFCR_DLAB); 3470#endif 3471 /* 3472 * Only set the divisor registers if they would change, 3473 * since on some 16550 incompatibles (UMC8669F), setting 3474 * them while input is arriving them loses sync until 3475 * data stops arriving. 3476 */ 3477 dlbl = divisor & 0xFF; 3478#ifdef PC98 3479 if (inb(iobase + (com_dlbl << port_shift)) != dlbl) 3480 outb(iobase + (com_dlbl << port_shift), dlbl); 3481 dlbh = (u_int) divisor >> 8; 3482 if (inb(iobase + (com_dlbh << port_shift)) != dlbh) 3483 outb(iobase + (com_dlbh << port_shift), dlbh); 3484#else 3485 if (inb(iobase + com_dlbl) != dlbl) 3486 outb(iobase + com_dlbl, dlbl); 3487 dlbh = (u_int) divisor >> 8; 3488 if (inb(iobase + com_dlbh) != dlbh) 3489 outb(iobase + com_dlbh, dlbh); 3490#endif 3491 } 3492 3493 3494#ifdef PC98 3495 } 3496 outb(iobase + (com_cfcr << port_shift), com->cfcr_image = cfcr); 3497#else 3498 outb(iobase + com_cfcr, com->cfcr_image = cfcr); 3499#endif 3500 3501 if (!(tp->t_state & TS_TTSTOP)) 3502 com->state |= CS_TTGO; 3503 3504 if (cflag & CRTS_IFLOW) { 3505 if (com->st16650a) { 3506 outb(iobase + com_cfcr, 0xbf); 3507 outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x40); 3508 } 3509 com->state |= CS_RTS_IFLOW; 3510 /* 3511 * If CS_RTS_IFLOW just changed from off to on, the change 3512 * needs to be propagated to MCR_RTS. This isn't urgent, 3513 * so do it later by calling comstart() instead of repeating 3514 * a lot of code from comstart() here. 3515 */ 3516 } else if (com->state & CS_RTS_IFLOW) { 3517 com->state &= ~CS_RTS_IFLOW; 3518 /* 3519 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS 3520 * on here, since comstart() won't do it later. 3521 */ 3522#ifdef PC98 3523 if (IS_8251(com->pc98_if_type)) 3524 com_tiocm_bis(com, TIOCM_RTS); 3525 else 3526#endif 3527 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3528 if (com->st16650a) { 3529 outb(iobase + com_cfcr, 0xbf); 3530 outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x40); 3531 } 3532 } 3533 3534 3535 /* 3536 * Set up state to handle output flow control. 3537 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level? 3538 * Now has 10+ msec latency, while CTS flow has 50- usec latency. 3539 */ 3540 com->state |= CS_ODEVREADY; 3541 com->state &= ~CS_CTS_OFLOW; 3542#ifdef PC98 3543 if (com->pc98_if_type == COM_IF_RSA98III) { 3544 param = inb(com->rsabase + rsa_msr); 3545 outb(com->rsabase + rsa_msr, param & 0x14); 3546 } 3547#endif 3548 if (cflag & CCTS_OFLOW) { 3549 com->state |= CS_CTS_OFLOW; 3550#ifdef PC98 3551 if (IS_8251(com->pc98_if_type)) { 3552 if (!(pc98_get_modem_status(com) & TIOCM_CTS)) 3553 com->state &= ~CS_ODEVREADY; 3554 } else { 3555#endif 3556#ifdef PC98 3557 if (com->pc98_if_type == COM_IF_RSA98III) { 3558 /* Set automatic flow control mode */ 3559 outb(com->rsabase + rsa_msr, param | 0x08); 3560 } else 3561#endif 3562 if (!(com->last_modem_status & MSR_CTS)) 3563 com->state &= ~CS_ODEVREADY; 3564 if (com->st16650a) { 3565 outb(iobase + com_cfcr, 0xbf); 3566 outb(iobase + com_fifo, inb(iobase + com_fifo) | 0x80); 3567 } 3568#ifdef PC98 3569 } 3570#endif 3571 } else { 3572 if (com->st16650a) { 3573 outb(iobase + com_cfcr, 0xbf); 3574 outb(iobase + com_fifo, inb(iobase + com_fifo) & ~0x80); 3575 } 3576 } 3577 3578 3579#ifdef PC98 3580 outb(iobase + (com_cfcr << port_shift), com->cfcr_image); 3581#else 3582 outb(iobase + com_cfcr, com->cfcr_image); 3583#endif 3584 3585 3586 /* XXX shouldn't call functions while intrs are disabled. */ 3587 disc_optim(tp, t, com); 3588 /* 3589 * Recover from fiddling with CS_TTGO. We used to call siointr1() 3590 * unconditionally, but that defeated the careful discarding of 3591 * stale input in sioopen(). 3592 */ 3593 if (com->state >= (CS_BUSY | CS_TTGO)) 3594 siointr1(com); 3595 3596 enable_intr(); 3597 splx(s); 3598 comstart(tp); 3599 if (com->ibufold != NULL) { 3600 free(com->ibufold, M_DEVBUF); 3601 com->ibufold = NULL; 3602 } 3603 return (0); 3604} 3605 3606static int 3607siosetwater(com, speed) 3608 struct com_s *com; 3609 speed_t speed; 3610{ 3611 int cp4ticks; 3612 u_char *ibuf; 3613 int ibufsize; 3614 struct tty *tp; 3615 3616 /* 3617 * Make the buffer size large enough to handle a softtty interrupt 3618 * latency of about 2 ticks without loss of throughput or data 3619 * (about 3 ticks if input flow control is not used or not honoured, 3620 * but a bit less for CS5-CS7 modes). 3621 */ 3622 cp4ticks = speed / 10 / hz * 4; 3623 for (ibufsize = 128; ibufsize < cp4ticks;) 3624 ibufsize <<= 1; 3625#ifdef PC98 3626 if (com->pc98_if_type == COM_IF_RSA98III) 3627 ibufsize = 2048; 3628#endif 3629 if (ibufsize == com->ibufsize) { 3630 disable_intr(); 3631 return (0); 3632 } 3633 3634 /* 3635 * Allocate input buffer. The extra factor of 2 in the size is 3636 * to allow for an error byte for each input byte. 3637 */ 3638 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT); 3639 if (ibuf == NULL) { 3640 disable_intr(); 3641 return (ENOMEM); 3642 } 3643 3644 /* Initialize non-critical variables. */ 3645 com->ibufold = com->ibuf; 3646 com->ibufsize = ibufsize; 3647 tp = com->tp; 3648 if (tp != NULL) { 3649 tp->t_ififosize = 2 * ibufsize; 3650 tp->t_ispeedwat = (speed_t)-1; 3651 tp->t_ospeedwat = (speed_t)-1; 3652 } 3653 3654 /* 3655 * Read current input buffer, if any. Continue with interrupts 3656 * disabled. 3657 */ 3658 disable_intr(); 3659 if (com->iptr != com->ibuf) 3660 sioinput(com); 3661 3662 /*- 3663 * Initialize critical variables, including input buffer watermarks. 3664 * The external device is asked to stop sending when the buffer 3665 * exactly reaches high water, or when the high level requests it. 3666 * The high level is notified immediately (rather than at a later 3667 * clock tick) when this watermark is reached. 3668 * The buffer size is chosen so the watermark should almost never 3669 * be reached. 3670 * The low watermark is invisibly 0 since the buffer is always 3671 * emptied all at once. 3672 */ 3673 com->iptr = com->ibuf = ibuf; 3674 com->ibufend = ibuf + ibufsize; 3675 com->ierroff = ibufsize; 3676 com->ihighwater = ibuf + 3 * ibufsize / 4; 3677 return (0); 3678} 3679 3680static void 3681comstart(tp) 3682 struct tty *tp; 3683{ 3684 struct com_s *com; 3685 int s; 3686 int unit; 3687 3688 unit = DEV_TO_UNIT(tp->t_dev); 3689 com = com_addr(unit); 3690 s = spltty(); 3691 disable_intr(); 3692 if (tp->t_state & TS_TTSTOP) 3693 com->state &= ~CS_TTGO; 3694 else 3695 com->state |= CS_TTGO; 3696 if (tp->t_state & TS_TBLOCK) { 3697#ifdef PC98 3698 if (IS_8251(com->pc98_if_type)) { 3699 if ((com_tiocm_get(com) & TIOCM_RTS) && 3700 (com->state & CS_RTS_IFLOW)) 3701 com_tiocm_bic(com, TIOCM_RTS); 3702 } else { 3703 if ((com->mcr_image & MCR_RTS) && 3704 (com->state & CS_RTS_IFLOW)) 3705 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3706 } 3707#else 3708 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW) 3709 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3710#endif 3711 } else { 3712#ifdef PC98 3713 if (IS_8251(com->pc98_if_type)) { 3714 if (!(com_tiocm_get(com) & TIOCM_RTS) && 3715 com->iptr < com->ihighwater && 3716 com->state & CS_RTS_IFLOW) 3717 com_tiocm_bis(com, TIOCM_RTS); 3718 } else { 3719 if (!(com->mcr_image & MCR_RTS) && 3720 com->iptr < com->ihighwater && 3721 com->state & CS_RTS_IFLOW) 3722 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3723 } 3724#else 3725 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater 3726 && com->state & CS_RTS_IFLOW) 3727 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3728#endif 3729 } 3730 enable_intr(); 3731 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) { 3732 ttwwakeup(tp); 3733#ifdef PC98 3734/* if(IS_8251(com->pc98_if_type)) 3735 com_int_Tx_enable(com); */ 3736#endif 3737 splx(s); 3738 return; 3739 } 3740 if (tp->t_outq.c_cc != 0) { 3741 struct lbq *qp; 3742 struct lbq *next; 3743 3744 if (!com->obufs[0].l_queued) { 3745 com->obufs[0].l_tail 3746 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1, 3747#ifndef PC98 3748 sizeof com->obuf1); 3749#else 3750 com->obufsize); 3751#endif 3752 com->obufs[0].l_next = NULL; 3753 com->obufs[0].l_queued = TRUE; 3754 disable_intr(); 3755 if (com->state & CS_BUSY) { 3756 qp = com->obufq.l_next; 3757 while ((next = qp->l_next) != NULL) 3758 qp = next; 3759 qp->l_next = &com->obufs[0]; 3760 } else { 3761 com->obufq.l_head = com->obufs[0].l_head; 3762 com->obufq.l_tail = com->obufs[0].l_tail; 3763 com->obufq.l_next = &com->obufs[0]; 3764 com->state |= CS_BUSY; 3765 } 3766 enable_intr(); 3767 } 3768 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) { 3769 com->obufs[1].l_tail 3770 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2, 3771#ifndef PC98 3772 sizeof com->obuf2); 3773#else 3774 com->obufsize); 3775#endif 3776 com->obufs[1].l_next = NULL; 3777 com->obufs[1].l_queued = TRUE; 3778 disable_intr(); 3779 if (com->state & CS_BUSY) { 3780 qp = com->obufq.l_next; 3781 while ((next = qp->l_next) != NULL) 3782 qp = next; 3783 qp->l_next = &com->obufs[1]; 3784 } else { 3785 com->obufq.l_head = com->obufs[1].l_head; 3786 com->obufq.l_tail = com->obufs[1].l_tail; 3787 com->obufq.l_next = &com->obufs[1]; 3788 com->state |= CS_BUSY; 3789 } 3790 enable_intr(); 3791 } 3792 tp->t_state |= TS_BUSY; 3793 } 3794 disable_intr(); 3795 if (com->state >= (CS_BUSY | CS_TTGO)) 3796 siointr1(com); /* fake interrupt to start output */ 3797 enable_intr(); 3798#ifdef PC98 3799/* if(IS_8251(com->pc98_if_type)) 3800 com_int_Tx_enable(com); */ 3801#endif 3802 ttwwakeup(tp); 3803 splx(s); 3804} 3805 3806static void 3807comstop(tp, rw) 3808 struct tty *tp; 3809 int rw; 3810{ 3811 struct com_s *com; 3812#ifdef PC98 3813 int port_shift = 0; 3814 int rsa98_tmp = 0; 3815#endif 3816 3817 com = com_addr(DEV_TO_UNIT(tp->t_dev)); 3818 if (com->gone) 3819 return; 3820#ifdef PC98 3821 if (!IS_8251(com->pc98_if_type)) 3822 port_shift = if_16550a_type[com->pc98_if_type & 0x0f].port_shift; 3823#endif 3824 disable_intr(); 3825 if (rw & FWRITE) { 3826 if (com->hasfifo) 3827#ifdef COM_ESP 3828 /* XXX avoid h/w bug. */ 3829 if (!com->esp) 3830#endif 3831#ifdef PC98 3832 outb(com->iobase + (com_fifo << port_shift), 3833 FIFO_XMT_RST | com->fifo_image); 3834 if (com->pc98_if_type == COM_IF_RSA98III) 3835 for(rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3836 outb(com->iobase + (com_fifo << port_shift), 3837 FIFO_XMT_RST | com->fifo_image); 3838#else 3839 outb(com->iobase + com_fifo, 3840 FIFO_XMT_RST | com->fifo_image); 3841#endif 3842 com->obufs[0].l_queued = FALSE; 3843 com->obufs[1].l_queued = FALSE; 3844 if (com->state & CS_ODONE) 3845 com_events -= LOTS_OF_EVENTS; 3846 com->state &= ~(CS_ODONE | CS_BUSY); 3847 com->tp->t_state &= ~TS_BUSY; 3848 } 3849 if (rw & FREAD) { 3850 if (com->hasfifo) 3851#ifdef COM_ESP 3852 /* XXX avoid h/w bug. */ 3853 if (!com->esp) 3854#endif 3855#ifdef PC98 3856 if (com->pc98_if_type == COM_IF_RSA98III) { 3857 for(rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3858 inb(com->data_port); 3859 } 3860 outb(com->iobase + (com_fifo << port_shift), 3861 FIFO_RCV_RST | com->fifo_image); 3862#else 3863 outb(com->iobase + com_fifo, 3864 FIFO_RCV_RST | com->fifo_image); 3865#endif 3866 com_events -= (com->iptr - com->ibuf); 3867 com->iptr = com->ibuf; 3868 } 3869 enable_intr(); 3870 comstart(tp); 3871} 3872 3873static int 3874commctl(com, bits, how) 3875 struct com_s *com; 3876 int bits; 3877 int how; 3878{ 3879 int mcr; 3880 int msr; 3881 3882 if (how == DMGET) { 3883 bits = TIOCM_LE; /* XXX - always enabled while open */ 3884 mcr = com->mcr_image; 3885 if (mcr & MCR_DTR) 3886 bits |= TIOCM_DTR; 3887 if (mcr & MCR_RTS) 3888 bits |= TIOCM_RTS; 3889 msr = com->prev_modem_status; 3890 if (msr & MSR_CTS) 3891 bits |= TIOCM_CTS; 3892 if (msr & MSR_DCD) 3893 bits |= TIOCM_CD; 3894 if (msr & MSR_DSR) 3895 bits |= TIOCM_DSR; 3896 /* 3897 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI 3898 * more volatile by reading the modem status a lot. Perhaps 3899 * we should latch both bits until the status is read here. 3900 */ 3901 if (msr & (MSR_RI | MSR_TERI)) 3902 bits |= TIOCM_RI; 3903 return (bits); 3904 } 3905 mcr = 0; 3906 if (bits & TIOCM_DTR) 3907 mcr |= MCR_DTR; 3908 if (bits & TIOCM_RTS) 3909 mcr |= MCR_RTS; 3910 if (com->gone) 3911 return(0); 3912 disable_intr(); 3913 switch (how) { 3914 case DMSET: 3915 outb(com->modem_ctl_port, 3916 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE)); 3917 break; 3918 case DMBIS: 3919 outb(com->modem_ctl_port, com->mcr_image |= mcr); 3920 break; 3921 case DMBIC: 3922 outb(com->modem_ctl_port, com->mcr_image &= ~mcr); 3923 break; 3924 } 3925 enable_intr(); 3926 return (0); 3927} 3928 3929static void 3930siosettimeout() 3931{ 3932 struct com_s *com; 3933 bool_t someopen; 3934 int unit; 3935 3936 /* 3937 * Set our timeout period to 1 second if no polled devices are open. 3938 * Otherwise set it to max(1/200, 1/hz). 3939 * Enable timeouts iff some device is open. 3940 */ 3941 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 3942 sio_timeout = hz; 3943 someopen = FALSE; 3944 for (unit = 0; unit < sio_numunits; ++unit) { 3945 com = com_addr(unit); 3946 if (com != NULL && com->tp != NULL 3947 && com->tp->t_state & TS_ISOPEN && !com->gone) { 3948 someopen = TRUE; 3949 if (com->poll || com->poll_output) { 3950 sio_timeout = hz > 200 ? hz / 200 : 1; 3951 break; 3952 } 3953 } 3954 } 3955 if (someopen) { 3956 sio_timeouts_until_log = hz / sio_timeout; 3957 sio_timeout_handle = timeout(comwakeup, (void *)NULL, 3958 sio_timeout); 3959 } else { 3960 /* Flush error messages, if any. */ 3961 sio_timeouts_until_log = 1; 3962 comwakeup((void *)NULL); 3963 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 3964 } 3965} 3966 3967static void 3968comwakeup(chan) 3969 void *chan; 3970{ 3971 struct com_s *com; 3972 int unit; 3973 3974 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout); 3975 3976 /* 3977 * Recover from lost output interrupts. 3978 * Poll any lines that don't use interrupts. 3979 */ 3980 for (unit = 0; unit < sio_numunits; ++unit) { 3981 com = com_addr(unit); 3982 if (com != NULL && !com->gone 3983 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) { 3984 disable_intr(); 3985 siointr1(com); 3986 enable_intr(); 3987 } 3988 } 3989 3990 /* 3991 * Check for and log errors, but not too often. 3992 */ 3993 if (--sio_timeouts_until_log > 0) 3994 return; 3995 sio_timeouts_until_log = hz / sio_timeout; 3996 for (unit = 0; unit < sio_numunits; ++unit) { 3997 int errnum; 3998 3999 com = com_addr(unit); 4000 if (com == NULL) 4001 continue; 4002 if (com->gone) 4003 continue; 4004 for (errnum = 0; errnum < CE_NTYPES; ++errnum) { 4005 u_int delta; 4006 u_long total; 4007 4008 disable_intr(); 4009 delta = com->delta_error_counts[errnum]; 4010 com->delta_error_counts[errnum] = 0; 4011 enable_intr(); 4012 if (delta == 0) 4013 continue; 4014 total = com->error_counts[errnum] += delta; 4015 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n", 4016 unit, delta, error_desc[errnum], 4017 delta == 1 ? "" : "s", total); 4018 } 4019 } 4020} 4021 4022#ifdef PC98 4023/* commint is called when modem control line changes */ 4024static void 4025commint(dev_t dev) 4026{ 4027 register struct tty *tp; 4028 int stat,delta; 4029 struct com_s *com; 4030 int mynor,unit; 4031 4032 mynor = minor(dev); 4033 unit = MINOR_TO_UNIT(mynor); 4034 com = com_addr(unit); 4035 tp = com->tp; 4036 4037 stat = com_tiocm_get(com); 4038 delta = com_tiocm_get_delta(com); 4039 4040 if (com->state & CS_CTS_OFLOW) { 4041 if (stat & TIOCM_CTS) 4042 com->state |= CS_ODEVREADY; 4043 else 4044 com->state &= ~CS_ODEVREADY; 4045 } 4046 if ((delta & TIOCM_CAR) && (mynor & CALLOUT_MASK) == 0) { 4047 if (stat & TIOCM_CAR ) 4048 (void)(*linesw[tp->t_line].l_modem)(tp, 1); 4049 else if ((*linesw[tp->t_line].l_modem)(tp, 0) == 0) { 4050 /* negate DTR, RTS */ 4051 com_tiocm_bic(com, (tp->t_cflag & HUPCL) ? 4052 TIOCM_DTR|TIOCM_RTS|TIOCM_LE : TIOCM_LE ); 4053 /* disable IENABLE */ 4054 com_int_TxRx_disable( com ); 4055 } 4056 } 4057} 4058#endif 4059 4060static void 4061disc_optim(tp, t, com) 4062 struct tty *tp; 4063 struct termios *t; 4064 struct com_s *com; 4065{ 4066 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 4067 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 4068 && (!(t->c_iflag & PARMRK) 4069 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 4070 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 4071 && linesw[tp->t_line].l_rint == ttyinput) 4072 tp->t_state |= TS_CAN_BYPASS_L_RINT; 4073 else 4074 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 4075 com->hotchar = linesw[tp->t_line].l_hotchar; 4076} 4077 4078/* 4079 * Following are all routines needed for SIO to act as console 4080 */ 4081#include <sys/cons.h> 4082 4083struct siocnstate { 4084 u_char dlbl; 4085 u_char dlbh; 4086 u_char ier; 4087 u_char cfcr; 4088 u_char mcr; 4089}; 4090 4091static speed_t siocngetspeed __P((Port_t, struct speedtab *)); 4092static void siocnclose __P((struct siocnstate *sp, Port_t iobase)); 4093static void siocnopen __P((struct siocnstate *sp, Port_t iobase, int speed)); 4094static void siocntxwait __P((Port_t iobase)); 4095 4096static cn_probe_t siocnprobe; 4097static cn_init_t siocninit; 4098static cn_checkc_t siocncheckc; 4099static cn_getc_t siocngetc; 4100static cn_putc_t siocnputc; 4101 4102#ifdef __i386__ 4103CONS_DRIVER(sio, siocnprobe, siocninit, NULL, siocngetc, siocncheckc, 4104 siocnputc, NULL); 4105#endif 4106 4107/* To get the GDB related variables */ 4108#if DDB > 0 4109#include <ddb/ddb.h> 4110#endif 4111 4112static void 4113siocntxwait(iobase) 4114 Port_t iobase; 4115{ 4116 int timo; 4117 4118 /* 4119 * Wait for any pending transmission to finish. Required to avoid 4120 * the UART lockup bug when the speed is changed, and for normal 4121 * transmits. 4122 */ 4123 timo = 100000; 4124 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY)) 4125 != (LSR_TSRE | LSR_TXRDY) && --timo != 0) 4126 ; 4127} 4128 4129/* 4130 * Read the serial port specified and try to figure out what speed 4131 * it's currently running at. We're assuming the serial port has 4132 * been initialized and is basicly idle. This routine is only intended 4133 * to be run at system startup. 4134 * 4135 * If the value read from the serial port doesn't make sense, return 0. 4136 */ 4137 4138static speed_t 4139siocngetspeed(iobase, table) 4140 Port_t iobase; 4141 struct speedtab *table; 4142{ 4143 int code; 4144 u_char dlbh; 4145 u_char dlbl; 4146 u_char cfcr; 4147 4148 cfcr = inb(iobase + com_cfcr); 4149 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 4150 4151 dlbl = inb(iobase + com_dlbl); 4152 dlbh = inb(iobase + com_dlbh); 4153 4154 outb(iobase + com_cfcr, cfcr); 4155 4156 code = dlbh << 8 | dlbl; 4157 4158 for (; table->sp_speed != -1; table++) 4159 if (table->sp_code == code) 4160 return (table->sp_speed); 4161 4162 return 0; /* didn't match anything sane */ 4163} 4164 4165static void 4166siocnopen(sp, iobase, speed) 4167 struct siocnstate *sp; 4168 Port_t iobase; 4169 int speed; 4170{ 4171 int divisor; 4172 u_char dlbh; 4173 u_char dlbl; 4174 4175 /* 4176 * Save all the device control registers except the fifo register 4177 * and set our default ones (cs8 -parenb speed=comdefaultrate). 4178 * We can't save the fifo register since it is read-only. 4179 */ 4180 sp->ier = inb(iobase + com_ier); 4181 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */ 4182 siocntxwait(iobase); 4183 sp->cfcr = inb(iobase + com_cfcr); 4184 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 4185 sp->dlbl = inb(iobase + com_dlbl); 4186 sp->dlbh = inb(iobase + com_dlbh); 4187 /* 4188 * Only set the divisor registers if they would change, since on 4189 * some 16550 incompatibles (Startech), setting them clears the 4190 * data input register. This also reduces the effects of the 4191 * UMC8669F bug. 4192 */ 4193 divisor = ttspeedtab(speed, comspeedtab); 4194 dlbl = divisor & 0xFF; 4195 if (sp->dlbl != dlbl) 4196 outb(iobase + com_dlbl, dlbl); 4197 dlbh = (u_int) divisor >> 8; 4198 if (sp->dlbh != dlbh) 4199 outb(iobase + com_dlbh, dlbh); 4200 outb(iobase + com_cfcr, CFCR_8BITS); 4201 sp->mcr = inb(iobase + com_mcr); 4202 /* 4203 * We don't want interrupts, but must be careful not to "disable" 4204 * them by clearing the MCR_IENABLE bit, since that might cause 4205 * an interrupt by floating the IRQ line. 4206 */ 4207 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS); 4208} 4209 4210static void 4211siocnclose(sp, iobase) 4212 struct siocnstate *sp; 4213 Port_t iobase; 4214{ 4215 /* 4216 * Restore the device control registers. 4217 */ 4218 siocntxwait(iobase); 4219 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 4220 if (sp->dlbl != inb(iobase + com_dlbl)) 4221 outb(iobase + com_dlbl, sp->dlbl); 4222 if (sp->dlbh != inb(iobase + com_dlbh)) 4223 outb(iobase + com_dlbh, sp->dlbh); 4224 outb(iobase + com_cfcr, sp->cfcr); 4225 /* 4226 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them. 4227 */ 4228 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS); 4229 outb(iobase + com_ier, sp->ier); 4230} 4231 4232static void 4233siocnprobe(cp) 4234 struct consdev *cp; 4235{ 4236 speed_t boot_speed; 4237 u_char cfcr; 4238 int s, unit; 4239 struct siocnstate sp; 4240 4241 /* 4242 * Find our first enabled console, if any. If it is a high-level 4243 * console device, then initialize it and return successfully. 4244 * If it is a low-level console device, then initialize it and 4245 * return unsuccessfully. It must be initialized in both cases 4246 * for early use by console drivers and debuggers. Initializing 4247 * the hardware is not necessary in all cases, since the i/o 4248 * routines initialize it on the fly, but it is necessary if 4249 * input might arrive while the hardware is switched back to an 4250 * uninitialized state. We can't handle multiple console devices 4251 * yet because our low-level routines don't take a device arg. 4252 * We trust the user to set the console flags properly so that we 4253 * don't need to probe. 4254 */ 4255 cp->cn_pri = CN_DEAD; 4256 4257 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */ 4258 int flags; 4259 int disabled; 4260 if (resource_int_value("sio", unit, "disabled", &disabled) == 0) { 4261 if (disabled) 4262 continue; 4263 } 4264 if (resource_int_value("sio", unit, "flags", &flags)) 4265 continue; 4266 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) { 4267 int port; 4268 Port_t iobase; 4269 4270 if (resource_int_value("sio", unit, "port", &port)) 4271 continue; 4272 iobase = port; 4273 s = spltty(); 4274 if (boothowto & RB_SERIAL) { 4275 boot_speed = siocngetspeed(iobase, comspeedtab); 4276 if (boot_speed) 4277 comdefaultrate = boot_speed; 4278 } 4279 4280 /* 4281 * Initialize the divisor latch. We can't rely on 4282 * siocnopen() to do this the first time, since it 4283 * avoids writing to the latch if the latch appears 4284 * to have the correct value. Also, if we didn't 4285 * just read the speed from the hardware, then we 4286 * need to set the speed in hardware so that 4287 * switching it later is null. 4288 */ 4289 cfcr = inb(iobase + com_cfcr); 4290 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 4291 outb(iobase + com_dlbl, 4292 COMBRD(comdefaultrate) & 0xff); 4293 outb(iobase + com_dlbh, 4294 (u_int) COMBRD(comdefaultrate) >> 8); 4295 outb(iobase + com_cfcr, cfcr); 4296 4297 siocnopen(&sp, iobase, comdefaultrate); 4298 4299 splx(s); 4300 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) { 4301 cp->cn_dev = makedev(CDEV_MAJOR, unit); 4302 cp->cn_pri = COM_FORCECONSOLE(flags) 4303 || boothowto & RB_SERIAL 4304 ? CN_REMOTE : CN_NORMAL; 4305 siocniobase = iobase; 4306 siocnunit = unit; 4307 } 4308 if (COM_DEBUGGER(flags)) { 4309 printf("sio%d: gdb debugging port\n", unit); 4310 siogdbiobase = iobase; 4311 siogdbunit = unit; 4312#if DDB > 0 4313 gdbdev = makedev(CDEV_MAJOR, unit); 4314 gdb_getc = siocngetc; 4315 gdb_putc = siocnputc; 4316#endif 4317 } 4318 } 4319 } 4320#ifdef __i386__ 4321#if DDB > 0 4322 /* 4323 * XXX Ugly Compatability. 4324 * If no gdb port has been specified, set it to be the console 4325 * as some configuration files don't specify the gdb port. 4326 */ 4327 if (gdbdev == NODEV && (boothowto & RB_GDB)) { 4328 printf("Warning: no GDB port specified. Defaulting to sio%d.\n", 4329 siocnunit); 4330 printf("Set flag 0x80 on desired GDB port in your\n"); 4331 printf("configuration file (currently sio only).\n"); 4332 siogdbiobase = siocniobase; 4333 siogdbunit = siocnunit; 4334 gdbdev = makedev(CDEV_MAJOR, siocnunit); 4335 gdb_getc = siocngetc; 4336 gdb_putc = siocnputc; 4337 } 4338#endif 4339#endif 4340} 4341 4342#ifdef __alpha__ 4343 4344CONS_DRIVER(sio, NULL, NULL, NULL, siocngetc, siocncheckc, siocnputc, NULL); 4345 4346int 4347siocnattach(port, speed) 4348 int port; 4349 int speed; 4350{ 4351 int s; 4352 u_char cfcr; 4353 struct siocnstate sp; 4354 4355 siocniobase = port; 4356 comdefaultrate = speed; 4357 sio_consdev.cn_pri = CN_NORMAL; 4358 sio_consdev.cn_dev = makedev(CDEV_MAJOR, 0); 4359 4360 s = spltty(); 4361 4362 /* 4363 * Initialize the divisor latch. We can't rely on 4364 * siocnopen() to do this the first time, since it 4365 * avoids writing to the latch if the latch appears 4366 * to have the correct value. Also, if we didn't 4367 * just read the speed from the hardware, then we 4368 * need to set the speed in hardware so that 4369 * switching it later is null. 4370 */ 4371 cfcr = inb(siocniobase + com_cfcr); 4372 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr); 4373 outb(siocniobase + com_dlbl, 4374 COMBRD(comdefaultrate) & 0xff); 4375 outb(siocniobase + com_dlbh, 4376 (u_int) COMBRD(comdefaultrate) >> 8); 4377 outb(siocniobase + com_cfcr, cfcr); 4378 4379 siocnopen(&sp, siocniobase, comdefaultrate); 4380 splx(s); 4381 4382 cn_tab = &sio_consdev; 4383 return 0; 4384} 4385 4386int 4387siogdbattach(port, speed) 4388 int port; 4389 int speed; 4390{ 4391 int s; 4392 u_char cfcr; 4393 struct siocnstate sp; 4394 4395 siogdbiobase = port; 4396 gdbdefaultrate = speed; 4397 4398 s = spltty(); 4399 4400 /* 4401 * Initialize the divisor latch. We can't rely on 4402 * siocnopen() to do this the first time, since it 4403 * avoids writing to the latch if the latch appears 4404 * to have the correct value. Also, if we didn't 4405 * just read the speed from the hardware, then we 4406 * need to set the speed in hardware so that 4407 * switching it later is null. 4408 */ 4409 cfcr = inb(siogdbiobase + com_cfcr); 4410 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr); 4411 outb(siogdbiobase + com_dlbl, 4412 COMBRD(gdbdefaultrate) & 0xff); 4413 outb(siogdbiobase + com_dlbh, 4414 (u_int) COMBRD(gdbdefaultrate) >> 8); 4415 outb(siogdbiobase + com_cfcr, cfcr); 4416 4417 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 4418 splx(s); 4419 4420 return 0; 4421} 4422 4423#endif 4424 4425static void 4426siocninit(cp) 4427 struct consdev *cp; 4428{ 4429 comconsole = DEV_TO_UNIT(cp->cn_dev); 4430} 4431 4432static int 4433siocncheckc(dev) 4434 dev_t dev; 4435{ 4436 int c; 4437 Port_t iobase; 4438 int s; 4439 struct siocnstate sp; 4440 4441 if (minor(dev) == siogdbunit) 4442 iobase = siogdbiobase; 4443 else 4444 iobase = siocniobase; 4445 s = spltty(); 4446 siocnopen(&sp, iobase, comdefaultrate); 4447 if (inb(iobase + com_lsr) & LSR_RXRDY) 4448 c = inb(iobase + com_data); 4449 else 4450 c = -1; 4451 siocnclose(&sp, iobase); 4452 splx(s); 4453 return (c); 4454} 4455 4456 4457int 4458siocngetc(dev) 4459 dev_t dev; 4460{ 4461 int c; 4462 Port_t iobase; 4463 int s; 4464 struct siocnstate sp; 4465 4466 if (minor(dev) == siogdbunit) 4467 iobase = siogdbiobase; 4468 else 4469 iobase = siocniobase; 4470 s = spltty(); 4471 siocnopen(&sp, iobase, comdefaultrate); 4472 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 4473 ; 4474 c = inb(iobase + com_data); 4475 siocnclose(&sp, iobase); 4476 splx(s); 4477 return (c); 4478} 4479 4480void 4481siocnputc(dev, c) 4482 dev_t dev; 4483 int c; 4484{ 4485 int s; 4486 struct siocnstate sp; 4487 Port_t iobase; 4488 4489 if (minor(dev) == siogdbunit) 4490 iobase = siogdbiobase; 4491 else 4492 iobase = siocniobase; 4493 s = spltty(); 4494 siocnopen(&sp, iobase, comdefaultrate); 4495 siocntxwait(iobase); 4496 outb(iobase + com_data, c); 4497 siocnclose(&sp, iobase); 4498 splx(s); 4499} 4500 4501#ifdef __alpha__ 4502int 4503siogdbgetc() 4504{ 4505 int c; 4506 Port_t iobase; 4507 int s; 4508 struct siocnstate sp; 4509 4510 iobase = siogdbiobase; 4511 s = spltty(); 4512 siocnopen(&sp, iobase, gdbdefaultrate); 4513 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 4514 ; 4515 c = inb(iobase + com_data); 4516 siocnclose(&sp, iobase); 4517 splx(s); 4518 return (c); 4519} 4520 4521void 4522siogdbputc(c) 4523 int c; 4524{ 4525 int s; 4526 struct siocnstate sp; 4527 4528 s = spltty(); 4529 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 4530 siocntxwait(siogdbiobase); 4531 outb(siogdbiobase + com_data, c); 4532 siocnclose(&sp, siogdbiobase); 4533 splx(s); 4534} 4535#endif 4536 4537DRIVER_MODULE(sio, isa, sio_isa_driver, sio_devclass, 0, 0); 4538#if NCARD > 0 4539DRIVER_MODULE(sio, pccard, sio_pccard_driver, sio_devclass, 0, 0); 4540#endif 4541 4542#ifdef PC98 4543/* 4544 * pc98 local function 4545 */ 4546 4547static void 4548com_tiocm_set(struct com_s *com, int msr) 4549{ 4550 int s; 4551 int tmp = 0; 4552 int mask = CMD8251_TxEN|CMD8251_RxEN|CMD8251_DTR|CMD8251_RTS; 4553 4554 s=spltty(); 4555 com->pc98_prev_modem_status = ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ) 4556 | ( com->pc98_prev_modem_status & ~(TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4557 tmp |= (CMD8251_TxEN|CMD8251_RxEN); 4558 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4559 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4560 pc98_i8251_clear_or_cmd( com, mask, tmp ); 4561 splx(s); 4562} 4563 4564static void 4565com_tiocm_bis(struct com_s *com, int msr) 4566{ 4567 int s; 4568 int tmp = 0; 4569 4570 s=spltty(); 4571 com->pc98_prev_modem_status |= ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4572 tmp |= CMD8251_TxEN|CMD8251_RxEN; 4573 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4574 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4575 4576 pc98_i8251_or_cmd( com, tmp ); 4577 splx(s); 4578} 4579 4580static void 4581com_tiocm_bic(struct com_s *com, int msr) 4582{ 4583 int s; 4584 int tmp = msr; 4585 4586 s=spltty(); 4587 com->pc98_prev_modem_status &= ~( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4588 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4589 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4590 4591 pc98_i8251_clear_cmd( com, tmp ); 4592 splx(s); 4593} 4594 4595static int 4596com_tiocm_get(struct com_s *com) 4597{ 4598 return( com->pc98_prev_modem_status ); 4599} 4600 4601static int 4602com_tiocm_get_delta(struct com_s *com) 4603{ 4604 int tmp; 4605 4606 tmp = com->pc98_modem_delta; 4607 com->pc98_modem_delta = 0; 4608 return( tmp ); 4609} 4610 4611/* convert to TIOCM_?? ( ioctl.h ) */ 4612static int 4613pc98_get_modem_status(struct com_s *com) 4614{ 4615 register int msr; 4616 4617 msr = com->pc98_prev_modem_status 4618 & ~(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 4619 if (com->pc98_8251fifo_enable) { 4620 int stat2; 4621 4622 stat2 = inb(I8251F_msr); 4623 if ( stat2 & CICSCDF_CD ) msr |= TIOCM_CAR; 4624 if ( stat2 & CICSCDF_CI ) msr |= TIOCM_RI; 4625 if ( stat2 & CICSCDF_DR ) msr |= TIOCM_DSR; 4626 if ( stat2 & CICSCDF_CS ) msr |= TIOCM_CTS; 4627#if COM_CARRIER_DETECT_EMULATE 4628 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 4629 msr |= TIOCM_CAR; 4630 } 4631#endif 4632 } else { 4633 int stat, stat2; 4634 4635 stat = inb(com->sts_port); 4636 stat2 = inb(com->in_modem_port); 4637 if ( !(stat2 & CICSCD_CD) ) msr |= TIOCM_CAR; 4638 if ( !(stat2 & CICSCD_CI) ) msr |= TIOCM_RI; 4639 if ( stat & STS8251_DSR ) msr |= TIOCM_DSR; 4640 if ( !(stat2 & CICSCD_CS) ) msr |= TIOCM_CTS; 4641#if COM_CARRIER_DETECT_EMULATE 4642 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 4643 msr |= TIOCM_CAR; 4644 } 4645#endif 4646 } 4647 return(msr); 4648} 4649 4650static void 4651pc98_check_msr(void* chan) 4652{ 4653 int msr, delta; 4654 int s; 4655 register struct tty *tp; 4656 struct com_s *com; 4657 int mynor; 4658 int unit; 4659 dev_t dev; 4660 4661 dev=(dev_t)chan; 4662 mynor = minor(dev); 4663 unit = MINOR_TO_UNIT(mynor); 4664 com = com_addr(unit); 4665 tp = com->tp; 4666 4667 s = spltty(); 4668 msr = pc98_get_modem_status(com); 4669 /* make change flag */ 4670 delta = msr ^ com->pc98_prev_modem_status; 4671 if ( delta & TIOCM_CAR ) { 4672 if ( com->modem_car_chg_timer ) { 4673 if ( -- com->modem_car_chg_timer ) 4674 msr ^= TIOCM_CAR; 4675 } else { 4676 if ((com->modem_car_chg_timer = (msr & TIOCM_CAR) ? 4677 DCD_ON_RECOGNITION : DCD_OFF_TOLERANCE) != 0) 4678 msr ^= TIOCM_CAR; 4679 } 4680 } else 4681 com->modem_car_chg_timer = 0; 4682 delta = ( msr ^ com->pc98_prev_modem_status ) & 4683 (TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 4684 com->pc98_prev_modem_status = msr; 4685 delta = ( com->pc98_modem_delta |= delta ); 4686 splx(s); 4687 if ( com->modem_checking || (tp->t_state & (TS_ISOPEN)) ) { 4688 if ( delta ) { 4689 commint(dev); 4690 } 4691 timeout(pc98_check_msr, (caddr_t)dev, 4692 PC98_CHECK_MODEM_INTERVAL); 4693 } else { 4694 com->modem_checking = 0; 4695 } 4696} 4697 4698static void 4699pc98_msrint_start(dev_t dev) 4700{ 4701 struct com_s *com; 4702 int mynor; 4703 int unit; 4704 int s = spltty(); 4705 4706 mynor = minor(dev); 4707 unit = MINOR_TO_UNIT(mynor); 4708 com = com_addr(unit); 4709 /* modem control line check routine envoke interval is 1/10 sec */ 4710 if ( com->modem_checking == 0 ) { 4711 com->pc98_prev_modem_status = pc98_get_modem_status(com); 4712 com->pc98_modem_delta = 0; 4713 timeout(pc98_check_msr, (caddr_t)dev, 4714 PC98_CHECK_MODEM_INTERVAL); 4715 com->modem_checking = 1; 4716 } 4717 splx(s); 4718} 4719 4720static void 4721pc98_disable_i8251_interrupt(struct com_s *com, int mod) 4722{ 4723 /* disable interrupt */ 4724 register int tmp; 4725 4726 mod |= ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4727 COM_INT_DISABLE 4728 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4729 outb( com->intr_ctrl_port, (com->intr_enable&=~mod) | tmp ); 4730 COM_INT_ENABLE 4731} 4732 4733static void 4734pc98_enable_i8251_interrupt(struct com_s *com, int mod) 4735{ 4736 register int tmp; 4737 4738 COM_INT_DISABLE 4739 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4740 outb( com->intr_ctrl_port, (com->intr_enable|=mod) | tmp ); 4741 COM_INT_ENABLE 4742} 4743 4744static int 4745pc98_check_i8251_interrupt(struct com_s *com) 4746{ 4747 return ( com->intr_enable & 0x07 ); 4748} 4749 4750static void 4751pc98_i8251_clear_cmd(struct com_s *com, int x) 4752{ 4753 int tmp; 4754 4755 COM_INT_DISABLE 4756 tmp = com->pc98_prev_siocmd & ~(x); 4757 if (com->pc98_8251fifo_enable) 4758 outb(I8251F_fcr, 0); 4759 outb(com->cmd_port, tmp); 4760 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4761 if (com->pc98_8251fifo_enable) 4762 outb(I8251F_fcr, CTRL8251F_ENABLE); 4763 COM_INT_ENABLE 4764} 4765 4766static void 4767pc98_i8251_or_cmd(struct com_s *com, int x) 4768{ 4769 int tmp; 4770 4771 COM_INT_DISABLE 4772 if (com->pc98_8251fifo_enable) 4773 outb(I8251F_fcr, 0); 4774 tmp = com->pc98_prev_siocmd | (x); 4775 outb(com->cmd_port, tmp); 4776 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4777 if (com->pc98_8251fifo_enable) 4778 outb(I8251F_fcr, CTRL8251F_ENABLE); 4779 COM_INT_ENABLE 4780} 4781 4782static void 4783pc98_i8251_set_cmd(struct com_s *com, int x) 4784{ 4785 int tmp; 4786 4787 COM_INT_DISABLE 4788 if (com->pc98_8251fifo_enable) 4789 outb(I8251F_fcr, 0); 4790 tmp = (x); 4791 outb(com->cmd_port, tmp); 4792 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4793 if (com->pc98_8251fifo_enable) 4794 outb(I8251F_fcr, CTRL8251F_ENABLE); 4795 COM_INT_ENABLE 4796} 4797 4798static void 4799pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x) 4800{ 4801 int tmp; 4802 COM_INT_DISABLE 4803 if (com->pc98_8251fifo_enable) 4804 outb(I8251F_fcr, 0); 4805 tmp = com->pc98_prev_siocmd & ~(clr); 4806 tmp |= (x); 4807 outb(com->cmd_port, tmp); 4808 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4809 if (com->pc98_8251fifo_enable) 4810 outb(I8251F_fcr, CTRL8251F_ENABLE); 4811 COM_INT_ENABLE 4812} 4813 4814static int 4815pc98_i8251_get_cmd(struct com_s *com) 4816{ 4817 return com->pc98_prev_siocmd; 4818} 4819 4820static int 4821pc98_i8251_get_mod(struct com_s *com) 4822{ 4823 return com->pc98_prev_siomod; 4824} 4825 4826static void 4827pc98_i8251_reset(struct com_s *com, int mode, int command) 4828{ 4829 if (com->pc98_8251fifo_enable) 4830 outb(I8251F_fcr, 0); 4831 outb(com->cmd_port, 0); /* dummy */ 4832 DELAY(2); 4833 outb(com->cmd_port, 0); /* dummy */ 4834 DELAY(2); 4835 outb(com->cmd_port, 0); /* dummy */ 4836 DELAY(2); 4837 outb(com->cmd_port, CMD8251_RESET); /* internal reset */ 4838 DELAY(2); 4839 outb(com->cmd_port, mode ); /* mode register */ 4840 com->pc98_prev_siomod = mode; 4841 DELAY(2); 4842 pc98_i8251_set_cmd( com, (command|CMD8251_ER) ); 4843 DELAY(10); 4844 if (com->pc98_8251fifo_enable) 4845 outb(I8251F_fcr, CTRL8251F_ENABLE | 4846 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 4847} 4848 4849static void 4850pc98_check_sysclock(void) 4851{ 4852 /* get system clock from port */ 4853 if ( pc98_machine_type & M_8M ) { 4854 /* 8 MHz system & H98 */ 4855 sysclock = 8; 4856 } else { 4857 /* 5 MHz system */ 4858 sysclock = 5; 4859 } 4860} 4861 4862static void 4863com_cflag_and_speed_set( struct com_s *com, int cflag, int speed) 4864{ 4865 int cfcr=0, count; 4866 int previnterrupt; 4867 4868 count = pc98_ttspeedtab( com, speed ); 4869 if ( count < 0 ) return; 4870 4871 previnterrupt = pc98_check_i8251_interrupt(com); 4872 pc98_disable_i8251_interrupt( com, IEN_Tx|IEN_TxEMP|IEN_Rx ); 4873 4874 switch ( cflag&CSIZE ) { 4875 case CS5: 4876 cfcr = MOD8251_5BITS; break; 4877 case CS6: 4878 cfcr = MOD8251_6BITS; break; 4879 case CS7: 4880 cfcr = MOD8251_7BITS; break; 4881 case CS8: 4882 cfcr = MOD8251_8BITS; break; 4883 } 4884 if ( cflag&PARENB ) { 4885 if ( cflag&PARODD ) 4886 cfcr |= MOD8251_PODD; 4887 else 4888 cfcr |= MOD8251_PEVEN; 4889 } else 4890 cfcr |= MOD8251_PDISAB; 4891 4892 if ( cflag&CSTOPB ) 4893 cfcr |= MOD8251_STOP2; 4894 else 4895 cfcr |= MOD8251_STOP1; 4896 4897 if ( count & 0x10000 ) 4898 cfcr |= MOD8251_CLKX1; 4899 else 4900 cfcr |= MOD8251_CLKX16; 4901 4902 if (epson_machine_id != 0x20) { /* XXX */ 4903 int tmp; 4904 while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP)) 4905 ; 4906 } 4907 /* set baud rate from ospeed */ 4908 pc98_set_baud_rate( com, count ); 4909 4910 if ( cfcr != pc98_i8251_get_mod(com) ) 4911 pc98_i8251_reset(com, cfcr, pc98_i8251_get_cmd(com) ); 4912 4913 pc98_enable_i8251_interrupt( com, previnterrupt ); 4914} 4915 4916static int 4917pc98_ttspeedtab(struct com_s *com, int speed) 4918{ 4919 int if_type, effect_sp, count = -1, mod; 4920 4921 if_type = com->pc98_if_type & 0x0f; 4922 4923 switch (com->pc98_if_type) { 4924 case COM_IF_INTERNAL: 4925 if (PC98SIO_baud_rate_port(if_type) != -1) { 4926 count = ttspeedtab(speed, if_8251_type[if_type].speedtab); 4927 if (count > 0) { 4928 count |= COM1_EXT_CLOCK; 4929 break; 4930 } 4931 } 4932 4933 /* for *1CLK asynchronous! mode, TEFUTEFU */ 4934 mod = (sysclock == 5) ? 2457600 : 1996800; 4935 effect_sp = ttspeedtab( speed, pc98speedtab ); 4936 if ( effect_sp < 0 ) /* XXX */ 4937 effect_sp = ttspeedtab( (speed - 1), pc98speedtab ); 4938 if ( effect_sp <= 0 ) 4939 return effect_sp; 4940 if ( effect_sp == speed ) 4941 mod /= 16; 4942 if ( mod % effect_sp ) 4943 return(-1); 4944 count = mod / effect_sp; 4945 if ( count > 65535 ) 4946 return(-1); 4947 if ( effect_sp != speed ) 4948 count |= 0x10000; 4949 break; 4950 case COM_IF_PC9861K_1: 4951 case COM_IF_PC9861K_2: 4952 count = 1; 4953 break; 4954 case COM_IF_IND_SS_1: 4955 case COM_IF_IND_SS_2: 4956 case COM_IF_PIO9032B_1: 4957 case COM_IF_PIO9032B_2: 4958 if ( speed == 0 ) return 0; 4959 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 4960 break; 4961 case COM_IF_B98_01_1: 4962 case COM_IF_B98_01_2: 4963 if ( speed == 0 ) return 0; 4964 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 4965#ifdef B98_01_OLD 4966 if (count == 0 || count == 1) { 4967 count += 4; 4968 count |= 0x20000; /* x1 mode for 76800 and 153600 */ 4969 } 4970#endif 4971 break; 4972 } 4973 4974 return count; 4975} 4976 4977static void 4978pc98_set_baud_rate( struct com_s *com, int count ) 4979{ 4980 int if_type, io, s; 4981 4982 if_type = com->pc98_if_type & 0x0f; 4983 io = com->iobase & 0xff00; 4984 4985 switch (com->pc98_if_type) { 4986 case COM_IF_INTERNAL: 4987 if (PC98SIO_baud_rate_port(if_type) != -1) { 4988 if (count & COM1_EXT_CLOCK) { 4989 outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff); 4990 break; 4991 } else { 4992 outb((Port_t)PC98SIO_baud_rate_port(if_type), 0x09); 4993 } 4994 } 4995 4996 if ( count < 0 ) { 4997 printf( "[ Illegal count : %d ]", count ); 4998 return; 4999 } else if ( count == 0 ) 5000 return; 5001 /* set i8253 */ 5002 s = splclock(); 5003 if (count != 3) 5004 outb( 0x77, 0xb6 ); 5005 else 5006 outb( 0x77, 0xb4 ); 5007 outb( 0x5f, 0); 5008 outb( 0x75, count & 0xff ); 5009 outb( 0x5f, 0); 5010 outb( 0x75, (count >> 8) & 0xff ); 5011 splx(s); 5012 break; 5013 case COM_IF_IND_SS_1: 5014 case COM_IF_IND_SS_2: 5015 outb(io | PC98SIO_intr_ctrl_port(if_type), 0); 5016 outb(io | PC98SIO_baud_rate_port(if_type), 0); 5017 outb(io | PC98SIO_baud_rate_port(if_type), 0xc0); 5018 outb(io | PC98SIO_baud_rate_port(if_type), (count >> 8) | 0x80); 5019 outb(io | PC98SIO_baud_rate_port(if_type), count & 0xff); 5020 break; 5021 case COM_IF_PIO9032B_1: 5022 case COM_IF_PIO9032B_2: 5023 outb(io | PC98SIO_baud_rate_port(if_type), count); 5024 break; 5025 case COM_IF_B98_01_1: 5026 case COM_IF_B98_01_2: 5027 outb(io | PC98SIO_baud_rate_port(if_type), count & 0x0f); 5028#ifdef B98_01_OLD 5029 /* 5030 * Some old B98_01 board should be controlled 5031 * in different way, but this hasn't been tested yet. 5032 */ 5033 outb(io | PC98SIO_func_port(if_type), 5034 (count & 0x20000) ? 0xf0 : 0xf2); 5035#endif 5036 break; 5037 } 5038} 5039static int 5040pc98_check_if_type(device_t dev, struct siodev *iod) 5041{ 5042 int irr, io, if_type, tmp; 5043 static short irq_tab[2][8] = { 5044 { 3, 5, 6, 9, 10, 12, 13, -1}, 5045 { 3, 10, 12, 13, 5, 6, 9, -1} 5046 }; 5047 5048 iod->if_type = if_type = GET_IFTYPE(device_get_flags(dev)); 5049 if ((if_type < 0 || if_type > COM_IF_END1) && 5050 (if_type < 0x10 || if_type > COM_IF_END2)) 5051 return(-1); 5052 if_type &= 0x0f; 5053 iod->irq = 0; 5054 io = isa_get_port(dev) & 0xff00; 5055 5056 if (IS_8251(iod->if_type)) { 5057 if (PC98SIO_func_port(if_type) != -1) { 5058 outb(io | PC98SIO_func_port(if_type), 0xf2); 5059 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab); 5060 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1) 5061 outb(io | PC98SIO_baud_rate_port(if_type), tmp); 5062 } 5063 5064 iod->cmd = io | PC98SIO_cmd_port(if_type); 5065 iod->sts = io | PC98SIO_sts_port(if_type); 5066 iod->mod = io | PC98SIO_in_modem_port(if_type); 5067 iod->ctrl = io | PC98SIO_intr_ctrl_port(if_type); 5068 5069 if (iod->if_type == COM_IF_INTERNAL) { 5070 iod->irq = 4; 5071 5072 if (pc98_check_8251vfast()) { 5073 PC98SIO_baud_rate_port(if_type) = I8251F_div; 5074 if_8251_type[if_type].speedtab = pc98fast_speedtab; 5075 } 5076 } else { 5077 tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask; 5078 if ((isa_get_port(dev) & 0xff) == IO_COM2) 5079 iod->irq = irq_tab[0][tmp]; 5080 else 5081 iod->irq = irq_tab[1][tmp]; 5082 } 5083 } else { 5084 irr = if_16550a_type[if_type].irr_read; 5085#ifdef COM_MULTIPORT 5086 if (!COM_ISMULTIPORT(device_get_flags(dev)) || 5087 device_get_unit(dev) == COM_MPMASTER(device_get_flags(dev))) 5088#endif 5089 if (irr != -1) { 5090 tmp = inb(io | irr); 5091 if (isa_get_port(dev) & 0x01) /* XXX depend on RSB-384 */ 5092 iod->irq = irq_tab[1][tmp >> 3]; 5093 else 5094 iod->irq = irq_tab[0][tmp & 0x07]; 5095 } 5096 } 5097 if ( iod->irq == -1 ) return -1; 5098 5099 return 0; 5100} 5101static int 5102pc98_set_ioport(struct com_s *com) 5103{ 5104 int if_type = com->pc98_if_type & 0x0f; 5105 int io = com->iobase & 0xff00; 5106 5107 if (IS_8251(com->pc98_if_type)) { 5108 pc98_check_sysclock(); 5109 com->data_port = io | PC98SIO_data_port(if_type); 5110 com->cmd_port = io | PC98SIO_cmd_port(if_type); 5111 com->sts_port = io | PC98SIO_sts_port(if_type); 5112 com->in_modem_port = io | PC98SIO_in_modem_port(if_type); 5113 com->intr_ctrl_port = io | PC98SIO_intr_ctrl_port(if_type); 5114 5115 return 0; 5116 } 5117 5118 return -1; 5119} 5120static int 5121pc98_check_8251vfast(void) 5122{ 5123 int i; 5124 5125 outb(I8251F_div, 0x8c); 5126 DELAY(10); 5127 for (i = 0; i < 100; i++) { 5128 if ((inb(I8251F_div) & 0x80) != 0) { 5129 i = 0; 5130 break; 5131 } 5132 DELAY(1); 5133 } 5134 outb(I8251F_div, 0); 5135 DELAY(10); 5136 for (; i < 100; i++) { 5137 if ((inb(I8251F_div) & 0x80) == 0) 5138 return 1; 5139 DELAY(1); 5140 } 5141 5142 return 0; 5143} 5144static int 5145pc98_check_8251fifo(void) 5146{ 5147 u_char tmp1, tmp2; 5148 5149 tmp1 = inb(I8251F_iir); 5150 DELAY(10); 5151 tmp2 = inb(I8251F_iir); 5152 if (((tmp1 ^ tmp2) & 0x40) != 0 && ((tmp1 | tmp2) & 0x20) == 0) 5153 return 1; 5154 5155 return 0; 5156} 5157#endif /* PC98 defined */ 5158