sio.c revision 129001
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 4. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: head/sys/pc98/cbus/sio.c 129001 2004-05-06 13:16:45Z nyan $ 30 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 31 * from: i386/isa sio.c,v 1.234 32 */ 33 34#include "opt_comconsole.h" 35#include "opt_compat.h" 36#include "opt_ddb.h" 37#include "opt_sio.h" 38 39/* 40 * Serial driver, based on 386BSD-0.1 com driver. 41 * Mostly rewritten to use pseudo-DMA. 42 * Works for National Semiconductor NS8250-NS16550AF UARTs. 43 * COM driver, based on HP dca driver. 44 * 45 * Changes for PC-Card integration: 46 * - Added PC-Card driver table and handlers 47 */ 48/*=============================================================== 49 * 386BSD(98),FreeBSD-1.1x(98) com driver. 50 * ----- 51 * modified for PC9801 by M.Ishii 52 * Kyoto University Microcomputer Club (KMC) 53 * Chou "TEFUTEFU" Hirotomi 54 * Kyoto Univ. the faculty of medicine 55 *=============================================================== 56 * FreeBSD-2.0.1(98) sio driver. 57 * ----- 58 * modified for pc98 Internal i8251 and MICRO CORE MC16550II 59 * T.Koike(hfc01340@niftyserve.or.jp) 60 * implement kernel device configuration 61 * aizu@orient.center.nitech.ac.jp 62 * 63 * Notes. 64 * ----- 65 * PC98 localization based on 386BSD(98) com driver. Using its PC98 local 66 * functions. 67 * This driver is under debugging,has bugs. 68 */ 69/* 70 * modified for AIWA B98-01 71 * by T.Hatanou <hatanou@yasuda.comm.waseda.ac.jp> last update: 15 Sep.1995 72 */ 73/* 74 * Modified by Y.Takahashi of Kogakuin University. 75 */ 76/* 77 * modified for 8251(FIFO) by Seigo TANIMURA <tanimura@FreeBSD.org> 78 */ 79 80#include <sys/param.h> 81#include <sys/systm.h> 82#include <sys/bus.h> 83#include <sys/conf.h> 84#include <sys/fcntl.h> 85#include <sys/interrupt.h> 86#include <sys/kernel.h> 87#include <sys/limits.h> 88#include <sys/lock.h> 89#include <sys/malloc.h> 90#include <sys/module.h> 91#include <sys/mutex.h> 92#include <sys/proc.h> 93#include <sys/reboot.h> 94#include <sys/sysctl.h> 95#include <sys/syslog.h> 96#include <sys/tty.h> 97#include <machine/bus.h> 98#include <sys/rman.h> 99#include <sys/timepps.h> 100#include <sys/uio.h> 101#include <sys/cons.h> 102#if DDB > 0 103#include <ddb/ddb.h> 104#endif 105 106#include <isa/isavar.h> 107 108#include <machine/resource.h> 109 110#include <dev/sio/sioreg.h> 111#include <dev/sio/siovar.h> 112 113#ifdef PC98 114#include <pc98/pc98/pc98.h> 115#include <pc98/pc98/pc98_machdep.h> 116#endif 117 118#ifdef COM_ESP 119#include <dev/ic/esp.h> 120#endif 121#include <dev/ic/ns16550.h> 122#ifdef PC98 123#include <dev/ic/i8251.h> 124#include <dev/ic/rsa.h> 125#endif 126 127#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */ 128 129#define CALLOUT_MASK 0x80 130#define CONTROL_MASK 0x60 131#define CONTROL_INIT_STATE 0x20 132#define CONTROL_LOCK_STATE 0x40 133#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev))) 134#define MINOR_TO_UNIT(mynor) ((((mynor) & ~0xffffU) >> (8 + 3)) \ 135 | ((mynor) & 0x1f)) 136#define UNIT_TO_MINOR(unit) ((((unit) & ~0x1fU) << (8 + 3)) \ 137 | ((unit) & 0x1f)) 138 139/* 140 * Meaning of flags: 141 * 142 * 0x00000001 shared IRQs 143 * 0x00000002 disable FIFO 144 * 0x00000008 recover sooner from lost output interrupts 145 * 0x00000010 device is potential system console 146 * 0x00000020 device is forced to become system console 147 * 0x00000040 device is reserved for low-level IO 148 * 0x00000080 use this port for remote kernel debugging 149 * 0x0000??00 minor number of master port 150 * 0x00010000 PPS timestamping on CTS instead of DCD 151 * 0x00080000 IIR_TXRDY bug 152 * 0x00400000 If no comconsole found then mark as a comconsole 153 * 0x1?000000 interface type 154 */ 155 156#ifdef COM_MULTIPORT 157/* checks in flags for multiport and which is multiport "master chip" 158 * for a given card 159 */ 160#define COM_ISMULTIPORT(flags) ((flags) & 0x01) 161#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff) 162#ifndef PC98 163#define COM_NOTAST4(flags) ((flags) & 0x04) 164#endif 165#else 166#define COM_ISMULTIPORT(flags) (0) 167#endif /* COM_MULTIPORT */ 168 169#define COM_C_IIR_TXRDYBUG 0x80000 170#define COM_CONSOLE(flags) ((flags) & 0x10) 171#define COM_DEBUGGER(flags) ((flags) & 0x80) 172#ifndef PC98 173#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24) 174#endif 175#define COM_FORCECONSOLE(flags) ((flags) & 0x20) 176#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG) 177#define COM_LLCONSOLE(flags) ((flags) & 0x40) 178#define COM_LOSESOUTINTS(flags) ((flags) & 0x08) 179#define COM_NOFIFO(flags) ((flags) & 0x02) 180#ifndef PC98 181#define COM_NOSCR(flags) ((flags) & 0x100000) 182#endif 183#define COM_PPSCTS(flags) ((flags) & 0x10000) 184#ifndef PC98 185#define COM_ST16650A(flags) ((flags) & 0x20000) 186#define COM_TI16754(flags) ((flags) & 0x200000) 187#endif 188 189#define sio_getreg(com, off) \ 190 (bus_space_read_1((com)->bst, (com)->bsh, (off))) 191#define sio_setreg(com, off, value) \ 192 (bus_space_write_1((com)->bst, (com)->bsh, (off), (value))) 193 194/* 195 * com state bits. 196 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher 197 * than the other bits so that they can be tested as a group without masking 198 * off the low bits. 199 * 200 * The following com and tty flags correspond closely: 201 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and 202 * comstop()) 203 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart()) 204 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam()) 205 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam()) 206 * TS_FLUSH is not used. 207 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON. 208 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state). 209 */ 210#define CS_BUSY 0x80 /* output in progress */ 211#define CS_TTGO 0x40 /* output not stopped by XOFF */ 212#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */ 213#define CS_CHECKMSR 1 /* check of MSR scheduled */ 214#define CS_CTS_OFLOW 2 /* use CTS output flow control */ 215#define CS_DTR_OFF 0x10 /* DTR held off */ 216#define CS_ODONE 4 /* output completed */ 217#define CS_RTS_IFLOW 8 /* use RTS input flow control */ 218#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */ 219 220static char const * const error_desc[] = { 221#define CE_OVERRUN 0 222 "silo overflow", 223#define CE_INTERRUPT_BUF_OVERFLOW 1 224 "interrupt-level buffer overflow", 225#define CE_TTY_BUF_OVERFLOW 2 226 "tty-level buffer overflow", 227}; 228 229#define CE_NTYPES 3 230#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum]) 231 232/* types. XXX - should be elsewhere */ 233typedef u_int Port_t; /* hardware port */ 234typedef u_char bool_t; /* boolean */ 235 236/* queue of linear buffers */ 237struct lbq { 238 u_char *l_head; /* next char to process */ 239 u_char *l_tail; /* one past the last char to process */ 240 struct lbq *l_next; /* next in queue */ 241 bool_t l_queued; /* nonzero if queued */ 242}; 243 244/* com device structure */ 245struct com_s { 246 u_char state; /* miscellaneous flag bits */ 247 bool_t active_out; /* nonzero if the callout device is open */ 248 u_char cfcr_image; /* copy of value written to CFCR */ 249#ifdef COM_ESP 250 bool_t esp; /* is this unit a hayes esp board? */ 251#endif 252 u_char extra_state; /* more flag bits, separate for order trick */ 253 u_char fifo_image; /* copy of value written to FIFO */ 254 bool_t hasfifo; /* nonzero for 16550 UARTs */ 255 bool_t loses_outints; /* nonzero if device loses output interrupts */ 256 u_char mcr_image; /* copy of value written to MCR */ 257#ifdef COM_MULTIPORT 258 bool_t multiport; /* is this unit part of a multiport device? */ 259#endif /* COM_MULTIPORT */ 260 bool_t no_irq; /* nonzero if irq is not attached */ 261 bool_t gone; /* hardware disappeared */ 262 bool_t poll; /* nonzero if polling is required */ 263 bool_t poll_output; /* nonzero if polling for output is required */ 264 bool_t st16650a; /* nonzero if Startech 16650A compatible */ 265 int unit; /* unit number */ 266 int dtr_wait; /* time to hold DTR down on close (* 1/hz) */ 267 u_int flags; /* copy of device flags */ 268 u_int tx_fifo_size; 269 u_int wopeners; /* # processes waiting for DCD in open() */ 270 271 /* 272 * The high level of the driver never reads status registers directly 273 * because there would be too many side effects to handle conveniently. 274 * Instead, it reads copies of the registers stored here by the 275 * interrupt handler. 276 */ 277 u_char last_modem_status; /* last MSR read by intr handler */ 278 u_char prev_modem_status; /* last MSR handled by high level */ 279 280 u_char hotchar; /* ldisc-specific char to be handled ASAP */ 281 u_char *ibuf; /* start of input buffer */ 282 u_char *ibufend; /* end of input buffer */ 283 u_char *ibufold; /* old input buffer, to be freed */ 284 u_char *ihighwater; /* threshold in input buffer */ 285 u_char *iptr; /* next free spot in input buffer */ 286 int ibufsize; /* size of ibuf (not include error bytes) */ 287 int ierroff; /* offset of error bytes in ibuf */ 288 289 struct lbq obufq; /* head of queue of output buffers */ 290 struct lbq obufs[2]; /* output buffers */ 291 292 bus_space_tag_t bst; 293 bus_space_handle_t bsh; 294 295#ifdef PC98 296 Port_t cmd_port; 297 Port_t sts_port; 298 Port_t in_modem_port; 299 Port_t intr_ctrl_port; 300 Port_t rsabase; /* Iobase address of an I/O-DATA RSA board. */ 301 int intr_enable; 302 int pc98_prev_modem_status; 303 int pc98_modem_delta; 304 int modem_car_chg_timer; 305 int pc98_prev_siocmd; 306 int pc98_prev_siomod; 307 int modem_checking; 308 int pc98_if_type; 309 310 bool_t pc98_8251fifo; 311 bool_t pc98_8251fifo_enable; 312#endif /* PC98 */ 313 Port_t data_port; /* i/o ports */ 314#ifdef COM_ESP 315 Port_t esp_port; 316#endif 317 Port_t int_ctl_port; 318 Port_t int_id_port; 319 Port_t modem_ctl_port; 320 Port_t line_status_port; 321 Port_t modem_status_port; 322 323 struct tty *tp; /* cross reference */ 324 325 /* Initial state. */ 326 struct termios it_in; /* should be in struct tty */ 327 struct termios it_out; 328 329 /* Lock state. */ 330 struct termios lt_in; /* should be in struct tty */ 331 struct termios lt_out; 332 333 bool_t do_timestamp; 334 bool_t do_dcd_timestamp; 335 struct timeval timestamp; 336 struct timeval dcd_timestamp; 337 struct pps_state pps; 338 int pps_bit; 339#ifdef ALT_BREAK_TO_DEBUGGER 340 int alt_brk_state; 341#endif 342 343 u_long bytes_in; /* statistics */ 344 u_long bytes_out; 345 u_int delta_error_counts[CE_NTYPES]; 346 u_long error_counts[CE_NTYPES]; 347 348 u_long rclk; 349 350 struct resource *irqres; 351 struct resource *ioportres; 352 int ioportrid; 353 void *cookie; 354 dev_t devs[6]; 355 356 /* 357 * Data area for output buffers. Someday we should build the output 358 * buffer queue without copying data. 359 */ 360#ifdef PC98 361 int obufsize; 362 u_char *obuf1; 363 u_char *obuf2; 364#else 365 u_char obuf1[256]; 366 u_char obuf2[256]; 367#endif 368}; 369 370#ifdef COM_ESP 371static int espattach(struct com_s *com, Port_t esp_port); 372#endif 373 374static timeout_t siobusycheck; 375static u_int siodivisor(u_long rclk, speed_t speed); 376static timeout_t siodtrwakeup; 377static void comhardclose(struct com_s *com); 378static void sioinput(struct com_s *com); 379static void siointr1(struct com_s *com); 380static void siointr(void *arg); 381static int commctl(struct com_s *com, int bits, int how); 382static int comparam(struct tty *tp, struct termios *t); 383static void siopoll(void *); 384static void siosettimeout(void); 385static int siosetwater(struct com_s *com, speed_t speed); 386static void comstart(struct tty *tp); 387static void comstop(struct tty *tp, int rw); 388static timeout_t comwakeup; 389static void disc_optim(struct tty *tp, struct termios *t, 390 struct com_s *com); 391 392char sio_driver_name[] = "sio"; 393static struct mtx sio_lock; 394static int sio_inited; 395 396/* table and macro for fast conversion from a unit number to its com struct */ 397devclass_t sio_devclass; 398#define com_addr(unit) ((struct com_s *) \ 399 devclass_get_softc(sio_devclass, unit)) /* XXX */ 400 401static d_open_t sioopen; 402static d_close_t sioclose; 403static d_read_t sioread; 404static d_write_t siowrite; 405static d_ioctl_t sioioctl; 406 407static struct cdevsw sio_cdevsw = { 408 .d_version = D_VERSION, 409 .d_open = sioopen, 410 .d_close = sioclose, 411 .d_read = sioread, 412 .d_write = siowrite, 413 .d_ioctl = sioioctl, 414 .d_name = sio_driver_name, 415 .d_flags = D_TTY | D_NEEDGIANT, 416}; 417 418int comconsole = -1; 419static volatile speed_t comdefaultrate = CONSPEED; 420static u_long comdefaultrclk = DEFAULT_RCLK; 421SYSCTL_ULONG(_machdep, OID_AUTO, conrclk, CTLFLAG_RW, &comdefaultrclk, 0, ""); 422static speed_t gdbdefaultrate = GDBSPEED; 423SYSCTL_UINT(_machdep, OID_AUTO, gdbspeed, CTLFLAG_RW, 424 &gdbdefaultrate, GDBSPEED, ""); 425static u_int com_events; /* input chars + weighted output completions */ 426static Port_t siocniobase; 427static int siocnunit = -1; 428static Port_t siogdbiobase; 429static int siogdbunit = -1; 430static void *sio_slow_ih; 431static void *sio_fast_ih; 432static int sio_timeout; 433static int sio_timeouts_until_log; 434static struct callout_handle sio_timeout_handle 435 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle); 436static int sio_numunits; 437 438#ifdef PC98 439struct siodev { 440 short if_type; 441 short irq; 442 Port_t cmd, sts, ctrl, mod; 443}; 444static int sysclock; 445 446#define COM_INT_DISABLE {int previpri; previpri=spltty(); 447#define COM_INT_ENABLE splx(previpri);} 448#define IEN_TxFLAG IEN_Tx 449 450#define COM_CARRIER_DETECT_EMULATE 0 451#define PC98_CHECK_MODEM_INTERVAL (hz/10) 452#define DCD_OFF_TOLERANCE 2 453#define DCD_ON_RECOGNITION 2 454#define IS_8251(if_type) (!(if_type & 0x10)) 455#define COM1_EXT_CLOCK 0x40000 456 457static void commint(dev_t dev); 458static void com_tiocm_set(struct com_s *com, int msr); 459static void com_tiocm_bis(struct com_s *com, int msr); 460static void com_tiocm_bic(struct com_s *com, int msr); 461static int com_tiocm_get(struct com_s *com); 462static int com_tiocm_get_delta(struct com_s *com); 463static void pc98_msrint_start(dev_t dev); 464static void com_cflag_and_speed_set(struct com_s *com, int cflag, int speed); 465static int pc98_ttspeedtab(struct com_s *com, int speed, u_int *divisor); 466static int pc98_get_modem_status(struct com_s *com); 467static timeout_t pc98_check_msr; 468static void pc98_set_baud_rate(struct com_s *com, u_int count); 469static void pc98_i8251_reset(struct com_s *com, int mode, int command); 470static void pc98_disable_i8251_interrupt(struct com_s *com, int mod); 471static void pc98_enable_i8251_interrupt(struct com_s *com, int mod); 472static int pc98_check_i8251_interrupt(struct com_s *com); 473static int pc98_i8251_get_cmd(struct com_s *com); 474static int pc98_i8251_get_mod(struct com_s *com); 475static void pc98_i8251_set_cmd(struct com_s *com, int x); 476static void pc98_i8251_or_cmd(struct com_s *com, int x); 477static void pc98_i8251_clear_cmd(struct com_s *com, int x); 478static void pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x); 479static int pc98_check_if_type(device_t dev, struct siodev *iod); 480static int pc98_check_8251vfast(void); 481static int pc98_check_8251fifo(void); 482static void pc98_check_sysclock(void); 483static void pc98_set_ioport(struct com_s *com); 484 485#define com_int_Tx_disable(com) \ 486 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP) 487#define com_int_Tx_enable(com) \ 488 pc98_enable_i8251_interrupt(com,IEN_TxFLAG) 489#define com_int_Rx_disable(com) \ 490 pc98_disable_i8251_interrupt(com,IEN_Rx) 491#define com_int_Rx_enable(com) \ 492 pc98_enable_i8251_interrupt(com,IEN_Rx) 493#define com_int_TxRx_disable(com) \ 494 pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP|IEN_Rx) 495#define com_int_TxRx_enable(com) \ 496 pc98_enable_i8251_interrupt(com,IEN_TxFLAG|IEN_Rx) 497#define com_send_break_on(com) \ 498 pc98_i8251_or_cmd(com,CMD8251_SBRK) 499#define com_send_break_off(com) \ 500 pc98_i8251_clear_cmd(com,CMD8251_SBRK) 501 502static struct speedtab pc98speedtab[] = { /* internal RS232C interface */ 503 { 0, 0, }, 504 { 50, 50, }, 505 { 75, 75, }, 506 { 150, 150, }, 507 { 200, 200, }, 508 { 300, 300, }, 509 { 600, 600, }, 510 { 1200, 1200, }, 511 { 2400, 2400, }, 512 { 4800, 4800, }, 513 { 9600, 9600, }, 514 { 19200, 19200, }, 515 { 38400, 38400, }, 516 { 51200, 51200, }, 517 { 76800, 76800, }, 518 { 20800, 20800, }, 519 { 31200, 31200, }, 520 { 41600, 41600, }, 521 { 62400, 62400, }, 522 { -1, -1 } 523}; 524static struct speedtab pc98fast_speedtab[] = { 525 { 9600, 0x80 | (DEFAULT_RCLK / (16 * (9600))), }, 526 { 19200, 0x80 | (DEFAULT_RCLK / (16 * (19200))), }, 527 { 38400, 0x80 | (DEFAULT_RCLK / (16 * (38400))), }, 528 { 57600, 0x80 | (DEFAULT_RCLK / (16 * (57600))), }, 529 { 115200, 0x80 | (DEFAULT_RCLK / (16 * (115200))), }, 530 { -1, -1 } 531}; 532static struct speedtab comspeedtab_pio9032b[] = { 533 { 300, 6, }, 534 { 600, 5, }, 535 { 1200, 4, }, 536 { 2400, 3, }, 537 { 4800, 2, }, 538 { 9600, 1, }, 539 { 19200, 0, }, 540 { 38400, 7, }, 541 { -1, -1 } 542}; 543static struct speedtab comspeedtab_b98_01[] = { 544 { 75, 11, }, 545 { 150, 10, }, 546 { 300, 9, }, 547 { 600, 8, }, 548 { 1200, 7, }, 549 { 2400, 6, }, 550 { 4800, 5, }, 551 { 9600, 4, }, 552 { 19200, 3, }, 553 { 38400, 2, }, 554 { 76800, 1, }, 555 { 153600, 0, }, 556 { -1, -1 } 557}; 558static struct speedtab comspeedtab_ind[] = { 559 { 300, 1536, }, 560 { 600, 768, }, 561 { 1200, 384, }, 562 { 2400, 192, }, 563 { 4800, 96, }, 564 { 9600, 48, }, 565 { 19200, 24, }, 566 { 38400, 12, }, 567 { 57600, 8, }, 568 { 115200, 4, }, 569 { 153600, 3, }, 570 { 230400, 2, }, 571 { 460800, 1, }, 572 { -1, -1 } 573}; 574 575struct { 576 char *name; 577 short port_table[7]; 578 short irr_mask; 579 struct speedtab *speedtab; 580 short check_irq; 581} if_8251_type[] = { 582 /* COM_IF_INTERNAL */ 583 { " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1}, 584 -1, pc98speedtab, 1 }, 585 /* COM_IF_PC9861K_1 */ 586 { " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1}, 587 3, NULL, 1 }, 588 /* COM_IF_PC9861K_2 */ 589 { " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1}, 590 3, NULL, 1 }, 591 /* COM_IF_IND_SS_1 */ 592 { " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1}, 593 3, comspeedtab_ind, 1 }, 594 /* COM_IF_IND_SS_2 */ 595 { " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1}, 596 3, comspeedtab_ind, 1 }, 597 /* COM_IF_PIO9032B_1 */ 598 { " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1}, 599 7, comspeedtab_pio9032b, 1 }, 600 /* COM_IF_PIO9032B_2 */ 601 { " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1}, 602 7, comspeedtab_pio9032b, 1 }, 603 /* COM_IF_B98_01_1 */ 604 { " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3}, 605 7, comspeedtab_b98_01, 0 }, 606 /* COM_IF_B98_01_2 */ 607 { " (B98-01)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xd5, 0xd7}, 608 7, comspeedtab_b98_01, 0 }, 609}; 610#define PC98SIO_data_port(type) (if_8251_type[type].port_table[0]) 611#define PC98SIO_cmd_port(type) (if_8251_type[type].port_table[1]) 612#define PC98SIO_sts_port(type) (if_8251_type[type].port_table[2]) 613#define PC98SIO_in_modem_port(type) (if_8251_type[type].port_table[3]) 614#define PC98SIO_intr_ctrl_port(type) (if_8251_type[type].port_table[4]) 615#define PC98SIO_baud_rate_port(type) (if_8251_type[type].port_table[5]) 616#define PC98SIO_func_port(type) (if_8251_type[type].port_table[6]) 617 618#define I8251F_data 0x130 619#define I8251F_lsr 0x132 620#define I8251F_msr 0x134 621#define I8251F_iir 0x136 622#define I8251F_fcr 0x138 623#define I8251F_div 0x13a 624 625 626static bus_addr_t port_table_0[] = 627 {0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007}; 628static bus_addr_t port_table_1[] = 629 {0x000, 0x002, 0x004, 0x006, 0x008, 0x00a, 0x00c, 0x00e}; 630static bus_addr_t port_table_8[] = 631 {0x000, 0x100, 0x200, 0x300, 0x400, 0x500, 0x600, 0x700}; 632static bus_addr_t port_table_rsa[] = { 633 0x008, 0x009, 0x00a, 0x00b, 0x00c, 0x00d, 0x00e, 0x00f, 634 0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007 635}; 636 637struct { 638 char *name; 639 short irr_read; 640 short irr_write; 641 bus_addr_t *iat; 642 bus_size_t iatsz; 643 u_long rclk; 644} if_16550a_type[] = { 645 /* COM_IF_RSA98 */ 646 {" (RSA-98)", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 647 /* COM_IF_NS16550 */ 648 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 649 /* COM_IF_SECOND_CCU */ 650 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 651 /* COM_IF_MC16550II */ 652 {" (MC16550II)", -1, 0x1000, port_table_8, IO_COMSIZE, 653 DEFAULT_RCLK * 4}, 654 /* COM_IF_MCRS98 */ 655 {" (MC-RS98)", -1, 0x1000, port_table_8, IO_COMSIZE, DEFAULT_RCLK * 4}, 656 /* COM_IF_RSB3000 */ 657 {" (RSB-3000)", 0xbf, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 10}, 658 /* COM_IF_RSB384 */ 659 {" (RSB-384)", 0xbf, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 10}, 660 /* COM_IF_MODEM_CARD */ 661 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 662 /* COM_IF_RSA98III */ 663 {" (RSA-98III)", -1, -1, port_table_rsa, 16, DEFAULT_RCLK * 8}, 664 /* COM_IF_ESP98 */ 665 {" (ESP98)", -1, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 4}, 666}; 667#endif /* PC98 */ 668 669#ifdef COM_ESP 670#ifdef PC98 671 672/* XXX configure this properly. */ 673/* XXX quite broken for new-bus. */ 674static Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 }; 675static Port_t likely_esp_ports[] = { 0xc0d0, 0 }; 676 677#define ESP98_CMD1 (ESP_CMD1 * 0x100) 678#define ESP98_CMD2 (ESP_CMD2 * 0x100) 679#define ESP98_STATUS1 (ESP_STATUS1 * 0x100) 680#define ESP98_STATUS2 (ESP_STATUS2 * 0x100) 681 682#else /* PC98 */ 683 684/* XXX configure this properly. */ 685static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, }; 686static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 }; 687 688#endif /* PC98 */ 689#endif 690 691/* 692 * handle sysctl read/write requests for console speed 693 * 694 * In addition to setting comdefaultrate for I/O through /dev/console, 695 * also set the initial and lock values for the /dev/ttyXX device 696 * if there is one associated with the console. Finally, if the /dev/tty 697 * device has already been open, change the speed on the open running port 698 * itself. 699 */ 700 701static int 702sysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS) 703{ 704 int error, s; 705 speed_t newspeed; 706 struct com_s *com; 707 struct tty *tp; 708 709 newspeed = comdefaultrate; 710 711 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req); 712 if (error || !req->newptr) 713 return (error); 714 715 comdefaultrate = newspeed; 716 717 if (comconsole < 0) /* serial console not selected? */ 718 return (0); 719 720 com = com_addr(comconsole); 721 if (com == NULL) 722 return (ENXIO); 723 724 /* 725 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX 726 * (note, the lock rates really are boolean -- if non-zero, disallow 727 * speed changes) 728 */ 729 com->it_in.c_ispeed = com->it_in.c_ospeed = 730 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 731 com->it_out.c_ispeed = com->it_out.c_ospeed = 732 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate; 733 734 /* 735 * if we're open, change the running rate too 736 */ 737 tp = com->tp; 738 if (tp && (tp->t_state & TS_ISOPEN)) { 739 tp->t_termios.c_ispeed = 740 tp->t_termios.c_ospeed = comdefaultrate; 741 s = spltty(); 742 error = comparam(tp, &tp->t_termios); 743 splx(s); 744 } 745 return error; 746} 747 748SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW, 749 0, 0, sysctl_machdep_comdefaultrate, "I", ""); 750 751/* 752 * Unload the driver and clear the table. 753 * XXX this is mostly wrong. 754 * XXX TODO: 755 * This is usually called when the card is ejected, but 756 * can be caused by a kldunload of a controller driver. 757 * The idea is to reset the driver's view of the device 758 * and ensure that any driver entry points such as 759 * read and write do not hang. 760 */ 761int 762siodetach(dev) 763 device_t dev; 764{ 765 struct com_s *com; 766 int i; 767 768 com = (struct com_s *) device_get_softc(dev); 769 if (com == NULL) { 770 device_printf(dev, "NULL com in siounload\n"); 771 return (0); 772 } 773 com->gone = TRUE; 774 for (i = 0 ; i < 6; i++) 775 destroy_dev(com->devs[i]); 776 if (com->irqres) { 777 bus_teardown_intr(dev, com->irqres, com->cookie); 778 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres); 779 } 780 if (com->ioportres) 781 bus_release_resource(dev, SYS_RES_IOPORT, com->ioportrid, 782 com->ioportres); 783 if (com->tp && (com->tp->t_state & TS_ISOPEN)) { 784 device_printf(dev, "still open, forcing close\n"); 785 (*linesw[com->tp->t_line].l_close)(com->tp, 0); 786 com->tp->t_gen++; 787 ttyclose(com->tp); 788 ttwakeup(com->tp); 789 ttwwakeup(com->tp); 790 } else { 791 if (com->ibuf != NULL) 792 free(com->ibuf, M_DEVBUF); 793#ifdef PC98 794 if (com->obuf1 != NULL) 795 free(com->obuf1, M_DEVBUF); 796#endif 797 device_set_softc(dev, NULL); 798 free(com, M_DEVBUF); 799 } 800 return (0); 801} 802 803int 804sioprobe(dev, xrid, rclk, noprobe) 805 device_t dev; 806 int xrid; 807 u_long rclk; 808 int noprobe; 809{ 810#if 0 811 static bool_t already_init; 812 device_t xdev; 813#endif 814 struct com_s *com; 815 u_int divisor; 816 bool_t failures[10]; 817 int fn; 818 device_t idev; 819 Port_t iobase; 820 intrmask_t irqmap[4]; 821 intrmask_t irqs; 822 u_char mcr_image; 823 int result; 824 u_long xirq; 825 u_int flags = device_get_flags(dev); 826 int rid; 827 struct resource *port; 828#ifdef PC98 829 int tmp; 830 struct siodev iod; 831#endif 832 833#ifdef PC98 834 iod.if_type = GET_IFTYPE(flags); 835 if ((iod.if_type < 0 || iod.if_type > COM_IF_END1) && 836 (iod.if_type < 0x10 || iod.if_type > COM_IF_END2)) 837 return ENXIO; 838#endif 839 840 rid = xrid; 841#ifdef PC98 842 if (IS_8251(iod.if_type)) { 843 port = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 844 RF_ACTIVE); 845 } else if (iod.if_type == COM_IF_MODEM_CARD || 846 iod.if_type == COM_IF_RSA98III || 847 isa_get_vendorid(dev)) { 848 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 849 if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE); 850 } else { 851 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, 852 if_16550a_type[iod.if_type & 0x0f].iat, 853 if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE); 854 } 855#else 856 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 857 0, ~0, IO_COMSIZE, RF_ACTIVE); 858#endif 859 if (!port) 860 return (ENXIO); 861#ifdef PC98 862 if (!IS_8251(iod.if_type)) { 863 if (isa_load_resourcev(port, 864 if_16550a_type[iod.if_type & 0x0f].iat, 865 if_16550a_type[iod.if_type & 0x0f].iatsz) != 0) { 866 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 867 return ENXIO; 868 } 869 } 870#endif 871 872 com = malloc(sizeof(*com), M_DEVBUF, M_NOWAIT | M_ZERO); 873 if (com == NULL) { 874 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 875 return (ENOMEM); 876 } 877 device_set_softc(dev, com); 878 com->bst = rman_get_bustag(port); 879 com->bsh = rman_get_bushandle(port); 880#ifdef PC98 881 if (!IS_8251(iod.if_type) && rclk == 0) 882 rclk = if_16550a_type[iod.if_type & 0x0f].rclk; 883#else 884 if (rclk == 0) 885 rclk = DEFAULT_RCLK; 886#endif 887 com->rclk = rclk; 888 889 while (sio_inited != 2) 890 if (atomic_cmpset_int(&sio_inited, 0, 1)) { 891 mtx_init(&sio_lock, sio_driver_name, NULL, 892 (comconsole != -1) ? 893 MTX_SPIN | MTX_QUIET : MTX_SPIN); 894 atomic_store_rel_int(&sio_inited, 2); 895 } 896 897#if 0 898 /* 899 * XXX this is broken - when we are first called, there are no 900 * previously configured IO ports. We could hard code 901 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse. 902 * This code has been doing nothing since the conversion since 903 * "count" is zero the first time around. 904 */ 905 if (!already_init) { 906 /* 907 * Turn off MCR_IENABLE for all likely serial ports. An unused 908 * port with its MCR_IENABLE gate open will inhibit interrupts 909 * from any used port that shares the interrupt vector. 910 * XXX the gate enable is elsewhere for some multiports. 911 */ 912 device_t *devs; 913 int count, i, xioport; 914#ifdef PC98 915 int xiftype; 916#endif 917 918 devclass_get_devices(sio_devclass, &devs, &count); 919#ifdef PC98 920 for (i = 0; i < count; i++) { 921 xdev = devs[i]; 922 xioport = bus_get_resource_start(xdev, SYS_RES_IOPORT, 0); 923 xiftype = GET_IFTYPE(device_get_flags(xdev)); 924 if (device_is_enabled(xdev) && xioport > 0) { 925 if (IS_8251(xiftype)) 926 outb((xioport & 0xff00) | PC98SIO_cmd_port(xiftype & 0x0f), 0xf2); 927 else 928 outb(xioport + if_16550a_type[xiftype & 0x0f].iat[com_mcr], 0); 929 } 930 } 931#else 932 for (i = 0; i < count; i++) { 933 xdev = devs[i]; 934 if (device_is_enabled(xdev) && 935 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport, 936 NULL) == 0) 937 outb(xioport + com_mcr, 0); 938 } 939#endif 940 free(devs, M_TEMP); 941 already_init = TRUE; 942 } 943#endif 944 945 if (COM_LLCONSOLE(flags)) { 946 printf("sio%d: reserved for low-level i/o\n", 947 device_get_unit(dev)); 948 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 949 device_set_softc(dev, NULL); 950 free(com, M_DEVBUF); 951 return (ENXIO); 952 } 953 954#ifdef PC98 955 DELAY(10); 956 957 /* 958 * If the port is i8251 UART (internal, B98_01) 959 */ 960 if (pc98_check_if_type(dev, &iod) == -1) { 961 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 962 device_set_softc(dev, NULL); 963 free(com, M_DEVBUF); 964 return (ENXIO); 965 } 966 if (iod.irq > 0) 967 bus_set_resource(dev, SYS_RES_IRQ, 0, iod.irq, 1); 968 if (IS_8251(iod.if_type)) { 969 outb(iod.cmd, 0); 970 DELAY(10); 971 outb(iod.cmd, 0); 972 DELAY(10); 973 outb(iod.cmd, 0); 974 DELAY(10); 975 outb(iod.cmd, CMD8251_RESET); 976 DELAY(1000); /* for a while...*/ 977 outb(iod.cmd, 0xf2); /* MODE (dummy) */ 978 DELAY(10); 979 outb(iod.cmd, 0x01); /* CMD (dummy) */ 980 DELAY(1000); /* for a while...*/ 981 if (( inb(iod.sts) & STS8251_TxEMP ) == 0 ) { 982 result = (ENXIO); 983 } 984 if (if_8251_type[iod.if_type & 0x0f].check_irq) { 985 COM_INT_DISABLE 986 tmp = ( inb( iod.ctrl ) & ~(IEN_Rx|IEN_TxEMP|IEN_Tx)); 987 outb( iod.ctrl, tmp|IEN_TxEMP ); 988 DELAY(10); 989 result = isa_irq_pending() ? 0 : ENXIO; 990 outb( iod.ctrl, tmp ); 991 COM_INT_ENABLE 992 } else { 993 /* 994 * B98_01 doesn't activate TxEMP interrupt line 995 * when being reset, so we can't check irq pending. 996 */ 997 result = 0; 998 } 999 if (epson_machine_id==0x20) { /* XXX */ 1000 result = 0; 1001 } 1002 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1003 if (result) { 1004 device_set_softc(dev, NULL); 1005 free(com, M_DEVBUF); 1006 } 1007 return result; 1008 } 1009#endif /* PC98 */ 1010 /* 1011 * If the device is on a multiport card and has an AST/4 1012 * compatible interrupt control register, initialize this 1013 * register and prepare to leave MCR_IENABLE clear in the mcr. 1014 * Otherwise, prepare to set MCR_IENABLE in the mcr. 1015 * Point idev to the device struct giving the correct id_irq. 1016 * This is the struct for the master device if there is one. 1017 */ 1018 idev = dev; 1019 mcr_image = MCR_IENABLE; 1020#ifdef COM_MULTIPORT 1021 if (COM_ISMULTIPORT(flags)) { 1022#ifndef PC98 1023 Port_t xiobase; 1024 u_long io; 1025#endif 1026 1027 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags)); 1028 if (idev == NULL) { 1029 printf("sio%d: master device %d not configured\n", 1030 device_get_unit(dev), COM_MPMASTER(flags)); 1031 idev = dev; 1032 } 1033#ifndef PC98 1034 if (!COM_NOTAST4(flags)) { 1035 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io, 1036 NULL) == 0) { 1037 xiobase = io; 1038 if (bus_get_resource(idev, SYS_RES_IRQ, 0, 1039 NULL, NULL) == 0) 1040 outb(xiobase + com_scr, 0x80); 1041 else 1042 outb(xiobase + com_scr, 0); 1043 } 1044 mcr_image = 0; 1045 } 1046#endif 1047 } 1048#endif /* COM_MULTIPORT */ 1049 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0) 1050 mcr_image = 0; 1051 1052 bzero(failures, sizeof failures); 1053 iobase = rman_get_start(port); 1054 1055#ifdef PC98 1056 if (iod.if_type == COM_IF_RSA98III) { 1057 mcr_image = 0; 1058 1059 outb(iobase + rsa_msr, 0x04); 1060 outb(iobase + rsa_frr, 0x00); 1061 if ((inb(iobase + rsa_srr) & 0x36) != 0x36) { 1062 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1063 device_set_softc(dev, NULL); 1064 free(com, M_DEVBUF); 1065 return (ENXIO); 1066 } 1067 outb(iobase + rsa_ier, 0x00); 1068 outb(iobase + rsa_frr, 0x00); 1069 outb(iobase + rsa_tivsr, 0x00); 1070 outb(iobase + rsa_tcr, 0x00); 1071 } 1072 1073 tmp = if_16550a_type[iod.if_type & 0x0f].irr_write; 1074 if (tmp != -1) { 1075 /* MC16550II */ 1076 int irqout; 1077 switch (isa_get_irq(idev)) { 1078 case 3: irqout = 4; break; 1079 case 5: irqout = 5; break; 1080 case 6: irqout = 6; break; 1081 case 12: irqout = 7; break; 1082 default: 1083 printf("sio%d: irq configuration error\n", 1084 device_get_unit(dev)); 1085 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1086 device_set_softc(dev, NULL); 1087 free(com, M_DEVBUF); 1088 return (ENXIO); 1089 } 1090 outb((iobase & 0x00ff) | tmp, irqout); 1091 } 1092#endif 1093 1094 /* 1095 * We don't want to get actual interrupts, just masked ones. 1096 * Interrupts from this line should already be masked in the ICU, 1097 * but mask them in the processor as well in case there are some 1098 * (misconfigured) shared interrupts. 1099 */ 1100 mtx_lock_spin(&sio_lock); 1101/* EXTRA DELAY? */ 1102 1103 /* 1104 * Initialize the speed and the word size and wait long enough to 1105 * drain the maximum of 16 bytes of junk in device output queues. 1106 * The speed is undefined after a master reset and must be set 1107 * before relying on anything related to output. There may be 1108 * junk after a (very fast) soft reboot and (apparently) after 1109 * master reset. 1110 * XXX what about the UART bug avoided by waiting in comparam()? 1111 * We don't want to to wait long enough to drain at 2 bps. 1112 */ 1113 if (iobase == siocniobase) 1114 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10)); 1115 else { 1116 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS); 1117 divisor = siodivisor(rclk, SIO_TEST_SPEED); 1118 sio_setreg(com, com_dlbl, divisor & 0xff); 1119 sio_setreg(com, com_dlbh, divisor >> 8); 1120 sio_setreg(com, com_cfcr, CFCR_8BITS); 1121 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10)); 1122 } 1123 1124 /* 1125 * Enable the interrupt gate and disable device interupts. This 1126 * should leave the device driving the interrupt line low and 1127 * guarantee an edge trigger if an interrupt can be generated. 1128 */ 1129/* EXTRA DELAY? */ 1130 sio_setreg(com, com_mcr, mcr_image); 1131 sio_setreg(com, com_ier, 0); 1132 DELAY(1000); /* XXX */ 1133 irqmap[0] = isa_irq_pending(); 1134 1135 /* 1136 * Attempt to set loopback mode so that we can send a null byte 1137 * without annoying any external device. 1138 */ 1139/* EXTRA DELAY? */ 1140 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK); 1141 1142 /* 1143 * Attempt to generate an output interrupt. On 8250's, setting 1144 * IER_ETXRDY generates an interrupt independent of the current 1145 * setting and independent of whether the THR is empty. On 16450's, 1146 * setting IER_ETXRDY generates an interrupt independent of the 1147 * current setting. On 16550A's, setting IER_ETXRDY only 1148 * generates an interrupt when IER_ETXRDY is not already set. 1149 */ 1150 sio_setreg(com, com_ier, IER_ETXRDY); 1151#ifdef PC98 1152 if (iod.if_type == COM_IF_RSA98III) 1153 outb(iobase + rsa_ier, 0x04); 1154#endif 1155 1156 /* 1157 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate 1158 * an interrupt. They'd better generate one for actually doing 1159 * output. Loopback may be broken on the same incompatibles but 1160 * it's unlikely to do more than allow the null byte out. 1161 */ 1162 sio_setreg(com, com_data, 0); 1163 if (iobase == siocniobase) 1164 DELAY((1 + 2) * 1000000 / (comdefaultrate / 10)); 1165 else 1166 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10)); 1167 1168 /* 1169 * Turn off loopback mode so that the interrupt gate works again 1170 * (MCR_IENABLE was hidden). This should leave the device driving 1171 * an interrupt line high. It doesn't matter if the interrupt 1172 * line oscillates while we are not looking at it, since interrupts 1173 * are disabled. 1174 */ 1175/* EXTRA DELAY? */ 1176 sio_setreg(com, com_mcr, mcr_image); 1177 1178 /* 1179 * It seems my Xircom CBEM56G Cardbus modem wants to be reset 1180 * to 8 bits *again*, or else probe test 0 will fail. 1181 * gwk@sgi.com, 4/19/2001 1182 */ 1183 sio_setreg(com, com_cfcr, CFCR_8BITS); 1184 1185 /* 1186 * Some PCMCIA cards (Palido 321s, DC-1S, ...) have the "TXRDY bug", 1187 * so we probe for a buggy IIR_TXRDY implementation even in the 1188 * noprobe case. We don't probe for it in the !noprobe case because 1189 * noprobe is always set for PCMCIA cards and the problem is not 1190 * known to affect any other cards. 1191 */ 1192 if (noprobe) { 1193 /* Read IIR a few times. */ 1194 for (fn = 0; fn < 2; fn ++) { 1195 DELAY(10000); 1196 failures[6] = sio_getreg(com, com_iir); 1197 } 1198 1199 /* IIR_TXRDY should be clear. Is it? */ 1200 result = 0; 1201 if (failures[6] & IIR_TXRDY) { 1202 /* 1203 * No. We seem to have the bug. Does our fix for 1204 * it work? 1205 */ 1206 sio_setreg(com, com_ier, 0); 1207 if (sio_getreg(com, com_iir) & IIR_NOPEND) { 1208 /* Yes. We discovered the TXRDY bug! */ 1209 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); 1210 } else { 1211 /* No. Just fail. XXX */ 1212 result = ENXIO; 1213 sio_setreg(com, com_mcr, 0); 1214 } 1215 } else { 1216 /* Yes. No bug. */ 1217 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); 1218 } 1219 sio_setreg(com, com_ier, 0); 1220 sio_setreg(com, com_cfcr, CFCR_8BITS); 1221 mtx_unlock_spin(&sio_lock); 1222 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1223 if (iobase == siocniobase) 1224 result = 0; 1225 if (result != 0) { 1226 device_set_softc(dev, NULL); 1227 free(com, M_DEVBUF); 1228 } 1229 return (result); 1230 } 1231 1232 /* 1233 * Check that 1234 * o the CFCR, IER and MCR in UART hold the values written to them 1235 * (the values happen to be all distinct - this is good for 1236 * avoiding false positive tests from bus echoes). 1237 * o an output interrupt is generated and its vector is correct. 1238 * o the interrupt goes away when the IIR in the UART is read. 1239 */ 1240/* EXTRA DELAY? */ 1241 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS; 1242 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY; 1243 failures[2] = sio_getreg(com, com_mcr) - mcr_image; 1244 DELAY(10000); /* Some internal modems need this time */ 1245 irqmap[1] = isa_irq_pending(); 1246 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY; 1247#ifdef PC98 1248 if (iod.if_type == COM_IF_RSA98III) 1249 inb(iobase + rsa_srr); 1250#endif 1251 DELAY(1000); /* XXX */ 1252 irqmap[2] = isa_irq_pending(); 1253 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 1254#ifdef PC98 1255 if (iod.if_type == COM_IF_RSA98III) 1256 inb(iobase + rsa_srr); 1257#endif 1258 1259 /* 1260 * Turn off all device interrupts and check that they go off properly. 1261 * Leave MCR_IENABLE alone. For ports without a master port, it gates 1262 * the OUT2 output of the UART to 1263 * the ICU input. Closing the gate would give a floating ICU input 1264 * (unless there is another device driving it) and spurious interrupts. 1265 * (On the system that this was first tested on, the input floats high 1266 * and gives a (masked) interrupt as soon as the gate is closed.) 1267 */ 1268 sio_setreg(com, com_ier, 0); 1269 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */ 1270 failures[7] = sio_getreg(com, com_ier); 1271#ifdef PC98 1272 if (iod.if_type == COM_IF_RSA98III) 1273 outb(iobase + rsa_ier, 0x00); 1274#endif 1275 DELAY(1000); /* XXX */ 1276 irqmap[3] = isa_irq_pending(); 1277 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 1278#ifdef PC98 1279 if (iod.if_type == COM_IF_RSA98III) { 1280 inb(iobase + rsa_srr); 1281 outb(iobase + rsa_frr, 0x00); 1282 } 1283#endif 1284 1285 mtx_unlock_spin(&sio_lock); 1286 1287 irqs = irqmap[1] & ~irqmap[0]; 1288 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 && 1289 ((1 << xirq) & irqs) == 0) { 1290 printf( 1291 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n", 1292 device_get_unit(dev), xirq, irqs); 1293 printf( 1294 "sio%d: port may not be enabled\n", 1295 device_get_unit(dev)); 1296 } 1297 if (bootverbose) 1298 printf("sio%d: irq maps: %#x %#x %#x %#x\n", 1299 device_get_unit(dev), 1300 irqmap[0], irqmap[1], irqmap[2], irqmap[3]); 1301 1302 result = 0; 1303 for (fn = 0; fn < sizeof failures; ++fn) 1304 if (failures[fn]) { 1305 sio_setreg(com, com_mcr, 0); 1306 result = ENXIO; 1307 if (bootverbose) { 1308 printf("sio%d: probe failed test(s):", 1309 device_get_unit(dev)); 1310 for (fn = 0; fn < sizeof failures; ++fn) 1311 if (failures[fn]) 1312 printf(" %d", fn); 1313 printf("\n"); 1314 } 1315 break; 1316 } 1317 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1318 if (iobase == siocniobase) 1319 result = 0; 1320 if (result != 0) { 1321 device_set_softc(dev, NULL); 1322 free(com, M_DEVBUF); 1323 } 1324 return (result); 1325} 1326 1327#ifdef COM_ESP 1328static int 1329espattach(com, esp_port) 1330 struct com_s *com; 1331 Port_t esp_port; 1332{ 1333 u_char dips; 1334 u_char val; 1335 1336 /* 1337 * Check the ESP-specific I/O port to see if we're an ESP 1338 * card. If not, return failure immediately. 1339 */ 1340 if ((inb(esp_port) & 0xf3) == 0) { 1341 printf(" port 0x%x is not an ESP board?\n", esp_port); 1342 return (0); 1343 } 1344 1345 /* 1346 * We've got something that claims to be a Hayes ESP card. 1347 * Let's hope so. 1348 */ 1349 1350 /* Get the dip-switch configuration */ 1351#ifdef PC98 1352 outb(esp_port + ESP98_CMD1, ESP_GETDIPS); 1353 dips = inb(esp_port + ESP98_STATUS1); 1354#else 1355 outb(esp_port + ESP_CMD1, ESP_GETDIPS); 1356 dips = inb(esp_port + ESP_STATUS1); 1357#endif 1358 1359 /* 1360 * Bits 0,1 of dips say which COM port we are. 1361 */ 1362#ifdef PC98 1363 if ((rman_get_start(com->ioportres) & 0xff) == 1364 likely_com_ports[dips & 0x03]) 1365#else 1366 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03]) 1367#endif 1368 printf(" : ESP"); 1369 else { 1370 printf(" esp_port has com %d\n", dips & 0x03); 1371 return (0); 1372 } 1373 1374 /* 1375 * Check for ESP version 2.0 or later: bits 4,5,6 = 010. 1376 */ 1377#ifdef PC98 1378 outb(esp_port + ESP98_CMD1, ESP_GETTEST); 1379 val = inb(esp_port + ESP98_STATUS1); /* clear reg 1 */ 1380 val = inb(esp_port + ESP98_STATUS2); 1381#else 1382 outb(esp_port + ESP_CMD1, ESP_GETTEST); 1383 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */ 1384 val = inb(esp_port + ESP_STATUS2); 1385#endif 1386 if ((val & 0x70) < 0x20) { 1387 printf("-old (%o)", val & 0x70); 1388 return (0); 1389 } 1390 1391 /* 1392 * Check for ability to emulate 16550: bit 7 == 1 1393 */ 1394 if ((dips & 0x80) == 0) { 1395 printf(" slave"); 1396 return (0); 1397 } 1398 1399 /* 1400 * Okay, we seem to be a Hayes ESP card. Whee. 1401 */ 1402 com->esp = TRUE; 1403 com->esp_port = esp_port; 1404 return (1); 1405} 1406#endif /* COM_ESP */ 1407 1408int 1409sioattach(dev, xrid, rclk) 1410 device_t dev; 1411 int xrid; 1412 u_long rclk; 1413{ 1414 struct com_s *com; 1415#ifdef COM_ESP 1416 Port_t *espp; 1417#endif 1418 Port_t iobase; 1419 int minorbase; 1420 int unit; 1421 u_int flags; 1422 int rid; 1423 struct resource *port; 1424 int ret; 1425#ifdef PC98 1426 u_char *obuf; 1427 u_long obufsize; 1428 int if_type = GET_IFTYPE(device_get_flags(dev)); 1429#endif 1430 1431 rid = xrid; 1432#ifdef PC98 1433 if (IS_8251(if_type)) { 1434 port = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1435 RF_ACTIVE); 1436 } else if (if_type == COM_IF_MODEM_CARD || 1437 if_type == COM_IF_RSA98III || 1438 isa_get_vendorid(dev)) { 1439 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 1440 if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE); 1441 } else { 1442 port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, 1443 if_16550a_type[if_type & 0x0f].iat, 1444 if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE); 1445 } 1446#else 1447 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1448 0, ~0, IO_COMSIZE, RF_ACTIVE); 1449#endif 1450 if (!port) 1451 return (ENXIO); 1452#ifdef PC98 1453 if (!IS_8251(if_type)) { 1454 if (isa_load_resourcev(port, 1455 if_16550a_type[if_type & 0x0f].iat, 1456 if_16550a_type[if_type & 0x0f].iatsz) != 0) { 1457 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1458 return ENXIO; 1459 } 1460 } 1461#endif 1462 1463 iobase = rman_get_start(port); 1464 unit = device_get_unit(dev); 1465 com = device_get_softc(dev); 1466 flags = device_get_flags(dev); 1467 1468 if (unit >= sio_numunits) 1469 sio_numunits = unit + 1; 1470 1471#ifdef PC98 1472 obufsize = 256; 1473 if (if_type == COM_IF_RSA98III) 1474 obufsize = 2048; 1475 if ((obuf = malloc(obufsize * 2, M_DEVBUF, M_NOWAIT)) == NULL) { 1476 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1477 return ENXIO; 1478 } 1479 bzero(obuf, obufsize * 2); 1480#endif 1481 1482 /* 1483 * sioprobe() has initialized the device registers as follows: 1484 * o cfcr = CFCR_8BITS. 1485 * It is most important that CFCR_DLAB is off, so that the 1486 * data port is not hidden when we enable interrupts. 1487 * o ier = 0. 1488 * Interrupts are only enabled when the line is open. 1489 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible 1490 * interrupt control register or the config specifies no irq. 1491 * Keeping MCR_DTR and MCR_RTS off might stop the external 1492 * device from sending before we are ready. 1493 */ 1494 bzero(com, sizeof *com); 1495 com->unit = unit; 1496 com->ioportres = port; 1497 com->ioportrid = rid; 1498 com->bst = rman_get_bustag(port); 1499 com->bsh = rman_get_bushandle(port); 1500 com->cfcr_image = CFCR_8BITS; 1501 com->dtr_wait = 3 * hz; 1502 com->loses_outints = COM_LOSESOUTINTS(flags) != 0; 1503 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0; 1504 com->tx_fifo_size = 1; 1505#ifdef PC98 1506 com->obufsize = obufsize; 1507 com->obuf1 = obuf; 1508 com->obuf2 = obuf + obufsize; 1509#endif 1510 com->obufs[0].l_head = com->obuf1; 1511 com->obufs[1].l_head = com->obuf2; 1512 1513#ifdef PC98 1514 com->pc98_if_type = if_type; 1515 1516 if (IS_8251(if_type)) { 1517 pc98_set_ioport(com); 1518 1519 if (if_type == COM_IF_INTERNAL && pc98_check_8251fifo()) { 1520 com->pc98_8251fifo = 1; 1521 com->pc98_8251fifo_enable = 0; 1522 } 1523 } else { 1524 bus_addr_t *iat = if_16550a_type[if_type & 0x0f].iat; 1525 1526 com->data_port = iobase + iat[com_data]; 1527 com->int_ctl_port = iobase + iat[com_ier]; 1528 com->int_id_port = iobase + iat[com_iir]; 1529 com->modem_ctl_port = iobase + iat[com_mcr]; 1530 com->mcr_image = inb(com->modem_ctl_port); 1531 com->line_status_port = iobase + iat[com_lsr]; 1532 com->modem_status_port = iobase + iat[com_msr]; 1533 } 1534#else /* not PC98 */ 1535 com->data_port = iobase + com_data; 1536 com->int_ctl_port = iobase + com_ier; 1537 com->int_id_port = iobase + com_iir; 1538 com->modem_ctl_port = iobase + com_mcr; 1539 com->mcr_image = inb(com->modem_ctl_port); 1540 com->line_status_port = iobase + com_lsr; 1541 com->modem_status_port = iobase + com_msr; 1542#endif 1543 1544#ifdef PC98 1545 if (!IS_8251(if_type) && rclk == 0) 1546 rclk = if_16550a_type[if_type & 0x0f].rclk; 1547#else 1548 if (rclk == 0) 1549 rclk = DEFAULT_RCLK; 1550#endif 1551 com->rclk = rclk; 1552 1553 /* 1554 * We don't use all the flags from <sys/ttydefaults.h> since they 1555 * are only relevant for logins. It's important to have echo off 1556 * initially so that the line doesn't start blathering before the 1557 * echo flag can be turned off. 1558 */ 1559 com->it_in.c_iflag = 0; 1560 com->it_in.c_oflag = 0; 1561 com->it_in.c_cflag = TTYDEF_CFLAG; 1562 com->it_in.c_lflag = 0; 1563 if (unit == comconsole) { 1564#ifdef PC98 1565 if (IS_8251(com->pc98_if_type)) 1566 DELAY(100000); 1567#endif 1568 com->it_in.c_iflag = TTYDEF_IFLAG; 1569 com->it_in.c_oflag = TTYDEF_OFLAG; 1570 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL; 1571 com->it_in.c_lflag = TTYDEF_LFLAG; 1572 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL; 1573 com->lt_out.c_ispeed = com->lt_out.c_ospeed = 1574 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 1575 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate; 1576 } else 1577 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED; 1578 if (siosetwater(com, com->it_in.c_ispeed) != 0) { 1579 mtx_unlock_spin(&sio_lock); 1580 /* 1581 * Leave i/o resources allocated if this is a `cn'-level 1582 * console, so that other devices can't snarf them. 1583 */ 1584 if (iobase != siocniobase) 1585 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1586 return (ENOMEM); 1587 } 1588 mtx_unlock_spin(&sio_lock); 1589 termioschars(&com->it_in); 1590 com->it_out = com->it_in; 1591 1592 /* attempt to determine UART type */ 1593 printf("sio%d: type", unit); 1594 1595 1596#ifndef PC98 1597 if (!COM_ISMULTIPORT(flags) && 1598 !COM_IIR_TXRDYBUG(flags) && !COM_NOSCR(flags)) { 1599 u_char scr; 1600 u_char scr1; 1601 u_char scr2; 1602 1603 scr = sio_getreg(com, com_scr); 1604 sio_setreg(com, com_scr, 0xa5); 1605 scr1 = sio_getreg(com, com_scr); 1606 sio_setreg(com, com_scr, 0x5a); 1607 scr2 = sio_getreg(com, com_scr); 1608 sio_setreg(com, com_scr, scr); 1609 if (scr1 != 0xa5 || scr2 != 0x5a) { 1610 printf(" 8250 or not responding"); 1611 goto determined_type; 1612 } 1613 } 1614#endif /* !PC98 */ 1615#ifdef PC98 1616 if (IS_8251(com->pc98_if_type)) { 1617 if (com->pc98_8251fifo && !COM_NOFIFO(flags)) 1618 com->tx_fifo_size = 16; 1619 com_int_TxRx_disable( com ); 1620 com_cflag_and_speed_set( com, com->it_in.c_cflag, comdefaultrate ); 1621 com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE ); 1622 com_send_break_off( com ); 1623 1624 if (com->pc98_if_type == COM_IF_INTERNAL) { 1625 printf(" (internal%s%s)", 1626 com->pc98_8251fifo ? " fifo" : "", 1627 PC98SIO_baud_rate_port(com->pc98_if_type) != -1 ? 1628 " v-fast" : ""); 1629 } else { 1630 printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name); 1631 } 1632 } else { 1633#endif /* PC98 */ 1634 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH); 1635 DELAY(100); 1636 switch (inb(com->int_id_port) & IIR_FIFO_MASK) { 1637 case FIFO_RX_LOW: 1638 printf(" 16450"); 1639 break; 1640 case FIFO_RX_MEDL: 1641 printf(" 16450?"); 1642 break; 1643 case FIFO_RX_MEDH: 1644 printf(" 16550?"); 1645 break; 1646 case FIFO_RX_HIGH: 1647 if (COM_NOFIFO(flags)) { 1648 printf(" 16550A fifo disabled"); 1649 break; 1650 } 1651 com->hasfifo = TRUE; 1652#ifdef PC98 1653 if (com->pc98_if_type == COM_IF_RSA98III) { 1654 com->tx_fifo_size = 2048; 1655 com->rsabase = iobase; 1656 outb(com->rsabase + rsa_ier, 0x00); 1657 outb(com->rsabase + rsa_frr, 0x00); 1658 } 1659#else 1660 if (COM_ST16650A(flags)) { 1661 printf(" ST16650A"); 1662 com->st16650a = TRUE; 1663 com->tx_fifo_size = 32; 1664 break; 1665 } 1666 if (COM_TI16754(flags)) { 1667 printf(" TI16754"); 1668 com->tx_fifo_size = 64; 1669 break; 1670 } 1671#endif 1672 printf(" 16550A"); 1673#ifdef COM_ESP 1674#ifdef PC98 1675 if (com->pc98_if_type == COM_IF_ESP98) 1676#endif 1677 for (espp = likely_esp_ports; *espp != 0; espp++) 1678 if (espattach(com, *espp)) { 1679 com->tx_fifo_size = 1024; 1680 break; 1681 } 1682 if (com->esp) 1683 break; 1684#endif 1685#ifdef PC98 1686 com->tx_fifo_size = 16; 1687#else 1688 com->tx_fifo_size = COM_FIFOSIZE(flags); 1689 if (com->tx_fifo_size == 0) 1690 com->tx_fifo_size = 16; 1691 else 1692 printf(" lookalike with %u bytes FIFO", 1693 com->tx_fifo_size); 1694#endif 1695 break; 1696 } 1697 1698#ifdef PC98 1699 if (com->pc98_if_type == COM_IF_RSB3000) { 1700 /* Set RSB-2000/3000 Extended Buffer mode. */ 1701 u_char lcr; 1702 lcr = sio_getreg(com, com_cfcr); 1703 sio_setreg(com, com_cfcr, lcr | CFCR_DLAB); 1704 sio_setreg(com, com_emr, EMR_EXBUFF | EMR_EFMODE); 1705 sio_setreg(com, com_cfcr, lcr); 1706 } 1707#endif 1708 1709#ifdef COM_ESP 1710 if (com->esp) { 1711 /* 1712 * Set 16550 compatibility mode. 1713 * We don't use the ESP_MODE_SCALE bit to increase the 1714 * fifo trigger levels because we can't handle large 1715 * bursts of input. 1716 * XXX flow control should be set in comparam(), not here. 1717 */ 1718#ifdef PC98 1719 outb(com->esp_port + ESP98_CMD1, ESP_SETMODE); 1720 outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1721#else 1722 outb(com->esp_port + ESP_CMD1, ESP_SETMODE); 1723 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1724#endif 1725 1726 /* Set RTS/CTS flow control. */ 1727#ifdef PC98 1728 outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE); 1729 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS); 1730 outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS); 1731#else 1732 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE); 1733 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS); 1734 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS); 1735#endif 1736 1737 /* Set flow-control levels. */ 1738#ifdef PC98 1739 outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW); 1740 outb(com->esp_port + ESP98_CMD2, HIBYTE(768)); 1741 outb(com->esp_port + ESP98_CMD2, LOBYTE(768)); 1742 outb(com->esp_port + ESP98_CMD2, HIBYTE(512)); 1743 outb(com->esp_port + ESP98_CMD2, LOBYTE(512)); 1744#else 1745 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW); 1746 outb(com->esp_port + ESP_CMD2, HIBYTE(768)); 1747 outb(com->esp_port + ESP_CMD2, LOBYTE(768)); 1748 outb(com->esp_port + ESP_CMD2, HIBYTE(512)); 1749 outb(com->esp_port + ESP_CMD2, LOBYTE(512)); 1750#endif 1751 1752#ifdef PC98 1753 /* Set UART clock prescaler. */ 1754 outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK); 1755 outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */ 1756#endif 1757 } 1758#endif /* COM_ESP */ 1759 sio_setreg(com, com_fifo, 0); 1760#ifdef PC98 1761 printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name); 1762#else 1763determined_type: ; 1764#endif 1765 1766#ifdef COM_MULTIPORT 1767 if (COM_ISMULTIPORT(flags)) { 1768 device_t masterdev; 1769 1770 com->multiport = TRUE; 1771 printf(" (multiport"); 1772 if (unit == COM_MPMASTER(flags)) 1773 printf(" master"); 1774 printf(")"); 1775 masterdev = devclass_get_device(sio_devclass, 1776 COM_MPMASTER(flags)); 1777 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev, 1778 SYS_RES_IRQ, 0, NULL, NULL) != 0); 1779 } 1780#endif /* COM_MULTIPORT */ 1781#ifdef PC98 1782 } 1783#endif 1784 if (unit == comconsole) 1785 printf(", console"); 1786 if (COM_IIR_TXRDYBUG(flags)) 1787 printf(" with a buggy IIR_TXRDY implementation"); 1788 printf("\n"); 1789 1790 if (sio_fast_ih == NULL) { 1791 swi_add(&tty_ithd, "tty:sio", siopoll, NULL, SWI_TTY, 0, 1792 &sio_fast_ih); 1793 swi_add(&clk_ithd, "tty:sio", siopoll, NULL, SWI_TTY, 0, 1794 &sio_slow_ih); 1795 } 1796 minorbase = UNIT_TO_MINOR(unit); 1797 com->devs[0] = make_dev(&sio_cdevsw, minorbase, 1798 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit); 1799 com->devs[1] = make_dev(&sio_cdevsw, minorbase | CONTROL_INIT_STATE, 1800 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit); 1801 com->devs[2] = make_dev(&sio_cdevsw, minorbase | CONTROL_LOCK_STATE, 1802 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit); 1803 com->devs[3] = make_dev(&sio_cdevsw, minorbase | CALLOUT_MASK, 1804 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit); 1805 com->devs[4] = make_dev(&sio_cdevsw, 1806 minorbase | CALLOUT_MASK | CONTROL_INIT_STATE, 1807 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit); 1808 com->devs[5] = make_dev(&sio_cdevsw, 1809 minorbase | CALLOUT_MASK | CONTROL_LOCK_STATE, 1810 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit); 1811 for (rid = 0; rid < 6; rid++) 1812 com->devs[rid]->si_drv1 = com; 1813 com->flags = flags; 1814 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1815 1816 if (COM_PPSCTS(flags)) 1817 com->pps_bit = MSR_CTS; 1818 else 1819 com->pps_bit = MSR_DCD; 1820 pps_init(&com->pps); 1821 1822 rid = 0; 1823 com->irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1824 RF_ACTIVE); 1825 if (com->irqres) { 1826 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres, 1827 INTR_TYPE_TTY | INTR_FAST, 1828 siointr, com, &com->cookie); 1829 if (ret) { 1830 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, 1831 com->irqres, INTR_TYPE_TTY, 1832 siointr, com, &com->cookie); 1833 if (ret == 0) 1834 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode\n"); 1835 } 1836 if (ret) 1837 device_printf(dev, "could not activate interrupt\n"); 1838#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \ 1839 defined(ALT_BREAK_TO_DEBUGGER)) 1840 /* 1841 * Enable interrupts for early break-to-debugger support 1842 * on the console. 1843 */ 1844 if (ret == 0 && unit == comconsole) 1845 outb(siocniobase + com_ier, IER_ERXRDY | IER_ERLS | 1846 IER_EMSC); 1847#endif 1848 } 1849 1850 return (0); 1851} 1852 1853static int 1854sioopen(dev, flag, mode, td) 1855 dev_t dev; 1856 int flag; 1857 int mode; 1858 struct thread *td; 1859{ 1860 struct com_s *com; 1861 int error; 1862 int mynor; 1863 int s; 1864 struct tty *tp; 1865 int unit; 1866 1867 mynor = minor(dev); 1868 unit = MINOR_TO_UNIT(mynor); 1869 com = com_addr(unit); 1870 if (com == NULL) 1871 return (ENXIO); 1872 if (com->gone) 1873 return (ENXIO); 1874 if (mynor & CONTROL_MASK) 1875 return (0); 1876 tp = dev->si_tty = com->tp = ttymalloc(com->tp); 1877 s = spltty(); 1878 /* 1879 * We jump to this label after all non-interrupted sleeps to pick 1880 * up any changes of the device state. 1881 */ 1882open_top: 1883 while (com->state & CS_DTR_OFF) { 1884 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0); 1885 if (com_addr(unit) == NULL) 1886 return (ENXIO); 1887 if (error != 0 || com->gone) 1888 goto out; 1889 } 1890 if (tp->t_state & TS_ISOPEN) { 1891 /* 1892 * The device is open, so everything has been initialized. 1893 * Handle conflicts. 1894 */ 1895 if (mynor & CALLOUT_MASK) { 1896 if (!com->active_out) { 1897 error = EBUSY; 1898 goto out; 1899 } 1900 } else { 1901 if (com->active_out) { 1902 if (flag & O_NONBLOCK) { 1903 error = EBUSY; 1904 goto out; 1905 } 1906 error = tsleep(&com->active_out, 1907 TTIPRI | PCATCH, "siobi", 0); 1908 if (com_addr(unit) == NULL) 1909 return (ENXIO); 1910 if (error != 0 || com->gone) 1911 goto out; 1912 goto open_top; 1913 } 1914 } 1915 if (tp->t_state & TS_XCLUDE && 1916 suser(td)) { 1917 error = EBUSY; 1918 goto out; 1919 } 1920 } else { 1921 /* 1922 * The device isn't open, so there are no conflicts. 1923 * Initialize it. Initialization is done twice in many 1924 * cases: to preempt sleeping callin opens if we are 1925 * callout, and to complete a callin open after DCD rises. 1926 */ 1927 tp->t_oproc = comstart; 1928 tp->t_param = comparam; 1929 tp->t_stop = comstop; 1930 tp->t_dev = dev; 1931 tp->t_termios = mynor & CALLOUT_MASK 1932 ? com->it_out : com->it_in; 1933#ifdef PC98 1934 if (!IS_8251(com->pc98_if_type)) 1935#endif 1936 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET); 1937 com->poll = com->no_irq; 1938 com->poll_output = com->loses_outints; 1939 ++com->wopeners; 1940 error = comparam(tp, &tp->t_termios); 1941 --com->wopeners; 1942 if (error != 0) 1943 goto out; 1944#ifdef PC98 1945 if (IS_8251(com->pc98_if_type)) { 1946 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS); 1947 pc98_msrint_start(dev); 1948 if (com->pc98_8251fifo) { 1949 com->pc98_8251fifo_enable = 1; 1950 outb(I8251F_fcr, CTRL8251F_ENABLE | 1951 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 1952 } 1953 } 1954#endif 1955 /* 1956 * XXX we should goto open_top if comparam() slept. 1957 */ 1958 if (com->hasfifo) { 1959 int i; 1960 /* 1961 * (Re)enable and drain fifos. 1962 * 1963 * Certain SMC chips cause problems if the fifos 1964 * are enabled while input is ready. Turn off the 1965 * fifo if necessary to clear the input. We test 1966 * the input ready bit after enabling the fifos 1967 * since we've already enabled them in comparam() 1968 * and to handle races between enabling and fresh 1969 * input. 1970 */ 1971 for (i = 0; i < 500; i++) { 1972 sio_setreg(com, com_fifo, 1973 FIFO_RCV_RST | FIFO_XMT_RST 1974 | com->fifo_image); 1975#ifdef PC98 1976 if (com->pc98_if_type == COM_IF_RSA98III) 1977 outb(com->rsabase + rsa_frr , 0x00); 1978#endif 1979 /* 1980 * XXX the delays are for superstitious 1981 * historical reasons. It must be less than 1982 * the character time at the maximum 1983 * supported speed (87 usec at 115200 bps 1984 * 8N1). Otherwise we might loop endlessly 1985 * if data is streaming in. We used to use 1986 * delays of 100. That usually worked 1987 * because DELAY(100) used to usually delay 1988 * for about 85 usec instead of 100. 1989 */ 1990 DELAY(50); 1991#ifdef PC98 1992 if (com->pc98_if_type == COM_IF_RSA98III ? 1993 !(inb(com->rsabase + rsa_srr) & 0x08) : 1994 !(inb(com->line_status_port) & LSR_RXRDY)) 1995 break; 1996#else 1997 if (!(inb(com->line_status_port) & LSR_RXRDY)) 1998 break; 1999#endif 2000 sio_setreg(com, com_fifo, 0); 2001 DELAY(50); 2002 (void) inb(com->data_port); 2003 } 2004 if (i == 500) { 2005 error = EIO; 2006 goto out; 2007 } 2008 } 2009 2010 mtx_lock_spin(&sio_lock); 2011#ifdef PC98 2012 if (IS_8251(com->pc98_if_type)) { 2013 com_tiocm_bis(com, TIOCM_LE); 2014 com->pc98_prev_modem_status = pc98_get_modem_status(com); 2015 com_int_Rx_enable(com); 2016 } else { 2017#endif 2018 (void) inb(com->line_status_port); 2019 (void) inb(com->data_port); 2020 com->prev_modem_status = com->last_modem_status 2021 = inb(com->modem_status_port); 2022 outb(com->int_ctl_port, 2023 IER_ERXRDY | IER_ERLS | IER_EMSC 2024 | (COM_IIR_TXRDYBUG(com->flags) ? 0 : IER_ETXRDY)); 2025#ifdef PC98 2026 if (com->pc98_if_type == COM_IF_RSA98III) { 2027 outb(com->rsabase + rsa_ier, 0x1d); 2028 outb(com->int_ctl_port, IER_ERLS | IER_EMSC); 2029 } 2030#endif 2031#ifdef PC98 2032 } 2033#endif 2034 mtx_unlock_spin(&sio_lock); 2035 /* 2036 * Handle initial DCD. Callout devices get a fake initial 2037 * DCD (trapdoor DCD). If we are callout, then any sleeping 2038 * callin opens get woken up and resume sleeping on "siobi" 2039 * instead of "siodcd". 2040 */ 2041 /* 2042 * XXX `mynor & CALLOUT_MASK' should be 2043 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where 2044 * TRAPDOOR_CARRIER is the default initial state for callout 2045 * devices and SOFT_CARRIER is like CLOCAL except it hides 2046 * the true carrier. 2047 */ 2048#ifdef PC98 2049 if ((IS_8251(com->pc98_if_type) && 2050 (pc98_get_modem_status(com) & TIOCM_CAR)) || 2051 (!IS_8251(com->pc98_if_type) && 2052 (com->prev_modem_status & MSR_DCD)) || 2053 mynor & CALLOUT_MASK) 2054 (*linesw[tp->t_line].l_modem)(tp, 1); 2055#else 2056 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK) 2057 (*linesw[tp->t_line].l_modem)(tp, 1); 2058#endif 2059 } 2060 /* 2061 * Wait for DCD if necessary. 2062 */ 2063 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK) 2064 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 2065 ++com->wopeners; 2066 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0); 2067 if (com_addr(unit) == NULL) 2068 return (ENXIO); 2069 --com->wopeners; 2070 if (error != 0 || com->gone) 2071 goto out; 2072 goto open_top; 2073 } 2074 error = (*linesw[tp->t_line].l_open)(dev, tp); 2075 disc_optim(tp, &tp->t_termios, com); 2076 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK) 2077 com->active_out = TRUE; 2078 siosettimeout(); 2079out: 2080 splx(s); 2081 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0) 2082 comhardclose(com); 2083 return (error); 2084} 2085 2086static int 2087sioclose(dev, flag, mode, td) 2088 dev_t dev; 2089 int flag; 2090 int mode; 2091 struct thread *td; 2092{ 2093 struct com_s *com; 2094 int mynor; 2095 int s; 2096 struct tty *tp; 2097 2098 mynor = minor(dev); 2099 if (mynor & CONTROL_MASK) 2100 return (0); 2101 com = com_addr(MINOR_TO_UNIT(mynor)); 2102 if (com == NULL) 2103 return (ENODEV); 2104 tp = com->tp; 2105 s = spltty(); 2106 (*linesw[tp->t_line].l_close)(tp, flag); 2107#ifdef PC98 2108 com->modem_checking = 0; 2109#endif 2110 disc_optim(tp, &tp->t_termios, com); 2111 comstop(tp, FREAD | FWRITE); 2112 comhardclose(com); 2113 ttyclose(tp); 2114 siosettimeout(); 2115 splx(s); 2116 if (com->gone) { 2117 printf("sio%d: gone\n", com->unit); 2118 s = spltty(); 2119 if (com->ibuf != NULL) 2120 free(com->ibuf, M_DEVBUF); 2121 bzero(tp, sizeof *tp); 2122 splx(s); 2123 } 2124 return (0); 2125} 2126 2127static void 2128comhardclose(com) 2129 struct com_s *com; 2130{ 2131 int s; 2132 struct tty *tp; 2133 2134 s = spltty(); 2135 com->poll = FALSE; 2136 com->poll_output = FALSE; 2137 com->do_timestamp = FALSE; 2138 com->do_dcd_timestamp = FALSE; 2139 com->pps.ppsparam.mode = 0; 2140#ifdef PC98 2141 if (IS_8251(com->pc98_if_type)) 2142 com_send_break_off(com); 2143 else 2144#endif 2145 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 2146 tp = com->tp; 2147 2148#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \ 2149 defined(ALT_BREAK_TO_DEBUGGER)) 2150 /* 2151 * Leave interrupts enabled and don't clear DTR if this is the 2152 * console. This allows us to detect break-to-debugger events 2153 * while the console device is closed. 2154 */ 2155 if (com->unit != comconsole) 2156#endif 2157 { 2158#ifdef PC98 2159 int tmp; 2160 if (IS_8251(com->pc98_if_type)) 2161 com_int_TxRx_disable(com); 2162 else 2163 sio_setreg(com, com_ier, 0); 2164 if (com->pc98_if_type == COM_IF_RSA98III) 2165 outb(com->rsabase + rsa_ier, 0x00); 2166 if (IS_8251(com->pc98_if_type)) 2167 tmp = pc98_get_modem_status(com) & TIOCM_CAR; 2168 else 2169 tmp = com->prev_modem_status & MSR_DCD; 2170#else 2171 sio_setreg(com, com_ier, 0); 2172#endif 2173 if (tp->t_cflag & HUPCL 2174 /* 2175 * XXX we will miss any carrier drop between here and the 2176 * next open. Perhaps we should watch DCD even when the 2177 * port is closed; it is not sufficient to check it at 2178 * the next open because it might go up and down while 2179 * we're not watching. 2180 */ 2181 || (!com->active_out 2182#ifdef PC98 2183 && !(tmp) 2184#else 2185 && !(com->prev_modem_status & MSR_DCD) 2186#endif 2187 && !(com->it_in.c_cflag & CLOCAL)) 2188 || !(tp->t_state & TS_ISOPEN)) { 2189#ifdef PC98 2190 if (IS_8251(com->pc98_if_type)) 2191 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 2192 else 2193#endif 2194 (void)commctl(com, TIOCM_DTR, DMBIC); 2195 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) { 2196 timeout(siodtrwakeup, com, com->dtr_wait); 2197 com->state |= CS_DTR_OFF; 2198 } 2199 } 2200#ifdef PC98 2201 else { 2202 if (IS_8251(com->pc98_if_type)) 2203 com_tiocm_bic(com, TIOCM_LE); 2204 } 2205#endif 2206 } 2207#ifdef PC98 2208 if (com->pc98_8251fifo) { 2209 if (com->pc98_8251fifo_enable) 2210 outb(I8251F_fcr, CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 2211 com->pc98_8251fifo_enable = 0; 2212 } 2213#endif 2214 if (com->hasfifo) { 2215 /* 2216 * Disable fifos so that they are off after controlled 2217 * reboots. Some BIOSes fail to detect 16550s when the 2218 * fifos are enabled. 2219 */ 2220 sio_setreg(com, com_fifo, 0); 2221 } 2222 com->active_out = FALSE; 2223 wakeup(&com->active_out); 2224 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */ 2225 splx(s); 2226} 2227 2228static int 2229sioread(dev, uio, flag) 2230 dev_t dev; 2231 struct uio *uio; 2232 int flag; 2233{ 2234 int mynor; 2235 struct com_s *com; 2236 2237 mynor = minor(dev); 2238 if (mynor & CONTROL_MASK) 2239 return (ENODEV); 2240 com = com_addr(MINOR_TO_UNIT(mynor)); 2241 if (com == NULL || com->gone) 2242 return (ENODEV); 2243 return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag)); 2244} 2245 2246static int 2247siowrite(dev, uio, flag) 2248 dev_t dev; 2249 struct uio *uio; 2250 int flag; 2251{ 2252 int mynor; 2253 struct com_s *com; 2254 int unit; 2255 2256 mynor = minor(dev); 2257 if (mynor & CONTROL_MASK) 2258 return (ENODEV); 2259 2260 unit = MINOR_TO_UNIT(mynor); 2261 com = com_addr(unit); 2262 if (com == NULL || com->gone) 2263 return (ENODEV); 2264 /* 2265 * (XXX) We disallow virtual consoles if the physical console is 2266 * a serial port. This is in case there is a display attached that 2267 * is not the console. In that situation we don't need/want the X 2268 * server taking over the console. 2269 */ 2270 if (constty != NULL && unit == comconsole) 2271 constty = NULL; 2272 return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag)); 2273} 2274 2275static void 2276siobusycheck(chan) 2277 void *chan; 2278{ 2279 struct com_s *com; 2280 int s; 2281 2282 com = (struct com_s *)chan; 2283 2284 /* 2285 * Clear TS_BUSY if low-level output is complete. 2286 * spl locking is sufficient because siointr1() does not set CS_BUSY. 2287 * If siointr1() clears CS_BUSY after we look at it, then we'll get 2288 * called again. Reading the line status port outside of siointr1() 2289 * is safe because CS_BUSY is clear so there are no output interrupts 2290 * to lose. 2291 */ 2292 s = spltty(); 2293 if (com->state & CS_BUSY) 2294 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */ 2295#ifdef PC98 2296 else if ((IS_8251(com->pc98_if_type) && 2297 ((com->pc98_8251fifo_enable && 2298 (inb(I8251F_lsr) & (STS8251F_TxRDY | STS8251F_TxEMP)) 2299 == (STS8251F_TxRDY | STS8251F_TxEMP)) || 2300 (!com->pc98_8251fifo_enable && 2301 (inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP)) 2302 == (STS8251_TxRDY | STS8251_TxEMP)))) || 2303 ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2304 == (LSR_TSRE | LSR_TXRDY))) { 2305#else 2306 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2307 == (LSR_TSRE | LSR_TXRDY)) { 2308#endif 2309 com->tp->t_state &= ~TS_BUSY; 2310 ttwwakeup(com->tp); 2311 com->extra_state &= ~CSE_BUSYCHECK; 2312 } else 2313 timeout(siobusycheck, com, hz / 100); 2314 splx(s); 2315} 2316 2317static u_int 2318siodivisor(rclk, speed) 2319 u_long rclk; 2320 speed_t speed; 2321{ 2322 long actual_speed; 2323 u_int divisor; 2324 int error; 2325 2326 if (speed == 0) 2327 return (0); 2328#if UINT_MAX > (ULONG_MAX - 1) / 8 2329 if (speed > (ULONG_MAX - 1) / 8) 2330 return (0); 2331#endif 2332 divisor = (rclk / (8UL * speed) + 1) / 2; 2333 if (divisor == 0 || divisor >= 65536) 2334 return (0); 2335 actual_speed = rclk / (16UL * divisor); 2336 2337 /* 10 times error in percent: */ 2338 error = ((actual_speed - (long)speed) * 2000 / (long)speed + 1) / 2; 2339 2340 /* 3.0% maximum error tolerance: */ 2341 if (error < -30 || error > 30) 2342 return (0); 2343 2344 return (divisor); 2345} 2346 2347static void 2348siodtrwakeup(chan) 2349 void *chan; 2350{ 2351 struct com_s *com; 2352 2353 com = (struct com_s *)chan; 2354 com->state &= ~CS_DTR_OFF; 2355 wakeup(&com->dtr_wait); 2356} 2357 2358/* 2359 * Call this function with the sio_lock mutex held. It will return with the 2360 * lock still held. 2361 */ 2362static void 2363sioinput(com) 2364 struct com_s *com; 2365{ 2366 u_char *buf; 2367 int incc; 2368 u_char line_status; 2369 int recv_data; 2370 struct tty *tp; 2371 2372 buf = com->ibuf; 2373 tp = com->tp; 2374 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) { 2375 com_events -= (com->iptr - com->ibuf); 2376 com->iptr = com->ibuf; 2377 return; 2378 } 2379 if (tp->t_state & TS_CAN_BYPASS_L_RINT) { 2380 /* 2381 * Avoid the grotesquely inefficient lineswitch routine 2382 * (ttyinput) in "raw" mode. It usually takes about 450 2383 * instructions (that's without canonical processing or echo!). 2384 * slinput is reasonably fast (usually 40 instructions plus 2385 * call overhead). 2386 */ 2387 do { 2388 /* 2389 * This may look odd, but it is using save-and-enable 2390 * semantics instead of the save-and-disable semantics 2391 * that are used everywhere else. 2392 */ 2393 mtx_unlock_spin(&sio_lock); 2394 incc = com->iptr - buf; 2395 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat 2396 && (com->state & CS_RTS_IFLOW 2397 || tp->t_iflag & IXOFF) 2398 && !(tp->t_state & TS_TBLOCK)) 2399 ttyblock(tp); 2400 com->delta_error_counts[CE_TTY_BUF_OVERFLOW] 2401 += b_to_q((char *)buf, incc, &tp->t_rawq); 2402 buf += incc; 2403 tk_nin += incc; 2404 tk_rawcc += incc; 2405 tp->t_rawcc += incc; 2406 ttwakeup(tp); 2407 if (tp->t_state & TS_TTSTOP 2408 && (tp->t_iflag & IXANY 2409 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) { 2410 tp->t_state &= ~TS_TTSTOP; 2411 tp->t_lflag &= ~FLUSHO; 2412 comstart(tp); 2413 } 2414 mtx_lock_spin(&sio_lock); 2415 } while (buf < com->iptr); 2416 } else { 2417 do { 2418 /* 2419 * This may look odd, but it is using save-and-enable 2420 * semantics instead of the save-and-disable semantics 2421 * that are used everywhere else. 2422 */ 2423 mtx_unlock_spin(&sio_lock); 2424 line_status = buf[com->ierroff]; 2425 recv_data = *buf++; 2426 if (line_status 2427 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) { 2428 if (line_status & LSR_BI) 2429 recv_data |= TTY_BI; 2430 if (line_status & LSR_FE) 2431 recv_data |= TTY_FE; 2432 if (line_status & LSR_OE) 2433 recv_data |= TTY_OE; 2434 if (line_status & LSR_PE) 2435 recv_data |= TTY_PE; 2436 } 2437 (*linesw[tp->t_line].l_rint)(recv_data, tp); 2438 mtx_lock_spin(&sio_lock); 2439 } while (buf < com->iptr); 2440 } 2441 com_events -= (com->iptr - com->ibuf); 2442 com->iptr = com->ibuf; 2443 2444 /* 2445 * There is now room for another low-level buffer full of input, 2446 * so enable RTS if it is now disabled and there is room in the 2447 * high-level buffer. 2448 */ 2449#ifdef PC98 2450 if (IS_8251(com->pc98_if_type)) { 2451 if ((com->state & CS_RTS_IFLOW) && 2452 !(com_tiocm_get(com) & TIOCM_RTS) && 2453 !(tp->t_state & TS_TBLOCK)) 2454 com_tiocm_bis(com, TIOCM_RTS); 2455 } else { 2456 if ((com->state & CS_RTS_IFLOW) && 2457 !(com->mcr_image & MCR_RTS) && 2458 !(tp->t_state & TS_TBLOCK)) 2459 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2460 } 2461#else 2462 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) && 2463 !(tp->t_state & TS_TBLOCK)) 2464 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2465#endif 2466} 2467 2468static void 2469siointr(arg) 2470 void *arg; 2471{ 2472 struct com_s *com; 2473#if defined(PC98) && defined(COM_MULTIPORT) 2474 u_char rsa_buf_status; 2475#endif 2476 2477#ifndef COM_MULTIPORT 2478 com = (struct com_s *)arg; 2479 2480 mtx_lock_spin(&sio_lock); 2481 siointr1(com); 2482 mtx_unlock_spin(&sio_lock); 2483#else /* COM_MULTIPORT */ 2484 bool_t possibly_more_intrs; 2485 int unit; 2486 2487 /* 2488 * Loop until there is no activity on any port. This is necessary 2489 * to get an interrupt edge more than to avoid another interrupt. 2490 * If the IRQ signal is just an OR of the IRQ signals from several 2491 * devices, then the edge from one may be lost because another is 2492 * on. 2493 */ 2494 mtx_lock_spin(&sio_lock); 2495 do { 2496 possibly_more_intrs = FALSE; 2497 for (unit = 0; unit < sio_numunits; ++unit) { 2498 com = com_addr(unit); 2499 /* 2500 * XXX COM_LOCK(); 2501 * would it work here, or be counter-productive? 2502 */ 2503#ifdef PC98 2504 if (com != NULL 2505 && !com->gone 2506 && IS_8251(com->pc98_if_type)) { 2507 siointr1(com); 2508 } else if (com != NULL 2509 && !com->gone 2510 && com->pc98_if_type == COM_IF_RSA98III) { 2511 rsa_buf_status = 2512 inb(com->rsabase + rsa_srr) & 0xc9; 2513 if ((rsa_buf_status & 0xc8) 2514 || !(rsa_buf_status & 0x01)) { 2515 siointr1(com); 2516 if (rsa_buf_status != 2517 (inb(com->rsabase + rsa_srr) & 0xc9)) 2518 possibly_more_intrs = TRUE; 2519 } 2520 } else 2521#endif 2522 if (com != NULL 2523 && !com->gone 2524 && (inb(com->int_id_port) & IIR_IMASK) 2525 != IIR_NOPEND) { 2526 siointr1(com); 2527 possibly_more_intrs = TRUE; 2528 } 2529 /* XXX COM_UNLOCK(); */ 2530 } 2531 } while (possibly_more_intrs); 2532 mtx_unlock_spin(&sio_lock); 2533#endif /* COM_MULTIPORT */ 2534} 2535 2536static struct timespec siots[8]; 2537static int siotso; 2538static int volatile siotsunit = -1; 2539 2540static int 2541sysctl_siots(SYSCTL_HANDLER_ARGS) 2542{ 2543 char buf[128]; 2544 long long delta; 2545 size_t len; 2546 int error, i, tso; 2547 2548 for (i = 1, tso = siotso; i < tso; i++) { 2549 delta = (long long)(siots[i].tv_sec - siots[i - 1].tv_sec) * 2550 1000000000 + 2551 (siots[i].tv_nsec - siots[i - 1].tv_nsec); 2552 len = sprintf(buf, "%lld\n", delta); 2553 if (delta >= 110000) 2554 len += sprintf(buf + len - 1, ": *** %ld.%09ld\n", 2555 (long)siots[i].tv_sec, siots[i].tv_nsec) - 1; 2556 if (i == tso - 1) 2557 buf[len - 1] = '\0'; 2558 error = SYSCTL_OUT(req, buf, len); 2559 if (error != 0) 2560 return (error); 2561 uio_yield(); 2562 } 2563 return (0); 2564} 2565 2566SYSCTL_PROC(_machdep, OID_AUTO, siots, CTLTYPE_STRING | CTLFLAG_RD, 2567 0, 0, sysctl_siots, "A", "sio timestamps"); 2568 2569static void 2570siointr1(com) 2571 struct com_s *com; 2572{ 2573 u_char int_ctl; 2574 u_char int_ctl_new; 2575 u_char line_status; 2576 u_char modem_status; 2577 u_char *ioptr; 2578 u_char recv_data; 2579 2580#ifdef PC98 2581 u_char tmp = 0; 2582 u_char rsa_buf_status = 0; 2583 int rsa_tx_fifo_size = 0; 2584#endif /* PC98 */ 2585 2586 if (COM_IIR_TXRDYBUG(com->flags)) { 2587 int_ctl = inb(com->int_ctl_port); 2588 int_ctl_new = int_ctl; 2589 } else { 2590 int_ctl = 0; 2591 int_ctl_new = 0; 2592 } 2593 2594 while (!com->gone) { 2595#ifdef PC98 2596status_read:; 2597 if (IS_8251(com->pc98_if_type)) { 2598 if (com->pc98_8251fifo_enable) 2599 tmp = inb(I8251F_lsr); 2600 else 2601 tmp = inb(com->sts_port); 2602more_intr: 2603 line_status = 0; 2604 if (com->pc98_8251fifo_enable) { 2605 if (tmp & STS8251F_TxRDY) line_status |= LSR_TXRDY; 2606 if (tmp & STS8251F_RxRDY) line_status |= LSR_RXRDY; 2607 if (tmp & STS8251F_TxEMP) line_status |= LSR_TSRE; 2608 if (tmp & STS8251F_PE) line_status |= LSR_PE; 2609 if (tmp & STS8251F_OE) line_status |= LSR_OE; 2610 if (tmp & STS8251F_BD_SD) line_status |= LSR_BI; 2611 } else { 2612 if (tmp & STS8251_TxRDY) line_status |= LSR_TXRDY; 2613 if (tmp & STS8251_RxRDY) line_status |= LSR_RXRDY; 2614 if (tmp & STS8251_TxEMP) line_status |= LSR_TSRE; 2615 if (tmp & STS8251_PE) line_status |= LSR_PE; 2616 if (tmp & STS8251_OE) line_status |= LSR_OE; 2617 if (tmp & STS8251_FE) line_status |= LSR_FE; 2618 if (tmp & STS8251_BD_SD) line_status |= LSR_BI; 2619 } 2620 } else { 2621#endif /* PC98 */ 2622 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) { 2623 modem_status = inb(com->modem_status_port); 2624 if ((modem_status ^ com->last_modem_status) & 2625 com->pps_bit) { 2626 pps_capture(&com->pps); 2627 pps_event(&com->pps, 2628 (modem_status & com->pps_bit) ? 2629 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR); 2630 } 2631 } 2632 line_status = inb(com->line_status_port); 2633#ifdef PC98 2634 } 2635 if (com->pc98_if_type == COM_IF_RSA98III) 2636 rsa_buf_status = inb(com->rsabase + rsa_srr); 2637#endif /* PC98 */ 2638 2639 /* input event? (check first to help avoid overruns) */ 2640#ifndef PC98 2641 while (line_status & LSR_RCV_MASK) { 2642#else 2643 while ((line_status & LSR_RCV_MASK) 2644 || (com->pc98_if_type == COM_IF_RSA98III 2645 && (rsa_buf_status & 0x08))) { 2646#endif /* PC98 */ 2647 /* break/unnattached error bits or real input? */ 2648#ifdef PC98 2649 if (IS_8251(com->pc98_if_type)) { 2650 if (com->pc98_8251fifo_enable) { 2651 recv_data = inb(I8251F_data); 2652 if (tmp & (STS8251F_PE | STS8251F_OE | 2653 STS8251F_BD_SD)) { 2654 pc98_i8251_or_cmd(com, CMD8251_ER); 2655 recv_data = 0; 2656 } 2657 } else { 2658 recv_data = inb(com->data_port); 2659 if (tmp & (STS8251_PE | STS8251_OE | 2660 STS8251_FE | STS8251_BD_SD)) { 2661 pc98_i8251_or_cmd(com, CMD8251_ER); 2662 recv_data = 0; 2663 } 2664 } 2665 } else if (com->pc98_if_type == COM_IF_RSA98III) { 2666 if (!(rsa_buf_status & 0x08)) 2667 recv_data = 0; 2668 else 2669 recv_data = inb(com->data_port); 2670 } else 2671#endif 2672 if (!(line_status & LSR_RXRDY)) 2673 recv_data = 0; 2674 else 2675 recv_data = inb(com->data_port); 2676#ifdef DDB 2677#ifdef ALT_BREAK_TO_DEBUGGER 2678 if (com->unit == comconsole && 2679 db_alt_break(recv_data, &com->alt_brk_state) != 0) 2680 breakpoint(); 2681#endif /* ALT_BREAK_TO_DEBUGGER */ 2682#endif /* DDB */ 2683 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) { 2684 /* 2685 * Don't store BI if IGNBRK or FE/PE if IGNPAR. 2686 * Otherwise, push the work to a higher level 2687 * (to handle PARMRK) if we're bypassing. 2688 * Otherwise, convert BI/FE and PE+INPCK to 0. 2689 * 2690 * This makes bypassing work right in the 2691 * usual "raw" case (IGNBRK set, and IGNPAR 2692 * and INPCK clear). 2693 * 2694 * Note: BI together with FE/PE means just BI. 2695 */ 2696 if (line_status & LSR_BI) { 2697#if defined(DDB) && defined(BREAK_TO_DEBUGGER) 2698 if (com->unit == comconsole) { 2699 breakpoint(); 2700 goto cont; 2701 } 2702#endif 2703 if (com->tp == NULL 2704 || com->tp->t_iflag & IGNBRK) 2705 goto cont; 2706 } else { 2707 if (com->tp == NULL 2708 || com->tp->t_iflag & IGNPAR) 2709 goto cont; 2710 } 2711 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT 2712 && (line_status & (LSR_BI | LSR_FE) 2713 || com->tp->t_iflag & INPCK)) 2714 recv_data = 0; 2715 } 2716 ++com->bytes_in; 2717 if (com->hotchar != 0 && recv_data == com->hotchar) 2718 swi_sched(sio_fast_ih, 0); 2719 ioptr = com->iptr; 2720 if (ioptr >= com->ibufend) 2721 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW); 2722 else { 2723 if (com->do_timestamp) 2724 microtime(&com->timestamp); 2725 ++com_events; 2726 swi_sched(sio_slow_ih, SWI_DELAY); 2727#if 0 /* for testing input latency vs efficiency */ 2728if (com->iptr - com->ibuf == 8) 2729 swi_sched(sio_fast_ih, 0); 2730#endif 2731 ioptr[0] = recv_data; 2732 ioptr[com->ierroff] = line_status; 2733 com->iptr = ++ioptr; 2734 if (ioptr == com->ihighwater 2735 && com->state & CS_RTS_IFLOW) 2736#ifdef PC98 2737 IS_8251(com->pc98_if_type) ? 2738 com_tiocm_bic(com, TIOCM_RTS) : 2739#endif 2740 outb(com->modem_ctl_port, 2741 com->mcr_image &= ~MCR_RTS); 2742 if (line_status & LSR_OE) 2743 CE_RECORD(com, CE_OVERRUN); 2744 } 2745cont: 2746 if (line_status & LSR_TXRDY 2747 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) 2748 goto txrdy; 2749 2750 /* 2751 * "& 0x7F" is to avoid the gcc-1.40 generating a slow 2752 * jump from the top of the loop to here 2753 */ 2754#ifdef PC98 2755 if (IS_8251(com->pc98_if_type)) 2756 goto status_read; 2757 else 2758#endif 2759 line_status = inb(com->line_status_port) & 0x7F; 2760#ifdef PC98 2761 if (com->pc98_if_type == COM_IF_RSA98III) 2762 rsa_buf_status = inb(com->rsabase + rsa_srr); 2763#endif /* PC98 */ 2764 } 2765 2766 /* modem status change? (always check before doing output) */ 2767#ifdef PC98 2768 if (!IS_8251(com->pc98_if_type)) { 2769#endif 2770 modem_status = inb(com->modem_status_port); 2771 if (modem_status != com->last_modem_status) { 2772 if (com->do_dcd_timestamp 2773 && !(com->last_modem_status & MSR_DCD) 2774 && modem_status & MSR_DCD) 2775 microtime(&com->dcd_timestamp); 2776 2777 /* 2778 * Schedule high level to handle DCD changes. Note 2779 * that we don't use the delta bits anywhere. Some 2780 * UARTs mess them up, and it's easy to remember the 2781 * previous bits and calculate the delta. 2782 */ 2783 com->last_modem_status = modem_status; 2784 if (!(com->state & CS_CHECKMSR)) { 2785 com_events += LOTS_OF_EVENTS; 2786 com->state |= CS_CHECKMSR; 2787 swi_sched(sio_fast_ih, 0); 2788 } 2789 2790 /* handle CTS change immediately for crisp flow ctl */ 2791 if (com->state & CS_CTS_OFLOW) { 2792 if (modem_status & MSR_CTS) 2793 com->state |= CS_ODEVREADY; 2794 else 2795 com->state &= ~CS_ODEVREADY; 2796 } 2797 } 2798#ifdef PC98 2799 } 2800#endif 2801 2802txrdy: 2803 /* output queued and everything ready? */ 2804#ifndef PC98 2805 if (line_status & LSR_TXRDY 2806 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 2807#else 2808 if (((com->pc98_if_type == COM_IF_RSA98III) 2809 ? (rsa_buf_status & 0x02) 2810 : (line_status & LSR_TXRDY)) 2811 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 2812#endif 2813#ifdef PC98 2814 Port_t tmp_data_port; 2815 2816 if (IS_8251(com->pc98_if_type) && 2817 com->pc98_8251fifo_enable) 2818 tmp_data_port = I8251F_data; 2819 else 2820 tmp_data_port = com->data_port; 2821#endif 2822 2823 ioptr = com->obufq.l_head; 2824 if (com->tx_fifo_size > 1 && com->unit != siotsunit) { 2825 u_int ocount; 2826 2827 ocount = com->obufq.l_tail - ioptr; 2828#ifdef PC98 2829 if (com->pc98_if_type == COM_IF_RSA98III) { 2830 rsa_buf_status = inb(com->rsabase + rsa_srr); 2831 rsa_tx_fifo_size = 1024; 2832 if (!(rsa_buf_status & 0x01)) 2833 rsa_tx_fifo_size = 2048; 2834 if (ocount > rsa_tx_fifo_size) 2835 ocount = rsa_tx_fifo_size; 2836 } else 2837#endif 2838 if (ocount > com->tx_fifo_size) 2839 ocount = com->tx_fifo_size; 2840 com->bytes_out += ocount; 2841 do 2842#ifdef PC98 2843 outb(tmp_data_port, *ioptr++); 2844#else 2845 outb(com->data_port, *ioptr++); 2846#endif 2847 while (--ocount != 0); 2848 } else { 2849#ifdef PC98 2850 outb(tmp_data_port, *ioptr++); 2851#else 2852 outb(com->data_port, *ioptr++); 2853#endif 2854 ++com->bytes_out; 2855 if (com->unit == siotsunit 2856 && siotso < sizeof siots / sizeof siots[0]) 2857 nanouptime(&siots[siotso++]); 2858 } 2859#ifdef PC98 2860 if (IS_8251(com->pc98_if_type)) 2861 if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG)) 2862 com_int_Tx_enable(com); 2863#endif 2864 com->obufq.l_head = ioptr; 2865 if (COM_IIR_TXRDYBUG(com->flags)) 2866 int_ctl_new = int_ctl | IER_ETXRDY; 2867 if (ioptr >= com->obufq.l_tail) { 2868 struct lbq *qp; 2869 2870 qp = com->obufq.l_next; 2871 qp->l_queued = FALSE; 2872 qp = qp->l_next; 2873 if (qp != NULL) { 2874 com->obufq.l_head = qp->l_head; 2875 com->obufq.l_tail = qp->l_tail; 2876 com->obufq.l_next = qp; 2877 } else { 2878 /* output just completed */ 2879 if (COM_IIR_TXRDYBUG(com->flags)) 2880 int_ctl_new = int_ctl 2881 & ~IER_ETXRDY; 2882 com->state &= ~CS_BUSY; 2883#if defined(PC98) 2884 if (IS_8251(com->pc98_if_type) && 2885 pc98_check_i8251_interrupt(com) & IEN_TxFLAG) 2886 com_int_Tx_disable(com); 2887#endif 2888 } 2889 if (!(com->state & CS_ODONE)) { 2890 com_events += LOTS_OF_EVENTS; 2891 com->state |= CS_ODONE; 2892 /* handle at high level ASAP */ 2893 swi_sched(sio_fast_ih, 0); 2894 } 2895 } 2896#ifdef PC98 2897 if (COM_IIR_TXRDYBUG(com->flags) 2898 && int_ctl != int_ctl_new) { 2899 if (com->pc98_if_type == COM_IF_RSA98III) { 2900 int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY); 2901 outb(com->int_ctl_port, int_ctl_new); 2902 outb(com->rsabase + rsa_ier, 0x1d); 2903 } else 2904 outb(com->int_ctl_port, int_ctl_new); 2905 } 2906#else 2907 if (COM_IIR_TXRDYBUG(com->flags) 2908 && int_ctl != int_ctl_new) 2909 outb(com->int_ctl_port, int_ctl_new); 2910#endif 2911 } 2912#ifdef PC98 2913 else if (line_status & LSR_TXRDY) { 2914 if (IS_8251(com->pc98_if_type)) 2915 if (pc98_check_i8251_interrupt(com) & IEN_TxFLAG) 2916 com_int_Tx_disable(com); 2917 } 2918 if (IS_8251(com->pc98_if_type)) { 2919 if (com->pc98_8251fifo_enable) { 2920 if ((tmp = inb(I8251F_lsr)) & STS8251F_RxRDY) 2921 goto more_intr; 2922 } else { 2923 if ((tmp = inb(com->sts_port)) & STS8251_RxRDY) 2924 goto more_intr; 2925 } 2926 } 2927#endif 2928 2929 /* finished? */ 2930#ifndef COM_MULTIPORT 2931#ifdef PC98 2932 if (IS_8251(com->pc98_if_type)) 2933 return; 2934#endif 2935 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND) 2936#endif /* COM_MULTIPORT */ 2937 return; 2938 } 2939} 2940 2941static int 2942sioioctl(dev, cmd, data, flag, td) 2943 dev_t dev; 2944 u_long cmd; 2945 caddr_t data; 2946 int flag; 2947 struct thread *td; 2948{ 2949 struct com_s *com; 2950 int error; 2951 int mynor; 2952 int s; 2953 struct tty *tp; 2954#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 2955 u_long oldcmd; 2956 struct termios term; 2957#endif 2958 2959 mynor = minor(dev); 2960 com = com_addr(MINOR_TO_UNIT(mynor)); 2961 if (com == NULL || com->gone) 2962 return (ENODEV); 2963 if (mynor & CONTROL_MASK) { 2964 struct termios *ct; 2965 2966 switch (mynor & CONTROL_MASK) { 2967 case CONTROL_INIT_STATE: 2968 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in; 2969 break; 2970 case CONTROL_LOCK_STATE: 2971 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in; 2972 break; 2973 default: 2974 return (ENODEV); /* /dev/nodev */ 2975 } 2976 switch (cmd) { 2977 case TIOCSETA: 2978 error = suser(td); 2979 if (error != 0) 2980 return (error); 2981 *ct = *(struct termios *)data; 2982 return (0); 2983 case TIOCGETA: 2984 *(struct termios *)data = *ct; 2985 return (0); 2986 case TIOCGETD: 2987 *(int *)data = TTYDISC; 2988 return (0); 2989 case TIOCGWINSZ: 2990 bzero(data, sizeof(struct winsize)); 2991 return (0); 2992 default: 2993 return (ENOTTY); 2994 } 2995 } 2996 tp = com->tp; 2997#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 2998 term = tp->t_termios; 2999 oldcmd = cmd; 3000 error = ttsetcompat(tp, &cmd, data, &term); 3001 if (error != 0) 3002 return (error); 3003 if (cmd != oldcmd) 3004 data = (caddr_t)&term; 3005#endif 3006 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) { 3007 int cc; 3008 struct termios *dt = (struct termios *)data; 3009 struct termios *lt = mynor & CALLOUT_MASK 3010 ? &com->lt_out : &com->lt_in; 3011 3012 dt->c_iflag = (tp->t_iflag & lt->c_iflag) 3013 | (dt->c_iflag & ~lt->c_iflag); 3014 dt->c_oflag = (tp->t_oflag & lt->c_oflag) 3015 | (dt->c_oflag & ~lt->c_oflag); 3016 dt->c_cflag = (tp->t_cflag & lt->c_cflag) 3017 | (dt->c_cflag & ~lt->c_cflag); 3018 dt->c_lflag = (tp->t_lflag & lt->c_lflag) 3019 | (dt->c_lflag & ~lt->c_lflag); 3020 for (cc = 0; cc < NCCS; ++cc) 3021 if (lt->c_cc[cc] != 0) 3022 dt->c_cc[cc] = tp->t_cc[cc]; 3023 if (lt->c_ispeed != 0) 3024 dt->c_ispeed = tp->t_ispeed; 3025 if (lt->c_ospeed != 0) 3026 dt->c_ospeed = tp->t_ospeed; 3027 } 3028 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, td); 3029 if (error != ENOIOCTL) 3030 return (error); 3031 s = spltty(); 3032 error = ttioctl(tp, cmd, data, flag); 3033 disc_optim(tp, &tp->t_termios, com); 3034 if (error != ENOIOCTL) { 3035 splx(s); 3036 return (error); 3037 } 3038#ifdef PC98 3039 if (IS_8251(com->pc98_if_type)) { 3040 switch (cmd) { 3041 case TIOCSBRK: 3042 com_send_break_on(com); 3043 break; 3044 case TIOCCBRK: 3045 com_send_break_off(com); 3046 break; 3047 case TIOCSDTR: 3048 com_tiocm_bis(com, TIOCM_DTR | TIOCM_RTS); 3049 break; 3050 case TIOCCDTR: 3051 com_tiocm_bic(com, TIOCM_DTR); 3052 break; 3053 /* 3054 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 3055 * changes get undone on the next call to comparam(). 3056 */ 3057 case TIOCMSET: 3058 com_tiocm_set(com, *(int *)data); 3059 break; 3060 case TIOCMBIS: 3061 com_tiocm_bis(com, *(int *)data); 3062 break; 3063 case TIOCMBIC: 3064 com_tiocm_bic(com, *(int *)data); 3065 break; 3066 case TIOCMGET: 3067 *(int *)data = com_tiocm_get(com); 3068 break; 3069 case TIOCMSDTRWAIT: 3070 /* must be root since the wait applies to following logins */ 3071 error = suser(td); 3072 if (error != 0) { 3073 splx(s); 3074 return (error); 3075 } 3076 com->dtr_wait = *(int *)data * hz / 100; 3077 break; 3078 case TIOCMGDTRWAIT: 3079 *(int *)data = com->dtr_wait * 100 / hz; 3080 break; 3081 case TIOCTIMESTAMP: 3082 com->do_timestamp = TRUE; 3083 *(struct timeval *)data = com->timestamp; 3084 break; 3085 case TIOCDCDTIMESTAMP: 3086 com->do_dcd_timestamp = TRUE; 3087 *(struct timeval *)data = com->dcd_timestamp; 3088 break; 3089 default: 3090 splx(s); 3091 error = pps_ioctl(cmd, data, &com->pps); 3092 if (error == ENODEV) 3093 error = ENOTTY; 3094 return (error); 3095 } 3096 } else { 3097#endif 3098 switch (cmd) { 3099 case TIOCSBRK: 3100 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK); 3101 break; 3102 case TIOCCBRK: 3103 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 3104 break; 3105 case TIOCSDTR: 3106 (void)commctl(com, TIOCM_DTR, DMBIS); 3107 break; 3108 case TIOCCDTR: 3109 (void)commctl(com, TIOCM_DTR, DMBIC); 3110 break; 3111 /* 3112 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 3113 * changes get undone on the next call to comparam(). 3114 */ 3115 case TIOCMSET: 3116 (void)commctl(com, *(int *)data, DMSET); 3117 break; 3118 case TIOCMBIS: 3119 (void)commctl(com, *(int *)data, DMBIS); 3120 break; 3121 case TIOCMBIC: 3122 (void)commctl(com, *(int *)data, DMBIC); 3123 break; 3124 case TIOCMGET: 3125 *(int *)data = commctl(com, 0, DMGET); 3126 break; 3127 case TIOCMSDTRWAIT: 3128 /* must be root since the wait applies to following logins */ 3129 error = suser(td); 3130 if (error != 0) { 3131 splx(s); 3132 return (error); 3133 } 3134 com->dtr_wait = *(int *)data * hz / 100; 3135 break; 3136 case TIOCMGDTRWAIT: 3137 *(int *)data = com->dtr_wait * 100 / hz; 3138 break; 3139 case TIOCTIMESTAMP: 3140 com->do_timestamp = TRUE; 3141 *(struct timeval *)data = com->timestamp; 3142 break; 3143 case TIOCDCDTIMESTAMP: 3144 com->do_dcd_timestamp = TRUE; 3145 *(struct timeval *)data = com->dcd_timestamp; 3146 break; 3147 default: 3148 splx(s); 3149 error = pps_ioctl(cmd, data, &com->pps); 3150 if (error == ENODEV) 3151 error = ENOTTY; 3152 return (error); 3153 } 3154#ifdef PC98 3155 } 3156#endif 3157 splx(s); 3158 return (0); 3159} 3160 3161/* software interrupt handler for SWI_TTY */ 3162static void 3163siopoll(void *dummy) 3164{ 3165 int unit; 3166 3167 if (com_events == 0) 3168 return; 3169repeat: 3170 for (unit = 0; unit < sio_numunits; ++unit) { 3171 struct com_s *com; 3172 int incc; 3173 struct tty *tp; 3174 3175 com = com_addr(unit); 3176 if (com == NULL) 3177 continue; 3178 tp = com->tp; 3179 if (tp == NULL || com->gone) { 3180 /* 3181 * Discard any events related to never-opened or 3182 * going-away devices. 3183 */ 3184 mtx_lock_spin(&sio_lock); 3185 incc = com->iptr - com->ibuf; 3186 com->iptr = com->ibuf; 3187 if (com->state & CS_CHECKMSR) { 3188 incc += LOTS_OF_EVENTS; 3189 com->state &= ~CS_CHECKMSR; 3190 } 3191 com_events -= incc; 3192 mtx_unlock_spin(&sio_lock); 3193 continue; 3194 } 3195 if (com->iptr != com->ibuf) { 3196 mtx_lock_spin(&sio_lock); 3197 sioinput(com); 3198 mtx_unlock_spin(&sio_lock); 3199 } 3200 if (com->state & CS_CHECKMSR) { 3201 u_char delta_modem_status; 3202 3203#ifdef PC98 3204 if (!IS_8251(com->pc98_if_type)) { 3205#endif 3206 mtx_lock_spin(&sio_lock); 3207 delta_modem_status = com->last_modem_status 3208 ^ com->prev_modem_status; 3209 com->prev_modem_status = com->last_modem_status; 3210 com_events -= LOTS_OF_EVENTS; 3211 com->state &= ~CS_CHECKMSR; 3212 mtx_unlock_spin(&sio_lock); 3213 if (delta_modem_status & MSR_DCD) 3214 (*linesw[tp->t_line].l_modem) 3215 (tp, com->prev_modem_status & MSR_DCD); 3216#ifdef PC98 3217 } 3218#endif 3219 } 3220 if (com->state & CS_ODONE) { 3221 mtx_lock_spin(&sio_lock); 3222 com_events -= LOTS_OF_EVENTS; 3223 com->state &= ~CS_ODONE; 3224 mtx_unlock_spin(&sio_lock); 3225 if (!(com->state & CS_BUSY) 3226 && !(com->extra_state & CSE_BUSYCHECK)) { 3227 timeout(siobusycheck, com, hz / 100); 3228 com->extra_state |= CSE_BUSYCHECK; 3229 } 3230 (*linesw[tp->t_line].l_start)(tp); 3231 } 3232 if (com_events == 0) 3233 break; 3234 } 3235 if (com_events >= LOTS_OF_EVENTS) 3236 goto repeat; 3237} 3238 3239static int 3240comparam(tp, t) 3241 struct tty *tp; 3242 struct termios *t; 3243{ 3244 u_int cfcr; 3245 int cflag; 3246 struct com_s *com; 3247 u_int divisor; 3248 u_char dlbh; 3249 u_char dlbl; 3250 u_char efr_flowbits; 3251 int s; 3252 int unit; 3253#ifdef PC98 3254 u_char param = 0; 3255#endif 3256 3257 unit = DEV_TO_UNIT(tp->t_dev); 3258 com = com_addr(unit); 3259 if (com == NULL) 3260 return (ENODEV); 3261 3262#ifdef PC98 3263 cfcr = 0; 3264 3265 if (IS_8251(com->pc98_if_type)) { 3266 if (pc98_ttspeedtab(com, t->c_ospeed, &divisor) != 0) 3267 return (EINVAL); 3268 } else { 3269#endif 3270 /* check requested parameters */ 3271 if (t->c_ispeed != (t->c_ospeed != 0 ? t->c_ospeed : tp->t_ospeed)) 3272 return (EINVAL); 3273 divisor = siodivisor(com->rclk, t->c_ispeed); 3274 if (divisor == 0) 3275 return (EINVAL); 3276#ifdef PC98 3277 } 3278#endif 3279 3280 /* parameters are OK, convert them to the com struct and the device */ 3281 s = spltty(); 3282#ifdef PC98 3283 if (IS_8251(com->pc98_if_type)) { 3284 if (t->c_ospeed == 0) 3285 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 3286 else 3287 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 3288 } else 3289#endif 3290 if (t->c_ospeed == 0) 3291 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */ 3292 else 3293 (void)commctl(com, TIOCM_DTR, DMBIS); 3294 cflag = t->c_cflag; 3295#ifdef PC98 3296 if (!IS_8251(com->pc98_if_type)) { 3297#endif 3298 switch (cflag & CSIZE) { 3299 case CS5: 3300 cfcr = CFCR_5BITS; 3301 break; 3302 case CS6: 3303 cfcr = CFCR_6BITS; 3304 break; 3305 case CS7: 3306 cfcr = CFCR_7BITS; 3307 break; 3308 default: 3309 cfcr = CFCR_8BITS; 3310 break; 3311 } 3312 if (cflag & PARENB) { 3313 cfcr |= CFCR_PENAB; 3314 if (!(cflag & PARODD)) 3315 cfcr |= CFCR_PEVEN; 3316 } 3317 if (cflag & CSTOPB) 3318 cfcr |= CFCR_STOPB; 3319 3320 if (com->hasfifo) { 3321 /* 3322 * Use a fifo trigger level low enough so that the input 3323 * latency from the fifo is less than about 16 msec and 3324 * the total latency is less than about 30 msec. These 3325 * latencies are reasonable for humans. Serial comms 3326 * protocols shouldn't expect anything better since modem 3327 * latencies are larger. 3328 * 3329 * The fifo trigger level cannot be set at RX_HIGH for high 3330 * speed connections without further work on reducing 3331 * interrupt disablement times in other parts of the system, 3332 * without producing silo overflow errors. 3333 */ 3334 com->fifo_image = com->unit == siotsunit ? 0 3335 : t->c_ispeed <= 4800 3336 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_MEDH; 3337#ifdef COM_ESP 3338 /* 3339 * The Hayes ESP card needs the fifo DMA mode bit set 3340 * in compatibility mode. If not, it will interrupt 3341 * for each character received. 3342 */ 3343 if (com->esp) 3344 com->fifo_image |= FIFO_DMA_MODE; 3345#endif 3346 sio_setreg(com, com_fifo, com->fifo_image); 3347 } 3348#ifdef PC98 3349 } 3350#endif 3351 3352 /* 3353 * This returns with interrupts disabled so that we can complete 3354 * the speed change atomically. Keeping interrupts disabled is 3355 * especially important while com_data is hidden. 3356 */ 3357 (void) siosetwater(com, t->c_ispeed); 3358 3359#ifdef PC98 3360 if (IS_8251(com->pc98_if_type)) 3361 com_cflag_and_speed_set(com, cflag, t->c_ospeed); 3362 else { 3363#endif 3364 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB); 3365 /* 3366 * Only set the divisor registers if they would change, since on 3367 * some 16550 incompatibles (UMC8669F), setting them while input 3368 * is arriving loses sync until data stops arriving. 3369 */ 3370 dlbl = divisor & 0xFF; 3371 if (sio_getreg(com, com_dlbl) != dlbl) 3372 sio_setreg(com, com_dlbl, dlbl); 3373 dlbh = divisor >> 8; 3374 if (sio_getreg(com, com_dlbh) != dlbh) 3375 sio_setreg(com, com_dlbh, dlbh); 3376#ifdef PC98 3377 } 3378#endif 3379 3380 efr_flowbits = 0; 3381 3382 if (cflag & CRTS_IFLOW) { 3383 com->state |= CS_RTS_IFLOW; 3384 efr_flowbits |= EFR_AUTORTS; 3385 /* 3386 * If CS_RTS_IFLOW just changed from off to on, the change 3387 * needs to be propagated to MCR_RTS. This isn't urgent, 3388 * so do it later by calling comstart() instead of repeating 3389 * a lot of code from comstart() here. 3390 */ 3391 } else if (com->state & CS_RTS_IFLOW) { 3392 com->state &= ~CS_RTS_IFLOW; 3393 /* 3394 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS 3395 * on here, since comstart() won't do it later. 3396 */ 3397#ifdef PC98 3398 if (IS_8251(com->pc98_if_type)) 3399 com_tiocm_bis(com, TIOCM_RTS); 3400 else 3401 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3402#else 3403 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3404#endif 3405 } 3406 3407 /* 3408 * Set up state to handle output flow control. 3409 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level? 3410 * Now has 10+ msec latency, while CTS flow has 50- usec latency. 3411 */ 3412 com->state |= CS_ODEVREADY; 3413 com->state &= ~CS_CTS_OFLOW; 3414#ifdef PC98 3415 if (com->pc98_if_type == COM_IF_RSA98III) { 3416 param = inb(com->rsabase + rsa_msr); 3417 outb(com->rsabase + rsa_msr, param & 0x14); 3418 } 3419#endif 3420 if (cflag & CCTS_OFLOW) { 3421 com->state |= CS_CTS_OFLOW; 3422 efr_flowbits |= EFR_AUTOCTS; 3423#ifdef PC98 3424 if (IS_8251(com->pc98_if_type)) { 3425 if (!(pc98_get_modem_status(com) & TIOCM_CTS)) 3426 com->state &= ~CS_ODEVREADY; 3427 } else if (com->pc98_if_type == COM_IF_RSA98III) { 3428 /* Set automatic flow control mode */ 3429 outb(com->rsabase + rsa_msr, param | 0x08); 3430 } else 3431#endif 3432 if (!(com->last_modem_status & MSR_CTS)) 3433 com->state &= ~CS_ODEVREADY; 3434 } 3435 3436#ifdef PC98 3437 if (!IS_8251(com->pc98_if_type)) 3438 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr); 3439#else 3440 if (com->st16650a) { 3441 sio_setreg(com, com_lcr, LCR_EFR_ENABLE); 3442 sio_setreg(com, com_efr, 3443 (sio_getreg(com, com_efr) 3444 & ~(EFR_AUTOCTS | EFR_AUTORTS)) | efr_flowbits); 3445 } 3446 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr); 3447#endif 3448 3449 /* XXX shouldn't call functions while intrs are disabled. */ 3450 disc_optim(tp, t, com); 3451 3452 mtx_unlock_spin(&sio_lock); 3453 splx(s); 3454 comstart(tp); 3455 if (com->ibufold != NULL) { 3456 free(com->ibufold, M_DEVBUF); 3457 com->ibufold = NULL; 3458 } 3459 return (0); 3460} 3461 3462/* 3463 * This function must be called with the sio_lock mutex released and will 3464 * return with it obtained. 3465 */ 3466static int 3467siosetwater(com, speed) 3468 struct com_s *com; 3469 speed_t speed; 3470{ 3471 int cp4ticks; 3472 u_char *ibuf; 3473 int ibufsize; 3474 struct tty *tp; 3475 3476 /* 3477 * Make the buffer size large enough to handle a softtty interrupt 3478 * latency of about 2 ticks without loss of throughput or data 3479 * (about 3 ticks if input flow control is not used or not honoured, 3480 * but a bit less for CS5-CS7 modes). 3481 */ 3482 cp4ticks = speed / 10 / hz * 4; 3483 for (ibufsize = 128; ibufsize < cp4ticks;) 3484 ibufsize <<= 1; 3485#ifdef PC98 3486 if (com->pc98_if_type == COM_IF_RSA98III) 3487 ibufsize = 2048; 3488#endif 3489 if (ibufsize == com->ibufsize) { 3490 mtx_lock_spin(&sio_lock); 3491 return (0); 3492 } 3493 3494 /* 3495 * Allocate input buffer. The extra factor of 2 in the size is 3496 * to allow for an error byte for each input byte. 3497 */ 3498 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT); 3499 if (ibuf == NULL) { 3500 mtx_lock_spin(&sio_lock); 3501 return (ENOMEM); 3502 } 3503 3504 /* Initialize non-critical variables. */ 3505 com->ibufold = com->ibuf; 3506 com->ibufsize = ibufsize; 3507 tp = com->tp; 3508 if (tp != NULL) { 3509 tp->t_ififosize = 2 * ibufsize; 3510 tp->t_ispeedwat = (speed_t)-1; 3511 tp->t_ospeedwat = (speed_t)-1; 3512 } 3513 3514 /* 3515 * Read current input buffer, if any. Continue with interrupts 3516 * disabled. 3517 */ 3518 mtx_lock_spin(&sio_lock); 3519 if (com->iptr != com->ibuf) 3520 sioinput(com); 3521 3522 /*- 3523 * Initialize critical variables, including input buffer watermarks. 3524 * The external device is asked to stop sending when the buffer 3525 * exactly reaches high water, or when the high level requests it. 3526 * The high level is notified immediately (rather than at a later 3527 * clock tick) when this watermark is reached. 3528 * The buffer size is chosen so the watermark should almost never 3529 * be reached. 3530 * The low watermark is invisibly 0 since the buffer is always 3531 * emptied all at once. 3532 */ 3533 com->iptr = com->ibuf = ibuf; 3534 com->ibufend = ibuf + ibufsize; 3535 com->ierroff = ibufsize; 3536 com->ihighwater = ibuf + 3 * ibufsize / 4; 3537 return (0); 3538} 3539 3540static void 3541comstart(tp) 3542 struct tty *tp; 3543{ 3544 struct com_s *com; 3545 int s; 3546 int unit; 3547 3548 unit = DEV_TO_UNIT(tp->t_dev); 3549 com = com_addr(unit); 3550 if (com == NULL) 3551 return; 3552 s = spltty(); 3553 mtx_lock_spin(&sio_lock); 3554 if (tp->t_state & TS_TTSTOP) 3555 com->state &= ~CS_TTGO; 3556 else 3557 com->state |= CS_TTGO; 3558 if (tp->t_state & TS_TBLOCK) { 3559#ifdef PC98 3560 if (IS_8251(com->pc98_if_type)) { 3561 if ((com_tiocm_get(com) & TIOCM_RTS) && 3562 (com->state & CS_RTS_IFLOW)) 3563 com_tiocm_bic(com, TIOCM_RTS); 3564 } else { 3565 if ((com->mcr_image & MCR_RTS) && 3566 (com->state & CS_RTS_IFLOW)) 3567 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3568 } 3569#else 3570 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW) 3571 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3572#endif 3573 } else { 3574#ifdef PC98 3575 if (IS_8251(com->pc98_if_type)) { 3576 if (!(com_tiocm_get(com) & TIOCM_RTS) && 3577 com->iptr < com->ihighwater && 3578 com->state & CS_RTS_IFLOW) 3579 com_tiocm_bis(com, TIOCM_RTS); 3580 } else { 3581 if (!(com->mcr_image & MCR_RTS) && 3582 com->iptr < com->ihighwater && 3583 com->state & CS_RTS_IFLOW) 3584 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3585 } 3586#else 3587 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater 3588 && com->state & CS_RTS_IFLOW) 3589 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3590#endif 3591 } 3592 mtx_unlock_spin(&sio_lock); 3593 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) { 3594 ttwwakeup(tp); 3595 splx(s); 3596 return; 3597 } 3598 if (tp->t_outq.c_cc != 0) { 3599 struct lbq *qp; 3600 struct lbq *next; 3601 3602 if (!com->obufs[0].l_queued) { 3603 com->obufs[0].l_tail 3604 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1, 3605#ifdef PC98 3606 com->obufsize); 3607#else 3608 sizeof com->obuf1); 3609#endif 3610 com->obufs[0].l_next = NULL; 3611 com->obufs[0].l_queued = TRUE; 3612 mtx_lock_spin(&sio_lock); 3613 if (com->state & CS_BUSY) { 3614 qp = com->obufq.l_next; 3615 while ((next = qp->l_next) != NULL) 3616 qp = next; 3617 qp->l_next = &com->obufs[0]; 3618 } else { 3619 com->obufq.l_head = com->obufs[0].l_head; 3620 com->obufq.l_tail = com->obufs[0].l_tail; 3621 com->obufq.l_next = &com->obufs[0]; 3622 com->state |= CS_BUSY; 3623 } 3624 mtx_unlock_spin(&sio_lock); 3625 } 3626 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) { 3627 com->obufs[1].l_tail 3628 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2, 3629#ifdef PC98 3630 com->obufsize); 3631#else 3632 sizeof com->obuf2); 3633#endif 3634 com->obufs[1].l_next = NULL; 3635 com->obufs[1].l_queued = TRUE; 3636 mtx_lock_spin(&sio_lock); 3637 if (com->state & CS_BUSY) { 3638 qp = com->obufq.l_next; 3639 while ((next = qp->l_next) != NULL) 3640 qp = next; 3641 qp->l_next = &com->obufs[1]; 3642 } else { 3643 com->obufq.l_head = com->obufs[1].l_head; 3644 com->obufq.l_tail = com->obufs[1].l_tail; 3645 com->obufq.l_next = &com->obufs[1]; 3646 com->state |= CS_BUSY; 3647 } 3648 mtx_unlock_spin(&sio_lock); 3649 } 3650 tp->t_state |= TS_BUSY; 3651 } 3652 mtx_lock_spin(&sio_lock); 3653 if (com->state >= (CS_BUSY | CS_TTGO)) 3654 siointr1(com); /* fake interrupt to start output */ 3655 mtx_unlock_spin(&sio_lock); 3656 ttwwakeup(tp); 3657 splx(s); 3658} 3659 3660static void 3661comstop(tp, rw) 3662 struct tty *tp; 3663 int rw; 3664{ 3665 struct com_s *com; 3666#ifdef PC98 3667 int rsa98_tmp = 0; 3668#endif 3669 3670 com = com_addr(DEV_TO_UNIT(tp->t_dev)); 3671 if (com == NULL || com->gone) 3672 return; 3673 mtx_lock_spin(&sio_lock); 3674 if (rw & FWRITE) { 3675#ifdef PC98 3676 if (!IS_8251(com->pc98_if_type)) { 3677#endif 3678 if (com->hasfifo) 3679#ifdef COM_ESP 3680 /* XXX avoid h/w bug. */ 3681 if (!com->esp) 3682#endif 3683 sio_setreg(com, com_fifo, 3684 FIFO_XMT_RST | com->fifo_image); 3685#ifdef PC98 3686 if (com->pc98_if_type == COM_IF_RSA98III) 3687 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3688 sio_setreg(com, com_fifo, 3689 FIFO_XMT_RST | com->fifo_image); 3690 } 3691#endif 3692 com->obufs[0].l_queued = FALSE; 3693 com->obufs[1].l_queued = FALSE; 3694 if (com->state & CS_ODONE) 3695 com_events -= LOTS_OF_EVENTS; 3696 com->state &= ~(CS_ODONE | CS_BUSY); 3697 com->tp->t_state &= ~TS_BUSY; 3698 } 3699 if (rw & FREAD) { 3700#ifdef PC98 3701 if (!IS_8251(com->pc98_if_type)) { 3702 if (com->pc98_if_type == COM_IF_RSA98III) 3703 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3704 sio_getreg(com, com_data); 3705#endif 3706 if (com->hasfifo) 3707#ifdef COM_ESP 3708 /* XXX avoid h/w bug. */ 3709 if (!com->esp) 3710#endif 3711 sio_setreg(com, com_fifo, 3712 FIFO_RCV_RST | com->fifo_image); 3713#ifdef PC98 3714 } 3715#endif 3716 com_events -= (com->iptr - com->ibuf); 3717 com->iptr = com->ibuf; 3718 } 3719 mtx_unlock_spin(&sio_lock); 3720 comstart(tp); 3721} 3722 3723static int 3724commctl(com, bits, how) 3725 struct com_s *com; 3726 int bits; 3727 int how; 3728{ 3729 int mcr; 3730 int msr; 3731 3732 if (how == DMGET) { 3733 bits = TIOCM_LE; /* XXX - always enabled while open */ 3734 mcr = com->mcr_image; 3735 if (mcr & MCR_DTR) 3736 bits |= TIOCM_DTR; 3737 if (mcr & MCR_RTS) 3738 bits |= TIOCM_RTS; 3739 msr = com->prev_modem_status; 3740 if (msr & MSR_CTS) 3741 bits |= TIOCM_CTS; 3742 if (msr & MSR_DCD) 3743 bits |= TIOCM_CD; 3744 if (msr & MSR_DSR) 3745 bits |= TIOCM_DSR; 3746 /* 3747 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI 3748 * more volatile by reading the modem status a lot. Perhaps 3749 * we should latch both bits until the status is read here. 3750 */ 3751 if (msr & (MSR_RI | MSR_TERI)) 3752 bits |= TIOCM_RI; 3753 return (bits); 3754 } 3755 mcr = 0; 3756 if (bits & TIOCM_DTR) 3757 mcr |= MCR_DTR; 3758 if (bits & TIOCM_RTS) 3759 mcr |= MCR_RTS; 3760 if (com->gone) 3761 return(0); 3762 mtx_lock_spin(&sio_lock); 3763 switch (how) { 3764 case DMSET: 3765 outb(com->modem_ctl_port, 3766 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE)); 3767 break; 3768 case DMBIS: 3769 outb(com->modem_ctl_port, com->mcr_image |= mcr); 3770 break; 3771 case DMBIC: 3772 outb(com->modem_ctl_port, com->mcr_image &= ~mcr); 3773 break; 3774 } 3775 mtx_unlock_spin(&sio_lock); 3776 return (0); 3777} 3778 3779static void 3780siosettimeout() 3781{ 3782 struct com_s *com; 3783 bool_t someopen; 3784 int unit; 3785 3786 /* 3787 * Set our timeout period to 1 second if no polled devices are open. 3788 * Otherwise set it to max(1/200, 1/hz). 3789 * Enable timeouts iff some device is open. 3790 */ 3791 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 3792 sio_timeout = hz; 3793 someopen = FALSE; 3794 for (unit = 0; unit < sio_numunits; ++unit) { 3795 com = com_addr(unit); 3796 if (com != NULL && com->tp != NULL 3797 && com->tp->t_state & TS_ISOPEN && !com->gone) { 3798 someopen = TRUE; 3799 if (com->poll || com->poll_output) { 3800 sio_timeout = hz > 200 ? hz / 200 : 1; 3801 break; 3802 } 3803 } 3804 } 3805 if (someopen) { 3806 sio_timeouts_until_log = hz / sio_timeout; 3807 sio_timeout_handle = timeout(comwakeup, (void *)NULL, 3808 sio_timeout); 3809 } else { 3810 /* Flush error messages, if any. */ 3811 sio_timeouts_until_log = 1; 3812 comwakeup((void *)NULL); 3813 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 3814 } 3815} 3816 3817static void 3818comwakeup(chan) 3819 void *chan; 3820{ 3821 struct com_s *com; 3822 int unit; 3823 3824 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout); 3825 3826 /* 3827 * Recover from lost output interrupts. 3828 * Poll any lines that don't use interrupts. 3829 */ 3830 for (unit = 0; unit < sio_numunits; ++unit) { 3831 com = com_addr(unit); 3832 if (com != NULL && !com->gone 3833 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) { 3834 mtx_lock_spin(&sio_lock); 3835 siointr1(com); 3836 mtx_unlock_spin(&sio_lock); 3837 } 3838 } 3839 3840 /* 3841 * Check for and log errors, but not too often. 3842 */ 3843 if (--sio_timeouts_until_log > 0) 3844 return; 3845 sio_timeouts_until_log = hz / sio_timeout; 3846 for (unit = 0; unit < sio_numunits; ++unit) { 3847 int errnum; 3848 3849 com = com_addr(unit); 3850 if (com == NULL) 3851 continue; 3852 if (com->gone) 3853 continue; 3854 for (errnum = 0; errnum < CE_NTYPES; ++errnum) { 3855 u_int delta; 3856 u_long total; 3857 3858 mtx_lock_spin(&sio_lock); 3859 delta = com->delta_error_counts[errnum]; 3860 com->delta_error_counts[errnum] = 0; 3861 mtx_unlock_spin(&sio_lock); 3862 if (delta == 0) 3863 continue; 3864 total = com->error_counts[errnum] += delta; 3865 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n", 3866 unit, delta, error_desc[errnum], 3867 delta == 1 ? "" : "s", total); 3868 } 3869 } 3870} 3871 3872#ifdef PC98 3873/* commint is called when modem control line changes */ 3874static void 3875commint(dev_t dev) 3876{ 3877 register struct tty *tp; 3878 int stat,delta; 3879 struct com_s *com; 3880 int mynor,unit; 3881 3882 mynor = minor(dev); 3883 unit = MINOR_TO_UNIT(mynor); 3884 com = com_addr(unit); 3885 tp = com->tp; 3886 3887 stat = com_tiocm_get(com); 3888 delta = com_tiocm_get_delta(com); 3889 3890 if (com->state & CS_CTS_OFLOW) { 3891 if (stat & TIOCM_CTS) 3892 com->state |= CS_ODEVREADY; 3893 else 3894 com->state &= ~CS_ODEVREADY; 3895 } 3896 if ((delta & TIOCM_CAR) && (mynor & CALLOUT_MASK) == 0) { 3897 if (stat & TIOCM_CAR ) 3898 (void)(*linesw[tp->t_line].l_modem)(tp, 1); 3899 else if ((*linesw[tp->t_line].l_modem)(tp, 0) == 0) { 3900 /* negate DTR, RTS */ 3901 com_tiocm_bic(com, (tp->t_cflag & HUPCL) ? 3902 TIOCM_DTR|TIOCM_RTS|TIOCM_LE : TIOCM_LE ); 3903 /* disable IENABLE */ 3904 com_int_TxRx_disable( com ); 3905 } 3906 } 3907} 3908#endif 3909 3910static void 3911disc_optim(tp, t, com) 3912 struct tty *tp; 3913 struct termios *t; 3914 struct com_s *com; 3915{ 3916 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 3917 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 3918 && (!(t->c_iflag & PARMRK) 3919 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 3920 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 3921 && linesw[tp->t_line].l_rint == ttyinput) 3922 tp->t_state |= TS_CAN_BYPASS_L_RINT; 3923 else 3924 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 3925 com->hotchar = linesw[tp->t_line].l_hotchar; 3926} 3927 3928/* 3929 * Following are all routines needed for SIO to act as console 3930 */ 3931struct siocnstate { 3932 u_char dlbl; 3933 u_char dlbh; 3934 u_char ier; 3935 u_char cfcr; 3936 u_char mcr; 3937}; 3938 3939/* 3940 * This is a function in order to not replicate "ttyd%d" more 3941 * places than absolutely necessary. 3942 */ 3943static void 3944siocnset(struct consdev *cd, int unit) 3945{ 3946 3947 cd->cn_unit = unit; 3948 sprintf(cd->cn_name, "ttyd%d", unit); 3949} 3950 3951#ifndef __alpha__ 3952static speed_t siocngetspeed(Port_t, u_long rclk); 3953#endif 3954static void siocnclose(struct siocnstate *sp, Port_t iobase); 3955static void siocnopen(struct siocnstate *sp, Port_t iobase, int speed); 3956static void siocntxwait(Port_t iobase); 3957 3958#ifdef __alpha__ 3959int siocnattach(int port, int speed); 3960int siogdbattach(int port, int speed); 3961int siogdbgetc(void); 3962void siogdbputc(int c); 3963#else 3964static cn_probe_t siocnprobe; 3965static cn_init_t siocninit; 3966static cn_term_t siocnterm; 3967#endif 3968static cn_checkc_t siocncheckc; 3969static cn_getc_t siocngetc; 3970static cn_putc_t siocnputc; 3971 3972#ifndef __alpha__ 3973CONS_DRIVER(sio, siocnprobe, siocninit, siocnterm, siocngetc, siocncheckc, 3974 siocnputc, NULL); 3975#endif 3976 3977#if DDB > 0 3978static struct consdev gdbconsdev; 3979#endif 3980 3981static void 3982siocntxwait(iobase) 3983 Port_t iobase; 3984{ 3985 int timo; 3986 3987 /* 3988 * Wait for any pending transmission to finish. Required to avoid 3989 * the UART lockup bug when the speed is changed, and for normal 3990 * transmits. 3991 */ 3992 timo = 100000; 3993 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY)) 3994 != (LSR_TSRE | LSR_TXRDY) && --timo != 0) 3995 ; 3996} 3997 3998#ifndef __alpha__ 3999 4000/* 4001 * Read the serial port specified and try to figure out what speed 4002 * it's currently running at. We're assuming the serial port has 4003 * been initialized and is basicly idle. This routine is only intended 4004 * to be run at system startup. 4005 * 4006 * If the value read from the serial port doesn't make sense, return 0. 4007 */ 4008 4009static speed_t 4010siocngetspeed(iobase, rclk) 4011 Port_t iobase; 4012 u_long rclk; 4013{ 4014 u_int divisor; 4015 u_char dlbh; 4016 u_char dlbl; 4017 u_char cfcr; 4018 4019 cfcr = inb(iobase + com_cfcr); 4020 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 4021 4022 dlbl = inb(iobase + com_dlbl); 4023 dlbh = inb(iobase + com_dlbh); 4024 4025 outb(iobase + com_cfcr, cfcr); 4026 4027 divisor = dlbh << 8 | dlbl; 4028 4029 /* XXX there should be more sanity checking. */ 4030 if (divisor == 0) 4031 return (CONSPEED); 4032 return (rclk / (16UL * divisor)); 4033} 4034 4035#endif 4036 4037static void 4038siocnopen(sp, iobase, speed) 4039 struct siocnstate *sp; 4040 Port_t iobase; 4041 int speed; 4042{ 4043 u_int divisor; 4044 u_char dlbh; 4045 u_char dlbl; 4046 4047 /* 4048 * Save all the device control registers except the fifo register 4049 * and set our default ones (cs8 -parenb speed=comdefaultrate). 4050 * We can't save the fifo register since it is read-only. 4051 */ 4052 sp->ier = inb(iobase + com_ier); 4053 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */ 4054 siocntxwait(iobase); 4055 sp->cfcr = inb(iobase + com_cfcr); 4056 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 4057 sp->dlbl = inb(iobase + com_dlbl); 4058 sp->dlbh = inb(iobase + com_dlbh); 4059 /* 4060 * Only set the divisor registers if they would change, since on 4061 * some 16550 incompatibles (Startech), setting them clears the 4062 * data input register. This also reduces the effects of the 4063 * UMC8669F bug. 4064 */ 4065 divisor = siodivisor(comdefaultrclk, speed); 4066 dlbl = divisor & 0xFF; 4067 if (sp->dlbl != dlbl) 4068 outb(iobase + com_dlbl, dlbl); 4069 dlbh = divisor >> 8; 4070 if (sp->dlbh != dlbh) 4071 outb(iobase + com_dlbh, dlbh); 4072 outb(iobase + com_cfcr, CFCR_8BITS); 4073 sp->mcr = inb(iobase + com_mcr); 4074 /* 4075 * We don't want interrupts, but must be careful not to "disable" 4076 * them by clearing the MCR_IENABLE bit, since that might cause 4077 * an interrupt by floating the IRQ line. 4078 */ 4079 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS); 4080} 4081 4082static void 4083siocnclose(sp, iobase) 4084 struct siocnstate *sp; 4085 Port_t iobase; 4086{ 4087 /* 4088 * Restore the device control registers. 4089 */ 4090 siocntxwait(iobase); 4091 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 4092 if (sp->dlbl != inb(iobase + com_dlbl)) 4093 outb(iobase + com_dlbl, sp->dlbl); 4094 if (sp->dlbh != inb(iobase + com_dlbh)) 4095 outb(iobase + com_dlbh, sp->dlbh); 4096 outb(iobase + com_cfcr, sp->cfcr); 4097 /* 4098 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them. 4099 */ 4100 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS); 4101 outb(iobase + com_ier, sp->ier); 4102} 4103 4104#ifndef __alpha__ 4105 4106static void 4107siocnprobe(cp) 4108 struct consdev *cp; 4109{ 4110 speed_t boot_speed; 4111 u_char cfcr; 4112 u_int divisor; 4113 int s, unit; 4114 struct siocnstate sp; 4115 4116 /* 4117 * Find our first enabled console, if any. If it is a high-level 4118 * console device, then initialize it and return successfully. 4119 * If it is a low-level console device, then initialize it and 4120 * return unsuccessfully. It must be initialized in both cases 4121 * for early use by console drivers and debuggers. Initializing 4122 * the hardware is not necessary in all cases, since the i/o 4123 * routines initialize it on the fly, but it is necessary if 4124 * input might arrive while the hardware is switched back to an 4125 * uninitialized state. We can't handle multiple console devices 4126 * yet because our low-level routines don't take a device arg. 4127 * We trust the user to set the console flags properly so that we 4128 * don't need to probe. 4129 */ 4130 cp->cn_pri = CN_DEAD; 4131 4132 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */ 4133 int flags; 4134 4135 if (resource_disabled("sio", unit)) 4136 continue; 4137 if (resource_int_value("sio", unit, "flags", &flags)) 4138 continue; 4139 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) { 4140 int port; 4141 Port_t iobase; 4142 4143 if (resource_int_value("sio", unit, "port", &port)) 4144 continue; 4145 iobase = port; 4146 s = spltty(); 4147 if (boothowto & RB_SERIAL) { 4148 boot_speed = 4149 siocngetspeed(iobase, comdefaultrclk); 4150 if (boot_speed) 4151 comdefaultrate = boot_speed; 4152 } 4153 4154 /* 4155 * Initialize the divisor latch. We can't rely on 4156 * siocnopen() to do this the first time, since it 4157 * avoids writing to the latch if the latch appears 4158 * to have the correct value. Also, if we didn't 4159 * just read the speed from the hardware, then we 4160 * need to set the speed in hardware so that 4161 * switching it later is null. 4162 */ 4163 cfcr = inb(iobase + com_cfcr); 4164 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 4165 divisor = siodivisor(comdefaultrclk, comdefaultrate); 4166 outb(iobase + com_dlbl, divisor & 0xff); 4167 outb(iobase + com_dlbh, divisor >> 8); 4168 outb(iobase + com_cfcr, cfcr); 4169 4170 siocnopen(&sp, iobase, comdefaultrate); 4171 4172 splx(s); 4173 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) { 4174 siocnset(cp, unit); 4175 cp->cn_pri = COM_FORCECONSOLE(flags) 4176 || boothowto & RB_SERIAL 4177 ? CN_REMOTE : CN_NORMAL; 4178 siocniobase = iobase; 4179 siocnunit = unit; 4180 } 4181 if (COM_DEBUGGER(flags)) { 4182 printf("sio%d: gdb debugging port\n", unit); 4183 siogdbiobase = iobase; 4184 siogdbunit = unit; 4185#if DDB > 0 4186 siocnset(&gdbconsdev, unit); 4187 gdb_arg = &gdbconsdev; 4188 gdb_getc = siocngetc; 4189 gdb_putc = siocnputc; 4190#endif 4191 } 4192 } 4193 } 4194#ifdef __i386__ 4195#if DDB > 0 4196 /* 4197 * XXX Ugly Compatability. 4198 * If no gdb port has been specified, set it to be the console 4199 * as some configuration files don't specify the gdb port. 4200 */ 4201 if (gdb_arg == NULL && (boothowto & RB_GDB)) { 4202 printf("Warning: no GDB port specified. Defaulting to sio%d.\n", 4203 siocnunit); 4204 printf("Set flag 0x80 on desired GDB port in your\n"); 4205 printf("configuration file (currently sio only).\n"); 4206 siogdbiobase = siocniobase; 4207 siogdbunit = siocnunit; 4208 siocnset(&gdbconsdev, siocnunit); 4209 gdb_arg = &gdbconsdev; 4210 gdb_getc = siocngetc; 4211 gdb_putc = siocnputc; 4212 } 4213#endif 4214#endif 4215} 4216 4217static void 4218siocninit(cp) 4219 struct consdev *cp; 4220{ 4221 comconsole = cp->cn_unit; 4222} 4223 4224static void 4225siocnterm(cp) 4226 struct consdev *cp; 4227{ 4228 comconsole = -1; 4229} 4230 4231#endif 4232 4233#ifdef __alpha__ 4234 4235CONS_DRIVER(sio, NULL, NULL, NULL, siocngetc, siocncheckc, siocnputc, NULL); 4236 4237int 4238siocnattach(port, speed) 4239 int port; 4240 int speed; 4241{ 4242 int s; 4243 u_char cfcr; 4244 u_int divisor; 4245 struct siocnstate sp; 4246 int unit = 0; /* XXX random value! */ 4247 4248 siocniobase = port; 4249 siocnunit = unit; 4250 comdefaultrate = speed; 4251 sio_consdev.cn_pri = CN_NORMAL; 4252 siocnset(&sio_consdev, unit); 4253 4254 s = spltty(); 4255 4256 /* 4257 * Initialize the divisor latch. We can't rely on 4258 * siocnopen() to do this the first time, since it 4259 * avoids writing to the latch if the latch appears 4260 * to have the correct value. Also, if we didn't 4261 * just read the speed from the hardware, then we 4262 * need to set the speed in hardware so that 4263 * switching it later is null. 4264 */ 4265 cfcr = inb(siocniobase + com_cfcr); 4266 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr); 4267 divisor = siodivisor(comdefaultrclk, comdefaultrate); 4268 outb(siocniobase + com_dlbl, divisor & 0xff); 4269 outb(siocniobase + com_dlbh, divisor >> 8); 4270 outb(siocniobase + com_cfcr, cfcr); 4271 4272 siocnopen(&sp, siocniobase, comdefaultrate); 4273 splx(s); 4274 4275 cnadd(&sio_consdev); 4276 return (0); 4277} 4278 4279int 4280siogdbattach(port, speed) 4281 int port; 4282 int speed; 4283{ 4284 int s; 4285 u_char cfcr; 4286 u_int divisor; 4287 struct siocnstate sp; 4288 int unit = 1; /* XXX random value! */ 4289 4290 siogdbiobase = port; 4291 gdbdefaultrate = speed; 4292 4293 printf("sio%d: gdb debugging port\n", unit); 4294 siogdbunit = unit; 4295#if DDB > 0 4296 siocnset(&gdbconsdev, unit); 4297 gdb_arg = &gdbconsdev; 4298 gdb_getc = siocngetc; 4299 gdb_putc = siocnputc; 4300#endif 4301 4302 s = spltty(); 4303 4304 /* 4305 * Initialize the divisor latch. We can't rely on 4306 * siocnopen() to do this the first time, since it 4307 * avoids writing to the latch if the latch appears 4308 * to have the correct value. Also, if we didn't 4309 * just read the speed from the hardware, then we 4310 * need to set the speed in hardware so that 4311 * switching it later is null. 4312 */ 4313 cfcr = inb(siogdbiobase + com_cfcr); 4314 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr); 4315 divisor = siodivisor(comdefaultrclk, gdbdefaultrate); 4316 outb(siogdbiobase + com_dlbl, divisor & 0xff); 4317 outb(siogdbiobase + com_dlbh, divisor >> 8); 4318 outb(siogdbiobase + com_cfcr, cfcr); 4319 4320 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 4321 splx(s); 4322 4323 return (0); 4324} 4325 4326#endif 4327 4328static int 4329siocncheckc(struct consdev *cd) 4330{ 4331 int c; 4332 Port_t iobase; 4333 int s; 4334 struct siocnstate sp; 4335 speed_t speed; 4336 4337 if (cd->cn_unit == siocnunit) { 4338 iobase = siocniobase; 4339 speed = comdefaultrate; 4340 } else { 4341 iobase = siogdbiobase; 4342 speed = gdbdefaultrate; 4343 } 4344 s = spltty(); 4345 siocnopen(&sp, iobase, speed); 4346 if (inb(iobase + com_lsr) & LSR_RXRDY) 4347 c = inb(iobase + com_data); 4348 else 4349 c = -1; 4350 siocnclose(&sp, iobase); 4351 splx(s); 4352 return (c); 4353} 4354 4355static int 4356siocngetc(struct consdev *cd) 4357{ 4358 int c; 4359 Port_t iobase; 4360 int s; 4361 struct siocnstate sp; 4362 speed_t speed; 4363 4364 if (cd->cn_unit == siocnunit) { 4365 iobase = siocniobase; 4366 speed = comdefaultrate; 4367 } else { 4368 iobase = siogdbiobase; 4369 speed = gdbdefaultrate; 4370 } 4371 s = spltty(); 4372 siocnopen(&sp, iobase, speed); 4373 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 4374 ; 4375 c = inb(iobase + com_data); 4376 siocnclose(&sp, iobase); 4377 splx(s); 4378 return (c); 4379} 4380 4381static void 4382siocnputc(struct consdev *cd, int c) 4383{ 4384 int need_unlock; 4385 int s; 4386 struct siocnstate sp; 4387 Port_t iobase; 4388 speed_t speed; 4389 4390 if (cd->cn_unit == siocnunit) { 4391 iobase = siocniobase; 4392 speed = comdefaultrate; 4393 } else { 4394 iobase = siogdbiobase; 4395 speed = gdbdefaultrate; 4396 } 4397 s = spltty(); 4398 need_unlock = 0; 4399 if (sio_inited == 2 && !mtx_owned(&sio_lock)) { 4400 mtx_lock_spin(&sio_lock); 4401 need_unlock = 1; 4402 } 4403 siocnopen(&sp, iobase, speed); 4404 siocntxwait(iobase); 4405 outb(iobase + com_data, c); 4406 siocnclose(&sp, iobase); 4407 if (need_unlock) 4408 mtx_unlock_spin(&sio_lock); 4409 splx(s); 4410} 4411 4412#ifdef __alpha__ 4413int 4414siogdbgetc() 4415{ 4416 int c; 4417 Port_t iobase; 4418 speed_t speed; 4419 int s; 4420 struct siocnstate sp; 4421 4422 if (siogdbunit == siocnunit) { 4423 iobase = siocniobase; 4424 speed = comdefaultrate; 4425 } else { 4426 iobase = siogdbiobase; 4427 speed = gdbdefaultrate; 4428 } 4429 4430 s = spltty(); 4431 siocnopen(&sp, iobase, speed); 4432 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 4433 ; 4434 c = inb(iobase + com_data); 4435 siocnclose(&sp, iobase); 4436 splx(s); 4437 return (c); 4438} 4439 4440void 4441siogdbputc(c) 4442 int c; 4443{ 4444 Port_t iobase; 4445 speed_t speed; 4446 int s; 4447 struct siocnstate sp; 4448 4449 if (siogdbunit == siocnunit) { 4450 iobase = siocniobase; 4451 speed = comdefaultrate; 4452 } else { 4453 iobase = siogdbiobase; 4454 speed = gdbdefaultrate; 4455 } 4456 4457 s = spltty(); 4458 siocnopen(&sp, iobase, speed); 4459 siocntxwait(siogdbiobase); 4460 outb(siogdbiobase + com_data, c); 4461 siocnclose(&sp, siogdbiobase); 4462 splx(s); 4463} 4464#endif 4465 4466#ifdef PC98 4467/* 4468 * pc98 local function 4469 */ 4470 4471static void 4472com_tiocm_set(struct com_s *com, int msr) 4473{ 4474 int s; 4475 int tmp = 0; 4476 int mask = CMD8251_TxEN|CMD8251_RxEN|CMD8251_DTR|CMD8251_RTS; 4477 4478 s=spltty(); 4479 com->pc98_prev_modem_status = ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ) 4480 | ( com->pc98_prev_modem_status & ~(TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4481 tmp |= (CMD8251_TxEN|CMD8251_RxEN); 4482 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4483 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4484 pc98_i8251_clear_or_cmd( com, mask, tmp ); 4485 splx(s); 4486} 4487 4488static void 4489com_tiocm_bis(struct com_s *com, int msr) 4490{ 4491 int s; 4492 int tmp = 0; 4493 4494 s=spltty(); 4495 com->pc98_prev_modem_status |= ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4496 tmp |= CMD8251_TxEN|CMD8251_RxEN; 4497 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4498 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4499 4500 pc98_i8251_or_cmd( com, tmp ); 4501 splx(s); 4502} 4503 4504static void 4505com_tiocm_bic(struct com_s *com, int msr) 4506{ 4507 int s; 4508 int tmp = msr; 4509 4510 s=spltty(); 4511 com->pc98_prev_modem_status &= ~( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4512 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4513 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4514 4515 pc98_i8251_clear_cmd( com, tmp ); 4516 splx(s); 4517} 4518 4519static int 4520com_tiocm_get(struct com_s *com) 4521{ 4522 return( com->pc98_prev_modem_status ); 4523} 4524 4525static int 4526com_tiocm_get_delta(struct com_s *com) 4527{ 4528 int tmp; 4529 4530 tmp = com->pc98_modem_delta; 4531 com->pc98_modem_delta = 0; 4532 return( tmp ); 4533} 4534 4535/* convert to TIOCM_?? ( ioctl.h ) */ 4536static int 4537pc98_get_modem_status(struct com_s *com) 4538{ 4539 register int msr; 4540 4541 msr = com->pc98_prev_modem_status 4542 & ~(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 4543 if (com->pc98_8251fifo_enable) { 4544 int stat2; 4545 4546 stat2 = inb(I8251F_msr); 4547 if ( stat2 & CICSCDF_CD ) msr |= TIOCM_CAR; 4548 if ( stat2 & CICSCDF_CI ) msr |= TIOCM_RI; 4549 if ( stat2 & CICSCDF_DR ) msr |= TIOCM_DSR; 4550 if ( stat2 & CICSCDF_CS ) msr |= TIOCM_CTS; 4551#if COM_CARRIER_DETECT_EMULATE 4552 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 4553 msr |= TIOCM_CAR; 4554 } 4555#endif 4556 } else { 4557 int stat, stat2; 4558 4559 stat = inb(com->sts_port); 4560 stat2 = inb(com->in_modem_port); 4561 if ( !(stat2 & CICSCD_CD) ) msr |= TIOCM_CAR; 4562 if ( !(stat2 & CICSCD_CI) ) msr |= TIOCM_RI; 4563 if ( stat & STS8251_DSR ) msr |= TIOCM_DSR; 4564 if ( !(stat2 & CICSCD_CS) ) msr |= TIOCM_CTS; 4565#if COM_CARRIER_DETECT_EMULATE 4566 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 4567 msr |= TIOCM_CAR; 4568 } 4569#endif 4570 } 4571 return(msr); 4572} 4573 4574static void 4575pc98_check_msr(void* chan) 4576{ 4577 int msr, delta; 4578 int s; 4579 register struct tty *tp; 4580 struct com_s *com; 4581 int mynor; 4582 int unit; 4583 dev_t dev; 4584 4585 dev=(dev_t)chan; 4586 mynor = minor(dev); 4587 unit = MINOR_TO_UNIT(mynor); 4588 com = com_addr(unit); 4589 tp = com->tp; 4590 4591 s = spltty(); 4592 msr = pc98_get_modem_status(com); 4593 /* make change flag */ 4594 delta = msr ^ com->pc98_prev_modem_status; 4595 if ( delta & TIOCM_CAR ) { 4596 if ( com->modem_car_chg_timer ) { 4597 if ( -- com->modem_car_chg_timer ) 4598 msr ^= TIOCM_CAR; 4599 } else { 4600 if ((com->modem_car_chg_timer = (msr & TIOCM_CAR) ? 4601 DCD_ON_RECOGNITION : DCD_OFF_TOLERANCE) != 0) 4602 msr ^= TIOCM_CAR; 4603 } 4604 } else 4605 com->modem_car_chg_timer = 0; 4606 delta = ( msr ^ com->pc98_prev_modem_status ) & 4607 (TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 4608 com->pc98_prev_modem_status = msr; 4609 delta = ( com->pc98_modem_delta |= delta ); 4610 splx(s); 4611 if ( com->modem_checking || (tp->t_state & (TS_ISOPEN)) ) { 4612 if ( delta ) { 4613 commint(dev); 4614 } 4615 timeout(pc98_check_msr, (caddr_t)dev, 4616 PC98_CHECK_MODEM_INTERVAL); 4617 } else { 4618 com->modem_checking = 0; 4619 } 4620} 4621 4622static void 4623pc98_msrint_start(dev_t dev) 4624{ 4625 struct com_s *com; 4626 int mynor; 4627 int unit; 4628 int s = spltty(); 4629 4630 mynor = minor(dev); 4631 unit = MINOR_TO_UNIT(mynor); 4632 com = com_addr(unit); 4633 /* modem control line check routine envoke interval is 1/10 sec */ 4634 if ( com->modem_checking == 0 ) { 4635 com->pc98_prev_modem_status = pc98_get_modem_status(com); 4636 com->pc98_modem_delta = 0; 4637 timeout(pc98_check_msr, (caddr_t)dev, 4638 PC98_CHECK_MODEM_INTERVAL); 4639 com->modem_checking = 1; 4640 } 4641 splx(s); 4642} 4643 4644static void 4645pc98_disable_i8251_interrupt(struct com_s *com, int mod) 4646{ 4647 /* disable interrupt */ 4648 register int tmp; 4649 4650 mod |= ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4651 COM_INT_DISABLE 4652 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4653 outb( com->intr_ctrl_port, (com->intr_enable&=~mod) | tmp ); 4654 COM_INT_ENABLE 4655} 4656 4657static void 4658pc98_enable_i8251_interrupt(struct com_s *com, int mod) 4659{ 4660 register int tmp; 4661 4662 COM_INT_DISABLE 4663 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4664 outb( com->intr_ctrl_port, (com->intr_enable|=mod) | tmp ); 4665 COM_INT_ENABLE 4666} 4667 4668static int 4669pc98_check_i8251_interrupt(struct com_s *com) 4670{ 4671 return ( com->intr_enable & 0x07 ); 4672} 4673 4674static void 4675pc98_i8251_clear_cmd(struct com_s *com, int x) 4676{ 4677 int tmp; 4678 4679 COM_INT_DISABLE 4680 tmp = com->pc98_prev_siocmd & ~(x); 4681 if (com->pc98_8251fifo_enable) 4682 outb(I8251F_fcr, 0); 4683 outb(com->cmd_port, tmp); 4684 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4685 if (com->pc98_8251fifo_enable) 4686 outb(I8251F_fcr, CTRL8251F_ENABLE); 4687 COM_INT_ENABLE 4688} 4689 4690static void 4691pc98_i8251_or_cmd(struct com_s *com, int x) 4692{ 4693 int tmp; 4694 4695 COM_INT_DISABLE 4696 if (com->pc98_8251fifo_enable) 4697 outb(I8251F_fcr, 0); 4698 tmp = com->pc98_prev_siocmd | (x); 4699 outb(com->cmd_port, tmp); 4700 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4701 if (com->pc98_8251fifo_enable) 4702 outb(I8251F_fcr, CTRL8251F_ENABLE); 4703 COM_INT_ENABLE 4704} 4705 4706static void 4707pc98_i8251_set_cmd(struct com_s *com, int x) 4708{ 4709 int tmp; 4710 4711 COM_INT_DISABLE 4712 if (com->pc98_8251fifo_enable) 4713 outb(I8251F_fcr, 0); 4714 tmp = (x); 4715 outb(com->cmd_port, tmp); 4716 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4717 if (com->pc98_8251fifo_enable) 4718 outb(I8251F_fcr, CTRL8251F_ENABLE); 4719 COM_INT_ENABLE 4720} 4721 4722static void 4723pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x) 4724{ 4725 int tmp; 4726 COM_INT_DISABLE 4727 if (com->pc98_8251fifo_enable) 4728 outb(I8251F_fcr, 0); 4729 tmp = com->pc98_prev_siocmd & ~(clr); 4730 tmp |= (x); 4731 outb(com->cmd_port, tmp); 4732 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4733 if (com->pc98_8251fifo_enable) 4734 outb(I8251F_fcr, CTRL8251F_ENABLE); 4735 COM_INT_ENABLE 4736} 4737 4738static int 4739pc98_i8251_get_cmd(struct com_s *com) 4740{ 4741 return com->pc98_prev_siocmd; 4742} 4743 4744static int 4745pc98_i8251_get_mod(struct com_s *com) 4746{ 4747 return com->pc98_prev_siomod; 4748} 4749 4750static void 4751pc98_i8251_reset(struct com_s *com, int mode, int command) 4752{ 4753 if (com->pc98_8251fifo_enable) 4754 outb(I8251F_fcr, 0); 4755 outb(com->cmd_port, 0); /* dummy */ 4756 DELAY(2); 4757 outb(com->cmd_port, 0); /* dummy */ 4758 DELAY(2); 4759 outb(com->cmd_port, 0); /* dummy */ 4760 DELAY(2); 4761 outb(com->cmd_port, CMD8251_RESET); /* internal reset */ 4762 DELAY(2); 4763 outb(com->cmd_port, mode ); /* mode register */ 4764 com->pc98_prev_siomod = mode; 4765 DELAY(2); 4766 pc98_i8251_set_cmd( com, (command|CMD8251_ER) ); 4767 DELAY(10); 4768 if (com->pc98_8251fifo_enable) 4769 outb(I8251F_fcr, CTRL8251F_ENABLE | 4770 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 4771} 4772 4773static void 4774pc98_check_sysclock(void) 4775{ 4776 /* get system clock from port */ 4777 if ( pc98_machine_type & M_8M ) { 4778 /* 8 MHz system & H98 */ 4779 sysclock = 8; 4780 } else { 4781 /* 5 MHz system */ 4782 sysclock = 5; 4783 } 4784} 4785 4786static void 4787com_cflag_and_speed_set( struct com_s *com, int cflag, int speed) 4788{ 4789 int cfcr=0; 4790 int previnterrupt; 4791 u_int count; 4792 4793 if (pc98_ttspeedtab(com, speed, &count) != 0) 4794 return; 4795 4796 previnterrupt = pc98_check_i8251_interrupt(com); 4797 pc98_disable_i8251_interrupt( com, IEN_Tx|IEN_TxEMP|IEN_Rx ); 4798 4799 switch ( cflag&CSIZE ) { 4800 case CS5: 4801 cfcr = MOD8251_5BITS; break; 4802 case CS6: 4803 cfcr = MOD8251_6BITS; break; 4804 case CS7: 4805 cfcr = MOD8251_7BITS; break; 4806 case CS8: 4807 cfcr = MOD8251_8BITS; break; 4808 } 4809 if ( cflag&PARENB ) { 4810 if ( cflag&PARODD ) 4811 cfcr |= MOD8251_PODD; 4812 else 4813 cfcr |= MOD8251_PEVEN; 4814 } else 4815 cfcr |= MOD8251_PDISAB; 4816 4817 if ( cflag&CSTOPB ) 4818 cfcr |= MOD8251_STOP2; 4819 else 4820 cfcr |= MOD8251_STOP1; 4821 4822 if ( count & 0x10000 ) 4823 cfcr |= MOD8251_CLKX1; 4824 else 4825 cfcr |= MOD8251_CLKX16; 4826 4827 if (epson_machine_id != 0x20) { /* XXX */ 4828 int tmp; 4829 while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP)) 4830 ; 4831 } 4832 /* set baud rate from ospeed */ 4833 pc98_set_baud_rate( com, count ); 4834 4835 if ( cfcr != pc98_i8251_get_mod(com) ) 4836 pc98_i8251_reset(com, cfcr, pc98_i8251_get_cmd(com) ); 4837 4838 pc98_enable_i8251_interrupt( com, previnterrupt ); 4839} 4840 4841static int 4842pc98_ttspeedtab(struct com_s *com, int speed, u_int *divisor) 4843{ 4844 int if_type, effect_sp, count = -1, mod; 4845 4846 if_type = com->pc98_if_type & 0x0f; 4847 4848 switch (com->pc98_if_type) { 4849 case COM_IF_INTERNAL: 4850 if (PC98SIO_baud_rate_port(if_type) != -1) { 4851 count = ttspeedtab(speed, if_8251_type[if_type].speedtab); 4852 if (count > 0) { 4853 count |= COM1_EXT_CLOCK; 4854 break; 4855 } 4856 } 4857 4858 /* for *1CLK asynchronous! mode, TEFUTEFU */ 4859 mod = (sysclock == 5) ? 2457600 : 1996800; 4860 effect_sp = ttspeedtab( speed, pc98speedtab ); 4861 if ( effect_sp < 0 ) /* XXX */ 4862 effect_sp = ttspeedtab( (speed - 1), pc98speedtab ); 4863 if ( effect_sp <= 0 ) 4864 return effect_sp; 4865 if ( effect_sp == speed ) 4866 mod /= 16; 4867 if ( mod % effect_sp ) 4868 return(-1); 4869 count = mod / effect_sp; 4870 if ( count > 65535 ) 4871 return(-1); 4872 if ( effect_sp != speed ) 4873 count |= 0x10000; 4874 break; 4875 case COM_IF_PC9861K_1: 4876 case COM_IF_PC9861K_2: 4877 count = 1; 4878 break; 4879 case COM_IF_IND_SS_1: 4880 case COM_IF_IND_SS_2: 4881 case COM_IF_PIO9032B_1: 4882 case COM_IF_PIO9032B_2: 4883 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 4884 break; 4885 case COM_IF_B98_01_1: 4886 case COM_IF_B98_01_2: 4887 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 4888#ifdef B98_01_OLD 4889 if (count == 0 || count == 1) { 4890 count += 4; 4891 count |= 0x20000; /* x1 mode for 76800 and 153600 */ 4892 } 4893#endif 4894 break; 4895 } 4896 4897 if (count < 0) 4898 return count; 4899 4900 *divisor = (u_int) count; 4901 return 0; 4902} 4903 4904static void 4905pc98_set_baud_rate( struct com_s *com, u_int count ) 4906{ 4907 int if_type, io, s; 4908 4909 if_type = com->pc98_if_type & 0x0f; 4910 io = rman_get_start(com->ioportres) & 0xff00; 4911 4912 switch (com->pc98_if_type) { 4913 case COM_IF_INTERNAL: 4914 if (PC98SIO_baud_rate_port(if_type) != -1) { 4915 if (count & COM1_EXT_CLOCK) { 4916 outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff); 4917 break; 4918 } else { 4919 outb((Port_t)PC98SIO_baud_rate_port(if_type), 0x09); 4920 } 4921 } 4922 4923 if (count == 0) 4924 return; 4925 4926 /* set i8253 */ 4927 s = splclock(); 4928 if (count != 3) 4929 outb( 0x77, 0xb6 ); 4930 else 4931 outb( 0x77, 0xb4 ); 4932 outb( 0x5f, 0); 4933 outb( 0x75, count & 0xff ); 4934 outb( 0x5f, 0); 4935 outb( 0x75, (count >> 8) & 0xff ); 4936 splx(s); 4937 break; 4938 case COM_IF_IND_SS_1: 4939 case COM_IF_IND_SS_2: 4940 outb(io | PC98SIO_intr_ctrl_port(if_type), 0); 4941 outb(io | PC98SIO_baud_rate_port(if_type), 0); 4942 outb(io | PC98SIO_baud_rate_port(if_type), 0xc0); 4943 outb(io | PC98SIO_baud_rate_port(if_type), (count >> 8) | 0x80); 4944 outb(io | PC98SIO_baud_rate_port(if_type), count & 0xff); 4945 break; 4946 case COM_IF_PIO9032B_1: 4947 case COM_IF_PIO9032B_2: 4948 outb(io | PC98SIO_baud_rate_port(if_type), count); 4949 break; 4950 case COM_IF_B98_01_1: 4951 case COM_IF_B98_01_2: 4952 outb(io | PC98SIO_baud_rate_port(if_type), count & 0x0f); 4953#ifdef B98_01_OLD 4954 /* 4955 * Some old B98_01 board should be controlled 4956 * in different way, but this hasn't been tested yet. 4957 */ 4958 outb(io | PC98SIO_func_port(if_type), 4959 (count & 0x20000) ? 0xf0 : 0xf2); 4960#endif 4961 break; 4962 } 4963} 4964static int 4965pc98_check_if_type(device_t dev, struct siodev *iod) 4966{ 4967 int irr, io, if_type, tmp; 4968 static short irq_tab[2][8] = { 4969 { 3, 5, 6, 9, 10, 12, 13, -1}, 4970 { 3, 10, 12, 13, 5, 6, 9, -1} 4971 }; 4972 4973 if_type = iod->if_type & 0x0f; 4974 iod->irq = 0; 4975 io = isa_get_port(dev) & 0xff00; 4976 4977 if (IS_8251(iod->if_type)) { 4978 if (PC98SIO_func_port(if_type) != -1) { 4979 outb(io | PC98SIO_func_port(if_type), 0xf2); 4980 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab); 4981 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1) 4982 outb(io | PC98SIO_baud_rate_port(if_type), tmp); 4983 } 4984 4985 iod->cmd = io | PC98SIO_cmd_port(if_type); 4986 iod->sts = io | PC98SIO_sts_port(if_type); 4987 iod->mod = io | PC98SIO_in_modem_port(if_type); 4988 iod->ctrl = io | PC98SIO_intr_ctrl_port(if_type); 4989 4990 if (iod->if_type == COM_IF_INTERNAL) { 4991 iod->irq = 4; 4992 4993 if (pc98_check_8251vfast()) { 4994 PC98SIO_baud_rate_port(if_type) = I8251F_div; 4995 if_8251_type[if_type].speedtab = pc98fast_speedtab; 4996 } 4997 } else { 4998 tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask; 4999 if ((isa_get_port(dev) & 0xff) == IO_COM2) 5000 iod->irq = irq_tab[0][tmp]; 5001 else 5002 iod->irq = irq_tab[1][tmp]; 5003 } 5004 } else { 5005 irr = if_16550a_type[if_type].irr_read; 5006#ifdef COM_MULTIPORT 5007 if (!COM_ISMULTIPORT(device_get_flags(dev)) || 5008 device_get_unit(dev) == COM_MPMASTER(device_get_flags(dev))) 5009#endif 5010 if (irr != -1) { 5011 tmp = inb(io | irr); 5012 if (isa_get_port(dev) & 0x01) /* XXX depend on RSB-384 */ 5013 iod->irq = irq_tab[1][tmp >> 3]; 5014 else 5015 iod->irq = irq_tab[0][tmp & 0x07]; 5016 } 5017 } 5018 if ( iod->irq == -1 ) return -1; 5019 5020 return 0; 5021} 5022static void 5023pc98_set_ioport(struct com_s *com) 5024{ 5025 int if_type = com->pc98_if_type & 0x0f; 5026 Port_t io = rman_get_start(com->ioportres) & 0xff00; 5027 5028 pc98_check_sysclock(); 5029 com->data_port = io | PC98SIO_data_port(if_type); 5030 com->cmd_port = io | PC98SIO_cmd_port(if_type); 5031 com->sts_port = io | PC98SIO_sts_port(if_type); 5032 com->in_modem_port = io | PC98SIO_in_modem_port(if_type); 5033 com->intr_ctrl_port = io | PC98SIO_intr_ctrl_port(if_type); 5034} 5035static int 5036pc98_check_8251vfast(void) 5037{ 5038 int i; 5039 5040 outb(I8251F_div, 0x8c); 5041 DELAY(10); 5042 for (i = 0; i < 100; i++) { 5043 if ((inb(I8251F_div) & 0x80) != 0) { 5044 i = 0; 5045 break; 5046 } 5047 DELAY(1); 5048 } 5049 outb(I8251F_div, 0); 5050 DELAY(10); 5051 for (; i < 100; i++) { 5052 if ((inb(I8251F_div) & 0x80) == 0) 5053 return 1; 5054 DELAY(1); 5055 } 5056 5057 return 0; 5058} 5059static int 5060pc98_check_8251fifo(void) 5061{ 5062 u_char tmp1, tmp2; 5063 5064 tmp1 = inb(I8251F_iir); 5065 DELAY(10); 5066 tmp2 = inb(I8251F_iir); 5067 if (((tmp1 ^ tmp2) & 0x40) != 0 && ((tmp1 | tmp2) & 0x20) == 0) 5068 return 1; 5069 5070 return 0; 5071} 5072#endif /* PC98 defined */ 5073