sio.c revision 103881
1169691Skan/*- 2169691Skan * Copyright (c) 1991 The Regents of the University of California. 3169691Skan * All rights reserved. 4169691Skan * 5169691Skan * Redistribution and use in source and binary forms, with or without 6169691Skan * modification, are permitted provided that the following conditions 7169691Skan * are met: 8169691Skan * 1. Redistributions of source code must retain the above copyright 9169691Skan * notice, this list of conditions and the following disclaimer. 10169691Skan * 2. Redistributions in binary form must reproduce the above copyright 11169691Skan * notice, this list of conditions and the following disclaimer in the 12169691Skan * documentation and/or other materials provided with the distribution. 13169691Skan * 3. All advertising materials mentioning features or use of this software 14169691Skan * must display the following acknowledgement: 15169691Skan * This product includes software developed by the University of 16169691Skan * California, Berkeley and its contributors. 17169691Skan * 4. Neither the name of the University nor the names of its contributors 18169691Skan * may be used to endorse or promote products derived from this software 19169691Skan * without specific prior written permission. 20169691Skan * 21169691Skan * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22169691Skan * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23169691Skan * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24169691Skan * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25169691Skan * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26169691Skan * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27169691Skan * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28169691Skan * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29169691Skan * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30169691Skan * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31169691Skan * SUCH DAMAGE. 32169691Skan * 33169691Skan * $FreeBSD: head/sys/pc98/cbus/sio.c 103881 2002-09-24 02:35:57Z nyan $ 34169691Skan * from: @(#)com.c 7.5 (Berkeley) 5/16/91 35169691Skan * from: i386/isa sio.c,v 1.234 36169691Skan */ 37169691Skan 38169691Skan#include "opt_comconsole.h" 39169691Skan#include "opt_compat.h" 40169691Skan#include "opt_ddb.h" 41169691Skan#include "opt_sio.h" 42169691Skan 43169691Skan/* 44169691Skan * Serial driver, based on 386BSD-0.1 com driver. 45169691Skan * Mostly rewritten to use pseudo-DMA. 46169691Skan * Works for National Semiconductor NS8250-NS16550AF UARTs. 47169691Skan * COM driver, based on HP dca driver. 48169691Skan * 49169691Skan * Changes for PC-Card integration: 50169691Skan * - Added PC-Card driver table and handlers 51169691Skan */ 52169691Skan/*=============================================================== 53169691Skan * 386BSD(98),FreeBSD-1.1x(98) com driver. 54169691Skan * ----- 55169691Skan * modified for PC9801 by M.Ishii 56169691Skan * Kyoto University Microcomputer Club (KMC) 57169691Skan * Chou "TEFUTEFU" Hirotomi 58169691Skan * Kyoto Univ. the faculty of medicine 59169691Skan *=============================================================== 60169691Skan * FreeBSD-2.0.1(98) sio driver. 61169691Skan * ----- 62169691Skan * modified for pc98 Internal i8251 and MICRO CORE MC16550II 63169691Skan * T.Koike(hfc01340@niftyserve.or.jp) 64169691Skan * implement kernel device configuration 65169691Skan * aizu@orient.center.nitech.ac.jp 66169691Skan * 67169691Skan * Notes. 68169691Skan * ----- 69169691Skan * PC98 localization based on 386BSD(98) com driver. Using its PC98 local 70169691Skan * functions. 71169691Skan * This driver is under debugging,has bugs. 72169691Skan * 73169691Skan * 1) config 74169691Skan * options COM_MULTIPORT #if using MC16550II 75169691Skan * device sio0 at nec? port 0x30 tty irq 4 #internal 76169691Skan * device sio1 at nec? port 0xd2 tty irq 5 flags 0x101 #mc1 77169691Skan * device sio2 at nec? port 0x8d2 tty flags 0x101 #mc2 78169691Skan * # ~~~~~iobase ~~multi port flag 79169691Skan * # ~ master device is sio1 80169691Skan * 2) device 81169691Skan * cd /dev; MAKEDEV ttyd0 ttyd1 .. 82169691Skan * 3) /etc/rc.serial 83169691Skan * 57600bps is too fast for sio0(internal8251) 84169691Skan * my ex. 85169691Skan * #set default speed 9600 86169691Skan * modem() 87169691Skan * : 88169691Skan * stty </dev/ttyid$i crtscts 9600 89169691Skan * : # ~~~~ default speed(can change after init.) 90169691Skan * modem 0 1 2 91169691Skan * 4) COMCONSOLE 92169691Skan * not changed. 93169691Skan * 5) PC9861K,PIO9032B,B98_01 94169691Skan * not tested. 95169691Skan */ 96169691Skan/* 97169691Skan * modified for AIWA B98-01 98169691Skan * by T.Hatanou <hatanou@yasuda.comm.waseda.ac.jp> last update: 15 Sep.1995 99169691Skan * 100169691Skan * How to configure... 101169691Skan * # options COM_MULTIPORT # support for MICROCORE MC16550II 102169691Skan * ... comment-out this line, which will conflict with B98_01. 103169691Skan * options "B98_01" # support for AIWA B98-01 104169691Skan * device sio1 at nec? port 0x00d1 tty irq ? 105169691Skan * device sio2 at nec? port 0x00d5 tty irq ? 106169691Skan * ... you can leave these lines `irq ?', irq will be autodetected. 107169691Skan */ 108169691Skan/* 109169691Skan * Modified by Y.Takahashi of Kogakuin University. 110169691Skan */ 111169691Skan/* 112169691Skan * modified for 8251(FIFO) by Seigo TANIMURA <tanimura@FreeBSD.org> 113169691Skan */ 114169691Skan 115169691Skan#include <sys/param.h> 116169691Skan#include <sys/systm.h> 117169691Skan#include <sys/bus.h> 118169691Skan#include <sys/conf.h> 119169691Skan#include <sys/dkstat.h> 120169691Skan#include <sys/fcntl.h> 121169691Skan#include <sys/interrupt.h> 122169691Skan#include <sys/kernel.h> 123169691Skan#include <sys/lock.h> 124169691Skan#include <sys/malloc.h> 125169691Skan#include <sys/module.h> 126169691Skan#include <sys/mutex.h> 127169691Skan#include <sys/proc.h> 128169691Skan#include <sys/reboot.h> 129169691Skan#include <sys/sysctl.h> 130169691Skan#include <sys/syslog.h> 131169691Skan#include <sys/tty.h> 132169691Skan#include <machine/bus.h> 133169691Skan#include <sys/rman.h> 134169691Skan#include <sys/timepps.h> 135169691Skan#include <sys/uio.h> 136169691Skan 137169691Skan#include <isa/isavar.h> 138169691Skan 139169691Skan#include <machine/limits.h> 140169691Skan#include <machine/resource.h> 141169691Skan 142169691Skan#include <dev/sio/sioreg.h> 143169691Skan#include <dev/sio/siovar.h> 144169691Skan 145169691Skan#ifdef PC98 146169691Skan#include <pc98/pc98/pc98.h> 147169691Skan#include <pc98/pc98/pc98_machdep.h> 148169691Skan#endif 149169691Skan 150169691Skan#ifdef COM_ESP 151169691Skan#include <dev/ic/esp.h> 152169691Skan#endif 153169691Skan#include <dev/ic/ns16550.h> 154169691Skan#ifdef PC98 155169691Skan#include <dev/ic/i8251.h> 156169691Skan#include <dev/ic/rsa.h> 157169691Skan#endif 158169691Skan 159169691Skan#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */ 160169691Skan 161169691Skan#define CALLOUT_MASK 0x80 162169691Skan#define CONTROL_MASK 0x60 163169691Skan#define CONTROL_INIT_STATE 0x20 164169691Skan#define CONTROL_LOCK_STATE 0x40 165169691Skan#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev))) 166169691Skan#define MINOR_TO_UNIT(mynor) ((((mynor) & ~0xffffU) >> (8 + 3)) \ 167169691Skan | ((mynor) & 0x1f)) 168169691Skan#define UNIT_TO_MINOR(unit) ((((unit) & ~0x1fU) << (8 + 3)) \ 169169691Skan | ((unit) & 0x1f)) 170169691Skan 171169691Skan#ifdef COM_MULTIPORT 172169691Skan/* checks in flags for multiport and which is multiport "master chip" 173169691Skan * for a given card 174169691Skan */ 175169691Skan#define COM_ISMULTIPORT(flags) ((flags) & 0x01) 176169691Skan#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff) 177169691Skan#define COM_NOTAST4(flags) ((flags) & 0x04) 178169691Skan#endif /* COM_MULTIPORT */ 179169691Skan 180169691Skan#define COM_CONSOLE(flags) ((flags) & 0x10) 181169691Skan#define COM_FORCECONSOLE(flags) ((flags) & 0x20) 182169691Skan#define COM_LLCONSOLE(flags) ((flags) & 0x40) 183169691Skan#define COM_DEBUGGER(flags) ((flags) & 0x80) 184169691Skan#define COM_LOSESOUTINTS(flags) ((flags) & 0x08) 185169691Skan#define COM_NOFIFO(flags) ((flags) & 0x02) 186169691Skan#define COM_ST16650A(flags) ((flags) & 0x20000) 187169691Skan#define COM_C_NOPROBE (0x40000) 188169691Skan#define COM_NOPROBE(flags) ((flags) & COM_C_NOPROBE) 189169691Skan#define COM_C_IIR_TXRDYBUG (0x80000) 190169691Skan#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG) 191169691Skan#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24) 192169691Skan 193169691Skan#define sio_getreg(com, off) \ 194169691Skan (bus_space_read_1((com)->bst, (com)->bsh, (off))) 195169691Skan#define sio_setreg(com, off, value) \ 196169691Skan (bus_space_write_1((com)->bst, (com)->bsh, (off), (value))) 197169691Skan 198169691Skan/* 199169691Skan * com state bits. 200169691Skan * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher 201169691Skan * than the other bits so that they can be tested as a group without masking 202169691Skan * off the low bits. 203169691Skan * 204169691Skan * The following com and tty flags correspond closely: 205169691Skan * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and 206169691Skan * comstop()) 207169691Skan * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart()) 208169691Skan * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam()) 209169691Skan * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam()) 210169691Skan * TS_FLUSH is not used. 211169691Skan * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON. 212169691Skan * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state). 213169691Skan */ 214169691Skan#define CS_BUSY 0x80 /* output in progress */ 215169691Skan#define CS_TTGO 0x40 /* output not stopped by XOFF */ 216169691Skan#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */ 217169691Skan#define CS_CHECKMSR 1 /* check of MSR scheduled */ 218169691Skan#define CS_CTS_OFLOW 2 /* use CTS output flow control */ 219169691Skan#define CS_DTR_OFF 0x10 /* DTR held off */ 220169691Skan#define CS_ODONE 4 /* output completed */ 221169691Skan#define CS_RTS_IFLOW 8 /* use RTS input flow control */ 222169691Skan#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */ 223169691Skan 224169691Skanstatic char const * const error_desc[] = { 225169691Skan#define CE_OVERRUN 0 226169691Skan "silo overflow", 227169691Skan#define CE_INTERRUPT_BUF_OVERFLOW 1 228169691Skan "interrupt-level buffer overflow", 229169691Skan#define CE_TTY_BUF_OVERFLOW 2 230169691Skan "tty-level buffer overflow", 231169691Skan}; 232169691Skan 233169691Skan#define CE_NTYPES 3 234169691Skan#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum]) 235169691Skan 236169691Skan/* types. XXX - should be elsewhere */ 237169691Skantypedef u_int Port_t; /* hardware port */ 238169691Skantypedef u_char bool_t; /* boolean */ 239169691Skan 240169691Skan/* queue of linear buffers */ 241169691Skanstruct lbq { 242169691Skan u_char *l_head; /* next char to process */ 243169691Skan u_char *l_tail; /* one past the last char to process */ 244169691Skan struct lbq *l_next; /* next in queue */ 245169691Skan bool_t l_queued; /* nonzero if queued */ 246169691Skan}; 247169691Skan 248169691Skan/* com device structure */ 249169691Skanstruct com_s { 250169691Skan u_int flags; /* Copy isa device flags */ 251169691Skan u_char state; /* miscellaneous flag bits */ 252169691Skan bool_t active_out; /* nonzero if the callout device is open */ 253169691Skan u_char cfcr_image; /* copy of value written to CFCR */ 254169691Skan#ifdef COM_ESP 255169691Skan bool_t esp; /* is this unit a hayes esp board? */ 256169691Skan#endif 257169691Skan u_char extra_state; /* more flag bits, separate for order trick */ 258169691Skan u_char fifo_image; /* copy of value written to FIFO */ 259169691Skan bool_t hasfifo; /* nonzero for 16550 UARTs */ 260169691Skan bool_t st16650a; /* Is a Startech 16650A or RTS/CTS compat */ 261169691Skan bool_t loses_outints; /* nonzero if device loses output interrupts */ 262169691Skan u_char mcr_image; /* copy of value written to MCR */ 263169691Skan#ifdef COM_MULTIPORT 264169691Skan bool_t multiport; /* is this unit part of a multiport device? */ 265169691Skan#endif /* COM_MULTIPORT */ 266169691Skan bool_t no_irq; /* nonzero if irq is not attached */ 267169691Skan bool_t gone; /* hardware disappeared */ 268169691Skan bool_t poll; /* nonzero if polling is required */ 269169691Skan bool_t poll_output; /* nonzero if polling for output is required */ 270169691Skan int unit; /* unit number */ 271169691Skan int dtr_wait; /* time to hold DTR down on close (* 1/hz) */ 272169691Skan u_int tx_fifo_size; 273169691Skan u_int wopeners; /* # processes waiting for DCD in open() */ 274169691Skan 275169691Skan /* 276169691Skan * The high level of the driver never reads status registers directly 277169691Skan * because there would be too many side effects to handle conveniently. 278169691Skan * Instead, it reads copies of the registers stored here by the 279169691Skan * interrupt handler. 280169691Skan */ 281169691Skan u_char last_modem_status; /* last MSR read by intr handler */ 282169691Skan u_char prev_modem_status; /* last MSR handled by high level */ 283169691Skan 284169691Skan u_char hotchar; /* ldisc-specific char to be handled ASAP */ 285169691Skan u_char *ibuf; /* start of input buffer */ 286169691Skan u_char *ibufend; /* end of input buffer */ 287169691Skan u_char *ibufold; /* old input buffer, to be freed */ 288169691Skan u_char *ihighwater; /* threshold in input buffer */ 289169691Skan u_char *iptr; /* next free spot in input buffer */ 290169691Skan int ibufsize; /* size of ibuf (not include error bytes) */ 291169691Skan int ierroff; /* offset of error bytes in ibuf */ 292169691Skan 293169691Skan struct lbq obufq; /* head of queue of output buffers */ 294169691Skan struct lbq obufs[2]; /* output buffers */ 295169691Skan 296169691Skan bus_space_tag_t bst; 297169691Skan bus_space_handle_t bsh; 298169691Skan 299169691Skan#ifdef PC98 300169691Skan Port_t cmd_port; 301169691Skan Port_t sts_port; 302169691Skan Port_t in_modem_port; 303169691Skan Port_t intr_ctrl_port; 304169691Skan Port_t rsabase; /* iobase address of a I/O-DATA RSA board */ 305169691Skan int intr_enable; 306169691Skan int pc98_prev_modem_status; 307169691Skan int pc98_modem_delta; 308169691Skan int modem_car_chg_timer; 309169691Skan int pc98_prev_siocmd; 310169691Skan int pc98_prev_siomod; 311169691Skan int modem_checking; 312169691Skan int pc98_if_type; 313169691Skan 314169691Skan bool_t pc98_8251fifo; 315169691Skan bool_t pc98_8251fifo_enable; 316169691Skan#endif /* PC98 */ 317169691Skan Port_t data_port; /* i/o ports */ 318169691Skan#ifdef COM_ESP 319169691Skan Port_t esp_port; 320169691Skan#endif 321169691Skan Port_t int_id_port; 322169691Skan Port_t modem_ctl_port; 323169691Skan Port_t line_status_port; 324169691Skan Port_t modem_status_port; 325169691Skan Port_t intr_ctl_port; /* Ports of IIR register */ 326169691Skan 327169691Skan struct tty *tp; /* cross reference */ 328169691Skan 329169691Skan /* Initial state. */ 330169691Skan struct termios it_in; /* should be in struct tty */ 331169691Skan struct termios it_out; 332169691Skan 333169691Skan /* Lock state. */ 334169691Skan struct termios lt_in; /* should be in struct tty */ 335169691Skan struct termios lt_out; 336169691Skan 337169691Skan bool_t do_timestamp; 338169691Skan bool_t do_dcd_timestamp; 339169691Skan struct timeval timestamp; 340169691Skan struct timeval dcd_timestamp; 341169691Skan struct pps_state pps; 342169691Skan 343169691Skan u_long bytes_in; /* statistics */ 344169691Skan u_long bytes_out; 345169691Skan u_int delta_error_counts[CE_NTYPES]; 346169691Skan u_long error_counts[CE_NTYPES]; 347169691Skan 348169691Skan u_long rclk; 349169691Skan 350169691Skan struct resource *irqres; 351169691Skan struct resource *ioportres; 352169691Skan void *cookie; 353169691Skan dev_t devs[6]; 354169691Skan 355169691Skan /* 356169691Skan * Data area for output buffers. Someday we should build the output 357169691Skan * buffer queue without copying data. 358169691Skan */ 359169691Skan#ifdef PC98 360169691Skan int obufsize; 361169691Skan u_char *obuf1; 362169691Skan u_char *obuf2; 363169691Skan#else 364169691Skan u_char obuf1[256]; 365169691Skan u_char obuf2[256]; 366169691Skan#endif 367169691Skan}; 368169691Skan 369169691Skan#ifdef COM_ESP 370169691Skanstatic int espattach(struct com_s *com, Port_t esp_port); 371169691Skan#endif 372169691Skan 373169691Skanstatic timeout_t siobusycheck; 374169691Skanstatic u_int siodivisor(u_long rclk, speed_t speed); 375169691Skanstatic timeout_t siodtrwakeup; 376169691Skanstatic void comhardclose(struct com_s *com); 377169691Skanstatic void sioinput(struct com_s *com); 378169691Skanstatic void siointr1(struct com_s *com); 379169691Skanstatic void siointr(void *arg); 380169691Skanstatic int commctl(struct com_s *com, int bits, int how); 381169691Skanstatic int comparam(struct tty *tp, struct termios *t); 382169691Skanstatic void siopoll(void *); 383169691Skanstatic void siosettimeout(void); 384169691Skanstatic int siosetwater(struct com_s *com, speed_t speed); 385169691Skanstatic void comstart(struct tty *tp); 386169691Skanstatic void comstop(struct tty *tp, int rw); 387169691Skanstatic timeout_t comwakeup; 388169691Skanstatic void disc_optim(struct tty *tp, struct termios *t, 389169691Skan struct com_s *com); 390169691Skan 391169691Skanchar sio_driver_name[] = "sio"; 392169691Skanstatic struct mtx sio_lock; 393169691Skanstatic int sio_inited; 394169691Skan 395169691Skan/* table and macro for fast conversion from a unit number to its com struct */ 396169691Skandevclass_t sio_devclass; 397169691Skan#define com_addr(unit) ((struct com_s *) \ 398169691Skan devclass_get_softc(sio_devclass, unit)) /* XXX */ 399169691Skan 400169691Skanstatic d_open_t sioopen; 401169691Skanstatic d_close_t sioclose; 402169691Skanstatic d_read_t sioread; 403169691Skanstatic d_write_t siowrite; 404169691Skanstatic d_ioctl_t sioioctl; 405169691Skan 406169691Skan#define CDEV_MAJOR 28 407169691Skanstatic struct cdevsw sio_cdevsw = { 408169691Skan /* open */ sioopen, 409169691Skan /* close */ sioclose, 410169691Skan /* read */ sioread, 411169691Skan /* write */ siowrite, 412169691Skan /* ioctl */ sioioctl, 413169691Skan /* poll */ ttypoll, 414169691Skan /* mmap */ nommap, 415169691Skan /* strategy */ nostrategy, 416169691Skan /* name */ sio_driver_name, 417169691Skan /* maj */ CDEV_MAJOR, 418169691Skan /* dump */ nodump, 419169691Skan /* psize */ nopsize, 420169691Skan /* flags */ D_TTY | D_KQFILTER, 421169691Skan /* kqfilter */ ttykqfilter, 422169691Skan}; 423169691Skan 424169691Skanint comconsole = -1; 425169691Skanstatic volatile speed_t comdefaultrate = CONSPEED; 426169691Skanstatic u_long comdefaultrclk = DEFAULT_RCLK; 427169691SkanSYSCTL_ULONG(_machdep, OID_AUTO, conrclk, CTLFLAG_RW, &comdefaultrclk, 0, ""); 428169691Skanstatic speed_t gdbdefaultrate = GDBSPEED; 429169691SkanSYSCTL_UINT(_machdep, OID_AUTO, gdbspeed, CTLFLAG_RW, 430169691Skan &gdbdefaultrate, GDBSPEED, ""); 431169691Skanstatic u_int com_events; /* input chars + weighted output completions */ 432169691Skanstatic Port_t siocniobase; 433169691Skanstatic int siocnunit = -1; 434169691Skanstatic Port_t siogdbiobase; 435169691Skanstatic int siogdbunit = -1; 436169691Skanstatic void *sio_slow_ih; 437169691Skanstatic void *sio_fast_ih; 438169691Skanstatic int sio_timeout; 439169691Skanstatic int sio_timeouts_until_log; 440169691Skanstatic struct callout_handle sio_timeout_handle 441169691Skan = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle); 442169691Skanstatic int sio_numunits; 443169691Skan 444169691Skan#ifdef PC98 445169691Skanstruct siodev { 446169691Skan short if_type; 447169691Skan short irq; 448169691Skan Port_t cmd, sts, ctrl, mod; 449169691Skan}; 450169691Skanstatic int sysclock; 451169691Skan 452169691Skan#define COM_INT_DISABLE {int previpri; previpri=spltty(); 453169691Skan#define COM_INT_ENABLE splx(previpri);} 454169691Skan#define IEN_TxFLAG IEN_Tx 455169691Skan 456169691Skan#define COM_CARRIER_DETECT_EMULATE 0 457169691Skan#define PC98_CHECK_MODEM_INTERVAL (hz/10) 458169691Skan#define DCD_OFF_TOLERANCE 2 459169691Skan#define DCD_ON_RECOGNITION 2 460169691Skan#define IS_8251(if_type) (!(if_type & 0x10)) 461169691Skan#define COM1_EXT_CLOCK 0x40000 462169691Skan 463169691Skanstatic void commint(dev_t dev); 464169691Skanstatic void com_tiocm_set(struct com_s *com, int msr); 465169691Skanstatic void com_tiocm_bis(struct com_s *com, int msr); 466169691Skanstatic void com_tiocm_bic(struct com_s *com, int msr); 467169691Skanstatic int com_tiocm_get(struct com_s *com); 468169691Skanstatic int com_tiocm_get_delta(struct com_s *com); 469169691Skanstatic void pc98_msrint_start(dev_t dev); 470169691Skanstatic void com_cflag_and_speed_set(struct com_s *com, int cflag, int speed); 471169691Skanstatic int pc98_ttspeedtab(struct com_s *com, int speed, u_int *divisor); 472169691Skanstatic int pc98_get_modem_status(struct com_s *com); 473169691Skanstatic timeout_t pc98_check_msr; 474169691Skanstatic void pc98_set_baud_rate(struct com_s *com, u_int count); 475169691Skanstatic void pc98_i8251_reset(struct com_s *com, int mode, int command); 476169691Skanstatic void pc98_disable_i8251_interrupt(struct com_s *com, int mod); 477169691Skanstatic void pc98_enable_i8251_interrupt(struct com_s *com, int mod); 478169691Skanstatic int pc98_check_i8251_interrupt(struct com_s *com); 479169691Skanstatic int pc98_i8251_get_cmd(struct com_s *com); 480169691Skanstatic int pc98_i8251_get_mod(struct com_s *com); 481169691Skanstatic void pc98_i8251_set_cmd(struct com_s *com, int x); 482169691Skanstatic void pc98_i8251_or_cmd(struct com_s *com, int x); 483169691Skanstatic void pc98_i8251_clear_cmd(struct com_s *com, int x); 484169691Skanstatic void pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x); 485169691Skanstatic int pc98_check_if_type(device_t dev, struct siodev *iod); 486169691Skanstatic int pc98_check_8251vfast(void); 487169691Skanstatic int pc98_check_8251fifo(void); 488169691Skanstatic void pc98_check_sysclock(void); 489169691Skanstatic void pc98_set_ioport(struct com_s *com); 490169691Skan 491169691Skan#define com_int_Tx_disable(com) \ 492169691Skan pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP) 493169691Skan#define com_int_Tx_enable(com) \ 494169691Skan pc98_enable_i8251_interrupt(com,IEN_TxFLAG) 495169691Skan#define com_int_Rx_disable(com) \ 496169691Skan pc98_disable_i8251_interrupt(com,IEN_Rx) 497169691Skan#define com_int_Rx_enable(com) \ 498169691Skan pc98_enable_i8251_interrupt(com,IEN_Rx) 499169691Skan#define com_int_TxRx_disable(com) \ 500169691Skan pc98_disable_i8251_interrupt(com,IEN_Tx|IEN_TxEMP|IEN_Rx) 501169691Skan#define com_int_TxRx_enable(com) \ 502169691Skan pc98_enable_i8251_interrupt(com,IEN_TxFLAG|IEN_Rx) 503169691Skan#define com_send_break_on(com) \ 504169691Skan pc98_i8251_or_cmd(com,CMD8251_SBRK) 505169691Skan#define com_send_break_off(com) \ 506169691Skan pc98_i8251_clear_cmd(com,CMD8251_SBRK) 507169691Skan 508169691Skanstatic struct speedtab pc98speedtab[] = { /* internal RS232C interface */ 509169691Skan { 0, 0, }, 510169691Skan { 50, 50, }, 511169691Skan { 75, 75, }, 512169691Skan { 150, 150, }, 513169691Skan { 200, 200, }, 514169691Skan { 300, 300, }, 515169691Skan { 600, 600, }, 516169691Skan { 1200, 1200, }, 517169691Skan { 2400, 2400, }, 518169691Skan { 4800, 4800, }, 519169691Skan { 9600, 9600, }, 520169691Skan { 19200, 19200, }, 521169691Skan { 38400, 38400, }, 522169691Skan { 51200, 51200, }, 523169691Skan { 76800, 76800, }, 524169691Skan { 20800, 20800, }, 525169691Skan { 31200, 31200, }, 526169691Skan { 41600, 41600, }, 527169691Skan { 62400, 62400, }, 528169691Skan { -1, -1 } 529169691Skan}; 530169691Skanstatic struct speedtab pc98fast_speedtab[] = { 531169691Skan { 9600, 0x80 | (DEFAULT_RCLK / (16 * (9600))), }, 532169691Skan { 19200, 0x80 | (DEFAULT_RCLK / (16 * (19200))), }, 533169691Skan { 38400, 0x80 | (DEFAULT_RCLK / (16 * (38400))), }, 534169691Skan { 57600, 0x80 | (DEFAULT_RCLK / (16 * (57600))), }, 535169691Skan { 115200, 0x80 | (DEFAULT_RCLK / (16 * (115200))), }, 536169691Skan { -1, -1 } 537169691Skan}; 538169691Skanstatic struct speedtab comspeedtab_pio9032b[] = { 539169691Skan { 300, 6, }, 540169691Skan { 600, 5, }, 541169691Skan { 1200, 4, }, 542169691Skan { 2400, 3, }, 543169691Skan { 4800, 2, }, 544169691Skan { 9600, 1, }, 545169691Skan { 19200, 0, }, 546169691Skan { 38400, 7, }, 547169691Skan { -1, -1 } 548169691Skan}; 549169691Skanstatic struct speedtab comspeedtab_b98_01[] = { 550169691Skan { 75, 11, }, 551169691Skan { 150, 10, }, 552169691Skan { 300, 9, }, 553169691Skan { 600, 8, }, 554169691Skan { 1200, 7, }, 555169691Skan { 2400, 6, }, 556169691Skan { 4800, 5, }, 557169691Skan { 9600, 4, }, 558169691Skan { 19200, 3, }, 559169691Skan { 38400, 2, }, 560169691Skan { 76800, 1, }, 561169691Skan { 153600, 0, }, 562169691Skan { -1, -1 } 563169691Skan}; 564169691Skanstatic struct speedtab comspeedtab_ind[] = { 565169691Skan { 300, 1536, }, 566169691Skan { 600, 768, }, 567169691Skan { 1200, 384, }, 568169691Skan { 2400, 192, }, 569169691Skan { 4800, 96, }, 570169691Skan { 9600, 48, }, 571169691Skan { 19200, 24, }, 572169691Skan { 38400, 12, }, 573169691Skan { 57600, 8, }, 574169691Skan { 115200, 4, }, 575169691Skan { 153600, 3, }, 576169691Skan { 230400, 2, }, 577169691Skan { 460800, 1, }, 578169691Skan { -1, -1 } 579169691Skan}; 580169691Skan 581169691Skanstruct { 582169691Skan char *name; 583169691Skan short port_table[7]; 584169691Skan short irr_mask; 585169691Skan struct speedtab *speedtab; 586169691Skan short check_irq; 587169691Skan} if_8251_type[] = { 588169691Skan /* COM_IF_INTERNAL */ 589169691Skan { " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1}, 590169691Skan -1, pc98speedtab, 1 }, 591169691Skan /* COM_IF_PC9861K_1 */ 592169691Skan { " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1}, 593169691Skan 3, NULL, 1 }, 594169691Skan /* COM_IF_PC9861K_2 */ 595169691Skan { " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1}, 596169691Skan 3, NULL, 1 }, 597169691Skan /* COM_IF_IND_SS_1 */ 598169691Skan { " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1}, 599169691Skan 3, comspeedtab_ind, 1 }, 600169691Skan /* COM_IF_IND_SS_2 */ 601169691Skan { " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1}, 602169691Skan 3, comspeedtab_ind, 1 }, 603169691Skan /* COM_IF_PIO9032B_1 */ 604169691Skan { " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1}, 605169691Skan 7, comspeedtab_pio9032b, 1 }, 606169691Skan /* COM_IF_PIO9032B_2 */ 607169691Skan { " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1}, 608169691Skan 7, comspeedtab_pio9032b, 1 }, 609169691Skan /* COM_IF_B98_01_1 */ 610169691Skan { " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3}, 611169691Skan 7, comspeedtab_b98_01, 0 }, 612169691Skan /* COM_IF_B98_01_2 */ 613169691Skan { " (B98-01)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xd5, 0xd7}, 614169691Skan 7, comspeedtab_b98_01, 0 }, 615169691Skan}; 616169691Skan#define PC98SIO_data_port(type) (if_8251_type[type].port_table[0]) 617169691Skan#define PC98SIO_cmd_port(type) (if_8251_type[type].port_table[1]) 618169691Skan#define PC98SIO_sts_port(type) (if_8251_type[type].port_table[2]) 619169691Skan#define PC98SIO_in_modem_port(type) (if_8251_type[type].port_table[3]) 620169691Skan#define PC98SIO_intr_ctrl_port(type) (if_8251_type[type].port_table[4]) 621169691Skan#define PC98SIO_baud_rate_port(type) (if_8251_type[type].port_table[5]) 622169691Skan#define PC98SIO_func_port(type) (if_8251_type[type].port_table[6]) 623169691Skan 624169691Skan#define I8251F_data 0x130 625169691Skan#define I8251F_lsr 0x132 626169691Skan#define I8251F_msr 0x134 627169691Skan#define I8251F_iir 0x136 628169691Skan#define I8251F_fcr 0x138 629169691Skan#define I8251F_div 0x13a 630169691Skan 631169691Skan 632169691Skanstatic bus_addr_t port_table_0[] = 633169691Skan {0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007}; 634169691Skanstatic bus_addr_t port_table_1[] = 635169691Skan {0x000, 0x002, 0x004, 0x006, 0x008, 0x00a, 0x00c, 0x00e}; 636169691Skanstatic bus_addr_t port_table_8[] = 637169691Skan {0x000, 0x100, 0x200, 0x300, 0x400, 0x500, 0x600, 0x700}; 638169691Skanstatic bus_addr_t port_table_rsa[] = { 639169691Skan 0x008, 0x009, 0x00a, 0x00b, 0x00c, 0x00d, 0x00e, 0x00f, 640169691Skan 0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007 641169691Skan}; 642169691Skan 643169691Skanstruct { 644169691Skan char *name; 645169691Skan short irr_read; 646169691Skan short irr_write; 647169691Skan bus_addr_t *iat; 648169691Skan bus_size_t iatsz; 649169691Skan u_long rclk; 650169691Skan} if_16550a_type[] = { 651169691Skan /* COM_IF_RSA98 */ 652169691Skan {" (RSA-98)", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 653169691Skan /* COM_IF_NS16550 */ 654169691Skan {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 655169691Skan /* COM_IF_SECOND_CCU */ 656169691Skan {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 657169691Skan /* COM_IF_MC16550II */ 658169691Skan {" (MC16550II)", -1, 0x1000, port_table_8, IO_COMSIZE, 659169691Skan DEFAULT_RCLK * 4}, 660169691Skan /* COM_IF_MCRS98 */ 661169691Skan {" (MC-RS98)", -1, 0x1000, port_table_8, IO_COMSIZE, DEFAULT_RCLK * 4}, 662169691Skan /* COM_IF_RSB3000 */ 663169691Skan {" (RSB-3000)", 0xbf, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 10}, 664169691Skan /* COM_IF_RSB384 */ 665169691Skan {" (RSB-384)", 0xbf, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 10}, 666169691Skan /* COM_IF_MODEM_CARD */ 667169691Skan {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, 668169691Skan /* COM_IF_RSA98III */ 669169691Skan {" (RSA-98III)", -1, -1, port_table_rsa, 16, DEFAULT_RCLK * 8}, 670169691Skan /* COM_IF_ESP98 */ 671169691Skan {" (ESP98)", -1, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 4}, 672169691Skan}; 673169691Skan#endif /* PC98 */ 674169691Skan 675169691Skan#ifdef COM_ESP 676169691Skan#ifdef PC98 677169691Skan 678169691Skan/* XXX configure this properly. */ 679169691Skan/* XXX quite broken for new-bus. */ 680169691Skanstatic Port_t likely_com_ports[] = { 0, 0xb0, 0xb1, 0 }; 681169691Skanstatic Port_t likely_esp_ports[] = { 0xc0d0, 0 }; 682169691Skan 683169691Skan#define ESP98_CMD1 (ESP_CMD1 * 0x100) 684169691Skan#define ESP98_CMD2 (ESP_CMD2 * 0x100) 685169691Skan#define ESP98_STATUS1 (ESP_STATUS1 * 0x100) 686169691Skan#define ESP98_STATUS2 (ESP_STATUS2 * 0x100) 687169691Skan 688169691Skan#else /* PC98 */ 689169691Skan 690169691Skan/* XXX configure this properly. */ 691169691Skanstatic Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, }; 692169691Skanstatic Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 }; 693169691Skan 694169691Skan#endif /* PC98 */ 695169691Skan#endif 696169691Skan 697169691Skan/* 698169691Skan * handle sysctl read/write requests for console speed 699169691Skan * 700169691Skan * In addition to setting comdefaultrate for I/O through /dev/console, 701169691Skan * also set the initial and lock values for the /dev/ttyXX device 702169691Skan * if there is one associated with the console. Finally, if the /dev/tty 703169691Skan * device has already been open, change the speed on the open running port 704169691Skan * itself. 705169691Skan */ 706169691Skan 707169691Skanstatic int 708169691Skansysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS) 709169691Skan{ 710169691Skan int error, s; 711169691Skan speed_t newspeed; 712169691Skan struct com_s *com; 713169691Skan struct tty *tp; 714169691Skan 715169691Skan newspeed = comdefaultrate; 716169691Skan 717169691Skan error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req); 718169691Skan if (error || !req->newptr) 719169691Skan return (error); 720169691Skan 721169691Skan comdefaultrate = newspeed; 722169691Skan 723169691Skan if (comconsole < 0) /* serial console not selected? */ 724169691Skan return (0); 725169691Skan 726169691Skan com = com_addr(comconsole); 727169691Skan if (com == NULL) 728169691Skan return (ENXIO); 729169691Skan 730169691Skan /* 731169691Skan * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX 732169691Skan * (note, the lock rates really are boolean -- if non-zero, disallow 733169691Skan * speed changes) 734169691Skan */ 735169691Skan com->it_in.c_ispeed = com->it_in.c_ospeed = 736169691Skan com->lt_in.c_ispeed = com->lt_in.c_ospeed = 737169691Skan com->it_out.c_ispeed = com->it_out.c_ospeed = 738169691Skan com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate; 739169691Skan 740169691Skan /* 741169691Skan * if we're open, change the running rate too 742169691Skan */ 743169691Skan tp = com->tp; 744169691Skan if (tp && (tp->t_state & TS_ISOPEN)) { 745169691Skan tp->t_termios.c_ispeed = 746169691Skan tp->t_termios.c_ospeed = comdefaultrate; 747169691Skan s = spltty(); 748169691Skan error = comparam(tp, &tp->t_termios); 749169691Skan splx(s); 750169691Skan } 751169691Skan return error; 752169691Skan} 753169691Skan 754169691SkanSYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW, 755169691Skan 0, 0, sysctl_machdep_comdefaultrate, "I", ""); 756169691Skan 757169691Skan/* 758169691Skan * Unload the driver and clear the table. 759169691Skan * XXX this is mostly wrong. 760169691Skan * XXX TODO: 761169691Skan * This is usually called when the card is ejected, but 762169691Skan * can be caused by a modunload of a controller driver. 763169691Skan * The idea is to reset the driver's view of the device 764169691Skan * and ensure that any driver entry points such as 765169691Skan * read and write do not hang. 766169691Skan */ 767169691Skanint 768169691Skansiodetach(dev) 769169691Skan device_t dev; 770169691Skan{ 771169691Skan struct com_s *com; 772169691Skan int i; 773169691Skan 774169691Skan com = (struct com_s *) device_get_softc(dev); 775169691Skan if (com == NULL) { 776169691Skan device_printf(dev, "NULL com in siounload\n"); 777169691Skan return (0); 778169691Skan } 779169691Skan com->gone = 1; 780169691Skan for (i = 0 ; i < 6; i++) 781169691Skan destroy_dev(com->devs[i]); 782169691Skan if (com->irqres) { 783169691Skan bus_teardown_intr(dev, com->irqres, com->cookie); 784169691Skan bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres); 785169691Skan } 786169691Skan if (com->ioportres) 787169691Skan bus_release_resource(dev, SYS_RES_IOPORT, 0, com->ioportres); 788169691Skan if (com->tp && (com->tp->t_state & TS_ISOPEN)) { 789169691Skan device_printf(dev, "still open, forcing close\n"); 790169691Skan (*linesw[com->tp->t_line].l_close)(com->tp, 0); 791169691Skan com->tp->t_gen++; 792169691Skan ttyclose(com->tp); 793169691Skan ttwakeup(com->tp); 794169691Skan ttwwakeup(com->tp); 795169691Skan } else { 796169691Skan if (com->ibuf != NULL) 797169691Skan free(com->ibuf, M_DEVBUF); 798169691Skan#ifdef PC98 799169691Skan if (com->obuf1 != NULL) 800169691Skan free(com->obuf1, M_DEVBUF); 801169691Skan#endif 802169691Skan device_set_softc(dev, NULL); 803169691Skan free(com, M_DEVBUF); 804169691Skan } 805169691Skan return (0); 806169691Skan} 807169691Skan 808169691Skanint 809169691Skansioprobe(dev, xrid, rclk, noprobe) 810169691Skan device_t dev; 811169691Skan int xrid; 812169691Skan u_long rclk; 813169691Skan int noprobe; 814169691Skan{ 815169691Skan#if 0 816169691Skan static bool_t already_init; 817169691Skan device_t xdev; 818169691Skan#endif 819169691Skan struct com_s *com; 820169691Skan u_int divisor; 821169691Skan bool_t failures[10]; 822169691Skan int fn; 823169691Skan device_t idev; 824169691Skan Port_t iobase; 825169691Skan intrmask_t irqmap[4]; 826169691Skan intrmask_t irqs; 827169691Skan u_char mcr_image; 828169691Skan int result; 829169691Skan u_long xirq; 830169691Skan u_int flags = device_get_flags(dev); 831169691Skan int rid; 832169691Skan struct resource *port; 833169691Skan#ifdef PC98 834169691Skan int tmp; 835169691Skan struct siodev iod; 836169691Skan#endif 837169691Skan 838169691Skan#ifdef PC98 839169691Skan iod.if_type = GET_IFTYPE(flags); 840169691Skan if ((iod.if_type < 0 || iod.if_type > COM_IF_END1) && 841169691Skan (iod.if_type < 0x10 || iod.if_type > COM_IF_END2)) 842169691Skan return ENXIO; 843169691Skan#endif 844169691Skan 845169691Skan rid = xrid; 846169691Skan#ifdef PC98 847169691Skan if (IS_8251(iod.if_type)) { 848169691Skan port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 849169691Skan 0, ~0, 1, RF_ACTIVE); 850169691Skan } else if (iod.if_type == COM_IF_MODEM_CARD || 851169691Skan iod.if_type == COM_IF_RSA98III || 852169691Skan isa_get_vendorid(dev)) { 853169691Skan port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 854169691Skan if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE); 855169691Skan } else { 856169691Skan port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, 857169691Skan if_16550a_type[iod.if_type & 0x0f].iat, 858169691Skan if_16550a_type[iod.if_type & 0x0f].iatsz, RF_ACTIVE); 859169691Skan } 860169691Skan#else 861169691Skan port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 862169691Skan 0, ~0, IO_COMSIZE, RF_ACTIVE); 863169691Skan#endif 864169691Skan if (!port) 865169691Skan return (ENXIO); 866169691Skan#ifdef PC98 867169691Skan if (!IS_8251(iod.if_type)) { 868169691Skan if (isa_load_resourcev(port, 869169691Skan if_16550a_type[iod.if_type & 0x0f].iat, 870169691Skan if_16550a_type[iod.if_type & 0x0f].iatsz) != 0) { 871169691Skan bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 872169691Skan return ENXIO; 873169691Skan } 874169691Skan } 875169691Skan#endif 876169691Skan 877169691Skan com = malloc(sizeof(*com), M_DEVBUF, M_NOWAIT | M_ZERO); 878169691Skan if (com == NULL) 879169691Skan return (ENOMEM); 880169691Skan device_set_softc(dev, com); 881169691Skan com->bst = rman_get_bustag(port); 882169691Skan com->bsh = rman_get_bushandle(port); 883169691Skan#ifdef PC98 884169691Skan if (!IS_8251(iod.if_type) && rclk == 0) 885169691Skan rclk = if_16550a_type[iod.if_type & 0x0f].rclk; 886169691Skan#else 887169691Skan if (rclk == 0) 888169691Skan rclk = DEFAULT_RCLK; 889169691Skan#endif 890169691Skan com->rclk = rclk; 891169691Skan 892169691Skan while (sio_inited != 2) 893169691Skan if (atomic_cmpset_int(&sio_inited, 0, 1)) { 894169691Skan mtx_init(&sio_lock, sio_driver_name, NULL, 895169691Skan (comconsole != -1) ? 896169691Skan MTX_SPIN | MTX_QUIET : MTX_SPIN); 897169691Skan atomic_store_rel_int(&sio_inited, 2); 898169691Skan } 899169691Skan 900169691Skan#if 0 901169691Skan /* 902169691Skan * XXX this is broken - when we are first called, there are no 903169691Skan * previously configured IO ports. We could hard code 904169691Skan * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse. 905169691Skan * This code has been doing nothing since the conversion since 906169691Skan * "count" is zero the first time around. 907169691Skan */ 908169691Skan if (!already_init) { 909169691Skan /* 910169691Skan * Turn off MCR_IENABLE for all likely serial ports. An unused 911169691Skan * port with its MCR_IENABLE gate open will inhibit interrupts 912169691Skan * from any used port that shares the interrupt vector. 913169691Skan * XXX the gate enable is elsewhere for some multiports. 914169691Skan */ 915169691Skan device_t *devs; 916169691Skan int count, i, xioport; 917169691Skan#ifdef PC98 918169691Skan int xiftype; 919169691Skan#endif 920169691Skan 921169691Skan devclass_get_devices(sio_devclass, &devs, &count); 922169691Skan#ifdef PC98 923169691Skan for (i = 0; i < count; i++) { 924169691Skan xdev = devs[i]; 925169691Skan xioport = bus_get_resource_start(xdev, SYS_RES_IOPORT, 0); 926169691Skan xiftype = GET_IFTYPE(device_get_flags(xdev)); 927169691Skan if (device_is_enabled(xdev) && xioport > 0) { 928169691Skan if (IS_8251(xiftype)) 929169691Skan outb((xioport & 0xff00) | PC98SIO_cmd_port(xiftype & 0x0f), 0xf2); 930169691Skan else 931169691Skan outb(xioport + if_16550a_type[xiftype & 0x0f].iat[com_mcr], 0); 932169691Skan } 933169691Skan } 934169691Skan#else 935169691Skan for (i = 0; i < count; i++) { 936169691Skan xdev = devs[i]; 937169691Skan if (device_is_enabled(xdev) && 938169691Skan bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport, 939169691Skan NULL) == 0) 940169691Skan outb(xioport + com_mcr, 0); 941169691Skan } 942169691Skan#endif 943169691Skan free(devs, M_TEMP); 944169691Skan already_init = TRUE; 945169691Skan } 946169691Skan#endif 947169691Skan 948169691Skan if (COM_LLCONSOLE(flags)) { 949169691Skan printf("sio%d: reserved for low-level i/o\n", 950169691Skan device_get_unit(dev)); 951169691Skan bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 952169691Skan device_set_softc(dev, NULL); 953169691Skan free(com, M_DEVBUF); 954169691Skan return (ENXIO); 955169691Skan } 956169691Skan 957169691Skan#ifdef PC98 958169691Skan DELAY(10); 959169691Skan 960169691Skan /* 961169691Skan * If the port is i8251 UART (internal, B98_01) 962169691Skan */ 963169691Skan if (pc98_check_if_type(dev, &iod) == -1) { 964169691Skan bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 965169691Skan device_set_softc(dev, NULL); 966169691Skan free(com, M_DEVBUF); 967169691Skan return (ENXIO); 968169691Skan } 969169691Skan if (iod.irq > 0) 970169691Skan bus_set_resource(dev, SYS_RES_IRQ, 0, iod.irq, 1); 971169691Skan if (IS_8251(iod.if_type)) { 972169691Skan outb(iod.cmd, 0); 973169691Skan DELAY(10); 974169691Skan outb(iod.cmd, 0); 975169691Skan DELAY(10); 976169691Skan outb(iod.cmd, 0); 977169691Skan DELAY(10); 978169691Skan outb(iod.cmd, CMD8251_RESET); 979169691Skan DELAY(1000); /* for a while...*/ 980169691Skan outb(iod.cmd, 0xf2); /* MODE (dummy) */ 981169691Skan DELAY(10); 982169691Skan outb(iod.cmd, 0x01); /* CMD (dummy) */ 983169691Skan DELAY(1000); /* for a while...*/ 984169691Skan if (( inb(iod.sts) & STS8251_TxEMP ) == 0 ) { 985169691Skan result = (ENXIO); 986169691Skan } 987169691Skan if (if_8251_type[iod.if_type & 0x0f].check_irq) { 988169691Skan COM_INT_DISABLE 989169691Skan tmp = ( inb( iod.ctrl ) & ~(IEN_Rx|IEN_TxEMP|IEN_Tx)); 990169691Skan outb( iod.ctrl, tmp|IEN_TxEMP ); 991169691Skan DELAY(10); 992169691Skan result = isa_irq_pending() ? 0 : ENXIO; 993169691Skan outb( iod.ctrl, tmp ); 994169691Skan COM_INT_ENABLE 995169691Skan } else { 996169691Skan /* 997169691Skan * B98_01 doesn't activate TxEMP interrupt line 998169691Skan * when being reset, so we can't check irq pending. 999169691Skan */ 1000169691Skan result = 0; 1001169691Skan } 1002169691Skan if (epson_machine_id==0x20) { /* XXX */ 1003169691Skan result = 0; 1004169691Skan } 1005169691Skan bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1006169691Skan if (result) { 1007169691Skan device_set_softc(dev, NULL); 1008169691Skan free(com, M_DEVBUF); 1009169691Skan } 1010169691Skan return result; 1011169691Skan } 1012169691Skan#endif /* PC98 */ 1013169691Skan /* 1014169691Skan * If the device is on a multiport card and has an AST/4 1015169691Skan * compatible interrupt control register, initialize this 1016169691Skan * register and prepare to leave MCR_IENABLE clear in the mcr. 1017169691Skan * Otherwise, prepare to set MCR_IENABLE in the mcr. 1018169691Skan * Point idev to the device struct giving the correct id_irq. 1019169691Skan * This is the struct for the master device if there is one. 1020169691Skan */ 1021169691Skan idev = dev; 1022169691Skan mcr_image = MCR_IENABLE; 1023169691Skan#ifdef COM_MULTIPORT 1024169691Skan if (COM_ISMULTIPORT(flags)) { 1025169691Skan#ifndef PC98 1026169691Skan Port_t xiobase; 1027169691Skan u_long io; 1028169691Skan#endif 1029169691Skan 1030169691Skan idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags)); 1031169691Skan if (idev == NULL) { 1032169691Skan printf("sio%d: master device %d not configured\n", 1033169691Skan device_get_unit(dev), COM_MPMASTER(flags)); 1034169691Skan idev = dev; 1035169691Skan } 1036169691Skan#ifndef PC98 1037169691Skan if (!COM_NOTAST4(flags)) { 1038169691Skan if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io, 1039169691Skan NULL) == 0) { 1040169691Skan xiobase = io; 1041169691Skan if (bus_get_resource(idev, SYS_RES_IRQ, 0, 1042169691Skan NULL, NULL) == 0) 1043169691Skan outb(xiobase + com_scr, 0x80); 1044169691Skan else 1045169691Skan outb(xiobase + com_scr, 0); 1046169691Skan } 1047169691Skan mcr_image = 0; 1048169691Skan } 1049169691Skan#endif 1050169691Skan } 1051169691Skan#endif /* COM_MULTIPORT */ 1052169691Skan if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0) 1053169691Skan mcr_image = 0; 1054169691Skan 1055169691Skan bzero(failures, sizeof failures); 1056169691Skan iobase = rman_get_start(port); 1057169691Skan 1058169691Skan#ifdef PC98 1059169691Skan if (iod.if_type == COM_IF_RSA98III) { 1060169691Skan mcr_image = 0; 1061169691Skan 1062169691Skan outb(iobase + rsa_msr, 0x04); 1063169691Skan outb(iobase + rsa_frr, 0x00); 1064169691Skan if ((inb(iobase + rsa_srr) & 0x36) != 0x36) { 1065169691Skan bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1066169691Skan device_set_softc(dev, NULL); 1067169691Skan free(com, M_DEVBUF); 1068169691Skan return (ENXIO); 1069169691Skan } 1070169691Skan outb(iobase + rsa_ier, 0x00); 1071169691Skan outb(iobase + rsa_frr, 0x00); 1072169691Skan outb(iobase + rsa_tivsr, 0x00); 1073169691Skan outb(iobase + rsa_tcr, 0x00); 1074169691Skan } 1075169691Skan 1076169691Skan tmp = if_16550a_type[iod.if_type & 0x0f].irr_write; 1077169691Skan if (tmp != -1) { 1078169691Skan /* MC16550II */ 1079169691Skan int irqout; 1080169691Skan switch (isa_get_irq(idev)) { 1081169691Skan case 3: irqout = 4; break; 1082169691Skan case 5: irqout = 5; break; 1083169691Skan case 6: irqout = 6; break; 1084169691Skan case 12: irqout = 7; break; 1085169691Skan default: 1086169691Skan printf("sio%d: irq configuration error\n", 1087169691Skan device_get_unit(dev)); 1088169691Skan bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1089169691Skan device_set_softc(dev, NULL); 1090169691Skan free(com, M_DEVBUF); 1091169691Skan return (ENXIO); 1092169691Skan } 1093169691Skan outb((iobase & 0x00ff) | tmp, irqout); 1094169691Skan } 1095169691Skan#endif 1096169691Skan 1097169691Skan /* 1098169691Skan * We don't want to get actual interrupts, just masked ones. 1099169691Skan * Interrupts from this line should already be masked in the ICU, 1100169691Skan * but mask them in the processor as well in case there are some 1101169691Skan * (misconfigured) shared interrupts. 1102169691Skan */ 1103169691Skan mtx_lock_spin(&sio_lock); 1104169691Skan/* EXTRA DELAY? */ 1105169691Skan 1106169691Skan /* 1107169691Skan * Initialize the speed and the word size and wait long enough to 1108169691Skan * drain the maximum of 16 bytes of junk in device output queues. 1109169691Skan * The speed is undefined after a master reset and must be set 1110169691Skan * before relying on anything related to output. There may be 1111169691Skan * junk after a (very fast) soft reboot and (apparently) after 1112169691Skan * master reset. 1113169691Skan * XXX what about the UART bug avoided by waiting in comparam()? 1114169691Skan * We don't want to to wait long enough to drain at 2 bps. 1115169691Skan */ 1116169691Skan if (iobase == siocniobase) 1117169691Skan DELAY((16 + 1) * 1000000 / (comdefaultrate / 10)); 1118169691Skan else { 1119169691Skan sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS); 1120169691Skan divisor = siodivisor(rclk, SIO_TEST_SPEED); 1121169691Skan sio_setreg(com, com_dlbl, divisor & 0xff); 1122169691Skan sio_setreg(com, com_dlbh, divisor >> 8); 1123169691Skan sio_setreg(com, com_cfcr, CFCR_8BITS); 1124169691Skan DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10)); 1125169691Skan } 1126169691Skan 1127169691Skan /* 1128169691Skan * Enable the interrupt gate and disable device interupts. This 1129169691Skan * should leave the device driving the interrupt line low and 1130169691Skan * guarantee an edge trigger if an interrupt can be generated. 1131169691Skan */ 1132169691Skan/* EXTRA DELAY? */ 1133169691Skan sio_setreg(com, com_mcr, mcr_image); 1134169691Skan sio_setreg(com, com_ier, 0); 1135169691Skan DELAY(1000); /* XXX */ 1136169691Skan irqmap[0] = isa_irq_pending(); 1137169691Skan 1138169691Skan /* 1139169691Skan * Attempt to set loopback mode so that we can send a null byte 1140169691Skan * without annoying any external device. 1141169691Skan */ 1142169691Skan/* EXTRA DELAY? */ 1143169691Skan sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK); 1144169691Skan 1145169691Skan /* 1146169691Skan * Attempt to generate an output interrupt. On 8250's, setting 1147169691Skan * IER_ETXRDY generates an interrupt independent of the current 1148169691Skan * setting and independent of whether the THR is empty. On 16450's, 1149169691Skan * setting IER_ETXRDY generates an interrupt independent of the 1150169691Skan * current setting. On 16550A's, setting IER_ETXRDY only 1151169691Skan * generates an interrupt when IER_ETXRDY is not already set. 1152169691Skan */ 1153169691Skan sio_setreg(com, com_ier, IER_ETXRDY); 1154169691Skan#ifdef PC98 1155169691Skan if (iod.if_type == COM_IF_RSA98III) 1156169691Skan outb(iobase + rsa_ier, 0x04); 1157169691Skan#endif 1158169691Skan 1159169691Skan /* 1160169691Skan * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate 1161169691Skan * an interrupt. They'd better generate one for actually doing 1162169691Skan * output. Loopback may be broken on the same incompatibles but 1163169691Skan * it's unlikely to do more than allow the null byte out. 1164169691Skan */ 1165169691Skan sio_setreg(com, com_data, 0); 1166169691Skan DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10)); 1167169691Skan 1168169691Skan /* 1169169691Skan * Turn off loopback mode so that the interrupt gate works again 1170169691Skan * (MCR_IENABLE was hidden). This should leave the device driving 1171169691Skan * an interrupt line high. It doesn't matter if the interrupt 1172169691Skan * line oscillates while we are not looking at it, since interrupts 1173169691Skan * are disabled. 1174169691Skan */ 1175169691Skan/* EXTRA DELAY? */ 1176169691Skan sio_setreg(com, com_mcr, mcr_image); 1177169691Skan 1178169691Skan /* 1179169691Skan * It seems my Xircom CBEM56G Cardbus modem wants to be reset 1180169691Skan * to 8 bits *again*, or else probe test 0 will fail. 1181169691Skan * gwk@sgi.com, 4/19/2001 1182169691Skan */ 1183169691Skan sio_setreg(com, com_cfcr, CFCR_8BITS); 1184169691Skan 1185169691Skan /* 1186169691Skan * Some pcmcia cards have the "TXRDY bug", so we check everyone 1187169691Skan * for IIR_TXRDY implementation ( Palido 321s, DC-1S... ) 1188169691Skan */ 1189169691Skan if (noprobe) { 1190169691Skan /* Reading IIR register twice */ 1191169691Skan for (fn = 0; fn < 2; fn ++) { 1192169691Skan DELAY(10000); 1193169691Skan failures[6] = sio_getreg(com, com_iir); 1194169691Skan } 1195169691Skan /* Check IIR_TXRDY clear ? */ 1196169691Skan result = 0; 1197169691Skan if (failures[6] & IIR_TXRDY) { 1198169691Skan /* No, Double check with clearing IER */ 1199169691Skan sio_setreg(com, com_ier, 0); 1200169691Skan if (sio_getreg(com, com_iir) & IIR_NOPEND) { 1201169691Skan /* Ok. We discovered TXRDY bug! */ 1202169691Skan SET_FLAG(dev, COM_C_IIR_TXRDYBUG); 1203169691Skan } else { 1204169691Skan /* Unknown, Just omit this chip.. XXX */ 1205169691Skan result = ENXIO; 1206169691Skan sio_setreg(com, com_mcr, 0); 1207169691Skan } 1208169691Skan } else { 1209169691Skan /* OK. this is well-known guys */ 1210169691Skan CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); 1211169691Skan } 1212169691Skan sio_setreg(com, com_ier, 0); 1213169691Skan sio_setreg(com, com_cfcr, CFCR_8BITS); 1214169691Skan mtx_unlock_spin(&sio_lock); 1215169691Skan bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1216169691Skan if (iobase == siocniobase) 1217169691Skan result = 0; 1218169691Skan if (result != 0) { 1219169691Skan device_set_softc(dev, NULL); 1220169691Skan free(com, M_DEVBUF); 1221169691Skan } 1222169691Skan return (result); 1223169691Skan } 1224169691Skan 1225169691Skan /* 1226169691Skan * Check that 1227169691Skan * o the CFCR, IER and MCR in UART hold the values written to them 1228169691Skan * (the values happen to be all distinct - this is good for 1229169691Skan * avoiding false positive tests from bus echoes). 1230169691Skan * o an output interrupt is generated and its vector is correct. 1231169691Skan * o the interrupt goes away when the IIR in the UART is read. 1232169691Skan */ 1233169691Skan/* EXTRA DELAY? */ 1234169691Skan failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS; 1235169691Skan failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY; 1236169691Skan failures[2] = sio_getreg(com, com_mcr) - mcr_image; 1237169691Skan DELAY(10000); /* Some internal modems need this time */ 1238169691Skan irqmap[1] = isa_irq_pending(); 1239169691Skan failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY; 1240169691Skan#ifdef PC98 1241169691Skan if (iod.if_type == COM_IF_RSA98III) 1242169691Skan inb(iobase + rsa_srr); 1243169691Skan#endif 1244169691Skan DELAY(1000); /* XXX */ 1245169691Skan irqmap[2] = isa_irq_pending(); 1246169691Skan failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 1247169691Skan#ifdef PC98 1248169691Skan if (iod.if_type == COM_IF_RSA98III) 1249169691Skan inb(iobase + rsa_srr); 1250169691Skan#endif 1251169691Skan 1252169691Skan /* 1253169691Skan * Turn off all device interrupts and check that they go off properly. 1254169691Skan * Leave MCR_IENABLE alone. For ports without a master port, it gates 1255169691Skan * the OUT2 output of the UART to 1256169691Skan * the ICU input. Closing the gate would give a floating ICU input 1257169691Skan * (unless there is another device driving it) and spurious interrupts. 1258169691Skan * (On the system that this was first tested on, the input floats high 1259169691Skan * and gives a (masked) interrupt as soon as the gate is closed.) 1260169691Skan */ 1261169691Skan sio_setreg(com, com_ier, 0); 1262169691Skan sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */ 1263169691Skan failures[7] = sio_getreg(com, com_ier); 1264169691Skan#ifdef PC98 1265169691Skan if (iod.if_type == COM_IF_RSA98III) 1266169691Skan outb(iobase + rsa_ier, 0x00); 1267169691Skan#endif 1268169691Skan DELAY(1000); /* XXX */ 1269169691Skan irqmap[3] = isa_irq_pending(); 1270169691Skan failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 1271169691Skan#ifdef PC98 1272169691Skan if (iod.if_type == COM_IF_RSA98III) { 1273169691Skan inb(iobase + rsa_srr); 1274169691Skan outb(iobase + rsa_frr, 0x00); 1275169691Skan } 1276169691Skan#endif 1277169691Skan 1278169691Skan mtx_unlock_spin(&sio_lock); 1279169691Skan 1280169691Skan irqs = irqmap[1] & ~irqmap[0]; 1281169691Skan if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 && 1282169691Skan ((1 << xirq) & irqs) == 0) { 1283169691Skan printf( 1284169691Skan "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n", 1285169691Skan device_get_unit(dev), xirq, irqs); 1286169691Skan printf( 1287169691Skan "sio%d: port may not be enabled\n", 1288169691Skan device_get_unit(dev)); 1289169691Skan } 1290169691Skan if (bootverbose) 1291169691Skan printf("sio%d: irq maps: %#x %#x %#x %#x\n", 1292169691Skan device_get_unit(dev), 1293169691Skan irqmap[0], irqmap[1], irqmap[2], irqmap[3]); 1294169691Skan 1295169691Skan result = 0; 1296169691Skan for (fn = 0; fn < sizeof failures; ++fn) 1297169691Skan if (failures[fn]) { 1298169691Skan sio_setreg(com, com_mcr, 0); 1299169691Skan result = ENXIO; 1300169691Skan if (bootverbose) { 1301169691Skan printf("sio%d: probe failed test(s):", 1302169691Skan device_get_unit(dev)); 1303169691Skan for (fn = 0; fn < sizeof failures; ++fn) 1304169691Skan if (failures[fn]) 1305169691Skan printf(" %d", fn); 1306169691Skan printf("\n"); 1307169691Skan } 1308169691Skan break; 1309169691Skan } 1310169691Skan bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1311169691Skan if (iobase == siocniobase) 1312169691Skan result = 0; 1313169691Skan if (result != 0) { 1314169691Skan device_set_softc(dev, NULL); 1315169691Skan free(com, M_DEVBUF); 1316169691Skan } 1317169691Skan return (result); 1318169691Skan} 1319169691Skan 1320169691Skan#ifdef COM_ESP 1321169691Skanstatic int 1322169691Skanespattach(com, esp_port) 1323169691Skan struct com_s *com; 1324169691Skan Port_t esp_port; 1325169691Skan{ 1326169691Skan u_char dips; 1327169691Skan u_char val; 1328169691Skan 1329169691Skan /* 1330169691Skan * Check the ESP-specific I/O port to see if we're an ESP 1331169691Skan * card. If not, return failure immediately. 1332169691Skan */ 1333169691Skan if ((inb(esp_port) & 0xf3) == 0) { 1334169691Skan printf(" port 0x%x is not an ESP board?\n", esp_port); 1335169691Skan return (0); 1336169691Skan } 1337169691Skan 1338169691Skan /* 1339169691Skan * We've got something that claims to be a Hayes ESP card. 1340169691Skan * Let's hope so. 1341169691Skan */ 1342169691Skan 1343169691Skan /* Get the dip-switch configuration */ 1344169691Skan#ifdef PC98 1345169691Skan outb(esp_port + ESP98_CMD1, ESP_GETDIPS); 1346169691Skan dips = inb(esp_port + ESP98_STATUS1); 1347169691Skan#else 1348169691Skan outb(esp_port + ESP_CMD1, ESP_GETDIPS); 1349169691Skan dips = inb(esp_port + ESP_STATUS1); 1350169691Skan#endif 1351169691Skan 1352169691Skan /* 1353169691Skan * Bits 0,1 of dips say which COM port we are. 1354169691Skan */ 1355169691Skan#ifdef PC98 1356169691Skan if ((rman_get_start(com->ioportres) & 0xff) == 1357169691Skan likely_com_ports[dips & 0x03]) 1358169691Skan#else 1359169691Skan if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03]) 1360169691Skan#endif 1361169691Skan printf(" : ESP"); 1362169691Skan else { 1363169691Skan printf(" esp_port has com %d\n", dips & 0x03); 1364169691Skan return (0); 1365169691Skan } 1366169691Skan 1367169691Skan /* 1368169691Skan * Check for ESP version 2.0 or later: bits 4,5,6 = 010. 1369169691Skan */ 1370169691Skan#ifdef PC98 1371169691Skan outb(esp_port + ESP98_CMD1, ESP_GETTEST); 1372169691Skan val = inb(esp_port + ESP98_STATUS1); /* clear reg 1 */ 1373169691Skan val = inb(esp_port + ESP98_STATUS2); 1374169691Skan#else 1375169691Skan outb(esp_port + ESP_CMD1, ESP_GETTEST); 1376169691Skan val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */ 1377169691Skan val = inb(esp_port + ESP_STATUS2); 1378169691Skan#endif 1379169691Skan if ((val & 0x70) < 0x20) { 1380169691Skan printf("-old (%o)", val & 0x70); 1381169691Skan return (0); 1382169691Skan } 1383169691Skan 1384169691Skan /* 1385169691Skan * Check for ability to emulate 16550: bit 7 == 1 1386169691Skan */ 1387169691Skan if ((dips & 0x80) == 0) { 1388169691Skan printf(" slave"); 1389169691Skan return (0); 1390169691Skan } 1391169691Skan 1392169691Skan /* 1393169691Skan * Okay, we seem to be a Hayes ESP card. Whee. 1394169691Skan */ 1395169691Skan com->esp = TRUE; 1396169691Skan com->esp_port = esp_port; 1397169691Skan return (1); 1398169691Skan} 1399169691Skan#endif /* COM_ESP */ 1400169691Skan 1401169691Skanint 1402169691Skansioattach(dev, xrid, rclk) 1403169691Skan device_t dev; 1404169691Skan int xrid; 1405169691Skan u_long rclk; 1406169691Skan{ 1407169691Skan struct com_s *com; 1408169691Skan#ifdef COM_ESP 1409169691Skan Port_t *espp; 1410169691Skan#endif 1411169691Skan Port_t iobase; 1412169691Skan int minorbase; 1413169691Skan int unit; 1414169691Skan u_int flags; 1415169691Skan int rid; 1416169691Skan struct resource *port; 1417169691Skan int ret; 1418169691Skan#ifdef PC98 1419169691Skan u_char *obuf; 1420169691Skan u_long obufsize; 1421169691Skan int if_type = GET_IFTYPE(device_get_flags(dev)); 1422169691Skan#endif 1423169691Skan 1424169691Skan rid = xrid; 1425169691Skan#ifdef PC98 1426169691Skan if (IS_8251(if_type)) { 1427169691Skan port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1428169691Skan 0, ~0, 1, RF_ACTIVE); 1429169691Skan } else if (if_type == COM_IF_MODEM_CARD || 1430169691Skan if_type == COM_IF_RSA98III || 1431169691Skan isa_get_vendorid(dev)) { 1432169691Skan port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 1433169691Skan if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE); 1434169691Skan } else { 1435169691Skan port = isa_alloc_resourcev(dev, SYS_RES_IOPORT, &rid, 1436169691Skan if_16550a_type[if_type & 0x0f].iat, 1437169691Skan if_16550a_type[if_type & 0x0f].iatsz, RF_ACTIVE); 1438169691Skan } 1439169691Skan#else 1440169691Skan port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1441169691Skan 0, ~0, IO_COMSIZE, RF_ACTIVE); 1442169691Skan#endif 1443169691Skan if (!port) 1444169691Skan return (ENXIO); 1445169691Skan#ifdef PC98 1446169691Skan if (!IS_8251(if_type)) { 1447169691Skan if (isa_load_resourcev(port, 1448169691Skan if_16550a_type[if_type & 0x0f].iat, 1449169691Skan if_16550a_type[if_type & 0x0f].iatsz) != 0) { 1450169691Skan bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1451169691Skan return ENXIO; 1452169691Skan } 1453169691Skan } 1454169691Skan#endif 1455169691Skan 1456169691Skan iobase = rman_get_start(port); 1457169691Skan unit = device_get_unit(dev); 1458169691Skan com = device_get_softc(dev); 1459169691Skan flags = device_get_flags(dev); 1460169691Skan 1461169691Skan if (unit >= sio_numunits) 1462169691Skan sio_numunits = unit + 1; 1463169691Skan 1464169691Skan#ifdef PC98 1465169691Skan obufsize = 256; 1466169691Skan if (if_type == COM_IF_RSA98III) 1467169691Skan obufsize = 2048; 1468169691Skan if ((obuf = malloc(obufsize * 2, M_DEVBUF, M_NOWAIT)) == NULL) { 1469169691Skan bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1470169691Skan return ENXIO; 1471169691Skan } 1472169691Skan bzero(obuf, obufsize * 2); 1473169691Skan#endif 1474169691Skan 1475169691Skan /* 1476169691Skan * sioprobe() has initialized the device registers as follows: 1477169691Skan * o cfcr = CFCR_8BITS. 1478169691Skan * It is most important that CFCR_DLAB is off, so that the 1479169691Skan * data port is not hidden when we enable interrupts. 1480169691Skan * o ier = 0. 1481169691Skan * Interrupts are only enabled when the line is open. 1482169691Skan * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible 1483169691Skan * interrupt control register or the config specifies no irq. 1484169691Skan * Keeping MCR_DTR and MCR_RTS off might stop the external 1485169691Skan * device from sending before we are ready. 1486169691Skan */ 1487169691Skan bzero(com, sizeof *com); 1488169691Skan com->unit = unit; 1489169691Skan com->ioportres = port; 1490169691Skan com->bst = rman_get_bustag(port); 1491169691Skan com->bsh = rman_get_bushandle(port); 1492169691Skan com->cfcr_image = CFCR_8BITS; 1493169691Skan com->dtr_wait = 3 * hz; 1494169691Skan com->loses_outints = COM_LOSESOUTINTS(flags) != 0; 1495169691Skan com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0; 1496169691Skan com->tx_fifo_size = 1; 1497169691Skan#ifdef PC98 1498169691Skan com->obufsize = obufsize; 1499169691Skan com->obuf1 = obuf; 1500169691Skan com->obuf2 = obuf + obufsize; 1501169691Skan#endif 1502169691Skan com->obufs[0].l_head = com->obuf1; 1503169691Skan com->obufs[1].l_head = com->obuf2; 1504169691Skan 1505169691Skan#ifdef PC98 1506169691Skan com->pc98_if_type = if_type; 1507169691Skan 1508169691Skan if (IS_8251(if_type)) { 1509169691Skan pc98_set_ioport(com); 1510169691Skan 1511169691Skan if (if_type == COM_IF_INTERNAL && pc98_check_8251fifo()) { 1512169691Skan com->pc98_8251fifo = 1; 1513169691Skan com->pc98_8251fifo_enable = 0; 1514169691Skan } 1515169691Skan } else { 1516169691Skan bus_addr_t *iat = if_16550a_type[if_type & 0x0f].iat; 1517169691Skan 1518169691Skan com->data_port = iobase + iat[com_data]; 1519169691Skan com->int_id_port = iobase + iat[com_iir]; 1520169691Skan com->modem_ctl_port = iobase + iat[com_mcr]; 1521169691Skan com->mcr_image = inb(com->modem_ctl_port); 1522169691Skan com->line_status_port = iobase + iat[com_lsr]; 1523169691Skan com->modem_status_port = iobase + iat[com_msr]; 1524169691Skan com->intr_ctl_port = iobase + iat[com_ier]; 1525169691Skan } 1526169691Skan#else /* not PC98 */ 1527169691Skan com->data_port = iobase + com_data; 1528169691Skan com->int_id_port = iobase + com_iir; 1529169691Skan com->modem_ctl_port = iobase + com_mcr; 1530169691Skan com->mcr_image = inb(com->modem_ctl_port); 1531169691Skan com->line_status_port = iobase + com_lsr; 1532169691Skan com->modem_status_port = iobase + com_msr; 1533169691Skan com->intr_ctl_port = iobase + com_ier; 1534169691Skan#endif 1535169691Skan 1536169691Skan#ifdef PC98 1537169691Skan if (!IS_8251(if_type) && rclk == 0) 1538169691Skan rclk = if_16550a_type[if_type & 0x0f].rclk; 1539169691Skan#else 1540169691Skan if (rclk == 0) 1541169691Skan rclk = DEFAULT_RCLK; 1542169691Skan#endif 1543169691Skan com->rclk = rclk; 1544169691Skan 1545169691Skan /* 1546169691Skan * We don't use all the flags from <sys/ttydefaults.h> since they 1547169691Skan * are only relevant for logins. It's important to have echo off 1548169691Skan * initially so that the line doesn't start blathering before the 1549169691Skan * echo flag can be turned off. 1550169691Skan */ 1551169691Skan com->it_in.c_iflag = 0; 1552169691Skan com->it_in.c_oflag = 0; 1553169691Skan com->it_in.c_cflag = TTYDEF_CFLAG; 1554169691Skan com->it_in.c_lflag = 0; 1555169691Skan if (unit == comconsole) { 1556169691Skan#ifdef PC98 1557169691Skan if (IS_8251(com->pc98_if_type)) 1558169691Skan DELAY(100000); 1559169691Skan#endif 1560169691Skan com->it_in.c_iflag = TTYDEF_IFLAG; 1561169691Skan com->it_in.c_oflag = TTYDEF_OFLAG; 1562169691Skan com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL; 1563169691Skan com->it_in.c_lflag = TTYDEF_LFLAG; 1564169691Skan com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL; 1565169691Skan com->lt_out.c_ispeed = com->lt_out.c_ospeed = 1566169691Skan com->lt_in.c_ispeed = com->lt_in.c_ospeed = 1567169691Skan com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate; 1568169691Skan } else 1569169691Skan com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED; 1570169691Skan if (siosetwater(com, com->it_in.c_ispeed) != 0) { 1571169691Skan mtx_unlock_spin(&sio_lock); 1572169691Skan /* 1573169691Skan * Leave i/o resources allocated if this is a `cn'-level 1574169691Skan * console, so that other devices can't snarf them. 1575169691Skan */ 1576169691Skan if (iobase != siocniobase) 1577169691Skan bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 1578169691Skan return (ENOMEM); 1579169691Skan } 1580169691Skan mtx_unlock_spin(&sio_lock); 1581169691Skan termioschars(&com->it_in); 1582169691Skan com->it_out = com->it_in; 1583169691Skan 1584169691Skan /* attempt to determine UART type */ 1585169691Skan printf("sio%d: type", unit); 1586169691Skan 1587169691Skan 1588169691Skan#ifndef PC98 1589169691Skan#ifdef COM_MULTIPORT 1590169691Skan if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags)) 1591169691Skan#else 1592169691Skan if (!COM_IIR_TXRDYBUG(flags)) 1593169691Skan#endif 1594169691Skan { 1595169691Skan u_char scr; 1596169691Skan u_char scr1; 1597169691Skan u_char scr2; 1598169691Skan 1599169691Skan scr = sio_getreg(com, com_scr); 1600169691Skan sio_setreg(com, com_scr, 0xa5); 1601169691Skan scr1 = sio_getreg(com, com_scr); 1602169691Skan sio_setreg(com, com_scr, 0x5a); 1603169691Skan scr2 = sio_getreg(com, com_scr); 1604169691Skan sio_setreg(com, com_scr, scr); 1605169691Skan if (scr1 != 0xa5 || scr2 != 0x5a) { 1606169691Skan printf(" 8250 or not responding"); 1607169691Skan goto determined_type; 1608169691Skan } 1609169691Skan } 1610169691Skan#endif /* !PC98 */ 1611169691Skan#ifdef PC98 1612169691Skan if (IS_8251(com->pc98_if_type)) { 1613169691Skan if (com->pc98_8251fifo && !COM_NOFIFO(flags)) 1614169691Skan com->tx_fifo_size = 16; 1615169691Skan com_int_TxRx_disable( com ); 1616169691Skan com_cflag_and_speed_set( com, com->it_in.c_cflag, comdefaultrate ); 1617169691Skan com_tiocm_bic( com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE ); 1618169691Skan com_send_break_off( com ); 1619169691Skan 1620169691Skan if (com->pc98_if_type == COM_IF_INTERNAL) { 1621169691Skan printf(" (internal%s%s)", 1622169691Skan com->pc98_8251fifo ? " fifo" : "", 1623169691Skan PC98SIO_baud_rate_port(com->pc98_if_type) != -1 ? 1624169691Skan " v-fast" : ""); 1625169691Skan } else { 1626169691Skan printf(" 8251%s", if_8251_type[com->pc98_if_type & 0x0f].name); 1627169691Skan } 1628169691Skan } else { 1629169691Skan#endif /* PC98 */ 1630169691Skan sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH); 1631169691Skan DELAY(100); 1632169691Skan com->st16650a = 0; 1633169691Skan switch (inb(com->int_id_port) & IIR_FIFO_MASK) { 1634169691Skan case FIFO_RX_LOW: 1635169691Skan printf(" 16450"); 1636169691Skan break; 1637169691Skan case FIFO_RX_MEDL: 1638169691Skan printf(" 16450?"); 1639169691Skan break; 1640169691Skan case FIFO_RX_MEDH: 1641169691Skan printf(" 16550?"); 1642169691Skan break; 1643169691Skan case FIFO_RX_HIGH: 1644169691Skan if (COM_NOFIFO(flags)) { 1645169691Skan printf(" 16550A fifo disabled"); 1646169691Skan } else { 1647169691Skan com->hasfifo = TRUE; 1648169691Skan#ifdef PC98 1649169691Skan com->tx_fifo_size = 0; /* XXX flag conflicts. */ 1650169691Skan printf(" 16550A"); 1651169691Skan#else 1652169691Skan if (COM_ST16650A(flags)) { 1653169691Skan com->st16650a = 1; 1654169691Skan com->tx_fifo_size = 32; 1655169691Skan printf(" ST16650A"); 1656169691Skan } else { 1657169691Skan com->tx_fifo_size = COM_FIFOSIZE(flags); 1658169691Skan printf(" 16550A"); 1659169691Skan } 1660169691Skan#endif 1661169691Skan } 1662169691Skan#ifdef PC98 1663169691Skan if (com->pc98_if_type == COM_IF_RSA98III) { 1664169691Skan com->tx_fifo_size = 2048; 1665169691Skan com->rsabase = iobase; 1666169691Skan outb(com->rsabase + rsa_ier, 0x00); 1667169691Skan outb(com->rsabase + rsa_frr, 0x00); 1668169691Skan } 1669169691Skan#endif 1670169691Skan 1671169691Skan#ifdef COM_ESP 1672169691Skan#ifdef PC98 1673169691Skan if (com->pc98_if_type == COM_IF_ESP98) 1674169691Skan#endif 1675169691Skan for (espp = likely_esp_ports; *espp != 0; espp++) 1676169691Skan if (espattach(com, *espp)) { 1677169691Skan com->tx_fifo_size = 1024; 1678169691Skan break; 1679169691Skan } 1680169691Skan#endif 1681169691Skan if (!com->st16650a) { 1682169691Skan if (!com->tx_fifo_size) 1683169691Skan com->tx_fifo_size = 16; 1684169691Skan else 1685169691Skan printf(" lookalike with %d bytes FIFO", 1686169691Skan com->tx_fifo_size); 1687169691Skan } 1688169691Skan 1689169691Skan break; 1690169691Skan } 1691169691Skan 1692169691Skan#ifdef PC98 1693169691Skan if (com->pc98_if_type == COM_IF_RSB3000) { 1694169691Skan /* Set RSB-2000/3000 Extended Buffer mode. */ 1695169691Skan u_char lcr; 1696169691Skan lcr = sio_getreg(com, com_cfcr); 1697169691Skan sio_setreg(com, com_cfcr, lcr | CFCR_DLAB); 1698169691Skan sio_setreg(com, com_emr, EMR_EXBUFF | EMR_EFMODE); 1699169691Skan sio_setreg(com, com_cfcr, lcr); 1700169691Skan } 1701169691Skan#endif 1702169691Skan 1703169691Skan#ifdef COM_ESP 1704169691Skan if (com->esp) { 1705169691Skan /* 1706169691Skan * Set 16550 compatibility mode. 1707169691Skan * We don't use the ESP_MODE_SCALE bit to increase the 1708169691Skan * fifo trigger levels because we can't handle large 1709169691Skan * bursts of input. 1710169691Skan * XXX flow control should be set in comparam(), not here. 1711169691Skan */ 1712169691Skan#ifdef PC98 1713169691Skan outb(com->esp_port + ESP98_CMD1, ESP_SETMODE); 1714169691Skan outb(com->esp_port + ESP98_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1715169691Skan#else 1716169691Skan outb(com->esp_port + ESP_CMD1, ESP_SETMODE); 1717169691Skan outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 1718169691Skan#endif 1719169691Skan 1720169691Skan /* Set RTS/CTS flow control. */ 1721169691Skan#ifdef PC98 1722169691Skan outb(com->esp_port + ESP98_CMD1, ESP_SETFLOWTYPE); 1723169691Skan outb(com->esp_port + ESP98_CMD2, ESP_FLOW_RTS); 1724169691Skan outb(com->esp_port + ESP98_CMD2, ESP_FLOW_CTS); 1725169691Skan#else 1726169691Skan outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE); 1727169691Skan outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS); 1728169691Skan outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS); 1729169691Skan#endif 1730169691Skan 1731169691Skan /* Set flow-control levels. */ 1732169691Skan#ifdef PC98 1733169691Skan outb(com->esp_port + ESP98_CMD1, ESP_SETRXFLOW); 1734169691Skan outb(com->esp_port + ESP98_CMD2, HIBYTE(768)); 1735169691Skan outb(com->esp_port + ESP98_CMD2, LOBYTE(768)); 1736169691Skan outb(com->esp_port + ESP98_CMD2, HIBYTE(512)); 1737169691Skan outb(com->esp_port + ESP98_CMD2, LOBYTE(512)); 1738169691Skan#else 1739169691Skan outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW); 1740169691Skan outb(com->esp_port + ESP_CMD2, HIBYTE(768)); 1741169691Skan outb(com->esp_port + ESP_CMD2, LOBYTE(768)); 1742169691Skan outb(com->esp_port + ESP_CMD2, HIBYTE(512)); 1743169691Skan outb(com->esp_port + ESP_CMD2, LOBYTE(512)); 1744169691Skan#endif 1745169691Skan 1746169691Skan#ifdef PC98 1747169691Skan /* Set UART clock prescaler. */ 1748169691Skan outb(com->esp_port + ESP98_CMD1, ESP_SETCLOCK); 1749169691Skan outb(com->esp_port + ESP98_CMD2, 2); /* 4 times */ 1750169691Skan#endif 1751169691Skan } 1752169691Skan#endif /* COM_ESP */ 1753169691Skan sio_setreg(com, com_fifo, 0); 1754169691Skan#ifdef PC98 1755169691Skan printf("%s", if_16550a_type[com->pc98_if_type & 0x0f].name); 1756169691Skan#else 1757169691Skandetermined_type: ; 1758169691Skan#endif 1759169691Skan 1760169691Skan#ifdef COM_MULTIPORT 1761169691Skan if (COM_ISMULTIPORT(flags)) { 1762169691Skan device_t masterdev; 1763169691Skan 1764169691Skan com->multiport = TRUE; 1765169691Skan printf(" (multiport"); 1766169691Skan if (unit == COM_MPMASTER(flags)) 1767169691Skan printf(" master"); 1768169691Skan printf(")"); 1769169691Skan masterdev = devclass_get_device(sio_devclass, 1770169691Skan COM_MPMASTER(flags)); 1771169691Skan com->no_irq = (masterdev == NULL || bus_get_resource(masterdev, 1772169691Skan SYS_RES_IRQ, 0, NULL, NULL) != 0); 1773169691Skan } 1774169691Skan#endif /* COM_MULTIPORT */ 1775169691Skan#ifdef PC98 1776169691Skan } 1777169691Skan#endif 1778169691Skan if (unit == comconsole) 1779169691Skan printf(", console"); 1780169691Skan if (COM_IIR_TXRDYBUG(flags)) 1781169691Skan printf(" with a bogus IIR_TXRDY register"); 1782169691Skan printf("\n"); 1783169691Skan 1784169691Skan if (sio_fast_ih == NULL) { 1785169691Skan swi_add(&tty_ithd, "tty:sio", siopoll, NULL, SWI_TTY, 0, 1786169691Skan &sio_fast_ih); 1787169691Skan swi_add(&clk_ithd, "tty:sio", siopoll, NULL, SWI_TTY, 0, 1788169691Skan &sio_slow_ih); 1789169691Skan } 1790169691Skan minorbase = UNIT_TO_MINOR(unit); 1791169691Skan com->devs[0] = make_dev(&sio_cdevsw, minorbase, 1792169691Skan UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit); 1793169691Skan com->devs[1] = make_dev(&sio_cdevsw, minorbase | CONTROL_INIT_STATE, 1794169691Skan UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit); 1795169691Skan com->devs[2] = make_dev(&sio_cdevsw, minorbase | CONTROL_LOCK_STATE, 1796169691Skan UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit); 1797169691Skan com->devs[3] = make_dev(&sio_cdevsw, minorbase | CALLOUT_MASK, 1798169691Skan UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit); 1799169691Skan com->devs[4] = make_dev(&sio_cdevsw, 1800169691Skan minorbase | CALLOUT_MASK | CONTROL_INIT_STATE, 1801169691Skan UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit); 1802169691Skan com->devs[5] = make_dev(&sio_cdevsw, 1803169691Skan minorbase | CALLOUT_MASK | CONTROL_LOCK_STATE, 1804169691Skan UID_UUCP, GID_DIALER, 0660, "cuala%r", unit); 1805169691Skan com->flags = flags; 1806169691Skan com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1807169691Skan pps_init(&com->pps); 1808169691Skan 1809169691Skan rid = 0; 1810169691Skan com->irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1, 1811169691Skan RF_ACTIVE); 1812169691Skan if (com->irqres) { 1813169691Skan ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres, 1814169691Skan INTR_TYPE_TTY | INTR_FAST, 1815169691Skan siointr, com, &com->cookie); 1816169691Skan if (ret) { 1817169691Skan ret = BUS_SETUP_INTR(device_get_parent(dev), dev, 1818169691Skan com->irqres, INTR_TYPE_TTY, 1819169691Skan siointr, com, &com->cookie); 1820169691Skan if (ret == 0) 1821169691Skan device_printf(dev, "unable to activate interrupt in fast mode - using normal mode\n"); 1822169691Skan } 1823169691Skan if (ret) 1824169691Skan device_printf(dev, "could not activate interrupt\n"); 1825169691Skan#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \ 1826169691Skan defined(ALT_BREAK_TO_DEBUGGER)) 1827169691Skan /* 1828169691Skan * Enable interrupts for early break-to-debugger support 1829169691Skan * on the console. 1830169691Skan */ 1831169691Skan if (ret == 0 && unit == comconsole) 1832169691Skan outb(siocniobase + com_ier, IER_ERXRDY | IER_ERLS | 1833169691Skan IER_EMSC); 1834169691Skan#endif 1835169691Skan } 1836169691Skan 1837169691Skan return (0); 1838169691Skan} 1839169691Skan 1840169691Skanstatic int 1841169691Skansioopen(dev, flag, mode, td) 1842169691Skan dev_t dev; 1843169691Skan int flag; 1844169691Skan int mode; 1845169691Skan struct thread *td; 1846169691Skan{ 1847169691Skan struct com_s *com; 1848169691Skan int error; 1849169691Skan int mynor; 1850169691Skan int s; 1851169691Skan struct tty *tp; 1852169691Skan int unit; 1853169691Skan 1854169691Skan mynor = minor(dev); 1855169691Skan unit = MINOR_TO_UNIT(mynor); 1856169691Skan com = com_addr(unit); 1857169691Skan if (com == NULL) 1858169691Skan return (ENXIO); 1859169691Skan if (com->gone) 1860169691Skan return (ENXIO); 1861169691Skan if (mynor & CONTROL_MASK) 1862169691Skan return (0); 1863169691Skan tp = dev->si_tty = com->tp = ttymalloc(com->tp); 1864169691Skan s = spltty(); 1865169691Skan /* 1866169691Skan * We jump to this label after all non-interrupted sleeps to pick 1867169691Skan * up any changes of the device state. 1868169691Skan */ 1869169691Skanopen_top: 1870169691Skan while (com->state & CS_DTR_OFF) { 1871169691Skan error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0); 1872169691Skan if (com_addr(unit) == NULL) 1873169691Skan return (ENXIO); 1874169691Skan if (error != 0 || com->gone) 1875169691Skan goto out; 1876169691Skan } 1877169691Skan if (tp->t_state & TS_ISOPEN) { 1878169691Skan /* 1879169691Skan * The device is open, so everything has been initialized. 1880169691Skan * Handle conflicts. 1881169691Skan */ 1882169691Skan if (mynor & CALLOUT_MASK) { 1883169691Skan if (!com->active_out) { 1884169691Skan error = EBUSY; 1885169691Skan goto out; 1886169691Skan } 1887169691Skan } else { 1888169691Skan if (com->active_out) { 1889169691Skan if (flag & O_NONBLOCK) { 1890169691Skan error = EBUSY; 1891169691Skan goto out; 1892169691Skan } 1893169691Skan error = tsleep(&com->active_out, 1894169691Skan TTIPRI | PCATCH, "siobi", 0); 1895169691Skan if (com_addr(unit) == NULL) 1896169691Skan return (ENXIO); 1897169691Skan if (error != 0 || com->gone) 1898169691Skan goto out; 1899169691Skan goto open_top; 1900169691Skan } 1901169691Skan } 1902169691Skan if (tp->t_state & TS_XCLUDE && 1903169691Skan suser(td)) { 1904169691Skan error = EBUSY; 1905169691Skan goto out; 1906169691Skan } 1907169691Skan } else { 1908169691Skan /* 1909169691Skan * The device isn't open, so there are no conflicts. 1910169691Skan * Initialize it. Initialization is done twice in many 1911169691Skan * cases: to preempt sleeping callin opens if we are 1912169691Skan * callout, and to complete a callin open after DCD rises. 1913169691Skan */ 1914169691Skan tp->t_oproc = comstart; 1915169691Skan tp->t_param = comparam; 1916169691Skan tp->t_stop = comstop; 1917169691Skan tp->t_dev = dev; 1918169691Skan tp->t_termios = mynor & CALLOUT_MASK 1919169691Skan ? com->it_out : com->it_in; 1920169691Skan#ifdef PC98 1921169691Skan if (!IS_8251(com->pc98_if_type)) 1922169691Skan#endif 1923169691Skan (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET); 1924169691Skan com->poll = com->no_irq; 1925169691Skan com->poll_output = com->loses_outints; 1926169691Skan ++com->wopeners; 1927169691Skan error = comparam(tp, &tp->t_termios); 1928169691Skan --com->wopeners; 1929169691Skan if (error != 0) 1930169691Skan goto out; 1931169691Skan#ifdef PC98 1932169691Skan if (IS_8251(com->pc98_if_type)) { 1933169691Skan com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS); 1934169691Skan pc98_msrint_start(dev); 1935169691Skan if (com->pc98_8251fifo) { 1936169691Skan com->pc98_8251fifo_enable = 1; 1937169691Skan outb(I8251F_fcr, CTRL8251F_ENABLE | 1938169691Skan CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 1939169691Skan } 1940169691Skan } 1941169691Skan#endif 1942169691Skan /* 1943169691Skan * XXX we should goto open_top if comparam() slept. 1944169691Skan */ 1945169691Skan if (com->hasfifo) { 1946169691Skan int i; 1947169691Skan /* 1948169691Skan * (Re)enable and drain fifos. 1949169691Skan * 1950169691Skan * Certain SMC chips cause problems if the fifos 1951169691Skan * are enabled while input is ready. Turn off the 1952169691Skan * fifo if necessary to clear the input. We test 1953169691Skan * the input ready bit after enabling the fifos 1954169691Skan * since we've already enabled them in comparam() 1955169691Skan * and to handle races between enabling and fresh 1956169691Skan * input. 1957169691Skan */ 1958169691Skan for (i = 0; i < 500; i++) { 1959169691Skan sio_setreg(com, com_fifo, 1960169691Skan FIFO_RCV_RST | FIFO_XMT_RST 1961169691Skan | com->fifo_image); 1962169691Skan#ifdef PC98 1963169691Skan if (com->pc98_if_type == COM_IF_RSA98III) 1964169691Skan outb(com->rsabase + rsa_frr , 0x00); 1965169691Skan#endif 1966169691Skan /* 1967169691Skan * XXX the delays are for superstitious 1968169691Skan * historical reasons. It must be less than 1969169691Skan * the character time at the maximum 1970169691Skan * supported speed (87 usec at 115200 bps 1971169691Skan * 8N1). Otherwise we might loop endlessly 1972169691Skan * if data is streaming in. We used to use 1973169691Skan * delays of 100. That usually worked 1974169691Skan * because DELAY(100) used to usually delay 1975169691Skan * for about 85 usec instead of 100. 1976169691Skan */ 1977169691Skan DELAY(50); 1978169691Skan#ifdef PC98 1979169691Skan if (com->pc98_if_type == COM_IF_RSA98III ? 1980169691Skan !(inb(com->rsabase + rsa_srr) & 0x08) : 1981169691Skan !(inb(com->line_status_port) & LSR_RXRDY)) 1982169691Skan break; 1983169691Skan#else 1984169691Skan if (!(inb(com->line_status_port) & LSR_RXRDY)) 1985169691Skan break; 1986169691Skan#endif 1987169691Skan sio_setreg(com, com_fifo, 0); 1988169691Skan DELAY(50); 1989169691Skan (void) inb(com->data_port); 1990169691Skan } 1991169691Skan if (i == 500) { 1992169691Skan error = EIO; 1993169691Skan goto out; 1994169691Skan } 1995169691Skan } 1996169691Skan 1997169691Skan mtx_lock_spin(&sio_lock); 1998169691Skan#ifdef PC98 1999169691Skan if (IS_8251(com->pc98_if_type)) { 2000169691Skan com_tiocm_bis(com, TIOCM_LE); 2001169691Skan com->pc98_prev_modem_status = pc98_get_modem_status(com); 2002169691Skan com_int_Rx_enable(com); 2003169691Skan } else { 2004169691Skan#endif 2005169691Skan (void) inb(com->line_status_port); 2006169691Skan (void) inb(com->data_port); 2007169691Skan com->prev_modem_status = com->last_modem_status 2008169691Skan = inb(com->modem_status_port); 2009169691Skan if (COM_IIR_TXRDYBUG(com->flags)) { 2010169691Skan outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS 2011169691Skan | IER_EMSC); 2012169691Skan } else { 2013169691Skan outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY 2014169691Skan | IER_ERLS | IER_EMSC); 2015169691Skan } 2016169691Skan#ifdef PC98 2017169691Skan if (com->pc98_if_type == COM_IF_RSA98III) { 2018169691Skan outb(com->rsabase + rsa_ier, 0x1d); 2019169691Skan outb(com->intr_ctl_port, IER_ERLS | IER_EMSC); 2020169691Skan } 2021169691Skan#endif 2022169691Skan#ifdef PC98 2023169691Skan } 2024169691Skan#endif 2025169691Skan mtx_unlock_spin(&sio_lock); 2026169691Skan /* 2027169691Skan * Handle initial DCD. Callout devices get a fake initial 2028169691Skan * DCD (trapdoor DCD). If we are callout, then any sleeping 2029169691Skan * callin opens get woken up and resume sleeping on "siobi" 2030169691Skan * instead of "siodcd". 2031169691Skan */ 2032169691Skan /* 2033169691Skan * XXX `mynor & CALLOUT_MASK' should be 2034169691Skan * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where 2035169691Skan * TRAPDOOR_CARRIER is the default initial state for callout 2036169691Skan * devices and SOFT_CARRIER is like CLOCAL except it hides 2037169691Skan * the true carrier. 2038169691Skan */ 2039169691Skan#ifdef PC98 2040169691Skan if ((IS_8251(com->pc98_if_type) && 2041169691Skan (pc98_get_modem_status(com) & TIOCM_CAR)) || 2042169691Skan (!IS_8251(com->pc98_if_type) && 2043169691Skan (com->prev_modem_status & MSR_DCD)) || 2044169691Skan mynor & CALLOUT_MASK) 2045169691Skan (*linesw[tp->t_line].l_modem)(tp, 1); 2046169691Skan#else 2047169691Skan if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK) 2048169691Skan (*linesw[tp->t_line].l_modem)(tp, 1); 2049169691Skan#endif 2050169691Skan } 2051169691Skan /* 2052169691Skan * Wait for DCD if necessary. 2053169691Skan */ 2054169691Skan if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK) 2055169691Skan && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 2056169691Skan ++com->wopeners; 2057169691Skan error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0); 2058169691Skan if (com_addr(unit) == NULL) 2059169691Skan return (ENXIO); 2060169691Skan --com->wopeners; 2061169691Skan if (error != 0 || com->gone) 2062169691Skan goto out; 2063169691Skan goto open_top; 2064169691Skan } 2065169691Skan error = (*linesw[tp->t_line].l_open)(dev, tp); 2066169691Skan disc_optim(tp, &tp->t_termios, com); 2067169691Skan if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK) 2068169691Skan com->active_out = TRUE; 2069169691Skan siosettimeout(); 2070169691Skanout: 2071169691Skan splx(s); 2072169691Skan if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0) 2073169691Skan comhardclose(com); 2074169691Skan return (error); 2075169691Skan} 2076169691Skan 2077169691Skanstatic int 2078169691Skansioclose(dev, flag, mode, td) 2079169691Skan dev_t dev; 2080169691Skan int flag; 2081169691Skan int mode; 2082169691Skan struct thread *td; 2083169691Skan{ 2084169691Skan struct com_s *com; 2085169691Skan int mynor; 2086169691Skan int s; 2087169691Skan struct tty *tp; 2088169691Skan 2089169691Skan mynor = minor(dev); 2090169691Skan if (mynor & CONTROL_MASK) 2091169691Skan return (0); 2092169691Skan com = com_addr(MINOR_TO_UNIT(mynor)); 2093169691Skan if (com == NULL) 2094169691Skan return (ENODEV); 2095169691Skan tp = com->tp; 2096169691Skan s = spltty(); 2097169691Skan (*linesw[tp->t_line].l_close)(tp, flag); 2098169691Skan#ifdef PC98 2099169691Skan com->modem_checking = 0; 2100169691Skan#endif 2101169691Skan disc_optim(tp, &tp->t_termios, com); 2102169691Skan comstop(tp, FREAD | FWRITE); 2103169691Skan comhardclose(com); 2104169691Skan ttyclose(tp); 2105169691Skan siosettimeout(); 2106169691Skan splx(s); 2107169691Skan if (com->gone) { 2108169691Skan printf("sio%d: gone\n", com->unit); 2109169691Skan s = spltty(); 2110169691Skan if (com->ibuf != NULL) 2111169691Skan free(com->ibuf, M_DEVBUF); 2112169691Skan bzero(tp, sizeof *tp); 2113169691Skan splx(s); 2114169691Skan } 2115169691Skan return (0); 2116169691Skan} 2117169691Skan 2118169691Skanstatic void 2119169691Skancomhardclose(com) 2120169691Skan struct com_s *com; 2121169691Skan{ 2122169691Skan int s; 2123169691Skan struct tty *tp; 2124169691Skan int unit; 2125169691Skan 2126169691Skan unit = com->unit; 2127169691Skan s = spltty(); 2128169691Skan com->poll = FALSE; 2129169691Skan com->poll_output = FALSE; 2130169691Skan com->do_timestamp = FALSE; 2131169691Skan com->do_dcd_timestamp = FALSE; 2132169691Skan com->pps.ppsparam.mode = 0; 2133169691Skan#ifdef PC98 2134169691Skan if (IS_8251(com->pc98_if_type)) 2135169691Skan com_send_break_off(com); 2136169691Skan else 2137169691Skan#endif 2138169691Skan sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 2139169691Skan tp = com->tp; 2140169691Skan 2141169691Skan#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \ 2142169691Skan defined(ALT_BREAK_TO_DEBUGGER)) 2143169691Skan /* 2144169691Skan * Leave interrupts enabled and don't clear DTR if this is the 2145169691Skan * console. This allows us to detect break-to-debugger events 2146169691Skan * while the console device is closed. 2147169691Skan */ 2148169691Skan if (com->unit != comconsole) 2149169691Skan#endif 2150169691Skan { 2151169691Skan#ifdef PC98 2152169691Skan int tmp; 2153169691Skan if (IS_8251(com->pc98_if_type)) 2154169691Skan com_int_TxRx_disable(com); 2155169691Skan else 2156169691Skan sio_setreg(com, com_ier, 0); 2157169691Skan if (com->pc98_if_type == COM_IF_RSA98III) 2158169691Skan outb(com->rsabase + rsa_ier, 0x00); 2159169691Skan if (IS_8251(com->pc98_if_type)) 2160169691Skan tmp = pc98_get_modem_status(com) & TIOCM_CAR; 2161169691Skan else 2162169691Skan tmp = com->prev_modem_status & MSR_DCD; 2163169691Skan#else 2164169691Skan sio_setreg(com, com_ier, 0); 2165169691Skan#endif 2166169691Skan if (tp->t_cflag & HUPCL 2167169691Skan /* 2168169691Skan * XXX we will miss any carrier drop between here and the 2169169691Skan * next open. Perhaps we should watch DCD even when the 2170169691Skan * port is closed; it is not sufficient to check it at 2171169691Skan * the next open because it might go up and down while 2172169691Skan * we're not watching. 2173169691Skan */ 2174169691Skan || (!com->active_out 2175169691Skan#ifdef PC98 2176169691Skan && !(tmp) 2177169691Skan#else 2178169691Skan && !(com->prev_modem_status & MSR_DCD) 2179169691Skan#endif 2180169691Skan && !(com->it_in.c_cflag & CLOCAL)) 2181169691Skan || !(tp->t_state & TS_ISOPEN)) { 2182169691Skan#ifdef PC98 2183169691Skan if (IS_8251(com->pc98_if_type)) 2184169691Skan com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 2185169691Skan else 2186169691Skan#endif 2187169691Skan (void)commctl(com, TIOCM_DTR, DMBIC); 2188169691Skan if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) { 2189169691Skan timeout(siodtrwakeup, com, com->dtr_wait); 2190169691Skan com->state |= CS_DTR_OFF; 2191169691Skan } 2192169691Skan } 2193169691Skan#ifdef PC98 2194169691Skan else { 2195169691Skan if (IS_8251(com->pc98_if_type)) 2196169691Skan com_tiocm_bic(com, TIOCM_LE); 2197169691Skan } 2198169691Skan#endif 2199169691Skan } 2200169691Skan#ifdef PC98 2201169691Skan if (com->pc98_8251fifo) { 2202169691Skan if (com->pc98_8251fifo_enable) 2203169691Skan outb(I8251F_fcr, CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 2204169691Skan com->pc98_8251fifo_enable = 0; 2205169691Skan } 2206169691Skan#endif 2207169691Skan if (com->hasfifo) { 2208169691Skan /* 2209169691Skan * Disable fifos so that they are off after controlled 2210169691Skan * reboots. Some BIOSes fail to detect 16550s when the 2211169691Skan * fifos are enabled. 2212169691Skan */ 2213169691Skan sio_setreg(com, com_fifo, 0); 2214169691Skan } 2215169691Skan com->active_out = FALSE; 2216169691Skan wakeup(&com->active_out); 2217169691Skan wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */ 2218169691Skan splx(s); 2219169691Skan} 2220169691Skan 2221169691Skanstatic int 2222169691Skansioread(dev, uio, flag) 2223169691Skan dev_t dev; 2224169691Skan struct uio *uio; 2225169691Skan int flag; 2226169691Skan{ 2227169691Skan int mynor; 2228169691Skan struct com_s *com; 2229169691Skan 2230169691Skan mynor = minor(dev); 2231169691Skan if (mynor & CONTROL_MASK) 2232169691Skan return (ENODEV); 2233169691Skan com = com_addr(MINOR_TO_UNIT(mynor)); 2234169691Skan if (com == NULL || com->gone) 2235169691Skan return (ENODEV); 2236169691Skan return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag)); 2237169691Skan} 2238169691Skan 2239169691Skanstatic int 2240169691Skansiowrite(dev, uio, flag) 2241169691Skan dev_t dev; 2242169691Skan struct uio *uio; 2243169691Skan int flag; 2244169691Skan{ 2245169691Skan int mynor; 2246169691Skan struct com_s *com; 2247169691Skan int unit; 2248169691Skan 2249169691Skan mynor = minor(dev); 2250169691Skan if (mynor & CONTROL_MASK) 2251169691Skan return (ENODEV); 2252169691Skan 2253169691Skan unit = MINOR_TO_UNIT(mynor); 2254169691Skan com = com_addr(unit); 2255169691Skan if (com == NULL || com->gone) 2256169691Skan return (ENODEV); 2257169691Skan /* 2258169691Skan * (XXX) We disallow virtual consoles if the physical console is 2259169691Skan * a serial port. This is in case there is a display attached that 2260169691Skan * is not the console. In that situation we don't need/want the X 2261169691Skan * server taking over the console. 2262169691Skan */ 2263169691Skan if (constty != NULL && unit == comconsole) 2264169691Skan constty = NULL; 2265169691Skan return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag)); 2266169691Skan} 2267169691Skan 2268169691Skanstatic void 2269169691Skansiobusycheck(chan) 2270169691Skan void *chan; 2271169691Skan{ 2272169691Skan struct com_s *com; 2273169691Skan int s; 2274169691Skan 2275169691Skan com = (struct com_s *)chan; 2276169691Skan 2277169691Skan /* 2278169691Skan * Clear TS_BUSY if low-level output is complete. 2279169691Skan * spl locking is sufficient because siointr1() does not set CS_BUSY. 2280169691Skan * If siointr1() clears CS_BUSY after we look at it, then we'll get 2281169691Skan * called again. Reading the line status port outside of siointr1() 2282169691Skan * is safe because CS_BUSY is clear so there are no output interrupts 2283169691Skan * to lose. 2284169691Skan */ 2285169691Skan s = spltty(); 2286169691Skan if (com->state & CS_BUSY) 2287169691Skan com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */ 2288169691Skan#ifdef PC98 2289169691Skan else if ((IS_8251(com->pc98_if_type) && 2290169691Skan ((com->pc98_8251fifo_enable && 2291169691Skan (inb(I8251F_lsr) & (STS8251F_TxRDY | STS8251F_TxEMP)) 2292169691Skan == (STS8251F_TxRDY | STS8251F_TxEMP)) || 2293169691Skan (!com->pc98_8251fifo_enable && 2294169691Skan (inb(com->sts_port) & (STS8251_TxRDY | STS8251_TxEMP)) 2295169691Skan == (STS8251_TxRDY | STS8251_TxEMP)))) || 2296169691Skan ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2297169691Skan == (LSR_TSRE | LSR_TXRDY))) { 2298169691Skan#else 2299169691Skan else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 2300169691Skan == (LSR_TSRE | LSR_TXRDY)) { 2301169691Skan#endif 2302169691Skan com->tp->t_state &= ~TS_BUSY; 2303169691Skan ttwwakeup(com->tp); 2304169691Skan com->extra_state &= ~CSE_BUSYCHECK; 2305169691Skan } else 2306169691Skan timeout(siobusycheck, com, hz / 100); 2307169691Skan splx(s); 2308169691Skan} 2309169691Skan 2310169691Skanstatic u_int 2311169691Skansiodivisor(rclk, speed) 2312169691Skan u_long rclk; 2313169691Skan speed_t speed; 2314169691Skan{ 2315169691Skan long actual_speed; 2316169691Skan u_int divisor; 2317169691Skan int error; 2318169691Skan 2319169691Skan if (speed == 0 || speed > (ULONG_MAX - 1) / 8) 2320169691Skan return (0); 2321169691Skan divisor = (rclk / (8UL * speed) + 1) / 2; 2322169691Skan if (divisor == 0 || divisor >= 65536) 2323169691Skan return (0); 2324169691Skan actual_speed = rclk / (16UL * divisor); 2325169691Skan 2326169691Skan /* 10 times error in percent: */ 2327169691Skan error = ((actual_speed - (long)speed) * 2000 / (long)speed + 1) / 2; 2328169691Skan 2329169691Skan /* 3.0% maximum error tolerance: */ 2330169691Skan if (error < -30 || error > 30) 2331169691Skan return (0); 2332169691Skan 2333169691Skan return (divisor); 2334169691Skan} 2335169691Skan 2336169691Skanstatic void 2337169691Skansiodtrwakeup(chan) 2338169691Skan void *chan; 2339169691Skan{ 2340169691Skan struct com_s *com; 2341169691Skan 2342169691Skan com = (struct com_s *)chan; 2343169691Skan com->state &= ~CS_DTR_OFF; 2344169691Skan wakeup(&com->dtr_wait); 2345169691Skan} 2346169691Skan 2347169691Skan/* 2348169691Skan * Call this function with the sio_lock mutex held. It will return with the 2349169691Skan * lock still held. 2350169691Skan */ 2351169691Skanstatic void 2352169691Skansioinput(com) 2353169691Skan struct com_s *com; 2354169691Skan{ 2355169691Skan u_char *buf; 2356169691Skan int incc; 2357169691Skan u_char line_status; 2358169691Skan int recv_data; 2359169691Skan struct tty *tp; 2360169691Skan 2361169691Skan buf = com->ibuf; 2362169691Skan tp = com->tp; 2363169691Skan if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) { 2364169691Skan com_events -= (com->iptr - com->ibuf); 2365169691Skan com->iptr = com->ibuf; 2366169691Skan return; 2367169691Skan } 2368169691Skan if (tp->t_state & TS_CAN_BYPASS_L_RINT) { 2369169691Skan /* 2370169691Skan * Avoid the grotesquely inefficient lineswitch routine 2371169691Skan * (ttyinput) in "raw" mode. It usually takes about 450 2372169691Skan * instructions (that's without canonical processing or echo!). 2373169691Skan * slinput is reasonably fast (usually 40 instructions plus 2374169691Skan * call overhead). 2375169691Skan */ 2376169691Skan do { 2377169691Skan /* 2378169691Skan * This may look odd, but it is using save-and-enable 2379169691Skan * semantics instead of the save-and-disable semantics 2380169691Skan * that are used everywhere else. 2381169691Skan */ 2382169691Skan mtx_unlock_spin(&sio_lock); 2383169691Skan incc = com->iptr - buf; 2384169691Skan if (tp->t_rawq.c_cc + incc > tp->t_ihiwat 2385169691Skan && (com->state & CS_RTS_IFLOW 2386169691Skan || tp->t_iflag & IXOFF) 2387169691Skan && !(tp->t_state & TS_TBLOCK)) 2388169691Skan ttyblock(tp); 2389169691Skan com->delta_error_counts[CE_TTY_BUF_OVERFLOW] 2390169691Skan += b_to_q((char *)buf, incc, &tp->t_rawq); 2391169691Skan buf += incc; 2392169691Skan tk_nin += incc; 2393169691Skan tk_rawcc += incc; 2394169691Skan tp->t_rawcc += incc; 2395169691Skan ttwakeup(tp); 2396169691Skan if (tp->t_state & TS_TTSTOP 2397169691Skan && (tp->t_iflag & IXANY 2398169691Skan || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) { 2399169691Skan tp->t_state &= ~TS_TTSTOP; 2400169691Skan tp->t_lflag &= ~FLUSHO; 2401169691Skan comstart(tp); 2402169691Skan } 2403169691Skan mtx_lock_spin(&sio_lock); 2404169691Skan } while (buf < com->iptr); 2405169691Skan } else { 2406169691Skan do { 2407169691Skan /* 2408169691Skan * This may look odd, but it is using save-and-enable 2409169691Skan * semantics instead of the save-and-disable semantics 2410169691Skan * that are used everywhere else. 2411169691Skan */ 2412169691Skan mtx_unlock_spin(&sio_lock); 2413169691Skan line_status = buf[com->ierroff]; 2414169691Skan recv_data = *buf++; 2415169691Skan if (line_status 2416169691Skan & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) { 2417169691Skan if (line_status & LSR_BI) 2418169691Skan recv_data |= TTY_BI; 2419169691Skan if (line_status & LSR_FE) 2420169691Skan recv_data |= TTY_FE; 2421169691Skan if (line_status & LSR_OE) 2422169691Skan recv_data |= TTY_OE; 2423169691Skan if (line_status & LSR_PE) 2424169691Skan recv_data |= TTY_PE; 2425169691Skan } 2426169691Skan (*linesw[tp->t_line].l_rint)(recv_data, tp); 2427169691Skan mtx_lock_spin(&sio_lock); 2428169691Skan } while (buf < com->iptr); 2429169691Skan } 2430169691Skan com_events -= (com->iptr - com->ibuf); 2431169691Skan com->iptr = com->ibuf; 2432169691Skan 2433169691Skan /* 2434169691Skan * There is now room for another low-level buffer full of input, 2435169691Skan * so enable RTS if it is now disabled and there is room in the 2436169691Skan * high-level buffer. 2437169691Skan */ 2438169691Skan#ifdef PC98 2439169691Skan if (IS_8251(com->pc98_if_type)) { 2440169691Skan if ((com->state & CS_RTS_IFLOW) && 2441169691Skan !(com_tiocm_get(com) & TIOCM_RTS) && 2442169691Skan !(tp->t_state & TS_TBLOCK)) 2443169691Skan com_tiocm_bis(com, TIOCM_RTS); 2444169691Skan } else { 2445169691Skan if ((com->state & CS_RTS_IFLOW) && 2446169691Skan !(com->mcr_image & MCR_RTS) && 2447169691Skan !(tp->t_state & TS_TBLOCK)) 2448169691Skan outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2449169691Skan } 2450169691Skan#else 2451169691Skan if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) && 2452169691Skan !(tp->t_state & TS_TBLOCK)) 2453169691Skan outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2454169691Skan#endif 2455169691Skan} 2456169691Skan 2457169691Skanvoid 2458169691Skansiointr(arg) 2459169691Skan void *arg; 2460169691Skan{ 2461169691Skan struct com_s *com; 2462169691Skan#ifdef PC98 2463169691Skan u_char rsa_buf_status; 2464169691Skan#endif 2465169691Skan 2466169691Skan#ifndef COM_MULTIPORT 2467169691Skan com = (struct com_s *)arg; 2468169691Skan 2469169691Skan mtx_lock_spin(&sio_lock); 2470169691Skan siointr1(com); 2471169691Skan mtx_unlock_spin(&sio_lock); 2472169691Skan#else /* COM_MULTIPORT */ 2473169691Skan bool_t possibly_more_intrs; 2474169691Skan int unit; 2475169691Skan 2476169691Skan /* 2477169691Skan * Loop until there is no activity on any port. This is necessary 2478169691Skan * to get an interrupt edge more than to avoid another interrupt. 2479169691Skan * If the IRQ signal is just an OR of the IRQ signals from several 2480169691Skan * devices, then the edge from one may be lost because another is 2481169691Skan * on. 2482169691Skan */ 2483169691Skan mtx_lock_spin(&sio_lock); 2484169691Skan do { 2485169691Skan possibly_more_intrs = FALSE; 2486169691Skan for (unit = 0; unit < sio_numunits; ++unit) { 2487169691Skan com = com_addr(unit); 2488169691Skan /* 2489169691Skan * XXX COM_LOCK(); 2490169691Skan * would it work here, or be counter-productive? 2491169691Skan */ 2492169691Skan#ifdef PC98 2493169691Skan if (com != NULL 2494169691Skan && !com->gone 2495169691Skan && IS_8251(com->pc98_if_type)) { 2496169691Skan siointr1(com); 2497169691Skan } else if (com != NULL 2498169691Skan && !com->gone 2499169691Skan && com->pc98_if_type == COM_IF_RSA98III) { 2500169691Skan rsa_buf_status = 2501169691Skan inb(com->rsabase + rsa_srr) & 0xc9; 2502169691Skan if ((rsa_buf_status & 0xc8) 2503169691Skan || !(rsa_buf_status & 0x01)) { 2504169691Skan siointr1(com); 2505169691Skan if (rsa_buf_status != 2506169691Skan (inb(com->rsabase + rsa_srr) & 0xc9)) 2507169691Skan possibly_more_intrs = TRUE; 2508169691Skan } 2509169691Skan } else 2510169691Skan#endif 2511169691Skan if (com != NULL 2512169691Skan && !com->gone 2513169691Skan && (inb(com->int_id_port) & IIR_IMASK) 2514169691Skan != IIR_NOPEND) { 2515169691Skan siointr1(com); 2516169691Skan possibly_more_intrs = TRUE; 2517169691Skan } 2518169691Skan /* XXX COM_UNLOCK(); */ 2519169691Skan } 2520169691Skan } while (possibly_more_intrs); 2521169691Skan mtx_unlock_spin(&sio_lock); 2522169691Skan#endif /* COM_MULTIPORT */ 2523169691Skan} 2524169691Skan 2525169691Skanstatic struct timespec siots[8192]; 2526169691Skanstatic int siotso; 2527169691Skanstatic int volatile siotsunit = -1; 2528169691Skan 2529169691Skanstatic int 2530169691Skansysctl_siots(SYSCTL_HANDLER_ARGS) 2531169691Skan{ 2532169691Skan char buf[128]; 2533169691Skan long long delta; 2534169691Skan size_t len; 2535169691Skan int error, i; 2536169691Skan 2537169691Skan for (i = 1; i < siotso; i++) { 2538169691Skan delta = (long long)(siots[i].tv_sec - siots[i - 1].tv_sec) * 2539169691Skan 1000000000 + 2540169691Skan (siots[i].tv_nsec - siots[i - 1].tv_nsec); 2541169691Skan len = sprintf(buf, "%lld\n", delta); 2542169691Skan if (delta >= 110000) 2543169691Skan len += sprintf(buf + len - 1, ": *** %ld.%09ld\n", 2544169691Skan (long)siots[i].tv_sec, siots[i].tv_nsec); 2545169691Skan if (i == siotso - 1) 2546169691Skan buf[len - 1] = '\0'; 2547169691Skan error = SYSCTL_OUT(req, buf, len); 2548169691Skan if (error != 0) 2549169691Skan return (error); 2550169691Skan uio_yield(); 2551169691Skan } 2552169691Skan return (0); 2553169691Skan} 2554169691Skan 2555169691SkanSYSCTL_PROC(_machdep, OID_AUTO, siots, CTLTYPE_STRING | CTLFLAG_RD, 2556169691Skan 0, 0, sysctl_siots, "A", "sio timestamps"); 2557169691Skan 2558169691Skanstatic void 2559169691Skansiointr1(com) 2560169691Skan struct com_s *com; 2561169691Skan{ 2562169691Skan u_char line_status; 2563169691Skan u_char modem_status; 2564169691Skan u_char *ioptr; 2565169691Skan u_char recv_data; 2566169691Skan u_char int_ctl; 2567169691Skan u_char int_ctl_new; 2568169691Skan 2569169691Skan#ifdef PC98 2570169691Skan u_char tmp = 0; 2571169691Skan u_char rsa_buf_status = 0; 2572169691Skan int rsa_tx_fifo_size = 0; 2573169691Skan#endif /* PC98 */ 2574169691Skan 2575169691Skan int_ctl = inb(com->intr_ctl_port); 2576169691Skan int_ctl_new = int_ctl; 2577169691Skan 2578169691Skan while (!com->gone) { 2579169691Skan#ifdef PC98 2580169691Skanstatus_read:; 2581169691Skan if (IS_8251(com->pc98_if_type)) { 2582169691Skan if (com->pc98_8251fifo_enable) 2583169691Skan tmp = inb(I8251F_lsr); 2584169691Skan else 2585169691Skan tmp = inb(com->sts_port); 2586169691Skanmore_intr: 2587169691Skan line_status = 0; 2588169691Skan if (com->pc98_8251fifo_enable) { 2589169691Skan if (tmp & STS8251F_TxRDY) line_status |= LSR_TXRDY; 2590169691Skan if (tmp & STS8251F_RxRDY) line_status |= LSR_RXRDY; 2591169691Skan if (tmp & STS8251F_TxEMP) line_status |= LSR_TSRE; 2592169691Skan if (tmp & STS8251F_PE) line_status |= LSR_PE; 2593169691Skan if (tmp & STS8251F_OE) line_status |= LSR_OE; 2594169691Skan if (tmp & STS8251F_BD_SD) line_status |= LSR_BI; 2595169691Skan } else { 2596169691Skan if (tmp & STS8251_TxRDY) line_status |= LSR_TXRDY; 2597169691Skan if (tmp & STS8251_RxRDY) line_status |= LSR_RXRDY; 2598169691Skan if (tmp & STS8251_TxEMP) line_status |= LSR_TSRE; 2599169691Skan if (tmp & STS8251_PE) line_status |= LSR_PE; 2600169691Skan if (tmp & STS8251_OE) line_status |= LSR_OE; 2601169691Skan if (tmp & STS8251_FE) line_status |= LSR_FE; 2602169691Skan if (tmp & STS8251_BD_SD) line_status |= LSR_BI; 2603169691Skan } 2604169691Skan } else { 2605169691Skan#endif /* PC98 */ 2606169691Skan if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) { 2607169691Skan modem_status = inb(com->modem_status_port); 2608169691Skan if ((modem_status ^ com->last_modem_status) & MSR_DCD) { 2609169691Skan pps_capture(&com->pps); 2610169691Skan pps_event(&com->pps, (modem_status & MSR_DCD) ? 2611169691Skan PPS_CAPTUREASSERT : PPS_CAPTURECLEAR); 2612169691Skan } 2613169691Skan } 2614169691Skan line_status = inb(com->line_status_port); 2615169691Skan#ifdef PC98 2616169691Skan } 2617169691Skan if (com->pc98_if_type == COM_IF_RSA98III) 2618169691Skan rsa_buf_status = inb(com->rsabase + rsa_srr); 2619169691Skan#endif /* PC98 */ 2620169691Skan 2621169691Skan /* input event? (check first to help avoid overruns) */ 2622169691Skan#ifndef PC98 2623169691Skan while (line_status & LSR_RCV_MASK) { 2624169691Skan#else 2625169691Skan while ((line_status & LSR_RCV_MASK) 2626169691Skan || (com->pc98_if_type == COM_IF_RSA98III 2627169691Skan && (rsa_buf_status & 0x08))) { 2628169691Skan#endif /* PC98 */ 2629169691Skan /* break/unnattached error bits or real input? */ 2630169691Skan#ifdef PC98 2631169691Skan if (IS_8251(com->pc98_if_type)) { 2632169691Skan if (com->pc98_8251fifo_enable) { 2633169691Skan recv_data = inb(I8251F_data); 2634169691Skan if (tmp & (STS8251F_PE | STS8251F_OE | 2635169691Skan STS8251F_BD_SD)) { 2636169691Skan pc98_i8251_or_cmd(com, CMD8251_ER); 2637169691Skan recv_data = 0; 2638169691Skan } 2639169691Skan } else { 2640169691Skan recv_data = inb(com->data_port); 2641169691Skan if (tmp & (STS8251_PE | STS8251_OE | 2642169691Skan STS8251_FE | STS8251_BD_SD)) { 2643169691Skan pc98_i8251_or_cmd(com, CMD8251_ER); 2644169691Skan recv_data = 0; 2645169691Skan } 2646169691Skan } 2647169691Skan } else if (com->pc98_if_type == COM_IF_RSA98III) { 2648169691Skan if (!(rsa_buf_status & 0x08)) 2649169691Skan recv_data = 0; 2650169691Skan else 2651169691Skan recv_data = inb(com->data_port); 2652169691Skan } else 2653169691Skan#endif 2654169691Skan if (!(line_status & LSR_RXRDY)) 2655169691Skan recv_data = 0; 2656169691Skan else 2657169691Skan recv_data = inb(com->data_port); 2658169691Skan#if defined(DDB) && defined(ALT_BREAK_TO_DEBUGGER) 2659169691Skan /* 2660169691Skan * Solaris implements a new BREAK which is initiated 2661169691Skan * by a character sequence CR ~ ^b which is similar 2662169691Skan * to a familiar pattern used on Sun servers by the 2663169691Skan * Remote Console. 2664169691Skan */ 2665169691Skan#define KEY_CRTLB 2 /* ^B */ 2666169691Skan#define KEY_CR 13 /* CR '\r' */ 2667169691Skan#define KEY_TILDE 126 /* ~ */ 2668169691Skan 2669169691Skan if (com->unit == comconsole) { 2670169691Skan static int brk_state1 = 0, brk_state2 = 0; 2671169691Skan if (recv_data == KEY_CR) { 2672169691Skan brk_state1 = recv_data; 2673169691Skan brk_state2 = 0; 2674169691Skan } else if (brk_state1 == KEY_CR && (recv_data == KEY_TILDE || recv_data == KEY_CRTLB)) { 2675169691Skan if (recv_data == KEY_TILDE) 2676169691Skan brk_state2 = recv_data; 2677169691Skan else if (brk_state2 == KEY_TILDE && recv_data == KEY_CRTLB) { 2678169691Skan breakpoint(); 2679169691Skan brk_state1 = brk_state2 = 0; 2680169691Skan goto cont; 2681169691Skan } else 2682169691Skan brk_state2 = 0; 2683169691Skan } else 2684169691Skan brk_state1 = 0; 2685169691Skan } 2686169691Skan#endif 2687169691Skan if (line_status & (LSR_BI | LSR_FE | LSR_PE)) { 2688169691Skan /* 2689169691Skan * Don't store BI if IGNBRK or FE/PE if IGNPAR. 2690169691Skan * Otherwise, push the work to a higher level 2691169691Skan * (to handle PARMRK) if we're bypassing. 2692169691Skan * Otherwise, convert BI/FE and PE+INPCK to 0. 2693169691Skan * 2694169691Skan * This makes bypassing work right in the 2695169691Skan * usual "raw" case (IGNBRK set, and IGNPAR 2696169691Skan * and INPCK clear). 2697169691Skan * 2698169691Skan * Note: BI together with FE/PE means just BI. 2699169691Skan */ 2700169691Skan if (line_status & LSR_BI) { 2701169691Skan#if defined(DDB) && defined(BREAK_TO_DEBUGGER) 2702169691Skan if (com->unit == comconsole) { 2703169691Skan breakpoint(); 2704169691Skan goto cont; 2705169691Skan } 2706169691Skan#endif 2707169691Skan if (com->tp == NULL 2708169691Skan || com->tp->t_iflag & IGNBRK) 2709169691Skan goto cont; 2710169691Skan } else { 2711169691Skan if (com->tp == NULL 2712169691Skan || com->tp->t_iflag & IGNPAR) 2713169691Skan goto cont; 2714169691Skan } 2715169691Skan if (com->tp->t_state & TS_CAN_BYPASS_L_RINT 2716169691Skan && (line_status & (LSR_BI | LSR_FE) 2717169691Skan || com->tp->t_iflag & INPCK)) 2718169691Skan recv_data = 0; 2719169691Skan } 2720169691Skan ++com->bytes_in; 2721169691Skan if (com->hotchar != 0 && recv_data == com->hotchar) 2722169691Skan swi_sched(sio_fast_ih, 0); 2723169691Skan ioptr = com->iptr; 2724169691Skan if (ioptr >= com->ibufend) 2725169691Skan CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW); 2726169691Skan else { 2727169691Skan if (com->do_timestamp) 2728169691Skan microtime(&com->timestamp); 2729169691Skan ++com_events; 2730169691Skan swi_sched(sio_slow_ih, SWI_DELAY); 2731169691Skan#if 0 /* for testing input latency vs efficiency */ 2732169691Skanif (com->iptr - com->ibuf == 8) 2733169691Skan swi_sched(sio_fast_ih, 0); 2734169691Skan#endif 2735169691Skan ioptr[0] = recv_data; 2736169691Skan ioptr[com->ierroff] = line_status; 2737169691Skan com->iptr = ++ioptr; 2738169691Skan if (ioptr == com->ihighwater 2739169691Skan && com->state & CS_RTS_IFLOW) 2740169691Skan#ifdef PC98 2741169691Skan IS_8251(com->pc98_if_type) ? 2742169691Skan com_tiocm_bic(com, TIOCM_RTS) : 2743169691Skan#endif 2744169691Skan outb(com->modem_ctl_port, 2745169691Skan com->mcr_image &= ~MCR_RTS); 2746169691Skan if (line_status & LSR_OE) 2747169691Skan CE_RECORD(com, CE_OVERRUN); 2748169691Skan } 2749169691Skancont: 2750169691Skan /* 2751169691Skan * "& 0x7F" is to avoid the gcc-1.40 generating a slow 2752169691Skan * jump from the top of the loop to here 2753169691Skan */ 2754169691Skan#ifdef PC98 2755169691Skan if (IS_8251(com->pc98_if_type)) 2756169691Skan goto status_read; 2757169691Skan else 2758169691Skan#endif 2759169691Skan line_status = inb(com->line_status_port) & 0x7F; 2760169691Skan#ifdef PC98 2761169691Skan if (com->pc98_if_type == COM_IF_RSA98III) 2762169691Skan rsa_buf_status = inb(com->rsabase + rsa_srr); 2763169691Skan#endif /* PC98 */ 2764169691Skan } 2765169691Skan 2766169691Skan /* modem status change? (always check before doing output) */ 2767169691Skan#ifdef PC98 2768169691Skan if (!IS_8251(com->pc98_if_type)) { 2769169691Skan#endif 2770169691Skan modem_status = inb(com->modem_status_port); 2771169691Skan if (modem_status != com->last_modem_status) { 2772169691Skan if (com->do_dcd_timestamp 2773169691Skan && !(com->last_modem_status & MSR_DCD) 2774169691Skan && modem_status & MSR_DCD) 2775169691Skan microtime(&com->dcd_timestamp); 2776169691Skan 2777169691Skan /* 2778169691Skan * Schedule high level to handle DCD changes. Note 2779169691Skan * that we don't use the delta bits anywhere. Some 2780169691Skan * UARTs mess them up, and it's easy to remember the 2781169691Skan * previous bits and calculate the delta. 2782169691Skan */ 2783169691Skan com->last_modem_status = modem_status; 2784169691Skan if (!(com->state & CS_CHECKMSR)) { 2785169691Skan com_events += LOTS_OF_EVENTS; 2786169691Skan com->state |= CS_CHECKMSR; 2787169691Skan swi_sched(sio_fast_ih, 0); 2788169691Skan } 2789169691Skan 2790169691Skan /* handle CTS change immediately for crisp flow ctl */ 2791169691Skan if (com->state & CS_CTS_OFLOW) { 2792169691Skan if (modem_status & MSR_CTS) 2793169691Skan com->state |= CS_ODEVREADY; 2794169691Skan else 2795169691Skan com->state &= ~CS_ODEVREADY; 2796169691Skan } 2797169691Skan } 2798169691Skan#ifdef PC98 2799169691Skan } 2800169691Skan#endif 2801169691Skan 2802169691Skan /* output queued and everything ready? */ 2803169691Skan#ifndef PC98 2804169691Skan if (line_status & LSR_TXRDY 2805169691Skan && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 2806169691Skan#else 2807169691Skan if (((com->pc98_if_type == COM_IF_RSA98III) 2808169691Skan ? (rsa_buf_status & 0x02) 2809169691Skan : (line_status & LSR_TXRDY)) 2810169691Skan && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 2811169691Skan#endif 2812169691Skan#ifdef PC98 2813169691Skan Port_t tmp_data_port; 2814169691Skan 2815169691Skan if (IS_8251(com->pc98_if_type) && 2816169691Skan com->pc98_8251fifo_enable) 2817169691Skan tmp_data_port = I8251F_data; 2818169691Skan else 2819169691Skan tmp_data_port = com->data_port; 2820169691Skan#endif 2821169691Skan 2822169691Skan ioptr = com->obufq.l_head; 2823169691Skan if (com->tx_fifo_size > 1 && com->unit != siotsunit) { 2824169691Skan u_int ocount; 2825169691Skan 2826169691Skan ocount = com->obufq.l_tail - ioptr; 2827169691Skan#ifdef PC98 2828169691Skan if (com->pc98_if_type == COM_IF_RSA98III) { 2829169691Skan rsa_buf_status = inb(com->rsabase + rsa_srr); 2830169691Skan rsa_tx_fifo_size = 1024; 2831169691Skan if (!(rsa_buf_status & 0x01)) 2832169691Skan rsa_tx_fifo_size = 2048; 2833169691Skan if (ocount > rsa_tx_fifo_size) 2834169691Skan ocount = rsa_tx_fifo_size; 2835169691Skan } else 2836169691Skan#endif 2837169691Skan if (ocount > com->tx_fifo_size) 2838169691Skan ocount = com->tx_fifo_size; 2839169691Skan com->bytes_out += ocount; 2840169691Skan do 2841169691Skan#ifdef PC98 2842169691Skan outb(tmp_data_port, *ioptr++); 2843169691Skan#else 2844169691Skan outb(com->data_port, *ioptr++); 2845169691Skan#endif 2846169691Skan while (--ocount != 0); 2847169691Skan } else { 2848169691Skan#ifdef PC98 2849169691Skan outb(tmp_data_port, *ioptr++); 2850169691Skan#else 2851169691Skan outb(com->data_port, *ioptr++); 2852169691Skan#endif 2853169691Skan ++com->bytes_out; 2854169691Skan if (com->unit == siotsunit) { 2855169691Skan nanouptime(&siots[siotso]); 2856169691Skan siotso = (siotso + 1) % 2857169691Skan (sizeof siots / sizeof siots[0]); 2858169691Skan } 2859169691Skan } 2860169691Skan#ifdef PC98 2861169691Skan if (IS_8251(com->pc98_if_type)) 2862169691Skan if (!(pc98_check_i8251_interrupt(com) & IEN_TxFLAG)) 2863169691Skan com_int_Tx_enable(com); 2864169691Skan#endif 2865169691Skan com->obufq.l_head = ioptr; 2866169691Skan if (COM_IIR_TXRDYBUG(com->flags)) { 2867169691Skan int_ctl_new = int_ctl | IER_ETXRDY; 2868169691Skan } 2869169691Skan if (ioptr >= com->obufq.l_tail) { 2870169691Skan struct lbq *qp; 2871169691Skan 2872169691Skan qp = com->obufq.l_next; 2873169691Skan qp->l_queued = FALSE; 2874169691Skan qp = qp->l_next; 2875169691Skan if (qp != NULL) { 2876169691Skan com->obufq.l_head = qp->l_head; 2877169691Skan com->obufq.l_tail = qp->l_tail; 2878169691Skan com->obufq.l_next = qp; 2879169691Skan } else { 2880169691Skan /* output just completed */ 2881169691Skan if (COM_IIR_TXRDYBUG(com->flags)) { 2882169691Skan int_ctl_new = int_ctl & ~IER_ETXRDY; 2883169691Skan } 2884169691Skan com->state &= ~CS_BUSY; 2885169691Skan#if defined(PC98) 2886169691Skan if (IS_8251(com->pc98_if_type) && 2887169691Skan pc98_check_i8251_interrupt(com) & IEN_TxFLAG) 2888169691Skan com_int_Tx_disable(com); 2889169691Skan#endif 2890169691Skan } 2891169691Skan if (!(com->state & CS_ODONE)) { 2892169691Skan com_events += LOTS_OF_EVENTS; 2893169691Skan com->state |= CS_ODONE; 2894169691Skan /* handle at high level ASAP */ 2895169691Skan swi_sched(sio_fast_ih, 0); 2896169691Skan } 2897169691Skan } 2898169691Skan if (COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) { 2899169691Skan#ifdef PC98 2900169691Skan if (com->pc98_if_type == COM_IF_RSA98III) { 2901169691Skan int_ctl_new &= ~(IER_ETXRDY | IER_ERXRDY); 2902169691Skan outb(com->intr_ctl_port, int_ctl_new); 2903169691Skan outb(com->rsabase + rsa_ier, 0x1d); 2904169691Skan } else 2905169691Skan#endif 2906169691Skan outb(com->intr_ctl_port, int_ctl_new); 2907169691Skan } 2908169691Skan } 2909169691Skan#ifdef PC98 2910169691Skan else if (line_status & LSR_TXRDY) { 2911169691Skan if (IS_8251(com->pc98_if_type)) 2912169691Skan if (pc98_check_i8251_interrupt(com) & IEN_TxFLAG) 2913169691Skan com_int_Tx_disable(com); 2914169691Skan } 2915169691Skan if (IS_8251(com->pc98_if_type)) { 2916169691Skan if (com->pc98_8251fifo_enable) { 2917169691Skan if ((tmp = inb(I8251F_lsr)) & STS8251F_RxRDY) 2918169691Skan goto more_intr; 2919169691Skan } else { 2920169691Skan if ((tmp = inb(com->sts_port)) & STS8251_RxRDY) 2921169691Skan goto more_intr; 2922169691Skan } 2923169691Skan } 2924169691Skan#endif 2925169691Skan 2926169691Skan /* finished? */ 2927169691Skan#ifndef COM_MULTIPORT 2928169691Skan#ifdef PC98 2929169691Skan if (IS_8251(com->pc98_if_type)) 2930169691Skan return; 2931169691Skan#endif 2932169691Skan if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND) 2933169691Skan#endif /* COM_MULTIPORT */ 2934169691Skan return; 2935169691Skan } 2936169691Skan} 2937169691Skan 2938169691Skanstatic int 2939169691Skansioioctl(dev, cmd, data, flag, td) 2940169691Skan dev_t dev; 2941169691Skan u_long cmd; 2942169691Skan caddr_t data; 2943169691Skan int flag; 2944169691Skan struct thread *td; 2945169691Skan{ 2946169691Skan struct com_s *com; 2947169691Skan int error; 2948169691Skan int mynor; 2949169691Skan int s; 2950169691Skan struct tty *tp; 2951169691Skan#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 2952169691Skan u_long oldcmd; 2953169691Skan struct termios term; 2954169691Skan#endif 2955169691Skan 2956169691Skan mynor = minor(dev); 2957169691Skan com = com_addr(MINOR_TO_UNIT(mynor)); 2958169691Skan if (com == NULL || com->gone) 2959169691Skan return (ENODEV); 2960169691Skan if (mynor & CONTROL_MASK) { 2961169691Skan struct termios *ct; 2962169691Skan 2963169691Skan switch (mynor & CONTROL_MASK) { 2964169691Skan case CONTROL_INIT_STATE: 2965169691Skan ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in; 2966169691Skan break; 2967169691Skan case CONTROL_LOCK_STATE: 2968169691Skan ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in; 2969169691Skan break; 2970169691Skan default: 2971169691Skan return (ENODEV); /* /dev/nodev */ 2972169691Skan } 2973169691Skan switch (cmd) { 2974169691Skan case TIOCSETA: 2975169691Skan error = suser(td); 2976169691Skan if (error != 0) 2977169691Skan return (error); 2978169691Skan *ct = *(struct termios *)data; 2979169691Skan return (0); 2980169691Skan case TIOCGETA: 2981169691Skan *(struct termios *)data = *ct; 2982169691Skan return (0); 2983169691Skan case TIOCGETD: 2984169691Skan *(int *)data = TTYDISC; 2985169691Skan return (0); 2986169691Skan case TIOCGWINSZ: 2987169691Skan bzero(data, sizeof(struct winsize)); 2988169691Skan return (0); 2989169691Skan default: 2990169691Skan return (ENOTTY); 2991169691Skan } 2992169691Skan } 2993169691Skan tp = com->tp; 2994169691Skan#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 2995169691Skan term = tp->t_termios; 2996169691Skan oldcmd = cmd; 2997169691Skan error = ttsetcompat(tp, &cmd, data, &term); 2998169691Skan if (error != 0) 2999169691Skan return (error); 3000169691Skan if (cmd != oldcmd) 3001169691Skan data = (caddr_t)&term; 3002169691Skan#endif 3003169691Skan if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) { 3004169691Skan int cc; 3005169691Skan struct termios *dt = (struct termios *)data; 3006169691Skan struct termios *lt = mynor & CALLOUT_MASK 3007169691Skan ? &com->lt_out : &com->lt_in; 3008169691Skan 3009169691Skan dt->c_iflag = (tp->t_iflag & lt->c_iflag) 3010169691Skan | (dt->c_iflag & ~lt->c_iflag); 3011169691Skan dt->c_oflag = (tp->t_oflag & lt->c_oflag) 3012169691Skan | (dt->c_oflag & ~lt->c_oflag); 3013169691Skan dt->c_cflag = (tp->t_cflag & lt->c_cflag) 3014169691Skan | (dt->c_cflag & ~lt->c_cflag); 3015169691Skan dt->c_lflag = (tp->t_lflag & lt->c_lflag) 3016169691Skan | (dt->c_lflag & ~lt->c_lflag); 3017169691Skan for (cc = 0; cc < NCCS; ++cc) 3018169691Skan if (lt->c_cc[cc] != 0) 3019169691Skan dt->c_cc[cc] = tp->t_cc[cc]; 3020169691Skan if (lt->c_ispeed != 0) 3021169691Skan dt->c_ispeed = tp->t_ispeed; 3022169691Skan if (lt->c_ospeed != 0) 3023169691Skan dt->c_ospeed = tp->t_ospeed; 3024169691Skan } 3025169691Skan error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, td); 3026169691Skan if (error != ENOIOCTL) 3027169691Skan return (error); 3028169691Skan s = spltty(); 3029169691Skan error = ttioctl(tp, cmd, data, flag); 3030169691Skan disc_optim(tp, &tp->t_termios, com); 3031169691Skan if (error != ENOIOCTL) { 3032169691Skan splx(s); 3033169691Skan return (error); 3034169691Skan } 3035169691Skan#ifdef PC98 3036169691Skan if (IS_8251(com->pc98_if_type)) { 3037169691Skan switch (cmd) { 3038169691Skan case TIOCSBRK: 3039169691Skan com_send_break_on(com); 3040169691Skan break; 3041169691Skan case TIOCCBRK: 3042169691Skan com_send_break_off(com); 3043169691Skan break; 3044169691Skan case TIOCSDTR: 3045169691Skan com_tiocm_bis(com, TIOCM_DTR | TIOCM_RTS); 3046169691Skan break; 3047169691Skan case TIOCCDTR: 3048169691Skan com_tiocm_bic(com, TIOCM_DTR); 3049169691Skan break; 3050169691Skan /* 3051169691Skan * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 3052169691Skan * changes get undone on the next call to comparam(). 3053169691Skan */ 3054169691Skan case TIOCMSET: 3055169691Skan com_tiocm_set(com, *(int *)data); 3056169691Skan break; 3057169691Skan case TIOCMBIS: 3058169691Skan com_tiocm_bis(com, *(int *)data); 3059169691Skan break; 3060169691Skan case TIOCMBIC: 3061169691Skan com_tiocm_bic(com, *(int *)data); 3062169691Skan break; 3063169691Skan case TIOCMGET: 3064169691Skan *(int *)data = com_tiocm_get(com); 3065169691Skan break; 3066169691Skan case TIOCMSDTRWAIT: 3067169691Skan /* must be root since the wait applies to following logins */ 3068169691Skan error = suser(td); 3069169691Skan if (error != 0) { 3070169691Skan splx(s); 3071169691Skan return (error); 3072169691Skan } 3073169691Skan com->dtr_wait = *(int *)data * hz / 100; 3074169691Skan break; 3075169691Skan case TIOCMGDTRWAIT: 3076169691Skan *(int *)data = com->dtr_wait * 100 / hz; 3077169691Skan break; 3078169691Skan case TIOCTIMESTAMP: 3079169691Skan com->do_timestamp = TRUE; 3080169691Skan *(struct timeval *)data = com->timestamp; 3081169691Skan break; 3082169691Skan case TIOCDCDTIMESTAMP: 3083169691Skan com->do_dcd_timestamp = TRUE; 3084169691Skan *(struct timeval *)data = com->dcd_timestamp; 3085169691Skan break; 3086169691Skan default: 3087169691Skan splx(s); 3088169691Skan error = pps_ioctl(cmd, data, &com->pps); 3089169691Skan if (error == ENODEV) 3090169691Skan error = ENOTTY; 3091169691Skan return (error); 3092169691Skan } 3093169691Skan } else { 3094169691Skan#endif 3095169691Skan switch (cmd) { 3096169691Skan case TIOCSBRK: 3097169691Skan sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK); 3098169691Skan break; 3099169691Skan case TIOCCBRK: 3100169691Skan sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 3101169691Skan break; 3102169691Skan case TIOCSDTR: 3103169691Skan (void)commctl(com, TIOCM_DTR, DMBIS); 3104169691Skan break; 3105169691Skan case TIOCCDTR: 3106169691Skan (void)commctl(com, TIOCM_DTR, DMBIC); 3107169691Skan break; 3108169691Skan /* 3109169691Skan * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 3110169691Skan * changes get undone on the next call to comparam(). 3111169691Skan */ 3112169691Skan case TIOCMSET: 3113169691Skan (void)commctl(com, *(int *)data, DMSET); 3114169691Skan break; 3115169691Skan case TIOCMBIS: 3116169691Skan (void)commctl(com, *(int *)data, DMBIS); 3117169691Skan break; 3118169691Skan case TIOCMBIC: 3119169691Skan (void)commctl(com, *(int *)data, DMBIC); 3120169691Skan break; 3121169691Skan case TIOCMGET: 3122169691Skan *(int *)data = commctl(com, 0, DMGET); 3123169691Skan break; 3124169691Skan case TIOCMSDTRWAIT: 3125169691Skan /* must be root since the wait applies to following logins */ 3126169691Skan error = suser(td); 3127169691Skan if (error != 0) { 3128169691Skan splx(s); 3129169691Skan return (error); 3130169691Skan } 3131169691Skan com->dtr_wait = *(int *)data * hz / 100; 3132169691Skan break; 3133169691Skan case TIOCMGDTRWAIT: 3134169691Skan *(int *)data = com->dtr_wait * 100 / hz; 3135169691Skan break; 3136169691Skan case TIOCTIMESTAMP: 3137169691Skan com->do_timestamp = TRUE; 3138169691Skan *(struct timeval *)data = com->timestamp; 3139169691Skan break; 3140169691Skan case TIOCDCDTIMESTAMP: 3141169691Skan com->do_dcd_timestamp = TRUE; 3142169691Skan *(struct timeval *)data = com->dcd_timestamp; 3143169691Skan break; 3144169691Skan default: 3145169691Skan splx(s); 3146169691Skan error = pps_ioctl(cmd, data, &com->pps); 3147169691Skan if (error == ENODEV) 3148 error = ENOTTY; 3149 return (error); 3150 } 3151#ifdef PC98 3152 } 3153#endif 3154 splx(s); 3155 return (0); 3156} 3157 3158/* software interrupt handler for SWI_TTY */ 3159static void 3160siopoll(void *dummy) 3161{ 3162 int unit; 3163 3164 if (com_events == 0) 3165 return; 3166repeat: 3167 for (unit = 0; unit < sio_numunits; ++unit) { 3168 struct com_s *com; 3169 int incc; 3170 struct tty *tp; 3171 3172 com = com_addr(unit); 3173 if (com == NULL) 3174 continue; 3175 tp = com->tp; 3176 if (tp == NULL || com->gone) { 3177 /* 3178 * Discard any events related to never-opened or 3179 * going-away devices. 3180 */ 3181 mtx_lock_spin(&sio_lock); 3182 incc = com->iptr - com->ibuf; 3183 com->iptr = com->ibuf; 3184 if (com->state & CS_CHECKMSR) { 3185 incc += LOTS_OF_EVENTS; 3186 com->state &= ~CS_CHECKMSR; 3187 } 3188 com_events -= incc; 3189 mtx_unlock_spin(&sio_lock); 3190 continue; 3191 } 3192 if (com->iptr != com->ibuf) { 3193 mtx_lock_spin(&sio_lock); 3194 sioinput(com); 3195 mtx_unlock_spin(&sio_lock); 3196 } 3197 if (com->state & CS_CHECKMSR) { 3198 u_char delta_modem_status; 3199 3200#ifdef PC98 3201 if (!IS_8251(com->pc98_if_type)) { 3202#endif 3203 mtx_lock_spin(&sio_lock); 3204 delta_modem_status = com->last_modem_status 3205 ^ com->prev_modem_status; 3206 com->prev_modem_status = com->last_modem_status; 3207 com_events -= LOTS_OF_EVENTS; 3208 com->state &= ~CS_CHECKMSR; 3209 mtx_unlock_spin(&sio_lock); 3210 if (delta_modem_status & MSR_DCD) 3211 (*linesw[tp->t_line].l_modem) 3212 (tp, com->prev_modem_status & MSR_DCD); 3213#ifdef PC98 3214 } 3215#endif 3216 } 3217 if (com->state & CS_ODONE) { 3218 mtx_lock_spin(&sio_lock); 3219 com_events -= LOTS_OF_EVENTS; 3220 com->state &= ~CS_ODONE; 3221 mtx_unlock_spin(&sio_lock); 3222 if (!(com->state & CS_BUSY) 3223 && !(com->extra_state & CSE_BUSYCHECK)) { 3224 timeout(siobusycheck, com, hz / 100); 3225 com->extra_state |= CSE_BUSYCHECK; 3226 } 3227 (*linesw[tp->t_line].l_start)(tp); 3228 } 3229 if (com_events == 0) 3230 break; 3231 } 3232 if (com_events >= LOTS_OF_EVENTS) 3233 goto repeat; 3234} 3235 3236static int 3237comparam(tp, t) 3238 struct tty *tp; 3239 struct termios *t; 3240{ 3241 u_int cfcr; 3242 int cflag; 3243 struct com_s *com; 3244 u_int divisor; 3245 u_char dlbh; 3246 u_char dlbl; 3247 int s; 3248 int unit; 3249#ifdef PC98 3250 u_char param = 0; 3251#endif 3252 3253 unit = DEV_TO_UNIT(tp->t_dev); 3254 com = com_addr(unit); 3255 if (com == NULL) 3256 return (ENODEV); 3257 3258#ifdef PC98 3259 cfcr = 0; 3260 3261 if (IS_8251(com->pc98_if_type)) { 3262 if (pc98_ttspeedtab(com, t->c_ospeed, &divisor) != 0) 3263 return (EINVAL); 3264 } else { 3265#endif 3266 /* do historical conversions */ 3267 if (t->c_ispeed == 0) 3268 t->c_ispeed = t->c_ospeed; 3269 3270 /* check requested parameters */ 3271 if (t->c_ospeed == 0) 3272 divisor = 0; 3273 else { 3274 if (t->c_ispeed != t->c_ospeed) 3275 return (EINVAL); 3276 divisor = siodivisor(com->rclk, t->c_ispeed); 3277 if (divisor == 0) 3278 return (EINVAL); 3279 } 3280#ifdef PC98 3281 } 3282#endif 3283 3284 /* parameters are OK, convert them to the com struct and the device */ 3285 s = spltty(); 3286#ifdef PC98 3287 if (IS_8251(com->pc98_if_type)) { 3288 if (divisor == 0) 3289 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 3290 else 3291 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 3292 } else 3293#endif 3294 if (divisor == 0) 3295 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */ 3296 else 3297 (void)commctl(com, TIOCM_DTR, DMBIS); 3298 cflag = t->c_cflag; 3299#ifdef PC98 3300 if (!IS_8251(com->pc98_if_type)) { 3301#endif 3302 switch (cflag & CSIZE) { 3303 case CS5: 3304 cfcr = CFCR_5BITS; 3305 break; 3306 case CS6: 3307 cfcr = CFCR_6BITS; 3308 break; 3309 case CS7: 3310 cfcr = CFCR_7BITS; 3311 break; 3312 default: 3313 cfcr = CFCR_8BITS; 3314 break; 3315 } 3316 if (cflag & PARENB) { 3317 cfcr |= CFCR_PENAB; 3318 if (!(cflag & PARODD)) 3319 cfcr |= CFCR_PEVEN; 3320 } 3321 if (cflag & CSTOPB) 3322 cfcr |= CFCR_STOPB; 3323 3324 if (com->hasfifo && divisor != 0) { 3325 /* 3326 * Use a fifo trigger level low enough so that the input 3327 * latency from the fifo is less than about 16 msec and 3328 * the total latency is less than about 30 msec. These 3329 * latencies are reasonable for humans. Serial comms 3330 * protocols shouldn't expect anything better since modem 3331 * latencies are larger. 3332 * 3333 * We have to set the FIFO trigger point such that we 3334 * don't overflow it accidently if a serial interrupt 3335 * is delayed. At high speeds, FIFO_RX_HIGH does not 3336 * leave enough slots free. 3337 */ 3338 com->fifo_image = com->unit == siotsunit ? 0 3339 : t->c_ospeed <= 4800 3340 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_MEDH; 3341#ifdef COM_ESP 3342 /* 3343 * The Hayes ESP card needs the fifo DMA mode bit set 3344 * in compatibility mode. If not, it will interrupt 3345 * for each character received. 3346 */ 3347 if (com->esp) 3348 com->fifo_image |= FIFO_DMA_MODE; 3349#endif 3350 sio_setreg(com, com_fifo, com->fifo_image); 3351 } 3352#ifdef PC98 3353 } 3354#endif 3355 3356 /* 3357 * This returns with interrupts disabled so that we can complete 3358 * the speed change atomically. Keeping interrupts disabled is 3359 * especially important while com_data is hidden. 3360 */ 3361 (void) siosetwater(com, t->c_ispeed); 3362 3363#ifdef PC98 3364 if (IS_8251(com->pc98_if_type)) 3365 com_cflag_and_speed_set(com, cflag, t->c_ospeed); 3366 else { 3367#endif 3368 if (divisor != 0) { 3369 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB); 3370 /* 3371 * Only set the divisor registers if they would change, 3372 * since on some 16550 incompatibles (UMC8669F), setting 3373 * them while input is arriving them loses sync until 3374 * data stops arriving. 3375 */ 3376 dlbl = divisor & 0xFF; 3377 if (sio_getreg(com, com_dlbl) != dlbl) 3378 sio_setreg(com, com_dlbl, dlbl); 3379 dlbh = divisor >> 8; 3380 if (sio_getreg(com, com_dlbh) != dlbh) 3381 sio_setreg(com, com_dlbh, dlbh); 3382 } 3383 3384 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr); 3385#ifdef PC98 3386 } 3387#endif 3388 3389 if (!(tp->t_state & TS_TTSTOP)) 3390 com->state |= CS_TTGO; 3391 3392 if (cflag & CRTS_IFLOW) { 3393#ifndef PC98 3394 if (com->st16650a) { 3395 sio_setreg(com, com_cfcr, 0xbf); 3396 sio_setreg(com, com_fifo, 3397 sio_getreg(com, com_fifo) | 0x40); 3398 } 3399#endif 3400 com->state |= CS_RTS_IFLOW; 3401 /* 3402 * If CS_RTS_IFLOW just changed from off to on, the change 3403 * needs to be propagated to MCR_RTS. This isn't urgent, 3404 * so do it later by calling comstart() instead of repeating 3405 * a lot of code from comstart() here. 3406 */ 3407 } else if (com->state & CS_RTS_IFLOW) { 3408 com->state &= ~CS_RTS_IFLOW; 3409 /* 3410 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS 3411 * on here, since comstart() won't do it later. 3412 */ 3413#ifdef PC98 3414 if (IS_8251(com->pc98_if_type)) 3415 com_tiocm_bis(com, TIOCM_RTS); 3416 else 3417 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3418#else 3419 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3420 if (com->st16650a) { 3421 sio_setreg(com, com_cfcr, 0xbf); 3422 sio_setreg(com, com_fifo, 3423 sio_getreg(com, com_fifo) & ~0x40); 3424 } 3425#endif 3426 } 3427 3428 3429 /* 3430 * Set up state to handle output flow control. 3431 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level? 3432 * Now has 10+ msec latency, while CTS flow has 50- usec latency. 3433 */ 3434 com->state |= CS_ODEVREADY; 3435 com->state &= ~CS_CTS_OFLOW; 3436#ifdef PC98 3437 if (com->pc98_if_type == COM_IF_RSA98III) { 3438 param = inb(com->rsabase + rsa_msr); 3439 outb(com->rsabase + rsa_msr, param & 0x14); 3440 } 3441#endif 3442 if (cflag & CCTS_OFLOW) { 3443 com->state |= CS_CTS_OFLOW; 3444#ifdef PC98 3445 if (IS_8251(com->pc98_if_type)) { 3446 if (!(pc98_get_modem_status(com) & TIOCM_CTS)) 3447 com->state &= ~CS_ODEVREADY; 3448 } else { 3449 if (com->pc98_if_type == COM_IF_RSA98III) { 3450 /* Set automatic flow control mode */ 3451 outb(com->rsabase + rsa_msr, param | 0x08); 3452 } else 3453#endif 3454 if (!(com->last_modem_status & MSR_CTS)) 3455 com->state &= ~CS_ODEVREADY; 3456#ifdef PC98 3457 } 3458#else 3459 if (com->st16650a) { 3460 sio_setreg(com, com_cfcr, 0xbf); 3461 sio_setreg(com, com_fifo, 3462 sio_getreg(com, com_fifo) | 0x80); 3463 } 3464 } else { 3465 if (com->st16650a) { 3466 sio_setreg(com, com_cfcr, 0xbf); 3467 sio_setreg(com, com_fifo, 3468 sio_getreg(com, com_fifo) & ~0x80); 3469 } 3470#endif 3471 } 3472 3473#ifdef PC98 3474 if (!IS_8251(com->pc98_if_type)) 3475#endif 3476 sio_setreg(com, com_cfcr, com->cfcr_image); 3477 3478 /* XXX shouldn't call functions while intrs are disabled. */ 3479 disc_optim(tp, t, com); 3480 /* 3481 * Recover from fiddling with CS_TTGO. We used to call siointr1() 3482 * unconditionally, but that defeated the careful discarding of 3483 * stale input in sioopen(). 3484 */ 3485 if (com->state >= (CS_BUSY | CS_TTGO)) 3486 siointr1(com); 3487 3488 mtx_unlock_spin(&sio_lock); 3489 splx(s); 3490 comstart(tp); 3491 if (com->ibufold != NULL) { 3492 free(com->ibufold, M_DEVBUF); 3493 com->ibufold = NULL; 3494 } 3495 return (0); 3496} 3497 3498/* 3499 * This function must be called with the sio_lock mutex released and will 3500 * return with it obtained. 3501 */ 3502static int 3503siosetwater(com, speed) 3504 struct com_s *com; 3505 speed_t speed; 3506{ 3507 int cp4ticks; 3508 u_char *ibuf; 3509 int ibufsize; 3510 struct tty *tp; 3511 3512 /* 3513 * Make the buffer size large enough to handle a softtty interrupt 3514 * latency of about 2 ticks without loss of throughput or data 3515 * (about 3 ticks if input flow control is not used or not honoured, 3516 * but a bit less for CS5-CS7 modes). 3517 */ 3518 cp4ticks = speed / 10 / hz * 4; 3519 for (ibufsize = 128; ibufsize < cp4ticks;) 3520 ibufsize <<= 1; 3521#ifdef PC98 3522 if (com->pc98_if_type == COM_IF_RSA98III) 3523 ibufsize = 2048; 3524#endif 3525 if (ibufsize == com->ibufsize) { 3526 mtx_lock_spin(&sio_lock); 3527 return (0); 3528 } 3529 3530 /* 3531 * Allocate input buffer. The extra factor of 2 in the size is 3532 * to allow for an error byte for each input byte. 3533 */ 3534 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT); 3535 if (ibuf == NULL) { 3536 mtx_lock_spin(&sio_lock); 3537 return (ENOMEM); 3538 } 3539 3540 /* Initialize non-critical variables. */ 3541 com->ibufold = com->ibuf; 3542 com->ibufsize = ibufsize; 3543 tp = com->tp; 3544 if (tp != NULL) { 3545 tp->t_ififosize = 2 * ibufsize; 3546 tp->t_ispeedwat = (speed_t)-1; 3547 tp->t_ospeedwat = (speed_t)-1; 3548 } 3549 3550 /* 3551 * Read current input buffer, if any. Continue with interrupts 3552 * disabled. 3553 */ 3554 mtx_lock_spin(&sio_lock); 3555 if (com->iptr != com->ibuf) 3556 sioinput(com); 3557 3558 /*- 3559 * Initialize critical variables, including input buffer watermarks. 3560 * The external device is asked to stop sending when the buffer 3561 * exactly reaches high water, or when the high level requests it. 3562 * The high level is notified immediately (rather than at a later 3563 * clock tick) when this watermark is reached. 3564 * The buffer size is chosen so the watermark should almost never 3565 * be reached. 3566 * The low watermark is invisibly 0 since the buffer is always 3567 * emptied all at once. 3568 */ 3569 com->iptr = com->ibuf = ibuf; 3570 com->ibufend = ibuf + ibufsize; 3571 com->ierroff = ibufsize; 3572 com->ihighwater = ibuf + 3 * ibufsize / 4; 3573 return (0); 3574} 3575 3576static void 3577comstart(tp) 3578 struct tty *tp; 3579{ 3580 struct com_s *com; 3581 int s; 3582 int unit; 3583 3584 unit = DEV_TO_UNIT(tp->t_dev); 3585 com = com_addr(unit); 3586 if (com == NULL) 3587 return; 3588 s = spltty(); 3589 mtx_lock_spin(&sio_lock); 3590 if (tp->t_state & TS_TTSTOP) 3591 com->state &= ~CS_TTGO; 3592 else 3593 com->state |= CS_TTGO; 3594 if (tp->t_state & TS_TBLOCK) { 3595#ifdef PC98 3596 if (IS_8251(com->pc98_if_type)) { 3597 if ((com_tiocm_get(com) & TIOCM_RTS) && 3598 (com->state & CS_RTS_IFLOW)) 3599 com_tiocm_bic(com, TIOCM_RTS); 3600 } else { 3601 if ((com->mcr_image & MCR_RTS) && 3602 (com->state & CS_RTS_IFLOW)) 3603 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3604 } 3605#else 3606 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW) 3607 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 3608#endif 3609 } else { 3610#ifdef PC98 3611 if (IS_8251(com->pc98_if_type)) { 3612 if (!(com_tiocm_get(com) & TIOCM_RTS) && 3613 com->iptr < com->ihighwater && 3614 com->state & CS_RTS_IFLOW) 3615 com_tiocm_bis(com, TIOCM_RTS); 3616 } else { 3617 if (!(com->mcr_image & MCR_RTS) && 3618 com->iptr < com->ihighwater && 3619 com->state & CS_RTS_IFLOW) 3620 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3621 } 3622#else 3623 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater 3624 && com->state & CS_RTS_IFLOW) 3625 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 3626#endif 3627 } 3628 mtx_unlock_spin(&sio_lock); 3629 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) { 3630 ttwwakeup(tp); 3631 splx(s); 3632 return; 3633 } 3634 if (tp->t_outq.c_cc != 0) { 3635 struct lbq *qp; 3636 struct lbq *next; 3637 3638 if (!com->obufs[0].l_queued) { 3639 com->obufs[0].l_tail 3640 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1, 3641#ifdef PC98 3642 com->obufsize); 3643#else 3644 sizeof com->obuf1); 3645#endif 3646 com->obufs[0].l_next = NULL; 3647 com->obufs[0].l_queued = TRUE; 3648 mtx_lock_spin(&sio_lock); 3649 if (com->state & CS_BUSY) { 3650 qp = com->obufq.l_next; 3651 while ((next = qp->l_next) != NULL) 3652 qp = next; 3653 qp->l_next = &com->obufs[0]; 3654 } else { 3655 com->obufq.l_head = com->obufs[0].l_head; 3656 com->obufq.l_tail = com->obufs[0].l_tail; 3657 com->obufq.l_next = &com->obufs[0]; 3658 com->state |= CS_BUSY; 3659 } 3660 mtx_unlock_spin(&sio_lock); 3661 } 3662 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) { 3663 com->obufs[1].l_tail 3664 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2, 3665#ifdef PC98 3666 com->obufsize); 3667#else 3668 sizeof com->obuf2); 3669#endif 3670 com->obufs[1].l_next = NULL; 3671 com->obufs[1].l_queued = TRUE; 3672 mtx_lock_spin(&sio_lock); 3673 if (com->state & CS_BUSY) { 3674 qp = com->obufq.l_next; 3675 while ((next = qp->l_next) != NULL) 3676 qp = next; 3677 qp->l_next = &com->obufs[1]; 3678 } else { 3679 com->obufq.l_head = com->obufs[1].l_head; 3680 com->obufq.l_tail = com->obufs[1].l_tail; 3681 com->obufq.l_next = &com->obufs[1]; 3682 com->state |= CS_BUSY; 3683 } 3684 mtx_unlock_spin(&sio_lock); 3685 } 3686 tp->t_state |= TS_BUSY; 3687 } 3688 mtx_lock_spin(&sio_lock); 3689 if (com->state >= (CS_BUSY | CS_TTGO)) 3690 siointr1(com); /* fake interrupt to start output */ 3691 mtx_unlock_spin(&sio_lock); 3692 ttwwakeup(tp); 3693 splx(s); 3694} 3695 3696static void 3697comstop(tp, rw) 3698 struct tty *tp; 3699 int rw; 3700{ 3701 struct com_s *com; 3702#ifdef PC98 3703 int rsa98_tmp = 0; 3704#endif 3705 3706 com = com_addr(DEV_TO_UNIT(tp->t_dev)); 3707 if (com == NULL || com->gone) 3708 return; 3709 mtx_lock_spin(&sio_lock); 3710 if (rw & FWRITE) { 3711#ifdef PC98 3712 if (!IS_8251(com->pc98_if_type)) { 3713#endif 3714 if (com->hasfifo) 3715#ifdef COM_ESP 3716 /* XXX avoid h/w bug. */ 3717 if (!com->esp) 3718#endif 3719 sio_setreg(com, com_fifo, 3720 FIFO_XMT_RST | com->fifo_image); 3721#ifdef PC98 3722 if (com->pc98_if_type == COM_IF_RSA98III) 3723 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3724 sio_setreg(com, com_fifo, 3725 FIFO_XMT_RST | com->fifo_image); 3726 } 3727#endif 3728 com->obufs[0].l_queued = FALSE; 3729 com->obufs[1].l_queued = FALSE; 3730 if (com->state & CS_ODONE) 3731 com_events -= LOTS_OF_EVENTS; 3732 com->state &= ~(CS_ODONE | CS_BUSY); 3733 com->tp->t_state &= ~TS_BUSY; 3734 } 3735 if (rw & FREAD) { 3736#ifdef PC98 3737 if (!IS_8251(com->pc98_if_type)) { 3738 if (com->pc98_if_type == COM_IF_RSA98III) 3739 for (rsa98_tmp = 0; rsa98_tmp < 2048; rsa98_tmp++) 3740 sio_getreg(com, com_data); 3741#endif 3742 if (com->hasfifo) 3743#ifdef COM_ESP 3744 /* XXX avoid h/w bug. */ 3745 if (!com->esp) 3746#endif 3747 sio_setreg(com, com_fifo, 3748 FIFO_RCV_RST | com->fifo_image); 3749#ifdef PC98 3750 } 3751#endif 3752 com_events -= (com->iptr - com->ibuf); 3753 com->iptr = com->ibuf; 3754 } 3755 mtx_unlock_spin(&sio_lock); 3756 comstart(tp); 3757} 3758 3759static int 3760commctl(com, bits, how) 3761 struct com_s *com; 3762 int bits; 3763 int how; 3764{ 3765 int mcr; 3766 int msr; 3767 3768 if (how == DMGET) { 3769 bits = TIOCM_LE; /* XXX - always enabled while open */ 3770 mcr = com->mcr_image; 3771 if (mcr & MCR_DTR) 3772 bits |= TIOCM_DTR; 3773 if (mcr & MCR_RTS) 3774 bits |= TIOCM_RTS; 3775 msr = com->prev_modem_status; 3776 if (msr & MSR_CTS) 3777 bits |= TIOCM_CTS; 3778 if (msr & MSR_DCD) 3779 bits |= TIOCM_CD; 3780 if (msr & MSR_DSR) 3781 bits |= TIOCM_DSR; 3782 /* 3783 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI 3784 * more volatile by reading the modem status a lot. Perhaps 3785 * we should latch both bits until the status is read here. 3786 */ 3787 if (msr & (MSR_RI | MSR_TERI)) 3788 bits |= TIOCM_RI; 3789 return (bits); 3790 } 3791 mcr = 0; 3792 if (bits & TIOCM_DTR) 3793 mcr |= MCR_DTR; 3794 if (bits & TIOCM_RTS) 3795 mcr |= MCR_RTS; 3796 if (com->gone) 3797 return(0); 3798 mtx_lock_spin(&sio_lock); 3799 switch (how) { 3800 case DMSET: 3801 outb(com->modem_ctl_port, 3802 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE)); 3803 break; 3804 case DMBIS: 3805 outb(com->modem_ctl_port, com->mcr_image |= mcr); 3806 break; 3807 case DMBIC: 3808 outb(com->modem_ctl_port, com->mcr_image &= ~mcr); 3809 break; 3810 } 3811 mtx_unlock_spin(&sio_lock); 3812 return (0); 3813} 3814 3815static void 3816siosettimeout() 3817{ 3818 struct com_s *com; 3819 bool_t someopen; 3820 int unit; 3821 3822 /* 3823 * Set our timeout period to 1 second if no polled devices are open. 3824 * Otherwise set it to max(1/200, 1/hz). 3825 * Enable timeouts iff some device is open. 3826 */ 3827 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 3828 sio_timeout = hz; 3829 someopen = FALSE; 3830 for (unit = 0; unit < sio_numunits; ++unit) { 3831 com = com_addr(unit); 3832 if (com != NULL && com->tp != NULL 3833 && com->tp->t_state & TS_ISOPEN && !com->gone) { 3834 someopen = TRUE; 3835 if (com->poll || com->poll_output) { 3836 sio_timeout = hz > 200 ? hz / 200 : 1; 3837 break; 3838 } 3839 } 3840 } 3841 if (someopen) { 3842 sio_timeouts_until_log = hz / sio_timeout; 3843 sio_timeout_handle = timeout(comwakeup, (void *)NULL, 3844 sio_timeout); 3845 } else { 3846 /* Flush error messages, if any. */ 3847 sio_timeouts_until_log = 1; 3848 comwakeup((void *)NULL); 3849 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 3850 } 3851} 3852 3853static void 3854comwakeup(chan) 3855 void *chan; 3856{ 3857 struct com_s *com; 3858 int unit; 3859 3860 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout); 3861 3862 /* 3863 * Recover from lost output interrupts. 3864 * Poll any lines that don't use interrupts. 3865 */ 3866 for (unit = 0; unit < sio_numunits; ++unit) { 3867 com = com_addr(unit); 3868 if (com != NULL && !com->gone 3869 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) { 3870 mtx_lock_spin(&sio_lock); 3871 siointr1(com); 3872 mtx_unlock_spin(&sio_lock); 3873 } 3874 } 3875 3876 /* 3877 * Check for and log errors, but not too often. 3878 */ 3879 if (--sio_timeouts_until_log > 0) 3880 return; 3881 sio_timeouts_until_log = hz / sio_timeout; 3882 for (unit = 0; unit < sio_numunits; ++unit) { 3883 int errnum; 3884 3885 com = com_addr(unit); 3886 if (com == NULL) 3887 continue; 3888 if (com->gone) 3889 continue; 3890 for (errnum = 0; errnum < CE_NTYPES; ++errnum) { 3891 u_int delta; 3892 u_long total; 3893 3894 mtx_lock_spin(&sio_lock); 3895 delta = com->delta_error_counts[errnum]; 3896 com->delta_error_counts[errnum] = 0; 3897 mtx_unlock_spin(&sio_lock); 3898 if (delta == 0) 3899 continue; 3900 total = com->error_counts[errnum] += delta; 3901 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n", 3902 unit, delta, error_desc[errnum], 3903 delta == 1 ? "" : "s", total); 3904 } 3905 } 3906} 3907 3908#ifdef PC98 3909/* commint is called when modem control line changes */ 3910static void 3911commint(dev_t dev) 3912{ 3913 register struct tty *tp; 3914 int stat,delta; 3915 struct com_s *com; 3916 int mynor,unit; 3917 3918 mynor = minor(dev); 3919 unit = MINOR_TO_UNIT(mynor); 3920 com = com_addr(unit); 3921 tp = com->tp; 3922 3923 stat = com_tiocm_get(com); 3924 delta = com_tiocm_get_delta(com); 3925 3926 if (com->state & CS_CTS_OFLOW) { 3927 if (stat & TIOCM_CTS) 3928 com->state |= CS_ODEVREADY; 3929 else 3930 com->state &= ~CS_ODEVREADY; 3931 } 3932 if ((delta & TIOCM_CAR) && (mynor & CALLOUT_MASK) == 0) { 3933 if (stat & TIOCM_CAR ) 3934 (void)(*linesw[tp->t_line].l_modem)(tp, 1); 3935 else if ((*linesw[tp->t_line].l_modem)(tp, 0) == 0) { 3936 /* negate DTR, RTS */ 3937 com_tiocm_bic(com, (tp->t_cflag & HUPCL) ? 3938 TIOCM_DTR|TIOCM_RTS|TIOCM_LE : TIOCM_LE ); 3939 /* disable IENABLE */ 3940 com_int_TxRx_disable( com ); 3941 } 3942 } 3943} 3944#endif 3945 3946static void 3947disc_optim(tp, t, com) 3948 struct tty *tp; 3949 struct termios *t; 3950 struct com_s *com; 3951{ 3952 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 3953 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 3954 && (!(t->c_iflag & PARMRK) 3955 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 3956 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 3957 && linesw[tp->t_line].l_rint == ttyinput) 3958 tp->t_state |= TS_CAN_BYPASS_L_RINT; 3959 else 3960 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 3961 com->hotchar = linesw[tp->t_line].l_hotchar; 3962} 3963 3964/* 3965 * Following are all routines needed for SIO to act as console 3966 */ 3967#include <sys/cons.h> 3968 3969struct siocnstate { 3970 u_char dlbl; 3971 u_char dlbh; 3972 u_char ier; 3973 u_char cfcr; 3974 u_char mcr; 3975}; 3976 3977#ifndef __alpha__ 3978static speed_t siocngetspeed(Port_t, u_long rclk); 3979#endif 3980static void siocnclose(struct siocnstate *sp, Port_t iobase); 3981static void siocnopen(struct siocnstate *sp, Port_t iobase, int speed); 3982static void siocntxwait(Port_t iobase); 3983 3984#ifdef __alpha__ 3985int siocnattach(int port, int speed); 3986int siogdbattach(int port, int speed); 3987int siogdbgetc(void); 3988void siogdbputc(int c); 3989#else 3990static cn_probe_t siocnprobe; 3991static cn_init_t siocninit; 3992static cn_term_t siocnterm; 3993#endif 3994static cn_checkc_t siocncheckc; 3995static cn_getc_t siocngetc; 3996static cn_putc_t siocnputc; 3997 3998#ifndef __alpha__ 3999CONS_DRIVER(sio, siocnprobe, siocninit, siocnterm, siocngetc, siocncheckc, 4000 siocnputc, NULL); 4001#endif 4002 4003/* To get the GDB related variables */ 4004#if DDB > 0 4005#include <ddb/ddb.h> 4006#endif 4007 4008static void 4009siocntxwait(iobase) 4010 Port_t iobase; 4011{ 4012 int timo; 4013 4014 /* 4015 * Wait for any pending transmission to finish. Required to avoid 4016 * the UART lockup bug when the speed is changed, and for normal 4017 * transmits. 4018 */ 4019 timo = 100000; 4020 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY)) 4021 != (LSR_TSRE | LSR_TXRDY) && --timo != 0) 4022 ; 4023} 4024 4025#ifndef __alpha__ 4026 4027/* 4028 * Read the serial port specified and try to figure out what speed 4029 * it's currently running at. We're assuming the serial port has 4030 * been initialized and is basicly idle. This routine is only intended 4031 * to be run at system startup. 4032 * 4033 * If the value read from the serial port doesn't make sense, return 0. 4034 */ 4035 4036static speed_t 4037siocngetspeed(iobase, rclk) 4038 Port_t iobase; 4039 u_long rclk; 4040{ 4041 u_int divisor; 4042 u_char dlbh; 4043 u_char dlbl; 4044 u_char cfcr; 4045 4046 cfcr = inb(iobase + com_cfcr); 4047 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 4048 4049 dlbl = inb(iobase + com_dlbl); 4050 dlbh = inb(iobase + com_dlbh); 4051 4052 outb(iobase + com_cfcr, cfcr); 4053 4054 divisor = dlbh << 8 | dlbl; 4055 4056 /* XXX there should be more sanity checking. */ 4057 if (divisor == 0) 4058 return (CONSPEED); 4059 return (rclk / (16UL * divisor)); 4060} 4061 4062#endif 4063 4064static void 4065siocnopen(sp, iobase, speed) 4066 struct siocnstate *sp; 4067 Port_t iobase; 4068 int speed; 4069{ 4070 u_int divisor; 4071 u_char dlbh; 4072 u_char dlbl; 4073 4074 /* 4075 * Save all the device control registers except the fifo register 4076 * and set our default ones (cs8 -parenb speed=comdefaultrate). 4077 * We can't save the fifo register since it is read-only. 4078 */ 4079 sp->ier = inb(iobase + com_ier); 4080 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */ 4081 siocntxwait(iobase); 4082 sp->cfcr = inb(iobase + com_cfcr); 4083 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 4084 sp->dlbl = inb(iobase + com_dlbl); 4085 sp->dlbh = inb(iobase + com_dlbh); 4086 /* 4087 * Only set the divisor registers if they would change, since on 4088 * some 16550 incompatibles (Startech), setting them clears the 4089 * data input register. This also reduces the effects of the 4090 * UMC8669F bug. 4091 */ 4092 divisor = siodivisor(comdefaultrclk, speed); 4093 dlbl = divisor & 0xFF; 4094 if (sp->dlbl != dlbl) 4095 outb(iobase + com_dlbl, dlbl); 4096 dlbh = divisor >> 8; 4097 if (sp->dlbh != dlbh) 4098 outb(iobase + com_dlbh, dlbh); 4099 outb(iobase + com_cfcr, CFCR_8BITS); 4100 sp->mcr = inb(iobase + com_mcr); 4101 /* 4102 * We don't want interrupts, but must be careful not to "disable" 4103 * them by clearing the MCR_IENABLE bit, since that might cause 4104 * an interrupt by floating the IRQ line. 4105 */ 4106 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS); 4107} 4108 4109static void 4110siocnclose(sp, iobase) 4111 struct siocnstate *sp; 4112 Port_t iobase; 4113{ 4114 /* 4115 * Restore the device control registers. 4116 */ 4117 siocntxwait(iobase); 4118 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 4119 if (sp->dlbl != inb(iobase + com_dlbl)) 4120 outb(iobase + com_dlbl, sp->dlbl); 4121 if (sp->dlbh != inb(iobase + com_dlbh)) 4122 outb(iobase + com_dlbh, sp->dlbh); 4123 outb(iobase + com_cfcr, sp->cfcr); 4124 /* 4125 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them. 4126 */ 4127 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS); 4128 outb(iobase + com_ier, sp->ier); 4129} 4130 4131#ifndef __alpha__ 4132 4133static void 4134siocnprobe(cp) 4135 struct consdev *cp; 4136{ 4137 speed_t boot_speed; 4138 u_char cfcr; 4139 u_int divisor; 4140 int s, unit; 4141 struct siocnstate sp; 4142 4143 /* 4144 * Find our first enabled console, if any. If it is a high-level 4145 * console device, then initialize it and return successfully. 4146 * If it is a low-level console device, then initialize it and 4147 * return unsuccessfully. It must be initialized in both cases 4148 * for early use by console drivers and debuggers. Initializing 4149 * the hardware is not necessary in all cases, since the i/o 4150 * routines initialize it on the fly, but it is necessary if 4151 * input might arrive while the hardware is switched back to an 4152 * uninitialized state. We can't handle multiple console devices 4153 * yet because our low-level routines don't take a device arg. 4154 * We trust the user to set the console flags properly so that we 4155 * don't need to probe. 4156 */ 4157 cp->cn_pri = CN_DEAD; 4158 4159 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */ 4160 int flags; 4161 int disabled; 4162 if (resource_int_value("sio", unit, "disabled", &disabled) == 0) { 4163 if (disabled) 4164 continue; 4165 } 4166 if (resource_int_value("sio", unit, "flags", &flags)) 4167 continue; 4168 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) { 4169 int port; 4170 Port_t iobase; 4171 4172 if (resource_int_value("sio", unit, "port", &port)) 4173 continue; 4174 iobase = port; 4175 s = spltty(); 4176 if (boothowto & RB_SERIAL) { 4177 boot_speed = 4178 siocngetspeed(iobase, comdefaultrclk); 4179 if (boot_speed) 4180 comdefaultrate = boot_speed; 4181 } 4182 4183 /* 4184 * Initialize the divisor latch. We can't rely on 4185 * siocnopen() to do this the first time, since it 4186 * avoids writing to the latch if the latch appears 4187 * to have the correct value. Also, if we didn't 4188 * just read the speed from the hardware, then we 4189 * need to set the speed in hardware so that 4190 * switching it later is null. 4191 */ 4192 cfcr = inb(iobase + com_cfcr); 4193 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 4194 divisor = siodivisor(comdefaultrclk, comdefaultrate); 4195 outb(iobase + com_dlbl, divisor & 0xff); 4196 outb(iobase + com_dlbh, divisor >> 8); 4197 outb(iobase + com_cfcr, cfcr); 4198 4199 siocnopen(&sp, iobase, comdefaultrate); 4200 4201 splx(s); 4202 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) { 4203 cp->cn_dev = makedev(CDEV_MAJOR, unit); 4204 cp->cn_pri = COM_FORCECONSOLE(flags) 4205 || boothowto & RB_SERIAL 4206 ? CN_REMOTE : CN_NORMAL; 4207 siocniobase = iobase; 4208 siocnunit = unit; 4209 } 4210 if (COM_DEBUGGER(flags)) { 4211 printf("sio%d: gdb debugging port\n", unit); 4212 siogdbiobase = iobase; 4213 siogdbunit = unit; 4214#if DDB > 0 4215 gdbdev = makedev(CDEV_MAJOR, unit); 4216 gdb_getc = siocngetc; 4217 gdb_putc = siocnputc; 4218#endif 4219 } 4220 } 4221 } 4222#ifdef __i386__ 4223#if DDB > 0 4224 /* 4225 * XXX Ugly Compatability. 4226 * If no gdb port has been specified, set it to be the console 4227 * as some configuration files don't specify the gdb port. 4228 */ 4229 if (gdbdev == NODEV && (boothowto & RB_GDB)) { 4230 printf("Warning: no GDB port specified. Defaulting to sio%d.\n", 4231 siocnunit); 4232 printf("Set flag 0x80 on desired GDB port in your\n"); 4233 printf("configuration file (currently sio only).\n"); 4234 siogdbiobase = siocniobase; 4235 siogdbunit = siocnunit; 4236 gdbdev = makedev(CDEV_MAJOR, siocnunit); 4237 gdb_getc = siocngetc; 4238 gdb_putc = siocnputc; 4239 } 4240#endif 4241#endif 4242} 4243 4244static void 4245siocninit(cp) 4246 struct consdev *cp; 4247{ 4248 comconsole = DEV_TO_UNIT(cp->cn_dev); 4249} 4250 4251static void 4252siocnterm(cp) 4253 struct consdev *cp; 4254{ 4255 comconsole = -1; 4256} 4257 4258#endif 4259 4260#ifdef __alpha__ 4261 4262CONS_DRIVER(sio, NULL, NULL, NULL, siocngetc, siocncheckc, siocnputc, NULL); 4263 4264int 4265siocnattach(port, speed) 4266 int port; 4267 int speed; 4268{ 4269 int s; 4270 u_char cfcr; 4271 u_int divisor; 4272 struct siocnstate sp; 4273 int unit = 0; /* XXX random value! */ 4274 4275 siocniobase = port; 4276 siocnunit = unit; 4277 comdefaultrate = speed; 4278 sio_consdev.cn_pri = CN_NORMAL; 4279 sio_consdev.cn_dev = makedev(CDEV_MAJOR, unit); 4280 4281 s = spltty(); 4282 4283 /* 4284 * Initialize the divisor latch. We can't rely on 4285 * siocnopen() to do this the first time, since it 4286 * avoids writing to the latch if the latch appears 4287 * to have the correct value. Also, if we didn't 4288 * just read the speed from the hardware, then we 4289 * need to set the speed in hardware so that 4290 * switching it later is null. 4291 */ 4292 cfcr = inb(siocniobase + com_cfcr); 4293 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr); 4294 divisor = siodivisor(comdefaultrclk, comdefaultrate); 4295 outb(siocniobase + com_dlbl, divisor & 0xff); 4296 outb(siocniobase + com_dlbh, divisor >> 8); 4297 outb(siocniobase + com_cfcr, cfcr); 4298 4299 siocnopen(&sp, siocniobase, comdefaultrate); 4300 splx(s); 4301 4302 cnadd(&sio_consdev); 4303 return (0); 4304} 4305 4306int 4307siogdbattach(port, speed) 4308 int port; 4309 int speed; 4310{ 4311 int s; 4312 u_char cfcr; 4313 u_int divisor; 4314 struct siocnstate sp; 4315 int unit = 1; /* XXX random value! */ 4316 4317 siogdbiobase = port; 4318 gdbdefaultrate = speed; 4319 4320 printf("sio%d: gdb debugging port\n", unit); 4321 siogdbunit = unit; 4322#if DDB > 0 4323 gdbdev = makedev(CDEV_MAJOR, unit); 4324 gdb_getc = siocngetc; 4325 gdb_putc = siocnputc; 4326#endif 4327 4328 s = spltty(); 4329 4330 /* 4331 * Initialize the divisor latch. We can't rely on 4332 * siocnopen() to do this the first time, since it 4333 * avoids writing to the latch if the latch appears 4334 * to have the correct value. Also, if we didn't 4335 * just read the speed from the hardware, then we 4336 * need to set the speed in hardware so that 4337 * switching it later is null. 4338 */ 4339 cfcr = inb(siogdbiobase + com_cfcr); 4340 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr); 4341 divisor = siodivisor(comdefaultrclk, gdbdefaultrate); 4342 outb(siogdbiobase + com_dlbl, divisor & 0xff); 4343 outb(siogdbiobase + com_dlbh, divisor >> 8); 4344 outb(siogdbiobase + com_cfcr, cfcr); 4345 4346 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 4347 splx(s); 4348 4349 return (0); 4350} 4351 4352#endif 4353 4354static int 4355siocncheckc(dev) 4356 dev_t dev; 4357{ 4358 int c; 4359 Port_t iobase; 4360 int s; 4361 struct siocnstate sp; 4362 speed_t speed; 4363 4364 if (minor(dev) == siocnunit) { 4365 iobase = siocniobase; 4366 speed = comdefaultrate; 4367 } else { 4368 iobase = siogdbiobase; 4369 speed = gdbdefaultrate; 4370 } 4371 s = spltty(); 4372 siocnopen(&sp, iobase, speed); 4373 if (inb(iobase + com_lsr) & LSR_RXRDY) 4374 c = inb(iobase + com_data); 4375 else 4376 c = -1; 4377 siocnclose(&sp, iobase); 4378 splx(s); 4379 return (c); 4380} 4381 4382 4383int 4384siocngetc(dev) 4385 dev_t dev; 4386{ 4387 int c; 4388 Port_t iobase; 4389 int s; 4390 struct siocnstate sp; 4391 speed_t speed; 4392 4393 if (minor(dev) == siocnunit) { 4394 iobase = siocniobase; 4395 speed = comdefaultrate; 4396 } else { 4397 iobase = siogdbiobase; 4398 speed = gdbdefaultrate; 4399 } 4400 s = spltty(); 4401 siocnopen(&sp, iobase, speed); 4402 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 4403 ; 4404 c = inb(iobase + com_data); 4405 siocnclose(&sp, iobase); 4406 splx(s); 4407 return (c); 4408} 4409 4410void 4411siocnputc(dev, c) 4412 dev_t dev; 4413 int c; 4414{ 4415 int need_unlock; 4416 int s; 4417 struct siocnstate sp; 4418 Port_t iobase; 4419 speed_t speed; 4420 4421 if (minor(dev) == siocnunit) { 4422 iobase = siocniobase; 4423 speed = comdefaultrate; 4424 } else { 4425 iobase = siogdbiobase; 4426 speed = gdbdefaultrate; 4427 } 4428 s = spltty(); 4429 need_unlock = 0; 4430 if (sio_inited == 2 && !mtx_owned(&sio_lock)) { 4431 mtx_lock_spin(&sio_lock); 4432 need_unlock = 1; 4433 } 4434 siocnopen(&sp, iobase, speed); 4435 siocntxwait(iobase); 4436 outb(iobase + com_data, c); 4437 siocnclose(&sp, iobase); 4438 if (need_unlock) 4439 mtx_unlock_spin(&sio_lock); 4440 splx(s); 4441} 4442 4443#ifdef __alpha__ 4444int 4445siogdbgetc() 4446{ 4447 int c; 4448 Port_t iobase; 4449 speed_t speed; 4450 int s; 4451 struct siocnstate sp; 4452 4453 if (siogdbunit == siocnunit) { 4454 iobase = siocniobase; 4455 speed = comdefaultrate; 4456 } else { 4457 iobase = siogdbiobase; 4458 speed = gdbdefaultrate; 4459 } 4460 4461 s = spltty(); 4462 siocnopen(&sp, iobase, speed); 4463 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 4464 ; 4465 c = inb(iobase + com_data); 4466 siocnclose(&sp, iobase); 4467 splx(s); 4468 return (c); 4469} 4470 4471void 4472siogdbputc(c) 4473 int c; 4474{ 4475 Port_t iobase; 4476 speed_t speed; 4477 int s; 4478 struct siocnstate sp; 4479 4480 if (siogdbunit == siocnunit) { 4481 iobase = siocniobase; 4482 speed = comdefaultrate; 4483 } else { 4484 iobase = siogdbiobase; 4485 speed = gdbdefaultrate; 4486 } 4487 4488 s = spltty(); 4489 siocnopen(&sp, iobase, speed); 4490 siocntxwait(siogdbiobase); 4491 outb(siogdbiobase + com_data, c); 4492 siocnclose(&sp, siogdbiobase); 4493 splx(s); 4494} 4495#endif 4496 4497#ifdef PC98 4498/* 4499 * pc98 local function 4500 */ 4501 4502static void 4503com_tiocm_set(struct com_s *com, int msr) 4504{ 4505 int s; 4506 int tmp = 0; 4507 int mask = CMD8251_TxEN|CMD8251_RxEN|CMD8251_DTR|CMD8251_RTS; 4508 4509 s=spltty(); 4510 com->pc98_prev_modem_status = ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ) 4511 | ( com->pc98_prev_modem_status & ~(TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4512 tmp |= (CMD8251_TxEN|CMD8251_RxEN); 4513 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4514 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4515 pc98_i8251_clear_or_cmd( com, mask, tmp ); 4516 splx(s); 4517} 4518 4519static void 4520com_tiocm_bis(struct com_s *com, int msr) 4521{ 4522 int s; 4523 int tmp = 0; 4524 4525 s=spltty(); 4526 com->pc98_prev_modem_status |= ( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4527 tmp |= CMD8251_TxEN|CMD8251_RxEN; 4528 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4529 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4530 4531 pc98_i8251_or_cmd( com, tmp ); 4532 splx(s); 4533} 4534 4535static void 4536com_tiocm_bic(struct com_s *com, int msr) 4537{ 4538 int s; 4539 int tmp = msr; 4540 4541 s=spltty(); 4542 com->pc98_prev_modem_status &= ~( msr & (TIOCM_LE|TIOCM_DTR|TIOCM_RTS) ); 4543 if ( msr & TIOCM_DTR ) tmp |= CMD8251_DTR; 4544 if ( msr & TIOCM_RTS ) tmp |= CMD8251_RTS; 4545 4546 pc98_i8251_clear_cmd( com, tmp ); 4547 splx(s); 4548} 4549 4550static int 4551com_tiocm_get(struct com_s *com) 4552{ 4553 return( com->pc98_prev_modem_status ); 4554} 4555 4556static int 4557com_tiocm_get_delta(struct com_s *com) 4558{ 4559 int tmp; 4560 4561 tmp = com->pc98_modem_delta; 4562 com->pc98_modem_delta = 0; 4563 return( tmp ); 4564} 4565 4566/* convert to TIOCM_?? ( ioctl.h ) */ 4567static int 4568pc98_get_modem_status(struct com_s *com) 4569{ 4570 register int msr; 4571 4572 msr = com->pc98_prev_modem_status 4573 & ~(TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 4574 if (com->pc98_8251fifo_enable) { 4575 int stat2; 4576 4577 stat2 = inb(I8251F_msr); 4578 if ( stat2 & CICSCDF_CD ) msr |= TIOCM_CAR; 4579 if ( stat2 & CICSCDF_CI ) msr |= TIOCM_RI; 4580 if ( stat2 & CICSCDF_DR ) msr |= TIOCM_DSR; 4581 if ( stat2 & CICSCDF_CS ) msr |= TIOCM_CTS; 4582#if COM_CARRIER_DETECT_EMULATE 4583 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 4584 msr |= TIOCM_CAR; 4585 } 4586#endif 4587 } else { 4588 int stat, stat2; 4589 4590 stat = inb(com->sts_port); 4591 stat2 = inb(com->in_modem_port); 4592 if ( !(stat2 & CICSCD_CD) ) msr |= TIOCM_CAR; 4593 if ( !(stat2 & CICSCD_CI) ) msr |= TIOCM_RI; 4594 if ( stat & STS8251_DSR ) msr |= TIOCM_DSR; 4595 if ( !(stat2 & CICSCD_CS) ) msr |= TIOCM_CTS; 4596#if COM_CARRIER_DETECT_EMULATE 4597 if ( msr & (TIOCM_DSR|TIOCM_CTS) ) { 4598 msr |= TIOCM_CAR; 4599 } 4600#endif 4601 } 4602 return(msr); 4603} 4604 4605static void 4606pc98_check_msr(void* chan) 4607{ 4608 int msr, delta; 4609 int s; 4610 register struct tty *tp; 4611 struct com_s *com; 4612 int mynor; 4613 int unit; 4614 dev_t dev; 4615 4616 dev=(dev_t)chan; 4617 mynor = minor(dev); 4618 unit = MINOR_TO_UNIT(mynor); 4619 com = com_addr(unit); 4620 tp = com->tp; 4621 4622 s = spltty(); 4623 msr = pc98_get_modem_status(com); 4624 /* make change flag */ 4625 delta = msr ^ com->pc98_prev_modem_status; 4626 if ( delta & TIOCM_CAR ) { 4627 if ( com->modem_car_chg_timer ) { 4628 if ( -- com->modem_car_chg_timer ) 4629 msr ^= TIOCM_CAR; 4630 } else { 4631 if ((com->modem_car_chg_timer = (msr & TIOCM_CAR) ? 4632 DCD_ON_RECOGNITION : DCD_OFF_TOLERANCE) != 0) 4633 msr ^= TIOCM_CAR; 4634 } 4635 } else 4636 com->modem_car_chg_timer = 0; 4637 delta = ( msr ^ com->pc98_prev_modem_status ) & 4638 (TIOCM_CAR|TIOCM_RI|TIOCM_DSR|TIOCM_CTS); 4639 com->pc98_prev_modem_status = msr; 4640 delta = ( com->pc98_modem_delta |= delta ); 4641 splx(s); 4642 if ( com->modem_checking || (tp->t_state & (TS_ISOPEN)) ) { 4643 if ( delta ) { 4644 commint(dev); 4645 } 4646 timeout(pc98_check_msr, (caddr_t)dev, 4647 PC98_CHECK_MODEM_INTERVAL); 4648 } else { 4649 com->modem_checking = 0; 4650 } 4651} 4652 4653static void 4654pc98_msrint_start(dev_t dev) 4655{ 4656 struct com_s *com; 4657 int mynor; 4658 int unit; 4659 int s = spltty(); 4660 4661 mynor = minor(dev); 4662 unit = MINOR_TO_UNIT(mynor); 4663 com = com_addr(unit); 4664 /* modem control line check routine envoke interval is 1/10 sec */ 4665 if ( com->modem_checking == 0 ) { 4666 com->pc98_prev_modem_status = pc98_get_modem_status(com); 4667 com->pc98_modem_delta = 0; 4668 timeout(pc98_check_msr, (caddr_t)dev, 4669 PC98_CHECK_MODEM_INTERVAL); 4670 com->modem_checking = 1; 4671 } 4672 splx(s); 4673} 4674 4675static void 4676pc98_disable_i8251_interrupt(struct com_s *com, int mod) 4677{ 4678 /* disable interrupt */ 4679 register int tmp; 4680 4681 mod |= ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4682 COM_INT_DISABLE 4683 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4684 outb( com->intr_ctrl_port, (com->intr_enable&=~mod) | tmp ); 4685 COM_INT_ENABLE 4686} 4687 4688static void 4689pc98_enable_i8251_interrupt(struct com_s *com, int mod) 4690{ 4691 register int tmp; 4692 4693 COM_INT_DISABLE 4694 tmp = inb( com->intr_ctrl_port ) & ~(IEN_Tx|IEN_TxEMP|IEN_Rx); 4695 outb( com->intr_ctrl_port, (com->intr_enable|=mod) | tmp ); 4696 COM_INT_ENABLE 4697} 4698 4699static int 4700pc98_check_i8251_interrupt(struct com_s *com) 4701{ 4702 return ( com->intr_enable & 0x07 ); 4703} 4704 4705static void 4706pc98_i8251_clear_cmd(struct com_s *com, int x) 4707{ 4708 int tmp; 4709 4710 COM_INT_DISABLE 4711 tmp = com->pc98_prev_siocmd & ~(x); 4712 if (com->pc98_8251fifo_enable) 4713 outb(I8251F_fcr, 0); 4714 outb(com->cmd_port, tmp); 4715 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4716 if (com->pc98_8251fifo_enable) 4717 outb(I8251F_fcr, CTRL8251F_ENABLE); 4718 COM_INT_ENABLE 4719} 4720 4721static void 4722pc98_i8251_or_cmd(struct com_s *com, int x) 4723{ 4724 int tmp; 4725 4726 COM_INT_DISABLE 4727 if (com->pc98_8251fifo_enable) 4728 outb(I8251F_fcr, 0); 4729 tmp = com->pc98_prev_siocmd | (x); 4730 outb(com->cmd_port, tmp); 4731 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4732 if (com->pc98_8251fifo_enable) 4733 outb(I8251F_fcr, CTRL8251F_ENABLE); 4734 COM_INT_ENABLE 4735} 4736 4737static void 4738pc98_i8251_set_cmd(struct com_s *com, int x) 4739{ 4740 int tmp; 4741 4742 COM_INT_DISABLE 4743 if (com->pc98_8251fifo_enable) 4744 outb(I8251F_fcr, 0); 4745 tmp = (x); 4746 outb(com->cmd_port, tmp); 4747 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4748 if (com->pc98_8251fifo_enable) 4749 outb(I8251F_fcr, CTRL8251F_ENABLE); 4750 COM_INT_ENABLE 4751} 4752 4753static void 4754pc98_i8251_clear_or_cmd(struct com_s *com, int clr, int x) 4755{ 4756 int tmp; 4757 COM_INT_DISABLE 4758 if (com->pc98_8251fifo_enable) 4759 outb(I8251F_fcr, 0); 4760 tmp = com->pc98_prev_siocmd & ~(clr); 4761 tmp |= (x); 4762 outb(com->cmd_port, tmp); 4763 com->pc98_prev_siocmd = tmp & ~(CMD8251_ER|CMD8251_RESET|CMD8251_EH); 4764 if (com->pc98_8251fifo_enable) 4765 outb(I8251F_fcr, CTRL8251F_ENABLE); 4766 COM_INT_ENABLE 4767} 4768 4769static int 4770pc98_i8251_get_cmd(struct com_s *com) 4771{ 4772 return com->pc98_prev_siocmd; 4773} 4774 4775static int 4776pc98_i8251_get_mod(struct com_s *com) 4777{ 4778 return com->pc98_prev_siomod; 4779} 4780 4781static void 4782pc98_i8251_reset(struct com_s *com, int mode, int command) 4783{ 4784 if (com->pc98_8251fifo_enable) 4785 outb(I8251F_fcr, 0); 4786 outb(com->cmd_port, 0); /* dummy */ 4787 DELAY(2); 4788 outb(com->cmd_port, 0); /* dummy */ 4789 DELAY(2); 4790 outb(com->cmd_port, 0); /* dummy */ 4791 DELAY(2); 4792 outb(com->cmd_port, CMD8251_RESET); /* internal reset */ 4793 DELAY(2); 4794 outb(com->cmd_port, mode ); /* mode register */ 4795 com->pc98_prev_siomod = mode; 4796 DELAY(2); 4797 pc98_i8251_set_cmd( com, (command|CMD8251_ER) ); 4798 DELAY(10); 4799 if (com->pc98_8251fifo_enable) 4800 outb(I8251F_fcr, CTRL8251F_ENABLE | 4801 CTRL8251F_XMT_RST | CTRL8251F_RCV_RST); 4802} 4803 4804static void 4805pc98_check_sysclock(void) 4806{ 4807 /* get system clock from port */ 4808 if ( pc98_machine_type & M_8M ) { 4809 /* 8 MHz system & H98 */ 4810 sysclock = 8; 4811 } else { 4812 /* 5 MHz system */ 4813 sysclock = 5; 4814 } 4815} 4816 4817static void 4818com_cflag_and_speed_set( struct com_s *com, int cflag, int speed) 4819{ 4820 int cfcr=0; 4821 int previnterrupt; 4822 u_int count; 4823 4824 if (pc98_ttspeedtab(com, speed, &count) != 0) 4825 return; 4826 4827 previnterrupt = pc98_check_i8251_interrupt(com); 4828 pc98_disable_i8251_interrupt( com, IEN_Tx|IEN_TxEMP|IEN_Rx ); 4829 4830 switch ( cflag&CSIZE ) { 4831 case CS5: 4832 cfcr = MOD8251_5BITS; break; 4833 case CS6: 4834 cfcr = MOD8251_6BITS; break; 4835 case CS7: 4836 cfcr = MOD8251_7BITS; break; 4837 case CS8: 4838 cfcr = MOD8251_8BITS; break; 4839 } 4840 if ( cflag&PARENB ) { 4841 if ( cflag&PARODD ) 4842 cfcr |= MOD8251_PODD; 4843 else 4844 cfcr |= MOD8251_PEVEN; 4845 } else 4846 cfcr |= MOD8251_PDISAB; 4847 4848 if ( cflag&CSTOPB ) 4849 cfcr |= MOD8251_STOP2; 4850 else 4851 cfcr |= MOD8251_STOP1; 4852 4853 if ( count & 0x10000 ) 4854 cfcr |= MOD8251_CLKX1; 4855 else 4856 cfcr |= MOD8251_CLKX16; 4857 4858 if (epson_machine_id != 0x20) { /* XXX */ 4859 int tmp; 4860 while (!((tmp = inb(com->sts_port)) & STS8251_TxEMP)) 4861 ; 4862 } 4863 /* set baud rate from ospeed */ 4864 pc98_set_baud_rate( com, count ); 4865 4866 if ( cfcr != pc98_i8251_get_mod(com) ) 4867 pc98_i8251_reset(com, cfcr, pc98_i8251_get_cmd(com) ); 4868 4869 pc98_enable_i8251_interrupt( com, previnterrupt ); 4870} 4871 4872static int 4873pc98_ttspeedtab(struct com_s *com, int speed, u_int *divisor) 4874{ 4875 int if_type, effect_sp, count = -1, mod; 4876 4877 if_type = com->pc98_if_type & 0x0f; 4878 4879 switch (com->pc98_if_type) { 4880 case COM_IF_INTERNAL: 4881 if (PC98SIO_baud_rate_port(if_type) != -1) { 4882 count = ttspeedtab(speed, if_8251_type[if_type].speedtab); 4883 if (count > 0) { 4884 count |= COM1_EXT_CLOCK; 4885 break; 4886 } 4887 } 4888 4889 /* for *1CLK asynchronous! mode, TEFUTEFU */ 4890 mod = (sysclock == 5) ? 2457600 : 1996800; 4891 effect_sp = ttspeedtab( speed, pc98speedtab ); 4892 if ( effect_sp < 0 ) /* XXX */ 4893 effect_sp = ttspeedtab( (speed - 1), pc98speedtab ); 4894 if ( effect_sp <= 0 ) 4895 return effect_sp; 4896 if ( effect_sp == speed ) 4897 mod /= 16; 4898 if ( mod % effect_sp ) 4899 return(-1); 4900 count = mod / effect_sp; 4901 if ( count > 65535 ) 4902 return(-1); 4903 if ( effect_sp != speed ) 4904 count |= 0x10000; 4905 break; 4906 case COM_IF_PC9861K_1: 4907 case COM_IF_PC9861K_2: 4908 count = 1; 4909 break; 4910 case COM_IF_IND_SS_1: 4911 case COM_IF_IND_SS_2: 4912 case COM_IF_PIO9032B_1: 4913 case COM_IF_PIO9032B_2: 4914 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 4915 break; 4916 case COM_IF_B98_01_1: 4917 case COM_IF_B98_01_2: 4918 count = ttspeedtab( speed, if_8251_type[if_type].speedtab ); 4919#ifdef B98_01_OLD 4920 if (count == 0 || count == 1) { 4921 count += 4; 4922 count |= 0x20000; /* x1 mode for 76800 and 153600 */ 4923 } 4924#endif 4925 break; 4926 } 4927 4928 if (count < 0) 4929 return count; 4930 4931 *divisor = (u_int) count; 4932 return 0; 4933} 4934 4935static void 4936pc98_set_baud_rate( struct com_s *com, u_int count ) 4937{ 4938 int if_type, io, s; 4939 4940 if_type = com->pc98_if_type & 0x0f; 4941 io = rman_get_start(com->ioportres) & 0xff00; 4942 4943 switch (com->pc98_if_type) { 4944 case COM_IF_INTERNAL: 4945 if (PC98SIO_baud_rate_port(if_type) != -1) { 4946 if (count & COM1_EXT_CLOCK) { 4947 outb((Port_t)PC98SIO_baud_rate_port(if_type), count & 0xff); 4948 break; 4949 } else { 4950 outb((Port_t)PC98SIO_baud_rate_port(if_type), 0x09); 4951 } 4952 } 4953 4954 if (count == 0) 4955 return; 4956 4957 /* set i8253 */ 4958 s = splclock(); 4959 if (count != 3) 4960 outb( 0x77, 0xb6 ); 4961 else 4962 outb( 0x77, 0xb4 ); 4963 outb( 0x5f, 0); 4964 outb( 0x75, count & 0xff ); 4965 outb( 0x5f, 0); 4966 outb( 0x75, (count >> 8) & 0xff ); 4967 splx(s); 4968 break; 4969 case COM_IF_IND_SS_1: 4970 case COM_IF_IND_SS_2: 4971 outb(io | PC98SIO_intr_ctrl_port(if_type), 0); 4972 outb(io | PC98SIO_baud_rate_port(if_type), 0); 4973 outb(io | PC98SIO_baud_rate_port(if_type), 0xc0); 4974 outb(io | PC98SIO_baud_rate_port(if_type), (count >> 8) | 0x80); 4975 outb(io | PC98SIO_baud_rate_port(if_type), count & 0xff); 4976 break; 4977 case COM_IF_PIO9032B_1: 4978 case COM_IF_PIO9032B_2: 4979 outb(io | PC98SIO_baud_rate_port(if_type), count); 4980 break; 4981 case COM_IF_B98_01_1: 4982 case COM_IF_B98_01_2: 4983 outb(io | PC98SIO_baud_rate_port(if_type), count & 0x0f); 4984#ifdef B98_01_OLD 4985 /* 4986 * Some old B98_01 board should be controlled 4987 * in different way, but this hasn't been tested yet. 4988 */ 4989 outb(io | PC98SIO_func_port(if_type), 4990 (count & 0x20000) ? 0xf0 : 0xf2); 4991#endif 4992 break; 4993 } 4994} 4995static int 4996pc98_check_if_type(device_t dev, struct siodev *iod) 4997{ 4998 int irr, io, if_type, tmp; 4999 static short irq_tab[2][8] = { 5000 { 3, 5, 6, 9, 10, 12, 13, -1}, 5001 { 3, 10, 12, 13, 5, 6, 9, -1} 5002 }; 5003 5004 if_type = iod->if_type & 0x0f; 5005 iod->irq = 0; 5006 io = isa_get_port(dev) & 0xff00; 5007 5008 if (IS_8251(iod->if_type)) { 5009 if (PC98SIO_func_port(if_type) != -1) { 5010 outb(io | PC98SIO_func_port(if_type), 0xf2); 5011 tmp = ttspeedtab(9600, if_8251_type[if_type].speedtab); 5012 if (tmp != -1 && PC98SIO_baud_rate_port(if_type) != -1) 5013 outb(io | PC98SIO_baud_rate_port(if_type), tmp); 5014 } 5015 5016 iod->cmd = io | PC98SIO_cmd_port(if_type); 5017 iod->sts = io | PC98SIO_sts_port(if_type); 5018 iod->mod = io | PC98SIO_in_modem_port(if_type); 5019 iod->ctrl = io | PC98SIO_intr_ctrl_port(if_type); 5020 5021 if (iod->if_type == COM_IF_INTERNAL) { 5022 iod->irq = 4; 5023 5024 if (pc98_check_8251vfast()) { 5025 PC98SIO_baud_rate_port(if_type) = I8251F_div; 5026 if_8251_type[if_type].speedtab = pc98fast_speedtab; 5027 } 5028 } else { 5029 tmp = inb( iod->mod ) & if_8251_type[if_type].irr_mask; 5030 if ((isa_get_port(dev) & 0xff) == IO_COM2) 5031 iod->irq = irq_tab[0][tmp]; 5032 else 5033 iod->irq = irq_tab[1][tmp]; 5034 } 5035 } else { 5036 irr = if_16550a_type[if_type].irr_read; 5037#ifdef COM_MULTIPORT 5038 if (!COM_ISMULTIPORT(device_get_flags(dev)) || 5039 device_get_unit(dev) == COM_MPMASTER(device_get_flags(dev))) 5040#endif 5041 if (irr != -1) { 5042 tmp = inb(io | irr); 5043 if (isa_get_port(dev) & 0x01) /* XXX depend on RSB-384 */ 5044 iod->irq = irq_tab[1][tmp >> 3]; 5045 else 5046 iod->irq = irq_tab[0][tmp & 0x07]; 5047 } 5048 } 5049 if ( iod->irq == -1 ) return -1; 5050 5051 return 0; 5052} 5053static void 5054pc98_set_ioport(struct com_s *com) 5055{ 5056 int if_type = com->pc98_if_type & 0x0f; 5057 Port_t io = rman_get_start(com->ioportres) & 0xff00; 5058 5059 pc98_check_sysclock(); 5060 com->data_port = io | PC98SIO_data_port(if_type); 5061 com->cmd_port = io | PC98SIO_cmd_port(if_type); 5062 com->sts_port = io | PC98SIO_sts_port(if_type); 5063 com->in_modem_port = io | PC98SIO_in_modem_port(if_type); 5064 com->intr_ctrl_port = io | PC98SIO_intr_ctrl_port(if_type); 5065} 5066static int 5067pc98_check_8251vfast(void) 5068{ 5069 int i; 5070 5071 outb(I8251F_div, 0x8c); 5072 DELAY(10); 5073 for (i = 0; i < 100; i++) { 5074 if ((inb(I8251F_div) & 0x80) != 0) { 5075 i = 0; 5076 break; 5077 } 5078 DELAY(1); 5079 } 5080 outb(I8251F_div, 0); 5081 DELAY(10); 5082 for (; i < 100; i++) { 5083 if ((inb(I8251F_div) & 0x80) == 0) 5084 return 1; 5085 DELAY(1); 5086 } 5087 5088 return 0; 5089} 5090static int 5091pc98_check_8251fifo(void) 5092{ 5093 u_char tmp1, tmp2; 5094 5095 tmp1 = inb(I8251F_iir); 5096 DELAY(10); 5097 tmp2 = inb(I8251F_iir); 5098 if (((tmp1 ^ tmp2) & 0x40) != 0 && ((tmp1 | tmp2) & 0x20) == 0) 5099 return 1; 5100 5101 return 0; 5102} 5103#endif /* PC98 defined */ 5104