pcrtc.c revision 32852
1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz and Don Ahn. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 37 * $Id: clock.c,v 1.39 1997/12/29 16:15:57 kato Exp $ 38 */ 39 40/* 41 * Routines to handle clock hardware. 42 */ 43 44/* 45 * inittodr, settodr and support routines written 46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 47 * 48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 49 */ 50 51/* 52 * modified for PC98 by Kakefuda 53 */ 54 55#include "opt_clock.h" 56 57#include <sys/param.h> 58#include <sys/systm.h> 59#include <sys/time.h> 60#include <sys/kernel.h> 61#ifndef SMP 62#include <sys/lock.h> 63#endif 64#include <sys/sysctl.h> 65 66#include <machine/clock.h> 67#ifdef CLK_CALIBRATION_LOOP 68#include <machine/cons.h> 69#endif 70#include <machine/cputypes.h> 71#include <machine/frame.h> 72#include <machine/ipl.h> 73#include <machine/limits.h> 74#include <machine/md_var.h> 75#ifdef APIC_IO 76#include <machine/segments.h> 77#endif 78#if defined(SMP) || defined(APIC_IO) 79#include <machine/smp.h> 80#endif /* SMP || APIC_IO */ 81#include <machine/specialreg.h> 82 83#include <i386/isa/icu.h> 84#ifdef PC98 85#include <pc98/pc98/pc98.h> 86#include <pc98/pc98/pc98_machdep.h> 87#include <i386/isa/isa_device.h> 88#else 89#include <i386/isa/isa.h> 90#include <i386/isa/rtc.h> 91#endif 92#include <i386/isa/timerreg.h> 93 94#include <sys/interrupt.h> 95 96#ifdef SMP 97#define disable_intr() CLOCK_DISABLE_INTR() 98#define enable_intr() CLOCK_ENABLE_INTR() 99#endif /* SMP */ 100 101/* 102 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 103 * can use a simple formula for leap years. 104 */ 105#define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 106#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 107 108#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) 109 110/* 111 * Time in timer cycles that it takes for microtime() to disable interrupts 112 * and latch the count. microtime() currently uses "cli; outb ..." so it 113 * normally takes less than 2 timer cycles. Add a few for cache misses. 114 * Add a few more to allow for latency in bogus calls to microtime() with 115 * interrupts already disabled. 116 */ 117#define TIMER0_LATCH_COUNT 20 118 119/* 120 * Maximum frequency that we are willing to allow for timer0. Must be 121 * low enough to guarantee that the timer interrupt handler returns 122 * before the next timer interrupt. Must result in a lower TIMER_DIV 123 * value than TIMER0_LATCH_COUNT so that we don't have to worry about 124 * underflow in the calculation of timer0_overflow_threshold. 125 */ 126#define TIMER0_MAX_FREQ 20000 127 128int adjkerntz; /* local offset from GMT in seconds */ 129int disable_rtc_set; /* disable resettodr() if != 0 */ 130u_int idelayed; 131int statclock_disable; 132u_int stat_imask = SWI_CLOCK_MASK; 133#ifdef TIMER_FREQ 134u_int timer_freq = TIMER_FREQ; 135#else 136#ifdef PC98 137#ifndef AUTO_CLOCK 138#ifndef PC98_8M 139u_int timer_freq = 2457600; 140#else /* !PC98_8M */ 141u_int timer_freq = 1996800; 142#endif /* PC98_8M */ 143#else /* AUTO_CLOCK */ 144u_int timer_freq = 2457600; 145#endif /* AUTO_CLOCK */ 146#else /* IBM-PC */ 147u_int timer_freq = 1193182; 148#endif /* PC98 */ 149#endif 150int timer0_max_count; 151u_int timer0_overflow_threshold; 152u_int timer0_prescaler_count; 153u_int tsc_bias; 154u_int tsc_comultiplier; 155u_int tsc_freq; 156u_int tsc_multiplier; 157u_int tsc_present; 158int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 159 160static int beeping = 0; 161static u_int clk_imask = HWI_MASK | SWI_MASK; 162static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 163static u_int hardclock_max_count; 164/* 165 * XXX new_function and timer_func should not handle clockframes, but 166 * timer_func currently needs to hold hardclock to handle the 167 * timer0_state == 0 case. We should use register_intr()/unregister_intr() 168 * to switch between clkintr() and a slightly different timerintr(). 169 */ 170static void (*new_function) __P((struct clockframe *frame)); 171static u_int new_rate; 172#ifndef PC98 173static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 174static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 175#endif 176 177/* Values for timerX_state: */ 178#define RELEASED 0 179#define RELEASE_PENDING 1 180#define ACQUIRED 2 181#define ACQUIRE_PENDING 3 182 183static u_char timer0_state; 184#ifdef PC98 185static u_char timer1_state; 186#endif 187static u_char timer2_state; 188static void (*timer_func) __P((struct clockframe *frame)) = hardclock; 189#ifdef PC98 190static void rtc_serialcombit __P((int)); 191static void rtc_serialcom __P((int)); 192static int rtc_inb __P((void)); 193static void rtc_outb __P((int)); 194#endif 195 196static void set_tsc_freq(u_int tsc_count, u_int i8254_freq); 197static void set_timer_freq(u_int freq, int intr_freq); 198 199static void 200clkintr(struct clockframe frame) 201{ 202 timer_func(&frame); 203 switch (timer0_state) { 204 205 case RELEASED: 206 setdelayed(); 207 break; 208 209 case ACQUIRED: 210 if ((timer0_prescaler_count += timer0_max_count) 211 >= hardclock_max_count) { 212 hardclock(&frame); 213 setdelayed(); 214 timer0_prescaler_count -= hardclock_max_count; 215 } 216 break; 217 218 case ACQUIRE_PENDING: 219 setdelayed(); 220 timer0_max_count = TIMER_DIV(new_rate); 221 timer0_overflow_threshold = 222 timer0_max_count - TIMER0_LATCH_COUNT; 223 disable_intr(); 224 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 225 outb(TIMER_CNTR0, timer0_max_count & 0xff); 226 outb(TIMER_CNTR0, timer0_max_count >> 8); 227 enable_intr(); 228 timer0_prescaler_count = 0; 229 timer_func = new_function; 230 timer0_state = ACQUIRED; 231 break; 232 233 case RELEASE_PENDING: 234 if ((timer0_prescaler_count += timer0_max_count) 235 >= hardclock_max_count) { 236 hardclock(&frame); 237 setdelayed(); 238 timer0_max_count = hardclock_max_count; 239 timer0_overflow_threshold = 240 timer0_max_count - TIMER0_LATCH_COUNT; 241 disable_intr(); 242 outb(TIMER_MODE, 243 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 244 outb(TIMER_CNTR0, timer0_max_count & 0xff); 245 outb(TIMER_CNTR0, timer0_max_count >> 8); 246 enable_intr(); 247 /* 248 * See microtime.s for this magic. 249 */ 250#ifdef PC98 251#ifndef AUTO_CLOCK 252#ifndef PC98_8M 253 time.tv_usec += (6667 * 254 (timer0_prescaler_count - hardclock_max_count)) 255 >> 14; 256#else /* PC98_8M */ 257 time.tv_usec += (16411 * 258 (timer0_prescaler_count - hardclock_max_count)) 259 >> 15; 260#endif /* PC98_8M */ 261#else /* AUTO_CLOCK */ 262 if (pc98_machine_type & M_8M) { 263 /* PC98_8M */ 264 time.tv_usec += (16411 * 265 (timer0_prescaler_count - 266 hardclock_max_count)) >> 15; 267 } else { 268 time.tv_usec += (6667 * 269 (timer0_prescaler_count - 270 hardclock_max_count)) >> 14; 271 } 272#endif /* AUTO_CLOCK */ 273#else /* IBM-PC */ 274 time.tv_usec += (27465 * 275 (timer0_prescaler_count - hardclock_max_count)) 276 >> 15; 277#endif /* PC98 */ 278 if (time.tv_usec >= 1000000) 279 time.tv_usec -= 1000000; 280 timer0_prescaler_count = 0; 281 timer_func = hardclock; 282 timer0_state = RELEASED; 283 } 284 break; 285 } 286} 287 288/* 289 * The acquire and release functions must be called at ipl >= splclock(). 290 */ 291int 292acquire_timer0(int rate, void (*function) __P((struct clockframe *frame))) 293{ 294 static int old_rate; 295 296 if (rate <= 0 || rate > TIMER0_MAX_FREQ) 297 return (-1); 298 switch (timer0_state) { 299 300 case RELEASED: 301 timer0_state = ACQUIRE_PENDING; 302 break; 303 304 case RELEASE_PENDING: 305 if (rate != old_rate) 306 return (-1); 307 /* 308 * The timer has been released recently, but is being 309 * re-acquired before the release completed. In this 310 * case, we simply reclaim it as if it had not been 311 * released at all. 312 */ 313 timer0_state = ACQUIRED; 314 break; 315 316 default: 317 return (-1); /* busy */ 318 } 319 new_function = function; 320 old_rate = new_rate = rate; 321 return (0); 322} 323 324#ifdef PC98 325int 326acquire_timer1(int mode) 327{ 328 329 if (timer1_state != RELEASED) 330 return (-1); 331 timer1_state = ACQUIRED; 332 333 /* 334 * This access to the timer registers is as atomic as possible 335 * because it is a single instruction. We could do better if we 336 * knew the rate. Use of splclock() limits glitches to 10-100us, 337 * and this is probably good enough for timer2, so we aren't as 338 * careful with it as with timer0. 339 */ 340 outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f)); 341 342 return (0); 343} 344#endif 345 346int 347acquire_timer2(int mode) 348{ 349 350 if (timer2_state != RELEASED) 351 return (-1); 352 timer2_state = ACQUIRED; 353 354 /* 355 * This access to the timer registers is as atomic as possible 356 * because it is a single instruction. We could do better if we 357 * knew the rate. Use of splclock() limits glitches to 10-100us, 358 * and this is probably good enough for timer2, so we aren't as 359 * careful with it as with timer0. 360 */ 361 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 362 363 return (0); 364} 365 366int 367release_timer0() 368{ 369 switch (timer0_state) { 370 371 case ACQUIRED: 372 timer0_state = RELEASE_PENDING; 373 break; 374 375 case ACQUIRE_PENDING: 376 /* Nothing happened yet, release quickly. */ 377 timer0_state = RELEASED; 378 break; 379 380 default: 381 return (-1); 382 } 383 return (0); 384} 385 386#ifdef PC98 387int 388release_timer1() 389{ 390 391 if (timer1_state != ACQUIRED) 392 return (-1); 393 timer1_state = RELEASED; 394 outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT); 395 return (0); 396} 397#endif 398 399int 400release_timer2() 401{ 402 403 if (timer2_state != ACQUIRED) 404 return (-1); 405 timer2_state = RELEASED; 406 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 407 return (0); 408} 409 410#ifndef PC98 411/* 412 * This routine receives statistical clock interrupts from the RTC. 413 * As explained above, these occur at 128 interrupts per second. 414 * When profiling, we receive interrupts at a rate of 1024 Hz. 415 * 416 * This does not actually add as much overhead as it sounds, because 417 * when the statistical clock is active, the hardclock driver no longer 418 * needs to keep (inaccurate) statistics on its own. This decouples 419 * statistics gathering from scheduling interrupts. 420 * 421 * The RTC chip requires that we read status register C (RTC_INTR) 422 * to acknowledge an interrupt, before it will generate the next one. 423 * Under high interrupt load, rtcintr() can be indefinitely delayed and 424 * the clock can tick immediately after the read from RTC_INTR. In this 425 * case, the mc146818A interrupt signal will not drop for long enough 426 * to register with the 8259 PIC. If an interrupt is missed, the stat 427 * clock will halt, considerably degrading system performance. This is 428 * why we use 'while' rather than a more straightforward 'if' below. 429 * Stat clock ticks can still be lost, causing minor loss of accuracy 430 * in the statistics, but the stat clock will no longer stop. 431 */ 432static void 433rtcintr(struct clockframe frame) 434{ 435 while (rtcin(RTC_INTR) & RTCIR_PERIOD) 436 statclock(&frame); 437} 438 439#include "opt_ddb.h" 440#ifdef DDB 441#include <ddb/ddb.h> 442 443DB_SHOW_COMMAND(rtc, rtc) 444{ 445 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 446 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 447 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 448 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 449} 450#endif /* DDB */ 451#endif /* for PC98 */ 452 453static int 454getit(void) 455{ 456 u_long ef; 457 int high, low; 458 459 ef = read_eflags(); 460 disable_intr(); 461 462 /* Select timer0 and latch counter value. */ 463 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 464 465 low = inb(TIMER_CNTR0); 466 high = inb(TIMER_CNTR0); 467 468 CLOCK_UNLOCK(); 469 write_eflags(ef); 470 return ((high << 8) | low); 471} 472 473/* 474 * Wait "n" microseconds. 475 * Relies on timer 1 counting down from (timer_freq / hz) 476 * Note: timer had better have been programmed before this is first used! 477 */ 478void 479DELAY(int n) 480{ 481 int delta, prev_tick, tick, ticks_left; 482 483#ifdef DELAYDEBUG 484 int getit_calls = 1; 485 int n1; 486 static int state = 0; 487 488 if (state == 0) { 489 state = 1; 490 for (n1 = 1; n1 <= 10000000; n1 *= 10) 491 DELAY(n1); 492 state = 2; 493 } 494 if (state == 1) 495 printf("DELAY(%d)...", n); 496#endif 497 /* 498 * Guard against the timer being uninitialized if we are called 499 * early for console i/o. 500 */ 501 if (timer0_max_count == 0) 502 set_timer_freq(timer_freq, hz); 503 504 /* 505 * Read the counter first, so that the rest of the setup overhead is 506 * counted. Guess the initial overhead is 20 usec (on most systems it 507 * takes about 1.5 usec for each of the i/o's in getit(). The loop 508 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 509 * multiplications and divisions to scale the count take a while). 510 */ 511 prev_tick = getit(); 512 n -= 0; /* XXX actually guess no initial overhead */ 513 /* 514 * Calculate (n * (timer_freq / 1e6)) without using floating point 515 * and without any avoidable overflows. 516 */ 517 if (n <= 0) 518 ticks_left = 0; 519 else if (n < 256) 520 /* 521 * Use fixed point to avoid a slow division by 1000000. 522 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest. 523 * 2^15 is the first power of 2 that gives exact results 524 * for n between 0 and 256. 525 */ 526 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15; 527 else 528 /* 529 * Don't bother using fixed point, although gcc-2.7.2 530 * generates particularly poor code for the long long 531 * division, since even the slow way will complete long 532 * before the delay is up (unless we're interrupted). 533 */ 534 ticks_left = ((u_int)n * (long long)timer_freq + 999999) 535 / 1000000; 536 537 while (ticks_left > 0) { 538 tick = getit(); 539#ifdef DELAYDEBUG 540 ++getit_calls; 541#endif 542 delta = prev_tick - tick; 543 prev_tick = tick; 544 if (delta < 0) { 545 delta += timer0_max_count; 546 /* 547 * Guard against timer0_max_count being wrong. 548 * This shouldn't happen in normal operation, 549 * but it may happen if set_timer_freq() is 550 * traced. 551 */ 552 if (delta < 0) 553 delta = 0; 554 } 555 ticks_left -= delta; 556 } 557#ifdef DELAYDEBUG 558 if (state == 1) 559 printf(" %d calls to getit() at %d usec each\n", 560 getit_calls, (n + 5) / getit_calls); 561#endif 562} 563 564static void 565sysbeepstop(void *chan) 566{ 567#ifdef PC98 /* PC98 */ 568 outb(IO_PPI, inb(IO_PPI)|0x08); /* disable counter1 output to speaker */ 569 release_timer1(); 570#else 571 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 572 release_timer2(); 573#endif 574 beeping = 0; 575} 576 577int 578sysbeep(int pitch, int period) 579{ 580 int x = splclock(); 581 582#ifdef PC98 583 if (acquire_timer1(TIMER_SQWAVE|TIMER_16BIT)) 584 if (!beeping) { 585 /* Something else owns it. */ 586 splx(x); 587 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 588 } 589 disable_intr(); 590 outb(0x3fdb, pitch); 591 outb(0x3fdb, (pitch>>8)); 592 enable_intr(); 593 if (!beeping) { 594 /* enable counter1 output to speaker */ 595 outb(IO_PPI, (inb(IO_PPI) & 0xf7)); 596 beeping = period; 597 timeout(sysbeepstop, (void *)NULL, period); 598 } 599#else 600 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 601 if (!beeping) { 602 /* Something else owns it. */ 603 splx(x); 604 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 605 } 606 disable_intr(); 607 outb(TIMER_CNTR2, pitch); 608 outb(TIMER_CNTR2, (pitch>>8)); 609 enable_intr(); 610 if (!beeping) { 611 /* enable counter2 output to speaker */ 612 outb(IO_PPI, inb(IO_PPI) | 3); 613 beeping = period; 614 timeout(sysbeepstop, (void *)NULL, period); 615 } 616#endif 617 splx(x); 618 return (0); 619} 620 621#ifndef PC98 622/* 623 * RTC support routines 624 */ 625 626int 627rtcin(reg) 628 int reg; 629{ 630 u_char val; 631 632 outb(IO_RTC, reg); 633 inb(0x84); 634 val = inb(IO_RTC + 1); 635 inb(0x84); 636 return (val); 637} 638 639static __inline void 640writertc(u_char reg, u_char val) 641{ 642 outb(IO_RTC, reg); 643 outb(IO_RTC + 1, val); 644} 645 646static __inline int 647readrtc(int port) 648{ 649 return(bcd2bin(rtcin(port))); 650} 651#endif 652 653#ifdef PC98 654unsigned int delaycount; 655#define FIRST_GUESS 0x2000 656static void findcpuspeed(void) 657{ 658 int i; 659 int remainder; 660 661 /* Put counter in count down mode */ 662 outb(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN); 663 outb(TIMER_CNTR0, 0xff); 664 outb(TIMER_CNTR0, 0xff); 665 for (i = FIRST_GUESS; i; i--) 666 ; 667 remainder = getit(); 668 delaycount = (FIRST_GUESS * TIMER_DIV(1000)) / (0xffff - remainder); 669} 670#endif 671 672#ifndef PC98 673static u_int 674calibrate_clocks(void) 675{ 676 u_int count, prev_count, tot_count; 677 int sec, start_sec, timeout; 678 679 if (bootverbose) 680 printf("Calibrating clock(s) ... "); 681 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 682 goto fail; 683 timeout = 100000000; 684 685 /* Read the mc146818A seconds counter. */ 686 for (;;) { 687 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 688 sec = rtcin(RTC_SEC); 689 break; 690 } 691 if (--timeout == 0) 692 goto fail; 693 } 694 695 /* Wait for the mC146818A seconds counter to change. */ 696 start_sec = sec; 697 for (;;) { 698 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 699 sec = rtcin(RTC_SEC); 700 if (sec != start_sec) 701 break; 702 } 703 if (--timeout == 0) 704 goto fail; 705 } 706 707 /* Start keeping track of the i8254 counter. */ 708 prev_count = getit(); 709 if (prev_count == 0 || prev_count > timer0_max_count) 710 goto fail; 711 tot_count = 0; 712 713 if (tsc_present) 714 wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */ 715 716 /* 717 * Wait for the mc146818A seconds counter to change. Read the i8254 718 * counter for each iteration since this is convenient and only 719 * costs a few usec of inaccuracy. The timing of the final reads 720 * of the counters almost matches the timing of the initial reads, 721 * so the main cause of inaccuracy is the varying latency from 722 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 723 * rtcin(RTC_SEC) that returns a changed seconds count. The 724 * maximum inaccuracy from this cause is < 10 usec on 486's. 725 */ 726 start_sec = sec; 727 for (;;) { 728 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 729 sec = rtcin(RTC_SEC); 730 count = getit(); 731 if (count == 0 || count > timer0_max_count) 732 goto fail; 733 if (count > prev_count) 734 tot_count += prev_count - (count - timer0_max_count); 735 else 736 tot_count += prev_count - count; 737 prev_count = count; 738 if (sec != start_sec) 739 break; 740 if (--timeout == 0) 741 goto fail; 742 } 743 744 /* 745 * Read the cpu cycle counter. The timing considerations are 746 * similar to those for the i8254 clock. 747 */ 748 if (tsc_present) { 749 set_tsc_freq((u_int)rdtsc(), tot_count); 750 if (bootverbose) 751 printf("TSC clock: %u Hz, ", tsc_freq); 752 } 753 754 if (bootverbose) 755 printf("i8254 clock: %u Hz\n", tot_count); 756 return (tot_count); 757 758fail: 759 if (bootverbose) 760 printf("failed, using default i8254 clock of %u Hz\n", 761 timer_freq); 762 return (timer_freq); 763} 764#endif /* !PC98 */ 765 766static void 767set_timer_freq(u_int freq, int intr_freq) 768{ 769 u_long ef; 770 771 ef = read_eflags(); 772 disable_intr(); 773 timer_freq = freq; 774 timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); 775 timer0_overflow_threshold = timer0_max_count - TIMER0_LATCH_COUNT; 776 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 777 outb(TIMER_CNTR0, timer0_max_count & 0xff); 778 outb(TIMER_CNTR0, timer0_max_count >> 8); 779 CLOCK_UNLOCK(); 780 write_eflags(ef); 781} 782 783/* 784 * Initialize 8253 timer 0 early so that it can be used in DELAY(). 785 * XXX initialization of other timers is unintentionally left blank. 786 */ 787void 788startrtclock() 789{ 790 u_int delta, freq; 791 792#ifdef PC98 793 findcpuspeed(); 794#ifndef AUTO_CLOCK 795 if (pc98_machine_type & M_8M) { 796#ifndef PC98_8M 797 printf("you must reconfig a kernel with \"PC98_8M\" option.\n"); 798#endif 799 } else { 800#ifdef PC98_8M 801 printf("You must reconfig a kernel without \"PC98_8M\" option.\n"); 802#endif 803 } 804#else /* AUTO_CLOCK */ 805 if (pc98_machine_type & M_8M) 806 timer_freq = 1996800L; /* 1.9968 MHz */ 807 else 808 timer_freq = 2457600L; /* 2.4576 MHz */ 809#endif /* AUTO_CLOCK */ 810#endif /* PC98 */ 811 812 if (cpu_feature & CPUID_TSC) 813 tsc_present = 1; 814 else 815 tsc_present = 0; 816 817#ifdef SMP 818 tsc_present = 0; 819#endif 820 821#ifndef PC98 822 writertc(RTC_STATUSA, rtc_statusa); 823 writertc(RTC_STATUSB, RTCSB_24HR); 824#endif 825 826#ifndef PC98 827 set_timer_freq(timer_freq, hz); 828 freq = calibrate_clocks(); 829#ifdef CLK_CALIBRATION_LOOP 830 if (bootverbose) { 831 printf( 832 "Press a key on the console to abort clock calibration\n"); 833 while (cncheckc() == -1) 834 calibrate_clocks(); 835 } 836#endif 837 838 /* 839 * Use the calibrated i8254 frequency if it seems reasonable. 840 * Otherwise use the default, and don't use the calibrated i586 841 * frequency. 842 */ 843 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; 844 if (delta < timer_freq / 100) { 845#ifndef CLK_USE_I8254_CALIBRATION 846 if (bootverbose) 847 printf( 848"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 849 freq = timer_freq; 850#endif 851 timer_freq = freq; 852 } else { 853 if (bootverbose) 854 printf( 855 "%d Hz differs from default of %d Hz by more than 1%%\n", 856 freq, timer_freq); 857 tsc_freq = 0; 858 } 859#endif 860 861 set_timer_freq(timer_freq, hz); 862 863#ifndef CLK_USE_TSC_CALIBRATION 864 if (tsc_freq != 0) { 865 if (bootverbose) 866 printf( 867"CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n"); 868 tsc_freq = 0; 869 } 870#endif 871 if (tsc_present && tsc_freq == 0) { 872 /* 873 * Calibration of the i586 clock relative to the mc146818A 874 * clock failed. Do a less accurate calibration relative 875 * to the i8254 clock. 876 */ 877 wrmsr(0x10, 0LL); /* XXX */ 878 DELAY(1000000); 879 set_tsc_freq((u_int)rdtsc(), timer_freq); 880#ifdef CLK_USE_TSC_CALIBRATION 881 if (bootverbose) 882 printf("TSC clock: %u Hz\n", tsc_freq); 883#endif 884 } 885} 886 887#ifdef PC98 888static void 889rtc_serialcombit(int i) 890{ 891 outb(IO_RTC, ((i&0x01)<<5)|0x07); 892 DELAY(1); 893 outb(IO_RTC, ((i&0x01)<<5)|0x17); 894 DELAY(1); 895 outb(IO_RTC, ((i&0x01)<<5)|0x07); 896 DELAY(1); 897} 898 899static void 900rtc_serialcom(int i) 901{ 902 rtc_serialcombit(i&0x01); 903 rtc_serialcombit((i&0x02)>>1); 904 rtc_serialcombit((i&0x04)>>2); 905 rtc_serialcombit((i&0x08)>>3); 906 outb(IO_RTC, 0x07); 907 DELAY(1); 908 outb(IO_RTC, 0x0f); 909 DELAY(1); 910 outb(IO_RTC, 0x07); 911 DELAY(1); 912} 913 914static void 915rtc_outb(int val) 916{ 917 int s; 918 int sa = 0; 919 920 for (s=0;s<8;s++) { 921 sa = ((val >> s) & 0x01) ? 0x27 : 0x07; 922 outb(IO_RTC, sa); /* set DI & CLK 0 */ 923 DELAY(1); 924 outb(IO_RTC, sa | 0x10); /* CLK 1 */ 925 DELAY(1); 926 } 927 outb(IO_RTC, sa & 0xef); /* CLK 0 */ 928} 929 930static int 931rtc_inb(void) 932{ 933 int s; 934 int sa = 0; 935 936 for (s=0;s<8;s++) { 937 sa |= ((inb(0x33) & 0x01) << s); 938 outb(IO_RTC, 0x17); /* CLK 1 */ 939 DELAY(1); 940 outb(IO_RTC, 0x07); /* CLK 0 */ 941 DELAY(2); 942 } 943 return sa; 944} 945#endif /* PC-98 */ 946 947/* 948 * Initialize the time of day register, based on the time base which is, e.g. 949 * from a filesystem. 950 */ 951void 952inittodr(time_t base) 953{ 954 unsigned long sec, days; 955 int yd; 956 int year, month; 957 int y, m, s; 958#ifdef PC98 959 int second, min, hour; 960#endif 961 962 if (base) { 963 s = splclock(); 964 time.tv_sec = base; 965 time.tv_usec = 0; 966 splx(s); 967 } 968 969#ifdef PC98 970 rtc_serialcom(0x03); /* Time Read */ 971 rtc_serialcom(0x01); /* Register shift command. */ 972 DELAY(20); 973 974 second = bcd2bin(rtc_inb() & 0xff); /* sec */ 975 min = bcd2bin(rtc_inb() & 0xff); /* min */ 976 hour = bcd2bin(rtc_inb() & 0xff); /* hour */ 977 days = bcd2bin(rtc_inb() & 0xff) - 1; /* date */ 978 979 month = (rtc_inb() >> 4) & 0x0f; /* month */ 980 for (m = 1; m < month; m++) 981 days += daysinmonth[m-1]; 982 year = bcd2bin(rtc_inb() & 0xff) + 1900; /* year */ 983 /* 2000 year problem */ 984 if (year < 1995) 985 year += 100; 986 if (year < 1970) 987 goto wrong_time; 988 for (y = 1970; y < year; y++) 989 days += DAYSPERYEAR + LEAPYEAR(y); 990 if ((month > 2) && LEAPYEAR(year)) 991 days ++; 992 sec = ((( days * 24 + 993 hour) * 60 + 994 min) * 60 + 995 second); 996 /* sec now contains the number of seconds, since Jan 1 1970, 997 in the local time zone */ 998#else /* IBM-PC */ 999 /* Look if we have a RTC present and the time is valid */ 1000 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 1001 goto wrong_time; 1002 1003 /* wait for time update to complete */ 1004 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 1005 while (rtcin(RTC_STATUSA) & RTCSA_TUP); 1006 1007 days = 0; 1008#ifdef USE_RTC_CENTURY 1009 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 1010#else 1011 year = readrtc(RTC_YEAR) + 1900; 1012 if (year < 1970) 1013 year += 100; 1014#endif 1015 if (year < 1970) 1016 goto wrong_time; 1017 month = readrtc(RTC_MONTH); 1018 for (m = 1; m < month; m++) 1019 days += daysinmonth[m-1]; 1020 if ((month > 2) && LEAPYEAR(year)) 1021 days ++; 1022 days += readrtc(RTC_DAY) - 1; 1023 yd = days; 1024 for (y = 1970; y < year; y++) 1025 days += DAYSPERYEAR + LEAPYEAR(y); 1026 sec = ((( days * 24 + 1027 readrtc(RTC_HRS)) * 60 + 1028 readrtc(RTC_MIN)) * 60 + 1029 readrtc(RTC_SEC)); 1030 /* sec now contains the number of seconds, since Jan 1 1970, 1031 in the local time zone */ 1032#endif 1033 1034 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1035 1036 s = splclock(); 1037 time.tv_sec = sec; 1038 splx(s); 1039 return; 1040 1041wrong_time: 1042 printf("Invalid time in real time clock.\n"); 1043 printf("Check and reset the date immediately!\n"); 1044} 1045 1046/* 1047 * Write system time back to RTC 1048 */ 1049void 1050resettodr() 1051{ 1052 unsigned long tm; 1053 int y, m, s; 1054#ifdef PC98 1055 int wd; 1056#endif 1057 1058 if (disable_rtc_set) 1059 return; 1060 1061 s = splclock(); 1062 tm = time.tv_sec; 1063 splx(s); 1064 1065#ifdef PC98 1066 rtc_serialcom(0x01); /* Register shift command. */ 1067 1068 /* Calculate local time to put in RTC */ 1069 1070 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1071 1072 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1073 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1074 rtc_outb(bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1075 1076 /* We have now the days since 01-01-1970 in tm */ 1077 wd = (tm+4)%7; 1078 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1079 tm >= m; 1080 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1081 tm -= m; 1082 1083 /* Now we have the years in y and the day-of-the-year in tm */ 1084 for (m = 0; ; m++) { 1085 int ml; 1086 1087 ml = daysinmonth[m]; 1088 if (m == 1 && LEAPYEAR(y)) 1089 ml++; 1090 if (tm < ml) 1091 break; 1092 tm -= ml; 1093 } 1094 1095 m++; 1096 rtc_outb(bin2bcd(tm+1)); /* Write back Day */ 1097 rtc_outb((m << 4) | wd); /* Write back Month & Weekday */ 1098 rtc_outb(bin2bcd(y%100)); /* Write back Year */ 1099 1100 rtc_serialcom(0x02); /* Time set & Counter hold command. */ 1101 rtc_serialcom(0x00); /* Register hold command. */ 1102#else 1103 /* Disable RTC updates and interrupts. */ 1104 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 1105 1106 /* Calculate local time to put in RTC */ 1107 1108 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1109 1110 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1111 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1112 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1113 1114 /* We have now the days since 01-01-1970 in tm */ 1115 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 1116 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1117 tm >= m; 1118 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1119 tm -= m; 1120 1121 /* Now we have the years in y and the day-of-the-year in tm */ 1122 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 1123#ifdef USE_RTC_CENTURY 1124 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 1125#endif 1126 for (m = 0; ; m++) { 1127 int ml; 1128 1129 ml = daysinmonth[m]; 1130 if (m == 1 && LEAPYEAR(y)) 1131 ml++; 1132 if (tm < ml) 1133 break; 1134 tm -= ml; 1135 } 1136 1137 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1138 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1139 1140 /* Reenable RTC updates and interrupts. */ 1141 writertc(RTC_STATUSB, rtc_statusb); 1142#endif 1143} 1144 1145 1146/* 1147 * Start both clocks running. 1148 */ 1149void 1150cpu_initclocks() 1151{ 1152#ifdef APIC_IO 1153 int x; 1154#endif /* APIC_IO */ 1155#ifndef PC98 1156 int diag; 1157 1158 if (statclock_disable) { 1159 /* 1160 * The stat interrupt mask is different without the 1161 * statistics clock. Also, don't set the interrupt 1162 * flag which would normally cause the RTC to generate 1163 * interrupts. 1164 */ 1165 stat_imask = HWI_MASK | SWI_MASK; 1166 rtc_statusb = RTCSB_24HR; 1167 } else { 1168 /* Setting stathz to nonzero early helps avoid races. */ 1169 stathz = RTC_NOPROFRATE; 1170 profhz = RTC_PROFRATE; 1171 } 1172#endif 1173 1174 /* Finish initializing 8253 timer 0. */ 1175#ifdef APIC_IO 1176 1177 /* 1st look for ExtInt on pin 0 */ 1178 if (apic_int_type(0, 0) == 3) { 1179 /* 1180 * Allow 8254 timer to INTerrupt 8259: 1181 * re-initialize master 8259: 1182 * reset; prog 4 bytes, single ICU, edge triggered 1183 */ 1184 outb(IO_ICU1, 0x13); 1185 outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */ 1186 outb(IO_ICU1 + 1, 0x00); /* ignore slave */ 1187 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */ 1188 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */ 1189 1190 /* program IO APIC for type 3 INT on INT0 */ 1191 if (ext_int_setup(0, 0) < 0) 1192 panic("8254 redirect via APIC pin0 impossible!"); 1193 1194 x = 0; 1195 /* XXX if (bootverbose) */ 1196 printf("APIC_IO: routing 8254 via 8259 on pin 0\n"); 1197 } 1198 1199 /* failing that, look for 8254 on pin 2 */ 1200 else if (isa_apic_pin(0) == 2) { 1201 x = 2; 1202 /* XXX if (bootverbose) */ 1203 printf("APIC_IO: routing 8254 via pin 2\n"); 1204 } 1205 1206 /* better write that 8254 INT discover code... */ 1207 else 1208 panic("neither pin 0 or pin 2 works for 8254"); 1209 1210 /* setup the vectors */ 1211 vec[x] = (u_int)vec8254; 1212 Xintr8254 = (u_int)ivectors[x]; 1213 mask8254 = (1 << x); 1214 1215 register_intr(/* irq */ x, /* XXX id */ 0, /* flags */ 0, 1216 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1217 /* unit */ 0); 1218 INTREN(mask8254); 1219 1220#else /* APIC_IO */ 1221 1222 register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0, 1223 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1224 /* unit */ 0); 1225 INTREN(IRQ0); 1226 1227#endif /* APIC_IO */ 1228 1229 /* 1230 * Finish setting up anti-jitter measures. 1231 */ 1232 if (tsc_freq != 0) 1233 tsc_bias = rdtsc(); 1234 1235#ifndef PC98 1236 /* Initialize RTC. */ 1237 writertc(RTC_STATUSA, rtc_statusa); 1238 writertc(RTC_STATUSB, RTCSB_24HR); 1239 1240 /* Don't bother enabling the statistics clock. */ 1241 if (statclock_disable) 1242 return; 1243 diag = rtcin(RTC_DIAG); 1244 if (diag != 0) 1245 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 1246 1247#ifdef APIC_IO 1248 if (isa_apic_pin(8) != 8) 1249 panic("APIC RTC != 8"); 1250#endif /* APIC_IO */ 1251 1252 register_intr(/* irq */ 8, /* XXX id */ 1, /* flags */ 0, 1253 /* XXX */ (inthand2_t *)rtcintr, &stat_imask, 1254 /* unit */ 0); 1255 1256#ifdef APIC_IO 1257 INTREN(APIC_IRQ8); 1258#else 1259 INTREN(IRQ8); 1260#endif /* APIC_IO */ 1261 1262 writertc(RTC_STATUSB, rtc_statusb); 1263#endif /* !PC98 */ 1264} 1265 1266void 1267setstatclockrate(int newhz) 1268{ 1269#ifndef PC98 1270 if (newhz == RTC_PROFRATE) 1271 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1272 else 1273 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1274 writertc(RTC_STATUSA, rtc_statusa); 1275#endif 1276} 1277 1278static int 1279sysctl_machdep_i8254_freq SYSCTL_HANDLER_ARGS 1280{ 1281 int error; 1282 u_int freq; 1283 1284 /* 1285 * Use `i8254' instead of `timer' in external names because `timer' 1286 * is is too generic. Should use it everywhere. 1287 */ 1288 freq = timer_freq; 1289 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1290 if (error == 0 && req->newptr != NULL) { 1291 if (timer0_state != 0) 1292 return (EBUSY); /* too much trouble to handle */ 1293 set_timer_freq(freq, hz); 1294 if (tsc_present) 1295 set_tsc_freq(tsc_freq, timer_freq); 1296 } 1297 return (error); 1298} 1299 1300SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 1301 0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", ""); 1302 1303static void 1304set_tsc_freq(u_int tsc_count, u_int i8254_freq) 1305{ 1306 u_int comultiplier, multiplier; 1307 u_long ef; 1308 1309 if (tsc_count == 0) { 1310 tsc_freq = tsc_count; 1311 return; 1312 } 1313 comultiplier = ((unsigned long long)tsc_count 1314 << TSC_COMULTIPLIER_SHIFT) / i8254_freq; 1315 multiplier = (1000000LL << TSC_MULTIPLIER_SHIFT) / tsc_count; 1316 ef = read_eflags(); 1317 disable_intr(); 1318 tsc_freq = tsc_count; 1319 tsc_comultiplier = comultiplier; 1320 tsc_multiplier = multiplier; 1321 CLOCK_UNLOCK(); 1322 write_eflags(ef); 1323} 1324 1325static int 1326sysctl_machdep_tsc_freq SYSCTL_HANDLER_ARGS 1327{ 1328 int error; 1329 u_int freq; 1330 1331 if (!tsc_present) 1332 return (EOPNOTSUPP); 1333 freq = tsc_freq; 1334 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1335 if (error == 0 && req->newptr != NULL) 1336 set_tsc_freq(freq, timer_freq); 1337 return (error); 1338} 1339 1340SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_INT | CTLFLAG_RW, 1341 0, sizeof(u_int), sysctl_machdep_tsc_freq, "I", ""); 1342