pcrtc.c revision 21673
1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz and Don Ahn. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 37 * $FreeBSD: head/sys/pc98/cbus/pcrtc.c 21673 1997-01-14 07:20:47Z jkh $ 38 */ 39 40/* 41 * Routines to handle clock hardware. 42 */ 43 44/* 45 * inittodr, settodr and support routines written 46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 47 * 48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 49 */ 50 51/* 52 * modified for PC98 by Kakefuda 53 */ 54 55#include "opt_clock.h" 56#include "opt_cpu.h" 57 58#include <sys/param.h> 59#include <sys/systm.h> 60#include <sys/time.h> 61#include <sys/kernel.h> 62#include <sys/sysctl.h> 63 64#include <machine/clock.h> 65#ifdef CLK_CALIBRATION_LOOP 66#include <machine/cons.h> 67#endif 68#include <machine/cpu.h> 69#include <machine/frame.h> 70 71#include <i386/isa/icu.h> 72#ifdef PC98 73#include <pc98/pc98/pc98.h> 74#include <i386/isa/isa_device.h> 75#else 76#include <i386/isa/isa.h> 77#include <i386/isa/isa_device.h> 78#include <i386/isa/rtc.h> 79#endif 80#include <i386/isa/timerreg.h> 81 82/* 83 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 84 * can use a simple formula for leap years. 85 */ 86#define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 87#define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 88 89#define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) 90 91/* 92 * Time in timer cycles that it takes for microtime() to disable interrupts 93 * and latch the count. microtime() currently uses "cli; outb ..." so it 94 * normally takes less than 2 timer cycles. Add a few for cache misses. 95 * Add a few more to allow for latency in bogus calls to microtime() with 96 * interrupts already disabled. 97 */ 98#define TIMER0_LATCH_COUNT 20 99 100/* 101 * Maximum frequency that we are willing to allow for timer0. Must be 102 * low enough to guarantee that the timer interrupt handler returns 103 * before the next timer interrupt. Must result in a lower TIMER_DIV 104 * value than TIMER0_LATCH_COUNT so that we don't have to worry about 105 * underflow in the calculation of timer0_overflow_threshold. 106 */ 107#define TIMER0_MAX_FREQ 20000 108 109int adjkerntz; /* local offset from GMT in seconds */ 110int disable_rtc_set; /* disable resettodr() if != 0 */ 111u_int idelayed; 112#if defined(I586_CPU) || defined(I686_CPU) 113u_int i586_ctr_bias; 114u_int i586_ctr_comultiplier; 115u_int i586_ctr_freq; 116u_int i586_ctr_multiplier; 117#endif 118int statclock_disable; 119u_int stat_imask = SWI_CLOCK_MASK; 120#ifdef TIMER_FREQ 121u_int timer_freq = TIMER_FREQ; 122#else 123#ifdef PC98 124#ifndef AUTO_CLOCK 125#ifndef PC98_8M 126u_int timer_freq = 2457600; 127#else /* !PC98_8M */ 128u_int timer_freq = 1996800; 129#endif /* PC98_8M */ 130#else /* AUTO_CLOCK */ 131u_int timer_freq = 2457600; 132#endif /* AUTO_CLOCK */ 133#else /* IBM-PC */ 134u_int timer_freq = 1193182; 135#endif /* PC98 */ 136#endif 137int timer0_max_count; 138u_int timer0_overflow_threshold; 139u_int timer0_prescaler_count; 140int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 141 142static int beeping = 0; 143static u_int clk_imask = HWI_MASK | SWI_MASK; 144static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 145static u_int hardclock_max_count; 146/* 147 * XXX new_function and timer_func should not handle clockframes, but 148 * timer_func currently needs to hold hardclock to handle the 149 * timer0_state == 0 case. We should use register_intr()/unregister_intr() 150 * to switch between clkintr() and a slightly different timerintr(). 151 */ 152static void (*new_function) __P((struct clockframe *frame)); 153static u_int new_rate; 154#ifndef PC98 155static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 156static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 157#endif 158 159/* Values for timerX_state: */ 160#define RELEASED 0 161#define RELEASE_PENDING 1 162#define ACQUIRED 2 163#define ACQUIRE_PENDING 3 164 165static u_char timer0_state; 166#ifdef PC98 167static u_char timer1_state; 168#endif 169static u_char timer2_state; 170static void (*timer_func) __P((struct clockframe *frame)) = hardclock; 171#ifdef PC98 172static void rtc_serialcombit __P((int)); 173static void rtc_serialcom __P((int)); 174static int rtc_inb __P((void)); 175static void rtc_outb __P((int)); 176#endif 177 178#if defined(I586_CPU) || defined(I686_CPU) 179static void set_i586_ctr_freq(u_int i586_freq, u_int i8254_freq); 180#endif 181 182static void 183clkintr(struct clockframe frame) 184{ 185 timer_func(&frame); 186 switch (timer0_state) { 187 188 case RELEASED: 189 setdelayed(); 190 break; 191 192 case ACQUIRED: 193 if ((timer0_prescaler_count += timer0_max_count) 194 >= hardclock_max_count) { 195 hardclock(&frame); 196 setdelayed(); 197 timer0_prescaler_count -= hardclock_max_count; 198 } 199 break; 200 201 case ACQUIRE_PENDING: 202 setdelayed(); 203 timer0_max_count = TIMER_DIV(new_rate); 204 timer0_overflow_threshold = 205 timer0_max_count - TIMER0_LATCH_COUNT; 206 disable_intr(); 207 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 208 outb(TIMER_CNTR0, timer0_max_count & 0xff); 209 outb(TIMER_CNTR0, timer0_max_count >> 8); 210 enable_intr(); 211 timer0_prescaler_count = 0; 212 timer_func = new_function; 213 timer0_state = ACQUIRED; 214 break; 215 216 case RELEASE_PENDING: 217 if ((timer0_prescaler_count += timer0_max_count) 218 >= hardclock_max_count) { 219 hardclock(&frame); 220 setdelayed(); 221 timer0_max_count = hardclock_max_count; 222 timer0_overflow_threshold = 223 timer0_max_count - TIMER0_LATCH_COUNT; 224 disable_intr(); 225 outb(TIMER_MODE, 226 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 227 outb(TIMER_CNTR0, timer0_max_count & 0xff); 228 outb(TIMER_CNTR0, timer0_max_count >> 8); 229 enable_intr(); 230 /* 231 * See microtime.s for this magic. 232 */ 233#ifdef PC98 234#ifndef AUTO_CLOCK 235#ifndef PC98_8M 236 time.tv_usec += (6667 * 237 (timer0_prescaler_count - hardclock_max_count)) 238 >> 14; 239#else /* PC98_8M */ 240 time.tv_usec += (16411 * 241 (timer0_prescaler_count - hardclock_max_count)) 242 >> 15; 243#endif /* PC98_8M */ 244#else /* AUTO_CLOCK */ 245 if (pc98_machine_type & M_8M) { 246 /* PC98_8M */ 247 time.tv_usec += (16411 * 248 (timer0_prescaler_count - 249 hardclock_max_count)) >> 15; 250 } else { 251 time.tv_usec += (6667 * 252 (timer0_prescaler_count - 253 hardclock_max_count)) >> 14; 254 } 255#endif /* AUTO_CLOCK */ 256#else /* IBM-PC */ 257 time.tv_usec += (27465 * 258 (timer0_prescaler_count - hardclock_max_count)) 259 >> 15; 260#endif /* PC98 */ 261 if (time.tv_usec >= 1000000) 262 time.tv_usec -= 1000000; 263 timer0_prescaler_count = 0; 264 timer_func = hardclock; 265 timer0_state = RELEASED; 266 } 267 break; 268 } 269} 270 271/* 272 * The acquire and release functions must be called at ipl >= splclock(). 273 */ 274int 275acquire_timer0(int rate, void (*function) __P((struct clockframe *frame))) 276{ 277 static int old_rate; 278 279 if (rate <= 0 || rate > TIMER0_MAX_FREQ) 280 return (-1); 281 switch (timer0_state) { 282 283 case RELEASED: 284 timer0_state = ACQUIRE_PENDING; 285 break; 286 287 case RELEASE_PENDING: 288 if (rate != old_rate) 289 return (-1); 290 /* 291 * The timer has been released recently, but is being 292 * re-acquired before the release completed. In this 293 * case, we simply reclaim it as if it had not been 294 * released at all. 295 */ 296 timer0_state = ACQUIRED; 297 break; 298 299 default: 300 return (-1); /* busy */ 301 } 302 new_function = function; 303 old_rate = new_rate = rate; 304 return (0); 305} 306 307#ifdef PC98 308int 309acquire_timer1(int mode) 310{ 311 312 if (timer1_state != RELEASED) 313 return (-1); 314 timer1_state = ACQUIRED; 315 316 /* 317 * This access to the timer registers is as atomic as possible 318 * because it is a single instruction. We could do better if we 319 * knew the rate. Use of splclock() limits glitches to 10-100us, 320 * and this is probably good enough for timer2, so we aren't as 321 * careful with it as with timer0. 322 */ 323 outb(TIMER_MODE, TIMER_SEL1 | (mode & 0x3f)); 324 325 return (0); 326} 327#endif 328 329int 330acquire_timer2(int mode) 331{ 332 333 if (timer2_state != RELEASED) 334 return (-1); 335 timer2_state = ACQUIRED; 336 337 /* 338 * This access to the timer registers is as atomic as possible 339 * because it is a single instruction. We could do better if we 340 * knew the rate. Use of splclock() limits glitches to 10-100us, 341 * and this is probably good enough for timer2, so we aren't as 342 * careful with it as with timer0. 343 */ 344 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 345 346 return (0); 347} 348 349int 350release_timer0() 351{ 352 switch (timer0_state) { 353 354 case ACQUIRED: 355 timer0_state = RELEASE_PENDING; 356 break; 357 358 case ACQUIRE_PENDING: 359 /* Nothing happened yet, release quickly. */ 360 timer0_state = RELEASED; 361 break; 362 363 default: 364 return (-1); 365 } 366 return (0); 367} 368 369#ifdef PC98 370int 371release_timer1() 372{ 373 374 if (timer1_state != ACQUIRED) 375 return (-1); 376 timer1_state = RELEASED; 377 outb(TIMER_MODE, TIMER_SEL1 | TIMER_SQWAVE | TIMER_16BIT); 378 return (0); 379} 380#endif 381 382int 383release_timer2() 384{ 385 386 if (timer2_state != ACQUIRED) 387 return (-1); 388 timer2_state = RELEASED; 389 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 390 return (0); 391} 392 393#ifndef PC98 394/* 395 * This routine receives statistical clock interrupts from the RTC. 396 * As explained above, these occur at 128 interrupts per second. 397 * When profiling, we receive interrupts at a rate of 1024 Hz. 398 * 399 * This does not actually add as much overhead as it sounds, because 400 * when the statistical clock is active, the hardclock driver no longer 401 * needs to keep (inaccurate) statistics on its own. This decouples 402 * statistics gathering from scheduling interrupts. 403 * 404 * The RTC chip requires that we read status register C (RTC_INTR) 405 * to acknowledge an interrupt, before it will generate the next one. 406 */ 407static void 408rtcintr(struct clockframe frame) 409{ 410 u_char stat; 411 stat = rtcin(RTC_INTR); 412 if(stat & RTCIR_PERIOD) { 413 statclock(&frame); 414 } 415} 416 417#include "opt_ddb.h" 418#ifdef DDB 419#include <ddb/ddb.h> 420 421DB_SHOW_COMMAND(rtc, rtc) 422{ 423 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 424 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 425 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 426 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 427} 428#endif /* DDB */ 429#endif /* for PC98 */ 430 431static int 432getit(void) 433{ 434 u_long ef; 435 int high, low; 436 437 ef = read_eflags(); 438 disable_intr(); 439 440 /* Select timer0 and latch counter value. */ 441 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 442 443 low = inb(TIMER_CNTR0); 444 high = inb(TIMER_CNTR0); 445 446 write_eflags(ef); 447 return ((high << 8) | low); 448} 449 450/* 451 * Wait "n" microseconds. 452 * Relies on timer 1 counting down from (timer_freq / hz) 453 * Note: timer had better have been programmed before this is first used! 454 */ 455void 456DELAY(int n) 457{ 458 int prev_tick, tick, ticks_left, sec, usec; 459 460#ifdef DELAYDEBUG 461 int getit_calls = 1; 462 int n1; 463 static int state = 0; 464 465 if (state == 0) { 466 state = 1; 467 for (n1 = 1; n1 <= 10000000; n1 *= 10) 468 DELAY(n1); 469 state = 2; 470 } 471 if (state == 1) 472 printf("DELAY(%d)...", n); 473#endif 474 /* 475 * Read the counter first, so that the rest of the setup overhead is 476 * counted. Guess the initial overhead is 20 usec (on most systems it 477 * takes about 1.5 usec for each of the i/o's in getit(). The loop 478 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 479 * multiplications and divisions to scale the count take a while). 480 */ 481 prev_tick = getit(); 482 n -= 20; 483 /* 484 * Calculate (n * (timer_freq / 1e6)) without using floating point 485 * and without any avoidable overflows. 486 */ 487 sec = n / 1000000; 488 usec = n - sec * 1000000; 489 ticks_left = sec * timer_freq 490 + usec * (timer_freq / 1000000) 491 + usec * ((timer_freq % 1000000) / 1000) / 1000 492 + usec * (timer_freq % 1000) / 1000000; 493 if (n < 0) 494 ticks_left = 0; /* XXX timer_freq is unsigned */ 495 496 while (ticks_left > 0) { 497 tick = getit(); 498#ifdef DELAYDEBUG 499 ++getit_calls; 500#endif 501 if (tick > prev_tick) 502 ticks_left -= prev_tick - (tick - timer0_max_count); 503 else 504 ticks_left -= prev_tick - tick; 505 prev_tick = tick; 506 } 507#ifdef DELAYDEBUG 508 if (state == 1) 509 printf(" %d calls to getit() at %d usec each\n", 510 getit_calls, (n + 5) / getit_calls); 511#endif 512} 513 514static void 515sysbeepstop(void *chan) 516{ 517#ifdef PC98 /* PC98 */ 518 outb(IO_PPI, inb(IO_PPI)|0x08); /* disable counter1 output to speaker */ 519 release_timer1(); 520#else 521 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 522 release_timer2(); 523#endif 524 beeping = 0; 525} 526 527int 528sysbeep(int pitch, int period) 529{ 530 int x = splclock(); 531 532#ifdef PC98 533 if (acquire_timer1(TIMER_SQWAVE|TIMER_16BIT)) 534 if (!beeping) { 535 /* Something else owns it. */ 536 splx(x); 537 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 538 } 539 disable_intr(); 540 outb(0x3fdb, pitch); 541 outb(0x3fdb, (pitch>>8)); 542 enable_intr(); 543 if (!beeping) { 544 /* enable counter1 output to speaker */ 545 outb(IO_PPI, (inb(IO_PPI) & 0xf7)); 546 beeping = period; 547 timeout(sysbeepstop, (void *)NULL, period); 548 } 549#else 550 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 551 if (!beeping) { 552 /* Something else owns it. */ 553 splx(x); 554 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 555 } 556 disable_intr(); 557 outb(TIMER_CNTR2, pitch); 558 outb(TIMER_CNTR2, (pitch>>8)); 559 enable_intr(); 560 if (!beeping) { 561 /* enable counter2 output to speaker */ 562 outb(IO_PPI, inb(IO_PPI) | 3); 563 beeping = period; 564 timeout(sysbeepstop, (void *)NULL, period); 565 } 566#endif 567 splx(x); 568 return (0); 569} 570 571#ifndef PC98 572/* 573 * RTC support routines 574 */ 575 576int 577rtcin(reg) 578 int reg; 579{ 580 u_char val; 581 582 outb(IO_RTC, reg); 583 inb(0x84); 584 val = inb(IO_RTC + 1); 585 inb(0x84); 586 return (val); 587} 588 589static __inline void 590writertc(u_char reg, u_char val) 591{ 592 outb(IO_RTC, reg); 593 outb(IO_RTC + 1, val); 594} 595 596static __inline int 597readrtc(int port) 598{ 599 return(bcd2bin(rtcin(port))); 600} 601#endif 602 603#ifdef PC98 604unsigned int delaycount; 605#define FIRST_GUESS 0x2000 606static void findcpuspeed(void) 607{ 608 int i; 609 int remainder; 610 611 /* Put counter in count down mode */ 612 outb(TIMER_MODE, TIMER_SEL0 | TIMER_16BIT | TIMER_RATEGEN); 613 outb(TIMER_CNTR0, 0xff); 614 outb(TIMER_CNTR0, 0xff); 615 for (i = FIRST_GUESS; i; i--) 616 ; 617 remainder = getit(); 618 delaycount = (FIRST_GUESS * TIMER_DIV(1000)) / (0xffff - remainder); 619} 620#endif 621 622#ifndef PC98 623static u_int 624calibrate_clocks(void) 625{ 626 u_int count, prev_count, tot_count; 627 int sec, start_sec, timeout; 628 629 printf("Calibrating clock(s) relative to mc146818A clock ... "); 630 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 631 goto fail; 632 timeout = 100000000; 633 634 /* Read the mc146818A seconds counter. */ 635 for (;;) { 636 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 637 sec = rtcin(RTC_SEC); 638 break; 639 } 640 if (--timeout == 0) 641 goto fail; 642 } 643 644 /* Wait for the mC146818A seconds counter to change. */ 645 start_sec = sec; 646 for (;;) { 647 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 648 sec = rtcin(RTC_SEC); 649 if (sec != start_sec) 650 break; 651 } 652 if (--timeout == 0) 653 goto fail; 654 } 655 656 /* Start keeping track of the i8254 counter. */ 657 prev_count = getit(); 658 if (prev_count == 0 || prev_count > timer0_max_count) 659 goto fail; 660 tot_count = 0; 661 662#if defined(I586_CPU) || defined(I686_CPU) 663 if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686) 664 wrmsr(0x10, 0LL); /* XXX 0x10 is the MSR for the TSC */ 665#endif 666 667 /* 668 * Wait for the mc146818A seconds counter to change. Read the i8254 669 * counter for each iteration since this is convenient and only 670 * costs a few usec of inaccuracy. The timing of the final reads 671 * of the counters almost matches the timing of the initial reads, 672 * so the main cause of inaccuracy is the varying latency from 673 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 674 * rtcin(RTC_SEC) that returns a changed seconds count. The 675 * maximum inaccuracy from this cause is < 10 usec on 486's. 676 */ 677 start_sec = sec; 678 for (;;) { 679 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 680 sec = rtcin(RTC_SEC); 681 count = getit(); 682 if (count == 0 || count > timer0_max_count) 683 goto fail; 684 if (count > prev_count) 685 tot_count += prev_count - (count - timer0_max_count); 686 else 687 tot_count += prev_count - count; 688 prev_count = count; 689 if (sec != start_sec) 690 break; 691 if (--timeout == 0) 692 goto fail; 693 } 694 695#if defined(I586_CPU) || defined(I686_CPU) 696 /* 697 * Read the cpu cycle counter. The timing considerations are 698 * similar to those for the i8254 clock. 699 */ 700 if (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686) { 701 set_i586_ctr_freq((u_int)rdtsc(), tot_count); 702 printf("i586 clock: %u Hz, ", i586_ctr_freq); 703 } 704#endif 705 706 printf("i8254 clock: %u Hz\n", tot_count); 707 return (tot_count); 708 709fail: 710 printf("failed, using default i8254 clock of %u Hz\n", timer_freq); 711 return (timer_freq); 712} 713#endif /* !PC98 */ 714 715static void 716set_timer_freq(u_int freq, int intr_freq) 717{ 718 u_long ef; 719 720 ef = read_eflags(); 721 disable_intr(); 722 timer_freq = freq; 723 timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); 724 timer0_overflow_threshold = timer0_max_count - TIMER0_LATCH_COUNT; 725 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 726 outb(TIMER_CNTR0, timer0_max_count & 0xff); 727 outb(TIMER_CNTR0, timer0_max_count >> 8); 728 write_eflags(ef); 729} 730 731/* 732 * Initialize 8253 timer 0 early so that it can be used in DELAY(). 733 * XXX initialization of other timers is unintentionally left blank. 734 */ 735void 736startrtclock() 737{ 738 u_int delta, freq; 739 740#ifdef PC98 741 findcpuspeed(); 742#ifndef AUTO_CLOCK 743 if (pc98_machine_type & M_8M) { 744#ifndef PC98_8M 745 printf("you must reconfig a kernel with \"PC98_8M\" option.\n"); 746#endif 747 } else { 748#ifdef PC98_8M 749 printf("You must reconfig a kernel without \"PC98_8M\" option.\n"); 750#endif 751 } 752#else /* AUTO_CLOCK */ 753 if (pc98_machine_type & M_8M) 754 timer_freq = 1996800L; /* 1.9968 MHz */ 755 else 756 timer_freq = 2457600L; /* 2.4576 MHz */ 757#endif /* AUTO_CLOCK */ 758#endif /* PC98 */ 759 760#ifndef PC98 761 writertc(RTC_STATUSA, rtc_statusa); 762 writertc(RTC_STATUSB, RTCSB_24HR); 763#endif 764 765#ifndef PC98 766 set_timer_freq(timer_freq, hz); 767 freq = calibrate_clocks(); 768#ifdef CLK_CALIBRATION_LOOP 769 if (bootverbose) { 770 printf( 771 "Press a key on the console to abort clock calibration\n"); 772 while (cncheckc() == -1) 773 calibrate_clocks(); 774 } 775#endif 776 777 /* 778 * Use the calibrated i8254 frequency if it seems reasonable. 779 * Otherwise use the default, and don't use the calibrated i586 780 * frequency. 781 */ 782 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; 783 if (delta < timer_freq / 100) { 784#ifndef CLK_USE_I8254_CALIBRATION 785 if (bootverbose) 786 printf( 787"CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 788 freq = timer_freq; 789#endif 790 timer_freq = freq; 791 } else { 792 printf("%d Hz differs from default of %d Hz by more than 1%%\n", 793 freq, timer_freq); 794#if defined(I586_CPU) || defined(I686_CPU) 795 i586_ctr_freq = 0; 796#endif 797 } 798#endif 799 800 set_timer_freq(timer_freq, hz); 801 802#if defined(I586_CPU) || defined(I686_CPU) 803#ifndef CLK_USE_I586_CALIBRATION 804 if (i586_ctr_freq != 0) { 805 if (bootverbose) 806 printf( 807"CLK_USE_I586_CALIBRATION not specified - using old calibration method\n"); 808 i586_ctr_freq = 0; 809 } 810#endif 811 if (i586_ctr_freq == 0 && 812 (cpu_class == CPUCLASS_586 || cpu_class == CPUCLASS_686)) { 813 /* 814 * Calibration of the i586 clock relative to the mc146818A 815 * clock failed. Do a less accurate calibration relative 816 * to the i8254 clock. 817 */ 818 wrmsr(0x10, 0LL); /* XXX */ 819 DELAY(1000000); 820 set_i586_ctr_freq((u_int)rdtsc(), timer_freq); 821#ifdef CLK_USE_I586_CALIBRATION 822 printf("i586 clock: %u Hz\n", i586_ctr_freq); 823#endif 824 } 825#endif 826} 827 828#ifdef PC98 829static void 830rtc_serialcombit(int i) 831{ 832 outb(IO_RTC, ((i&0x01)<<5)|0x07); 833 DELAY(1); 834 outb(IO_RTC, ((i&0x01)<<5)|0x17); 835 DELAY(1); 836 outb(IO_RTC, ((i&0x01)<<5)|0x07); 837 DELAY(1); 838} 839 840static void 841rtc_serialcom(int i) 842{ 843 rtc_serialcombit(i&0x01); 844 rtc_serialcombit((i&0x02)>>1); 845 rtc_serialcombit((i&0x04)>>2); 846 rtc_serialcombit((i&0x08)>>3); 847 outb(IO_RTC, 0x07); 848 DELAY(1); 849 outb(IO_RTC, 0x0f); 850 DELAY(1); 851 outb(IO_RTC, 0x07); 852 DELAY(1); 853} 854 855static void 856rtc_outb(int val) 857{ 858 int s; 859 int sa = 0; 860 861 for (s=0;s<8;s++) { 862 sa = ((val >> s) & 0x01) ? 0x27 : 0x07; 863 outb(IO_RTC, sa); /* set DI & CLK 0 */ 864 DELAY(1); 865 outb(IO_RTC, sa | 0x10); /* CLK 1 */ 866 DELAY(1); 867 } 868 outb(IO_RTC, sa & 0xef); /* CLK 0 */ 869} 870 871static int 872rtc_inb(void) 873{ 874 int s; 875 int sa = 0; 876 877 for (s=0;s<8;s++) { 878 sa |= ((inb(0x33) & 0x01) << s); 879 outb(IO_RTC, 0x17); /* CLK 1 */ 880 DELAY(1); 881 outb(IO_RTC, 0x07); /* CLK 0 */ 882 DELAY(2); 883 } 884 return sa; 885} 886#endif /* PC-98 */ 887 888/* 889 * Initialize the time of day register, based on the time base which is, e.g. 890 * from a filesystem. 891 */ 892void 893inittodr(time_t base) 894{ 895 unsigned long sec, days; 896 int yd; 897 int year, month; 898 int y, m, s; 899#ifdef PC98 900 int second, min, hour; 901#endif 902 903 s = splclock(); 904 time.tv_sec = base; 905 time.tv_usec = 0; 906 splx(s); 907 908#ifdef PC98 909 rtc_serialcom(0x03); /* Time Read */ 910 rtc_serialcom(0x01); /* Register shift command. */ 911 DELAY(20); 912 913 second = bcd2bin(rtc_inb() & 0xff); /* sec */ 914 min = bcd2bin(rtc_inb() & 0xff); /* min */ 915 hour = bcd2bin(rtc_inb() & 0xff); /* hour */ 916 days = bcd2bin(rtc_inb() & 0xff) - 1; /* date */ 917 918 month = (rtc_inb() >> 4) & 0x0f; /* month */ 919 for (m = 1; m < month; m++) 920 days += daysinmonth[m-1]; 921 year = bcd2bin(rtc_inb() & 0xff) + 1900; /* year */ 922 /* 2000 year problem */ 923 if (year < 1995) 924 year += 100; 925 if (year < 1970) 926 goto wrong_time; 927 for (y = 1970; y < year; y++) 928 days += DAYSPERYEAR + LEAPYEAR(y); 929 if ((month > 2) && LEAPYEAR(year)) 930 days ++; 931 sec = ((( days * 24 + 932 hour) * 60 + 933 min) * 60 + 934 second); 935 /* sec now contains the number of seconds, since Jan 1 1970, 936 in the local time zone */ 937#else /* IBM-PC */ 938 /* Look if we have a RTC present and the time is valid */ 939 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 940 goto wrong_time; 941 942 /* wait for time update to complete */ 943 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 944 while (rtcin(RTC_STATUSA) & RTCSA_TUP); 945 946 days = 0; 947#ifdef USE_RTC_CENTURY 948 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 949#else 950 year = readrtc(RTC_YEAR) + 1900; 951 if (year < 1970) 952 year += 100; 953#endif 954 if (year < 1970) 955 goto wrong_time; 956 month = readrtc(RTC_MONTH); 957 for (m = 1; m < month; m++) 958 days += daysinmonth[m-1]; 959 if ((month > 2) && LEAPYEAR(year)) 960 days ++; 961 days += readrtc(RTC_DAY) - 1; 962 yd = days; 963 for (y = 1970; y < year; y++) 964 days += DAYSPERYEAR + LEAPYEAR(y); 965 sec = ((( days * 24 + 966 readrtc(RTC_HRS)) * 60 + 967 readrtc(RTC_MIN)) * 60 + 968 readrtc(RTC_SEC)); 969 /* sec now contains the number of seconds, since Jan 1 1970, 970 in the local time zone */ 971#endif 972 973 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 974 975 s = splclock(); 976 time.tv_sec = sec; 977 splx(s); 978 return; 979 980wrong_time: 981 printf("Invalid time in real time clock.\n"); 982 printf("Check and reset the date immediately!\n"); 983} 984 985/* 986 * Write system time back to RTC 987 */ 988void 989resettodr() 990{ 991 unsigned long tm; 992 int y, m, s; 993#ifdef PC98 994 int wd; 995#endif 996 997 if (disable_rtc_set) 998 return; 999 1000 s = splclock(); 1001 tm = time.tv_sec; 1002 splx(s); 1003 1004#ifdef PC98 1005 rtc_serialcom(0x01); /* Register shift command. */ 1006 1007 /* Calculate local time to put in RTC */ 1008 1009 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1010 1011 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1012 rtc_outb(bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1013 rtc_outb(bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1014 1015 /* We have now the days since 01-01-1970 in tm */ 1016 wd = (tm+4)%7; 1017 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1018 tm >= m; 1019 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1020 tm -= m; 1021 1022 /* Now we have the years in y and the day-of-the-year in tm */ 1023 for (m = 0; ; m++) { 1024 int ml; 1025 1026 ml = daysinmonth[m]; 1027 if (m == 1 && LEAPYEAR(y)) 1028 ml++; 1029 if (tm < ml) 1030 break; 1031 tm -= ml; 1032 } 1033 1034 m++; 1035 rtc_outb(bin2bcd(tm+1)); /* Write back Day */ 1036 rtc_outb((m << 4) | wd); /* Write back Month & Weekday */ 1037 rtc_outb(bin2bcd(y%100)); /* Write back Year */ 1038 1039 rtc_serialcom(0x02); /* Time set & Counter hold command. */ 1040 rtc_serialcom(0x00); /* Register hold command. */ 1041#else 1042 /* Disable RTC updates and interrupts. */ 1043 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 1044 1045 /* Calculate local time to put in RTC */ 1046 1047 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 1048 1049 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 1050 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 1051 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 1052 1053 /* We have now the days since 01-01-1970 in tm */ 1054 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 1055 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 1056 tm >= m; 1057 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 1058 tm -= m; 1059 1060 /* Now we have the years in y and the day-of-the-year in tm */ 1061 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 1062#ifdef USE_RTC_CENTURY 1063 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 1064#endif 1065 for (m = 0; ; m++) { 1066 int ml; 1067 1068 ml = daysinmonth[m]; 1069 if (m == 1 && LEAPYEAR(y)) 1070 ml++; 1071 if (tm < ml) 1072 break; 1073 tm -= ml; 1074 } 1075 1076 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 1077 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 1078 1079 /* Reenable RTC updates and interrupts. */ 1080 writertc(RTC_STATUSB, rtc_statusb); 1081#endif 1082} 1083 1084/* 1085 * Start both clocks running. 1086 */ 1087void 1088cpu_initclocks() 1089{ 1090#ifndef PC98 1091 int diag; 1092 1093 if (statclock_disable) { 1094 /* 1095 * The stat interrupt mask is different without the 1096 * statistics clock. Also, don't set the interrupt 1097 * flag which would normally cause the RTC to generate 1098 * interrupts. 1099 */ 1100 stat_imask = HWI_MASK | SWI_MASK; 1101 rtc_statusb = RTCSB_24HR; 1102 } else { 1103 /* Setting stathz to nonzero early helps avoid races. */ 1104 stathz = RTC_NOPROFRATE; 1105 profhz = RTC_PROFRATE; 1106 } 1107#endif 1108 1109 /* Finish initializing 8253 timer 0. */ 1110 register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0, 1111 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1112 /* unit */ 0); 1113 INTREN(IRQ0); 1114#if defined(I586_CPU) || defined(I686_CPU) 1115 /* 1116 * Finish setting up anti-jitter measures. 1117 */ 1118 if (i586_ctr_freq != 0) 1119 i586_ctr_bias = rdtsc(); 1120#endif 1121 1122#ifndef PC98 1123 /* Initialize RTC. */ 1124 writertc(RTC_STATUSA, rtc_statusa); 1125 writertc(RTC_STATUSB, RTCSB_24HR); 1126 1127 /* Don't bother enabling the statistics clock. */ 1128 if (statclock_disable) 1129 return; 1130 diag = rtcin(RTC_DIAG); 1131 if (diag != 0) 1132 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 1133 register_intr(/* irq */ 8, /* XXX id */ 1, /* flags */ 0, 1134 /* XXX */ (inthand2_t *)rtcintr, &stat_imask, 1135 /* unit */ 0); 1136 INTREN(IRQ8); 1137 writertc(RTC_STATUSB, rtc_statusb); 1138#endif 1139} 1140 1141void 1142setstatclockrate(int newhz) 1143{ 1144#ifndef PC98 1145 if (newhz == RTC_PROFRATE) 1146 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1147 else 1148 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1149 writertc(RTC_STATUSA, rtc_statusa); 1150#endif 1151} 1152 1153static int 1154sysctl_machdep_i8254_freq SYSCTL_HANDLER_ARGS 1155{ 1156 int error; 1157 u_int freq; 1158 1159 /* 1160 * Use `i8254' instead of `timer' in external names because `timer' 1161 * is is too generic. Should use it everywhere. 1162 */ 1163 freq = timer_freq; 1164 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1165 if (error == 0 && req->newptr != NULL) { 1166 if (timer0_state != 0) 1167 return (EBUSY); /* too much trouble to handle */ 1168 set_timer_freq(freq, hz); 1169#if defined(I586_CPU) || defined(I686_CPU) 1170 set_i586_ctr_freq(i586_ctr_freq, timer_freq); 1171#endif 1172 } 1173 return (error); 1174} 1175 1176SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 1177 0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", ""); 1178 1179#if defined(I586_CPU) || defined(I686_CPU) 1180static void 1181set_i586_ctr_freq(u_int i586_freq, u_int i8254_freq) 1182{ 1183 u_int comultiplier, multiplier; 1184 u_long ef; 1185 1186 if (i586_freq == 0) { 1187 i586_ctr_freq = i586_freq; 1188 return; 1189 } 1190 comultiplier = ((unsigned long long)i586_freq 1191 << I586_CTR_COMULTIPLIER_SHIFT) / i8254_freq; 1192 multiplier = (1000000LL << I586_CTR_MULTIPLIER_SHIFT) / i586_freq; 1193 ef = read_eflags(); 1194 disable_intr(); 1195 i586_ctr_freq = i586_freq; 1196 i586_ctr_comultiplier = comultiplier; 1197 i586_ctr_multiplier = multiplier; 1198 write_eflags(ef); 1199} 1200 1201static int 1202sysctl_machdep_i586_freq SYSCTL_HANDLER_ARGS 1203{ 1204 int error; 1205 u_int freq; 1206 1207 if (cpu_class != CPUCLASS_586 && cpu_class != CPUCLASS_686) 1208 return (EOPNOTSUPP); 1209 freq = i586_ctr_freq; 1210 error = sysctl_handle_opaque(oidp, &freq, sizeof freq, req); 1211 if (error == 0 && req->newptr != NULL) 1212 set_i586_ctr_freq(freq, timer_freq); 1213 return (error); 1214} 1215 1216SYSCTL_PROC(_machdep, OID_AUTO, i586_freq, CTLTYPE_INT | CTLFLAG_RW, 1217 0, sizeof(u_int), sysctl_machdep_i586_freq, "I", ""); 1218#endif /* defined(I586_CPU) || defined(I686_CPU) */ 1219