116359Sasami/*- 216359Sasami * Copyright (c) 1991 The Regents of the University of California. 316359Sasami * All rights reserved. 416359Sasami * 516359Sasami * Redistribution and use in source and binary forms, with or without 616359Sasami * modification, are permitted provided that the following conditions 716359Sasami * are met: 816359Sasami * 1. Redistributions of source code must retain the above copyright 916359Sasami * notice, this list of conditions and the following disclaimer. 1016359Sasami * 2. Redistributions in binary form must reproduce the above copyright 1116359Sasami * notice, this list of conditions and the following disclaimer in the 1216359Sasami * documentation and/or other materials provided with the distribution. 1316359Sasami * 4. Neither the name of the University nor the names of its contributors 1416359Sasami * may be used to endorse or promote products derived from this software 1516359Sasami * without specific prior written permission. 1616359Sasami * 1716359Sasami * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 1816359Sasami * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1916359Sasami * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2016359Sasami * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 2116359Sasami * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2216359Sasami * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2316359Sasami * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2416359Sasami * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2516359Sasami * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2616359Sasami * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2716359Sasami * SUCH DAMAGE. 2816359Sasami * 2916359Sasami * from: @(#)fdreg.h 7.1 (Berkeley) 5/9/91 3050477Speter * $FreeBSD$ 3116359Sasami */ 3216359Sasami 3316359Sasami/* 3416359Sasami * AT floppy controller registers and bitfields 3516359Sasami */ 3616359Sasami 3716359Sasami/* uses NEC765 controller */ 3877726Sjoerg#include <dev/ic/nec765.h> 3916359Sasami 4018208Sasami#ifdef PC98 4118208Sasami/* registers */ 4216359Sasami#define FDSTS 0 /* NEC 765 Main Status Register (R) */ 4379704Snyan#define FDDATA 1 /* NEC 765 Data Register (R/W) */ 4479704Snyan#define FDCTL 2 /* FD Control Register */ 4579704Snyan#define FDC_RST 0x80 /* FDC RESET */ 4679704Snyan#define FDC_RDY 0x40 /* force READY */ 4779704Snyan#define FDC_DD 0x20 /* FDD Mode Exchange 0:1M 1:640K */ 4879704Snyan#define FDC_DMAE 0x10 /* enable floppy DMA */ 4979704Snyan#define FDC_MTON 0x08 /* MOTOR ON (when EMTON=1)*/ 5079704Snyan#define FDC_TMSK 0x04 /* TIMER MASK */ 5179704Snyan#define FDC_TTRG 0x01 /* TIMER TRIGER */ 5216359Sasami 5316359Sasami#define FDP_EMTON 0x04 /* enable MTON */ 5416359Sasami#define FDP_FDDEXC 0x02 /* FDD Mode Exchange 1:1M 0:640K */ 5516359Sasami#define FDP_PORTEXC 0x01 /* PORT Exchane 1:1M 0:640K */ 5616359Sasami 5716359Sasami#else 5816359Sasami/* registers */ 5916359Sasami#define FDOUT 2 /* Digital Output Register (W) */ 6016359Sasami#define FDO_FDSEL 0x03 /* floppy device select */ 6116359Sasami#define FDO_FRST 0x04 /* floppy controller reset */ 6216359Sasami#define FDO_FDMAEN 0x08 /* enable floppy DMA and Interrupt */ 6316359Sasami#define FDO_MOEN0 0x10 /* motor enable drive 0 */ 6416359Sasami#define FDO_MOEN1 0x20 /* motor enable drive 1 */ 6516359Sasami#define FDO_MOEN2 0x40 /* motor enable drive 2 */ 6616359Sasami#define FDO_MOEN3 0x80 /* motor enable drive 3 */ 6716359Sasami 6816359Sasami#define FDSTS 4 /* NEC 765 Main Status Register (R) */ 6916359Sasami#define FDDATA 5 /* NEC 765 Data Register (R/W) */ 7016359Sasami#define FDCTL 7 /* Control Register (W) */ 7179704Snyan#endif /* PC98 */ 7216359Sasami 7355652Snyan/* 7488011Snyan * The definitions for FDC_500KBPS etc. have been moved out to <sys/fdcio.h> 7588011Snyan * since they need to be visible in userland. They cover the lower two bits 7688011Snyan * of FDCTL when used for output. 7788011Snyan */ 7888011Snyan/* 7955652Snyan * this is the secret PIO data port (offset from base) 8055652Snyan */ 8155652Snyan#define FDC_YE_DATAPORT 6 8255652Snyan 8355652Snyan#ifndef PC98 8416359Sasami#define FDIN 7 /* Digital Input Register (R) */ 8516359Sasami#define FDI_DCHG 0x80 /* diskette has been changed */ 8616359Sasami /* requires drive and motor being selected */ 8716359Sasami /* is cleared by any step pulse to drive */ 8816359Sasami#endif 89