1219820Sjeff/* 2219820Sjeff * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3219820Sjeff * Copyright (c) 2005 Mellanox Technologies. All rights reserved. 4219820Sjeff * 5219820Sjeff * This software is available to you under a choice of one of two 6219820Sjeff * licenses. You may choose to be licensed under the terms of the GNU 7219820Sjeff * General Public License (GPL) Version 2, available from the file 8219820Sjeff * COPYING in the main directory of this source tree, or the 9219820Sjeff * OpenIB.org BSD license below: 10219820Sjeff * 11219820Sjeff * Redistribution and use in source and binary forms, with or 12219820Sjeff * without modification, are permitted provided that the following 13219820Sjeff * conditions are met: 14219820Sjeff * 15219820Sjeff * - Redistributions of source code must retain the above 16219820Sjeff * copyright notice, this list of conditions and the following 17219820Sjeff * disclaimer. 18219820Sjeff * 19219820Sjeff * - Redistributions in binary form must reproduce the above 20219820Sjeff * copyright notice, this list of conditions and the following 21219820Sjeff * disclaimer in the documentation and/or other materials 22219820Sjeff * provided with the distribution. 23219820Sjeff * 24219820Sjeff * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25219820Sjeff * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26219820Sjeff * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27219820Sjeff * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28219820Sjeff * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29219820Sjeff * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30219820Sjeff * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31219820Sjeff * SOFTWARE. 32219820Sjeff */ 33219820Sjeff 34219820Sjeff#include <linux/errno.h> 35219820Sjeff#include <linux/interrupt.h> 36219820Sjeff#include <linux/pci.h> 37219820Sjeff 38219820Sjeff#include "mthca_dev.h" 39219820Sjeff#include "mthca_cmd.h" 40219820Sjeff#include "mthca_config_reg.h" 41219820Sjeff 42219820Sjeffenum { 43219820Sjeff MTHCA_NUM_ASYNC_EQE = 0x80, 44219820Sjeff MTHCA_NUM_CMD_EQE = 0x80, 45219820Sjeff MTHCA_NUM_SPARE_EQE = 0x80, 46219820Sjeff MTHCA_EQ_ENTRY_SIZE = 0x20 47219820Sjeff}; 48219820Sjeff 49219820Sjeff/* 50219820Sjeff * Must be packed because start is 64 bits but only aligned to 32 bits. 51219820Sjeff */ 52219820Sjeffstruct mthca_eq_context { 53219820Sjeff __be32 flags; 54219820Sjeff __be64 start; 55219820Sjeff __be32 logsize_usrpage; 56219820Sjeff __be32 tavor_pd; /* reserved for Arbel */ 57219820Sjeff u8 reserved1[3]; 58219820Sjeff u8 intr; 59219820Sjeff __be32 arbel_pd; /* lost_count for Tavor */ 60219820Sjeff __be32 lkey; 61219820Sjeff u32 reserved2[2]; 62219820Sjeff __be32 consumer_index; 63219820Sjeff __be32 producer_index; 64219820Sjeff u32 reserved3[4]; 65219820Sjeff} __attribute__((packed)); 66219820Sjeff 67219820Sjeff#define MTHCA_EQ_STATUS_OK ( 0 << 28) 68219820Sjeff#define MTHCA_EQ_STATUS_OVERFLOW ( 9 << 28) 69219820Sjeff#define MTHCA_EQ_STATUS_WRITE_FAIL (10 << 28) 70219820Sjeff#define MTHCA_EQ_OWNER_SW ( 0 << 24) 71219820Sjeff#define MTHCA_EQ_OWNER_HW ( 1 << 24) 72219820Sjeff#define MTHCA_EQ_FLAG_TR ( 1 << 18) 73219820Sjeff#define MTHCA_EQ_FLAG_OI ( 1 << 17) 74219820Sjeff#define MTHCA_EQ_STATE_ARMED ( 1 << 8) 75219820Sjeff#define MTHCA_EQ_STATE_FIRED ( 2 << 8) 76219820Sjeff#define MTHCA_EQ_STATE_ALWAYS_ARMED ( 3 << 8) 77219820Sjeff#define MTHCA_EQ_STATE_ARBEL ( 8 << 8) 78219820Sjeff 79219820Sjeffenum { 80219820Sjeff MTHCA_EVENT_TYPE_COMP = 0x00, 81219820Sjeff MTHCA_EVENT_TYPE_PATH_MIG = 0x01, 82219820Sjeff MTHCA_EVENT_TYPE_COMM_EST = 0x02, 83219820Sjeff MTHCA_EVENT_TYPE_SQ_DRAINED = 0x03, 84219820Sjeff MTHCA_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, 85219820Sjeff MTHCA_EVENT_TYPE_SRQ_LIMIT = 0x14, 86219820Sjeff MTHCA_EVENT_TYPE_CQ_ERROR = 0x04, 87219820Sjeff MTHCA_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 88219820Sjeff MTHCA_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, 89219820Sjeff MTHCA_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 90219820Sjeff MTHCA_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 91219820Sjeff MTHCA_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 92219820Sjeff MTHCA_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 93219820Sjeff MTHCA_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, 94219820Sjeff MTHCA_EVENT_TYPE_PORT_CHANGE = 0x09, 95219820Sjeff MTHCA_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 96219820Sjeff MTHCA_EVENT_TYPE_ECC_DETECT = 0x0e, 97219820Sjeff MTHCA_EVENT_TYPE_CMD = 0x0a 98219820Sjeff}; 99219820Sjeff 100219820Sjeff#define MTHCA_ASYNC_EVENT_MASK ((1ULL << MTHCA_EVENT_TYPE_PATH_MIG) | \ 101219820Sjeff (1ULL << MTHCA_EVENT_TYPE_COMM_EST) | \ 102219820Sjeff (1ULL << MTHCA_EVENT_TYPE_SQ_DRAINED) | \ 103219820Sjeff (1ULL << MTHCA_EVENT_TYPE_CQ_ERROR) | \ 104219820Sjeff (1ULL << MTHCA_EVENT_TYPE_WQ_CATAS_ERROR) | \ 105219820Sjeff (1ULL << MTHCA_EVENT_TYPE_EEC_CATAS_ERROR) | \ 106219820Sjeff (1ULL << MTHCA_EVENT_TYPE_PATH_MIG_FAILED) | \ 107219820Sjeff (1ULL << MTHCA_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \ 108219820Sjeff (1ULL << MTHCA_EVENT_TYPE_WQ_ACCESS_ERROR) | \ 109219820Sjeff (1ULL << MTHCA_EVENT_TYPE_LOCAL_CATAS_ERROR) | \ 110219820Sjeff (1ULL << MTHCA_EVENT_TYPE_PORT_CHANGE) | \ 111219820Sjeff (1ULL << MTHCA_EVENT_TYPE_ECC_DETECT)) 112219820Sjeff#define MTHCA_SRQ_EVENT_MASK ((1ULL << MTHCA_EVENT_TYPE_SRQ_CATAS_ERROR) | \ 113219820Sjeff (1ULL << MTHCA_EVENT_TYPE_SRQ_QP_LAST_WQE) | \ 114219820Sjeff (1ULL << MTHCA_EVENT_TYPE_SRQ_LIMIT)) 115219820Sjeff#define MTHCA_CMD_EVENT_MASK (1ULL << MTHCA_EVENT_TYPE_CMD) 116219820Sjeff 117219820Sjeff#define MTHCA_EQ_DB_INC_CI (1 << 24) 118219820Sjeff#define MTHCA_EQ_DB_REQ_NOT (2 << 24) 119219820Sjeff#define MTHCA_EQ_DB_DISARM_CQ (3 << 24) 120219820Sjeff#define MTHCA_EQ_DB_SET_CI (4 << 24) 121219820Sjeff#define MTHCA_EQ_DB_ALWAYS_ARM (5 << 24) 122219820Sjeff 123219820Sjeffstruct mthca_eqe { 124219820Sjeff u8 reserved1; 125219820Sjeff u8 type; 126219820Sjeff u8 reserved2; 127219820Sjeff u8 subtype; 128219820Sjeff union { 129219820Sjeff u32 raw[6]; 130219820Sjeff struct { 131219820Sjeff __be32 cqn; 132219820Sjeff } __attribute__((packed)) comp; 133219820Sjeff struct { 134219820Sjeff u16 reserved1; 135219820Sjeff __be16 token; 136219820Sjeff u32 reserved2; 137219820Sjeff u8 reserved3[3]; 138219820Sjeff u8 status; 139219820Sjeff __be64 out_param; 140219820Sjeff } __attribute__((packed)) cmd; 141219820Sjeff struct { 142219820Sjeff __be32 qpn; 143219820Sjeff } __attribute__((packed)) qp; 144219820Sjeff struct { 145219820Sjeff __be32 srqn; 146219820Sjeff } __attribute__((packed)) srq; 147219820Sjeff struct { 148219820Sjeff __be32 cqn; 149219820Sjeff u32 reserved1; 150219820Sjeff u8 reserved2[3]; 151219820Sjeff u8 syndrome; 152219820Sjeff } __attribute__((packed)) cq_err; 153219820Sjeff struct { 154219820Sjeff u32 reserved1[2]; 155219820Sjeff __be32 port; 156219820Sjeff } __attribute__((packed)) port_change; 157219820Sjeff } event; 158219820Sjeff u8 reserved3[3]; 159219820Sjeff u8 owner; 160219820Sjeff} __attribute__((packed)); 161219820Sjeff 162219820Sjeff#define MTHCA_EQ_ENTRY_OWNER_SW (0 << 7) 163219820Sjeff#define MTHCA_EQ_ENTRY_OWNER_HW (1 << 7) 164219820Sjeff 165219820Sjeffstatic inline u64 async_mask(struct mthca_dev *dev) 166219820Sjeff{ 167219820Sjeff return dev->mthca_flags & MTHCA_FLAG_SRQ ? 168219820Sjeff MTHCA_ASYNC_EVENT_MASK | MTHCA_SRQ_EVENT_MASK : 169219820Sjeff MTHCA_ASYNC_EVENT_MASK; 170219820Sjeff} 171219820Sjeff 172219820Sjeffstatic inline void tavor_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci) 173219820Sjeff{ 174219820Sjeff /* 175219820Sjeff * This barrier makes sure that all updates to ownership bits 176219820Sjeff * done by set_eqe_hw() hit memory before the consumer index 177219820Sjeff * is updated. set_eq_ci() allows the HCA to possibly write 178219820Sjeff * more EQ entries, and we want to avoid the exceedingly 179219820Sjeff * unlikely possibility of the HCA writing an entry and then 180219820Sjeff * having set_eqe_hw() overwrite the owner field. 181219820Sjeff */ 182219820Sjeff wmb(); 183219820Sjeff mthca_write64(MTHCA_EQ_DB_SET_CI | eq->eqn, ci & (eq->nent - 1), 184219820Sjeff dev->kar + MTHCA_EQ_DOORBELL, 185219820Sjeff MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 186219820Sjeff} 187219820Sjeff 188219820Sjeffstatic inline void arbel_set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci) 189219820Sjeff{ 190219820Sjeff /* See comment in tavor_set_eq_ci() above. */ 191219820Sjeff wmb(); 192219820Sjeff __raw_writel((__force u32) cpu_to_be32(ci), 193219820Sjeff dev->eq_regs.arbel.eq_set_ci_base + eq->eqn * 8); 194219820Sjeff /* We still want ordering, just not swabbing, so add a barrier */ 195219820Sjeff mb(); 196219820Sjeff} 197219820Sjeff 198219820Sjeffstatic inline void set_eq_ci(struct mthca_dev *dev, struct mthca_eq *eq, u32 ci) 199219820Sjeff{ 200219820Sjeff if (mthca_is_memfree(dev)) 201219820Sjeff arbel_set_eq_ci(dev, eq, ci); 202219820Sjeff else 203219820Sjeff tavor_set_eq_ci(dev, eq, ci); 204219820Sjeff} 205219820Sjeff 206219820Sjeffstatic inline void tavor_eq_req_not(struct mthca_dev *dev, int eqn) 207219820Sjeff{ 208219820Sjeff mthca_write64(MTHCA_EQ_DB_REQ_NOT | eqn, 0, 209219820Sjeff dev->kar + MTHCA_EQ_DOORBELL, 210219820Sjeff MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 211219820Sjeff} 212219820Sjeff 213219820Sjeffstatic inline void arbel_eq_req_not(struct mthca_dev *dev, u32 eqn_mask) 214219820Sjeff{ 215219820Sjeff writel(eqn_mask, dev->eq_regs.arbel.eq_arm); 216219820Sjeff} 217219820Sjeff 218219820Sjeffstatic inline void disarm_cq(struct mthca_dev *dev, int eqn, int cqn) 219219820Sjeff{ 220219820Sjeff if (!mthca_is_memfree(dev)) { 221219820Sjeff mthca_write64(MTHCA_EQ_DB_DISARM_CQ | eqn, cqn, 222219820Sjeff dev->kar + MTHCA_EQ_DOORBELL, 223219820Sjeff MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock)); 224219820Sjeff } 225219820Sjeff} 226219820Sjeff 227219820Sjeffstatic inline struct mthca_eqe *get_eqe(struct mthca_eq *eq, u32 entry) 228219820Sjeff{ 229219820Sjeff unsigned long off = (entry & (eq->nent - 1)) * MTHCA_EQ_ENTRY_SIZE; 230219820Sjeff return eq->page_list[off / PAGE_SIZE].buf + off % PAGE_SIZE; 231219820Sjeff} 232219820Sjeff 233219820Sjeffstatic inline struct mthca_eqe *next_eqe_sw(struct mthca_eq *eq) 234219820Sjeff{ 235219820Sjeff struct mthca_eqe *eqe; 236219820Sjeff eqe = get_eqe(eq, eq->cons_index); 237219820Sjeff return (MTHCA_EQ_ENTRY_OWNER_HW & eqe->owner) ? NULL : eqe; 238219820Sjeff} 239219820Sjeff 240219820Sjeffstatic inline void set_eqe_hw(struct mthca_eqe *eqe) 241219820Sjeff{ 242219820Sjeff eqe->owner = MTHCA_EQ_ENTRY_OWNER_HW; 243219820Sjeff} 244219820Sjeff 245219820Sjeffstatic void port_change(struct mthca_dev *dev, int port, int active) 246219820Sjeff{ 247219820Sjeff struct ib_event record; 248219820Sjeff 249219820Sjeff mthca_dbg(dev, "Port change to %s for port %d\n", 250219820Sjeff active ? "active" : "down", port); 251219820Sjeff 252219820Sjeff record.device = &dev->ib_dev; 253219820Sjeff record.event = active ? IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 254219820Sjeff record.element.port_num = port; 255219820Sjeff 256219820Sjeff ib_dispatch_event(&record); 257219820Sjeff} 258219820Sjeff 259219820Sjeffstatic int mthca_eq_int(struct mthca_dev *dev, struct mthca_eq *eq) 260219820Sjeff{ 261219820Sjeff struct mthca_eqe *eqe; 262219820Sjeff int disarm_cqn; 263219820Sjeff int eqes_found = 0; 264219820Sjeff int set_ci = 0; 265219820Sjeff 266219820Sjeff while ((eqe = next_eqe_sw(eq))) { 267219820Sjeff /* 268219820Sjeff * Make sure we read EQ entry contents after we've 269219820Sjeff * checked the ownership bit. 270219820Sjeff */ 271219820Sjeff rmb(); 272219820Sjeff 273219820Sjeff switch (eqe->type) { 274219820Sjeff case MTHCA_EVENT_TYPE_COMP: 275219820Sjeff disarm_cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff; 276219820Sjeff disarm_cq(dev, eq->eqn, disarm_cqn); 277219820Sjeff mthca_cq_completion(dev, disarm_cqn); 278219820Sjeff break; 279219820Sjeff 280219820Sjeff case MTHCA_EVENT_TYPE_PATH_MIG: 281219820Sjeff mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff, 282219820Sjeff IB_EVENT_PATH_MIG); 283219820Sjeff break; 284219820Sjeff 285219820Sjeff case MTHCA_EVENT_TYPE_COMM_EST: 286219820Sjeff mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff, 287219820Sjeff IB_EVENT_COMM_EST); 288219820Sjeff break; 289219820Sjeff 290219820Sjeff case MTHCA_EVENT_TYPE_SQ_DRAINED: 291219820Sjeff mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff, 292219820Sjeff IB_EVENT_SQ_DRAINED); 293219820Sjeff break; 294219820Sjeff 295219820Sjeff case MTHCA_EVENT_TYPE_SRQ_QP_LAST_WQE: 296219820Sjeff mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff, 297219820Sjeff IB_EVENT_QP_LAST_WQE_REACHED); 298219820Sjeff break; 299219820Sjeff 300219820Sjeff case MTHCA_EVENT_TYPE_SRQ_LIMIT: 301219820Sjeff mthca_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) & 0xffffff, 302219820Sjeff IB_EVENT_SRQ_LIMIT_REACHED); 303219820Sjeff break; 304219820Sjeff 305219820Sjeff case MTHCA_EVENT_TYPE_WQ_CATAS_ERROR: 306219820Sjeff mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff, 307219820Sjeff IB_EVENT_QP_FATAL); 308219820Sjeff break; 309219820Sjeff 310219820Sjeff case MTHCA_EVENT_TYPE_PATH_MIG_FAILED: 311219820Sjeff mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff, 312219820Sjeff IB_EVENT_PATH_MIG_ERR); 313219820Sjeff break; 314219820Sjeff 315219820Sjeff case MTHCA_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 316219820Sjeff mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff, 317219820Sjeff IB_EVENT_QP_REQ_ERR); 318219820Sjeff break; 319219820Sjeff 320219820Sjeff case MTHCA_EVENT_TYPE_WQ_ACCESS_ERROR: 321219820Sjeff mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff, 322219820Sjeff IB_EVENT_QP_ACCESS_ERR); 323219820Sjeff break; 324219820Sjeff 325219820Sjeff case MTHCA_EVENT_TYPE_CMD: 326219820Sjeff mthca_cmd_event(dev, 327219820Sjeff be16_to_cpu(eqe->event.cmd.token), 328219820Sjeff eqe->event.cmd.status, 329219820Sjeff be64_to_cpu(eqe->event.cmd.out_param)); 330219820Sjeff break; 331219820Sjeff 332219820Sjeff case MTHCA_EVENT_TYPE_PORT_CHANGE: 333219820Sjeff port_change(dev, 334219820Sjeff (be32_to_cpu(eqe->event.port_change.port) >> 28) & 3, 335219820Sjeff eqe->subtype == 0x4); 336219820Sjeff break; 337219820Sjeff 338219820Sjeff case MTHCA_EVENT_TYPE_CQ_ERROR: 339219820Sjeff mthca_warn(dev, "CQ %s on CQN %06x\n", 340219820Sjeff eqe->event.cq_err.syndrome == 1 ? 341219820Sjeff "overrun" : "access violation", 342219820Sjeff be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff); 343219820Sjeff mthca_cq_event(dev, be32_to_cpu(eqe->event.cq_err.cqn), 344219820Sjeff IB_EVENT_CQ_ERR); 345219820Sjeff break; 346219820Sjeff 347219820Sjeff case MTHCA_EVENT_TYPE_EQ_OVERFLOW: 348219820Sjeff mthca_warn(dev, "EQ overrun on EQN %d\n", eq->eqn); 349219820Sjeff break; 350219820Sjeff 351219820Sjeff case MTHCA_EVENT_TYPE_EEC_CATAS_ERROR: 352219820Sjeff case MTHCA_EVENT_TYPE_SRQ_CATAS_ERROR: 353219820Sjeff case MTHCA_EVENT_TYPE_LOCAL_CATAS_ERROR: 354219820Sjeff case MTHCA_EVENT_TYPE_ECC_DETECT: 355219820Sjeff default: 356219820Sjeff mthca_warn(dev, "Unhandled event %02x(%02x) on EQ %d\n", 357219820Sjeff eqe->type, eqe->subtype, eq->eqn); 358219820Sjeff break; 359219820Sjeff }; 360219820Sjeff 361219820Sjeff set_eqe_hw(eqe); 362219820Sjeff ++eq->cons_index; 363219820Sjeff eqes_found = 1; 364219820Sjeff ++set_ci; 365219820Sjeff 366219820Sjeff /* 367219820Sjeff * The HCA will think the queue has overflowed if we 368219820Sjeff * don't tell it we've been processing events. We 369219820Sjeff * create our EQs with MTHCA_NUM_SPARE_EQE extra 370219820Sjeff * entries, so we must update our consumer index at 371219820Sjeff * least that often. 372219820Sjeff */ 373219820Sjeff if (unlikely(set_ci >= MTHCA_NUM_SPARE_EQE)) { 374219820Sjeff /* 375219820Sjeff * Conditional on hca_type is OK here because 376219820Sjeff * this is a rare case, not the fast path. 377219820Sjeff */ 378219820Sjeff set_eq_ci(dev, eq, eq->cons_index); 379219820Sjeff set_ci = 0; 380219820Sjeff } 381219820Sjeff } 382219820Sjeff 383219820Sjeff /* 384219820Sjeff * Rely on caller to set consumer index so that we don't have 385219820Sjeff * to test hca_type in our interrupt handling fast path. 386219820Sjeff */ 387219820Sjeff return eqes_found; 388219820Sjeff} 389219820Sjeff 390219820Sjeffstatic irqreturn_t mthca_tavor_interrupt(int irq, void *dev_ptr) 391219820Sjeff{ 392219820Sjeff struct mthca_dev *dev = dev_ptr; 393219820Sjeff u32 ecr; 394219820Sjeff int i; 395219820Sjeff 396219820Sjeff if (dev->eq_table.clr_mask) 397219820Sjeff writel(dev->eq_table.clr_mask, dev->eq_table.clr_int); 398219820Sjeff 399219820Sjeff ecr = readl(dev->eq_regs.tavor.ecr_base + 4); 400219820Sjeff if (!ecr) 401219820Sjeff return IRQ_NONE; 402219820Sjeff 403219820Sjeff writel(ecr, dev->eq_regs.tavor.ecr_base + 404219820Sjeff MTHCA_ECR_CLR_BASE - MTHCA_ECR_BASE + 4); 405219820Sjeff 406219820Sjeff for (i = 0; i < MTHCA_NUM_EQ; ++i) 407219820Sjeff if (ecr & dev->eq_table.eq[i].eqn_mask) { 408219820Sjeff if (mthca_eq_int(dev, &dev->eq_table.eq[i])) 409219820Sjeff tavor_set_eq_ci(dev, &dev->eq_table.eq[i], 410219820Sjeff dev->eq_table.eq[i].cons_index); 411219820Sjeff tavor_eq_req_not(dev, dev->eq_table.eq[i].eqn); 412219820Sjeff } 413219820Sjeff 414219820Sjeff return IRQ_HANDLED; 415219820Sjeff} 416219820Sjeff 417219820Sjeffstatic irqreturn_t mthca_tavor_msi_x_interrupt(int irq, void *eq_ptr) 418219820Sjeff{ 419219820Sjeff struct mthca_eq *eq = eq_ptr; 420219820Sjeff struct mthca_dev *dev = eq->dev; 421219820Sjeff 422219820Sjeff mthca_eq_int(dev, eq); 423219820Sjeff tavor_set_eq_ci(dev, eq, eq->cons_index); 424219820Sjeff tavor_eq_req_not(dev, eq->eqn); 425219820Sjeff 426219820Sjeff /* MSI-X vectors always belong to us */ 427219820Sjeff return IRQ_HANDLED; 428219820Sjeff} 429219820Sjeff 430219820Sjeffstatic irqreturn_t mthca_arbel_interrupt(int irq, void *dev_ptr) 431219820Sjeff{ 432219820Sjeff struct mthca_dev *dev = dev_ptr; 433219820Sjeff int work = 0; 434219820Sjeff int i; 435219820Sjeff 436219820Sjeff if (dev->eq_table.clr_mask) 437219820Sjeff writel(dev->eq_table.clr_mask, dev->eq_table.clr_int); 438219820Sjeff 439219820Sjeff for (i = 0; i < MTHCA_NUM_EQ; ++i) 440219820Sjeff if (mthca_eq_int(dev, &dev->eq_table.eq[i])) { 441219820Sjeff work = 1; 442219820Sjeff arbel_set_eq_ci(dev, &dev->eq_table.eq[i], 443219820Sjeff dev->eq_table.eq[i].cons_index); 444219820Sjeff } 445219820Sjeff 446219820Sjeff arbel_eq_req_not(dev, dev->eq_table.arm_mask); 447219820Sjeff 448219820Sjeff return IRQ_RETVAL(work); 449219820Sjeff} 450219820Sjeff 451219820Sjeffstatic irqreturn_t mthca_arbel_msi_x_interrupt(int irq, void *eq_ptr) 452219820Sjeff{ 453219820Sjeff struct mthca_eq *eq = eq_ptr; 454219820Sjeff struct mthca_dev *dev = eq->dev; 455219820Sjeff 456219820Sjeff mthca_eq_int(dev, eq); 457219820Sjeff arbel_set_eq_ci(dev, eq, eq->cons_index); 458219820Sjeff arbel_eq_req_not(dev, eq->eqn_mask); 459219820Sjeff 460219820Sjeff /* MSI-X vectors always belong to us */ 461219820Sjeff return IRQ_HANDLED; 462219820Sjeff} 463219820Sjeff 464219820Sjeffstatic int mthca_create_eq(struct mthca_dev *dev, 465219820Sjeff int nent, 466219820Sjeff u8 intr, 467219820Sjeff struct mthca_eq *eq) 468219820Sjeff{ 469219820Sjeff int npages; 470219820Sjeff u64 *dma_list = NULL; 471219820Sjeff dma_addr_t t; 472219820Sjeff struct mthca_mailbox *mailbox; 473219820Sjeff struct mthca_eq_context *eq_context; 474219820Sjeff int err = -ENOMEM; 475219820Sjeff int i; 476219820Sjeff u8 status; 477219820Sjeff 478219820Sjeff eq->dev = dev; 479219820Sjeff eq->nent = roundup_pow_of_two(max(nent, 2)); 480219820Sjeff npages = ALIGN(eq->nent * MTHCA_EQ_ENTRY_SIZE, PAGE_SIZE) / PAGE_SIZE; 481219820Sjeff 482219820Sjeff eq->page_list = kmalloc(npages * sizeof *eq->page_list, 483219820Sjeff GFP_KERNEL); 484219820Sjeff if (!eq->page_list) 485219820Sjeff goto err_out; 486219820Sjeff 487219820Sjeff for (i = 0; i < npages; ++i) 488219820Sjeff eq->page_list[i].buf = NULL; 489219820Sjeff 490219820Sjeff dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL); 491219820Sjeff if (!dma_list) 492219820Sjeff goto err_out_free; 493219820Sjeff 494219820Sjeff mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 495219820Sjeff if (IS_ERR(mailbox)) 496219820Sjeff goto err_out_free; 497219820Sjeff eq_context = mailbox->buf; 498219820Sjeff 499219820Sjeff for (i = 0; i < npages; ++i) { 500219820Sjeff eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev, 501219820Sjeff PAGE_SIZE, &t, GFP_KERNEL); 502219820Sjeff if (!eq->page_list[i].buf) 503219820Sjeff goto err_out_free_pages; 504219820Sjeff 505219820Sjeff dma_list[i] = t; 506219820Sjeff pci_unmap_addr_set(&eq->page_list[i], mapping, t); 507219820Sjeff 508219820Sjeff clear_page(eq->page_list[i].buf); 509219820Sjeff } 510219820Sjeff 511219820Sjeff for (i = 0; i < eq->nent; ++i) 512219820Sjeff set_eqe_hw(get_eqe(eq, i)); 513219820Sjeff 514219820Sjeff eq->eqn = mthca_alloc(&dev->eq_table.alloc); 515219820Sjeff if (eq->eqn == -1) 516219820Sjeff goto err_out_free_pages; 517219820Sjeff 518219820Sjeff err = mthca_mr_alloc_phys(dev, dev->driver_pd.pd_num, 519219820Sjeff dma_list, PAGE_SHIFT, npages, 520219820Sjeff 0, npages * PAGE_SIZE, 521219820Sjeff MTHCA_MPT_FLAG_LOCAL_WRITE | 522219820Sjeff MTHCA_MPT_FLAG_LOCAL_READ, 523219820Sjeff &eq->mr); 524219820Sjeff if (err) 525219820Sjeff goto err_out_free_eq; 526219820Sjeff 527219820Sjeff memset(eq_context, 0, sizeof *eq_context); 528219820Sjeff eq_context->flags = cpu_to_be32(MTHCA_EQ_STATUS_OK | 529219820Sjeff MTHCA_EQ_OWNER_HW | 530219820Sjeff MTHCA_EQ_STATE_ARMED | 531219820Sjeff MTHCA_EQ_FLAG_TR); 532219820Sjeff if (mthca_is_memfree(dev)) 533219820Sjeff eq_context->flags |= cpu_to_be32(MTHCA_EQ_STATE_ARBEL); 534219820Sjeff 535219820Sjeff eq_context->logsize_usrpage = cpu_to_be32((ffs(eq->nent) - 1) << 24); 536219820Sjeff if (mthca_is_memfree(dev)) { 537219820Sjeff eq_context->arbel_pd = cpu_to_be32(dev->driver_pd.pd_num); 538219820Sjeff } else { 539219820Sjeff eq_context->logsize_usrpage |= cpu_to_be32(dev->driver_uar.index); 540219820Sjeff eq_context->tavor_pd = cpu_to_be32(dev->driver_pd.pd_num); 541219820Sjeff } 542219820Sjeff eq_context->intr = intr; 543219820Sjeff eq_context->lkey = cpu_to_be32(eq->mr.ibmr.lkey); 544219820Sjeff 545219820Sjeff err = mthca_SW2HW_EQ(dev, mailbox, eq->eqn, &status); 546219820Sjeff if (err) { 547219820Sjeff mthca_warn(dev, "SW2HW_EQ failed (%d)\n", err); 548219820Sjeff goto err_out_free_mr; 549219820Sjeff } 550219820Sjeff if (status) { 551219820Sjeff mthca_warn(dev, "SW2HW_EQ returned status 0x%02x\n", 552219820Sjeff status); 553219820Sjeff err = -EINVAL; 554219820Sjeff goto err_out_free_mr; 555219820Sjeff } 556219820Sjeff 557219820Sjeff kfree(dma_list); 558219820Sjeff mthca_free_mailbox(dev, mailbox); 559219820Sjeff 560219820Sjeff eq->eqn_mask = swab32(1 << eq->eqn); 561219820Sjeff eq->cons_index = 0; 562219820Sjeff 563219820Sjeff dev->eq_table.arm_mask |= eq->eqn_mask; 564219820Sjeff 565219820Sjeff mthca_dbg(dev, "Allocated EQ %d with %d entries\n", 566219820Sjeff eq->eqn, eq->nent); 567219820Sjeff 568219820Sjeff return err; 569219820Sjeff 570219820Sjeff err_out_free_mr: 571219820Sjeff mthca_free_mr(dev, &eq->mr); 572219820Sjeff 573219820Sjeff err_out_free_eq: 574219820Sjeff mthca_free(&dev->eq_table.alloc, eq->eqn); 575219820Sjeff 576219820Sjeff err_out_free_pages: 577219820Sjeff for (i = 0; i < npages; ++i) 578219820Sjeff if (eq->page_list[i].buf) 579219820Sjeff dma_free_coherent(&dev->pdev->dev, PAGE_SIZE, 580219820Sjeff eq->page_list[i].buf, 581219820Sjeff pci_unmap_addr(&eq->page_list[i], 582219820Sjeff mapping)); 583219820Sjeff 584219820Sjeff mthca_free_mailbox(dev, mailbox); 585219820Sjeff 586219820Sjeff err_out_free: 587219820Sjeff kfree(eq->page_list); 588219820Sjeff kfree(dma_list); 589219820Sjeff 590219820Sjeff err_out: 591219820Sjeff return err; 592219820Sjeff} 593219820Sjeff 594219820Sjeffstatic void mthca_free_eq(struct mthca_dev *dev, 595219820Sjeff struct mthca_eq *eq) 596219820Sjeff{ 597219820Sjeff struct mthca_mailbox *mailbox; 598219820Sjeff int err; 599219820Sjeff u8 status; 600219820Sjeff int npages = (eq->nent * MTHCA_EQ_ENTRY_SIZE + PAGE_SIZE - 1) / 601219820Sjeff PAGE_SIZE; 602219820Sjeff int i; 603219820Sjeff 604219820Sjeff mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 605219820Sjeff if (IS_ERR(mailbox)) 606219820Sjeff return; 607219820Sjeff 608219820Sjeff err = mthca_HW2SW_EQ(dev, mailbox, eq->eqn, &status); 609219820Sjeff if (err) 610219820Sjeff mthca_warn(dev, "HW2SW_EQ failed (%d)\n", err); 611219820Sjeff if (status) 612219820Sjeff mthca_warn(dev, "HW2SW_EQ returned status 0x%02x\n", status); 613219820Sjeff 614219820Sjeff dev->eq_table.arm_mask &= ~eq->eqn_mask; 615219820Sjeff 616219820Sjeff if (0) { 617219820Sjeff mthca_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn); 618219820Sjeff for (i = 0; i < sizeof (struct mthca_eq_context) / 4; ++i) { 619219820Sjeff if (i % 4 == 0) 620219820Sjeff printk("[%02x] ", i * 4); 621219820Sjeff printk(" %08x", be32_to_cpup(mailbox->buf + i * 4)); 622219820Sjeff if ((i + 1) % 4 == 0) 623219820Sjeff printk("\n"); 624219820Sjeff } 625219820Sjeff } 626219820Sjeff 627219820Sjeff mthca_free_mr(dev, &eq->mr); 628219820Sjeff for (i = 0; i < npages; ++i) 629219820Sjeff pci_free_consistent(dev->pdev, PAGE_SIZE, 630219820Sjeff eq->page_list[i].buf, 631219820Sjeff pci_unmap_addr(&eq->page_list[i], mapping)); 632219820Sjeff 633219820Sjeff kfree(eq->page_list); 634219820Sjeff mthca_free_mailbox(dev, mailbox); 635219820Sjeff} 636219820Sjeff 637219820Sjeffstatic void mthca_free_irqs(struct mthca_dev *dev) 638219820Sjeff{ 639219820Sjeff int i; 640219820Sjeff 641219820Sjeff if (dev->eq_table.have_irq) 642219820Sjeff free_irq(dev->pdev->irq, dev); 643219820Sjeff for (i = 0; i < MTHCA_NUM_EQ; ++i) 644219820Sjeff if (dev->eq_table.eq[i].have_irq) { 645219820Sjeff free_irq(dev->eq_table.eq[i].msi_x_vector, 646219820Sjeff dev->eq_table.eq + i); 647219820Sjeff dev->eq_table.eq[i].have_irq = 0; 648219820Sjeff } 649219820Sjeff} 650219820Sjeff 651219820Sjeffstatic int mthca_map_reg(struct mthca_dev *dev, 652219820Sjeff unsigned long offset, unsigned long size, 653219820Sjeff void __iomem **map) 654219820Sjeff{ 655219820Sjeff unsigned long base = pci_resource_start(dev->pdev, 0); 656219820Sjeff 657219820Sjeff *map = ioremap(base + offset, size); 658219820Sjeff if (!*map) 659219820Sjeff return -ENOMEM; 660219820Sjeff 661219820Sjeff return 0; 662219820Sjeff} 663219820Sjeff 664219820Sjeffstatic int mthca_map_eq_regs(struct mthca_dev *dev) 665219820Sjeff{ 666219820Sjeff if (mthca_is_memfree(dev)) { 667219820Sjeff /* 668219820Sjeff * We assume that the EQ arm and EQ set CI registers 669219820Sjeff * fall within the first BAR. We can't trust the 670219820Sjeff * values firmware gives us, since those addresses are 671219820Sjeff * valid on the HCA's side of the PCI bus but not 672219820Sjeff * necessarily the host side. 673219820Sjeff */ 674219820Sjeff if (mthca_map_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) & 675219820Sjeff dev->fw.arbel.clr_int_base, MTHCA_CLR_INT_SIZE, 676219820Sjeff &dev->clr_base)) { 677219820Sjeff mthca_err(dev, "Couldn't map interrupt clear register, " 678219820Sjeff "aborting.\n"); 679219820Sjeff return -ENOMEM; 680219820Sjeff } 681219820Sjeff 682219820Sjeff /* 683219820Sjeff * Add 4 because we limit ourselves to EQs 0 ... 31, 684219820Sjeff * so we only need the low word of the register. 685219820Sjeff */ 686219820Sjeff if (mthca_map_reg(dev, ((pci_resource_len(dev->pdev, 0) - 1) & 687219820Sjeff dev->fw.arbel.eq_arm_base) + 4, 4, 688219820Sjeff &dev->eq_regs.arbel.eq_arm)) { 689219820Sjeff mthca_err(dev, "Couldn't map EQ arm register, aborting.\n"); 690219820Sjeff iounmap(dev->clr_base); 691219820Sjeff return -ENOMEM; 692219820Sjeff } 693219820Sjeff 694219820Sjeff if (mthca_map_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) & 695219820Sjeff dev->fw.arbel.eq_set_ci_base, 696219820Sjeff MTHCA_EQ_SET_CI_SIZE, 697219820Sjeff &dev->eq_regs.arbel.eq_set_ci_base)) { 698219820Sjeff mthca_err(dev, "Couldn't map EQ CI register, aborting.\n"); 699219820Sjeff iounmap(dev->eq_regs.arbel.eq_arm); 700219820Sjeff iounmap(dev->clr_base); 701219820Sjeff return -ENOMEM; 702219820Sjeff } 703219820Sjeff } else { 704219820Sjeff if (mthca_map_reg(dev, MTHCA_CLR_INT_BASE, MTHCA_CLR_INT_SIZE, 705219820Sjeff &dev->clr_base)) { 706219820Sjeff mthca_err(dev, "Couldn't map interrupt clear register, " 707219820Sjeff "aborting.\n"); 708219820Sjeff return -ENOMEM; 709219820Sjeff } 710219820Sjeff 711219820Sjeff if (mthca_map_reg(dev, MTHCA_ECR_BASE, 712219820Sjeff MTHCA_ECR_SIZE + MTHCA_ECR_CLR_SIZE, 713219820Sjeff &dev->eq_regs.tavor.ecr_base)) { 714219820Sjeff mthca_err(dev, "Couldn't map ecr register, " 715219820Sjeff "aborting.\n"); 716219820Sjeff iounmap(dev->clr_base); 717219820Sjeff return -ENOMEM; 718219820Sjeff } 719219820Sjeff } 720219820Sjeff 721219820Sjeff return 0; 722219820Sjeff 723219820Sjeff} 724219820Sjeff 725219820Sjeffstatic void mthca_unmap_eq_regs(struct mthca_dev *dev) 726219820Sjeff{ 727219820Sjeff if (mthca_is_memfree(dev)) { 728219820Sjeff iounmap(dev->eq_regs.arbel.eq_set_ci_base); 729219820Sjeff iounmap(dev->eq_regs.arbel.eq_arm); 730219820Sjeff iounmap(dev->clr_base); 731219820Sjeff } else { 732219820Sjeff iounmap(dev->eq_regs.tavor.ecr_base); 733219820Sjeff iounmap(dev->clr_base); 734219820Sjeff } 735219820Sjeff} 736219820Sjeff 737219820Sjeffint mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt) 738219820Sjeff{ 739219820Sjeff int ret; 740219820Sjeff u8 status; 741219820Sjeff 742219820Sjeff /* 743219820Sjeff * We assume that mapping one page is enough for the whole EQ 744219820Sjeff * context table. This is fine with all current HCAs, because 745219820Sjeff * we only use 32 EQs and each EQ uses 32 bytes of context 746219820Sjeff * memory, or 1 KB total. 747219820Sjeff */ 748219820Sjeff dev->eq_table.icm_virt = icm_virt; 749219820Sjeff dev->eq_table.icm_page = alloc_page(GFP_HIGHUSER); 750219820Sjeff if (!dev->eq_table.icm_page) 751219820Sjeff return -ENOMEM; 752219820Sjeff dev->eq_table.icm_dma = pci_map_page(dev->pdev, dev->eq_table.icm_page, 0, 753219820Sjeff PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 754219820Sjeff if (pci_dma_mapping_error(dev->pdev, dev->eq_table.icm_dma)) { 755219820Sjeff __free_page(dev->eq_table.icm_page); 756219820Sjeff return -ENOMEM; 757219820Sjeff } 758219820Sjeff 759219820Sjeff ret = mthca_MAP_ICM_page(dev, dev->eq_table.icm_dma, icm_virt, &status); 760219820Sjeff if (!ret && status) 761219820Sjeff ret = -EINVAL; 762219820Sjeff if (ret) { 763219820Sjeff pci_unmap_page(dev->pdev, dev->eq_table.icm_dma, PAGE_SIZE, 764219820Sjeff PCI_DMA_BIDIRECTIONAL); 765219820Sjeff __free_page(dev->eq_table.icm_page); 766219820Sjeff } 767219820Sjeff 768219820Sjeff return ret; 769219820Sjeff} 770219820Sjeff 771219820Sjeffvoid mthca_unmap_eq_icm(struct mthca_dev *dev) 772219820Sjeff{ 773219820Sjeff u8 status; 774219820Sjeff 775219820Sjeff mthca_UNMAP_ICM(dev, dev->eq_table.icm_virt, 1, &status); 776219820Sjeff pci_unmap_page(dev->pdev, dev->eq_table.icm_dma, PAGE_SIZE, 777219820Sjeff PCI_DMA_BIDIRECTIONAL); 778219820Sjeff __free_page(dev->eq_table.icm_page); 779219820Sjeff} 780219820Sjeff 781219820Sjeffint mthca_init_eq_table(struct mthca_dev *dev) 782219820Sjeff{ 783219820Sjeff int err; 784219820Sjeff u8 status; 785219820Sjeff u8 intr; 786219820Sjeff int i; 787219820Sjeff 788219820Sjeff err = mthca_alloc_init(&dev->eq_table.alloc, 789219820Sjeff dev->limits.num_eqs, 790219820Sjeff dev->limits.num_eqs - 1, 791219820Sjeff dev->limits.reserved_eqs); 792219820Sjeff if (err) 793219820Sjeff return err; 794219820Sjeff 795219820Sjeff err = mthca_map_eq_regs(dev); 796219820Sjeff if (err) 797219820Sjeff goto err_out_free; 798219820Sjeff 799219820Sjeff if (dev->mthca_flags & MTHCA_FLAG_MSI_X) { 800219820Sjeff dev->eq_table.clr_mask = 0; 801219820Sjeff } else { 802219820Sjeff dev->eq_table.clr_mask = 803219820Sjeff swab32(1 << (dev->eq_table.inta_pin & 31)); 804219820Sjeff dev->eq_table.clr_int = dev->clr_base + 805219820Sjeff (dev->eq_table.inta_pin < 32 ? 4 : 0); 806219820Sjeff } 807219820Sjeff 808219820Sjeff dev->eq_table.arm_mask = 0; 809219820Sjeff 810219820Sjeff intr = dev->eq_table.inta_pin; 811219820Sjeff 812219820Sjeff err = mthca_create_eq(dev, dev->limits.num_cqs + MTHCA_NUM_SPARE_EQE, 813219820Sjeff (dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 128 : intr, 814219820Sjeff &dev->eq_table.eq[MTHCA_EQ_COMP]); 815219820Sjeff if (err) 816219820Sjeff goto err_out_unmap; 817219820Sjeff 818219820Sjeff err = mthca_create_eq(dev, MTHCA_NUM_ASYNC_EQE + MTHCA_NUM_SPARE_EQE, 819219820Sjeff (dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 129 : intr, 820219820Sjeff &dev->eq_table.eq[MTHCA_EQ_ASYNC]); 821219820Sjeff if (err) 822219820Sjeff goto err_out_comp; 823219820Sjeff 824219820Sjeff err = mthca_create_eq(dev, MTHCA_NUM_CMD_EQE + MTHCA_NUM_SPARE_EQE, 825219820Sjeff (dev->mthca_flags & MTHCA_FLAG_MSI_X) ? 130 : intr, 826219820Sjeff &dev->eq_table.eq[MTHCA_EQ_CMD]); 827219820Sjeff if (err) 828219820Sjeff goto err_out_async; 829219820Sjeff 830219820Sjeff if (dev->mthca_flags & MTHCA_FLAG_MSI_X) { 831219820Sjeff static const char *eq_name[] = { 832219820Sjeff [MTHCA_EQ_COMP] = DRV_NAME " (comp)", 833219820Sjeff [MTHCA_EQ_ASYNC] = DRV_NAME " (async)", 834219820Sjeff [MTHCA_EQ_CMD] = DRV_NAME " (cmd)" 835219820Sjeff }; 836219820Sjeff 837219820Sjeff for (i = 0; i < MTHCA_NUM_EQ; ++i) { 838219820Sjeff err = request_irq(dev->eq_table.eq[i].msi_x_vector, 839219820Sjeff mthca_is_memfree(dev) ? 840219820Sjeff mthca_arbel_msi_x_interrupt : 841219820Sjeff mthca_tavor_msi_x_interrupt, 842219820Sjeff 0, eq_name[i], dev->eq_table.eq + i); 843219820Sjeff if (err) 844219820Sjeff goto err_out_cmd; 845219820Sjeff dev->eq_table.eq[i].have_irq = 1; 846219820Sjeff } 847219820Sjeff } else { 848219820Sjeff err = request_irq(dev->pdev->irq, 849219820Sjeff mthca_is_memfree(dev) ? 850219820Sjeff mthca_arbel_interrupt : 851219820Sjeff mthca_tavor_interrupt, 852219820Sjeff IRQF_SHARED, DRV_NAME, dev); 853219820Sjeff if (err) 854219820Sjeff goto err_out_cmd; 855219820Sjeff dev->eq_table.have_irq = 1; 856219820Sjeff } 857219820Sjeff 858219820Sjeff err = mthca_MAP_EQ(dev, async_mask(dev), 859219820Sjeff 0, dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, &status); 860219820Sjeff if (err) 861219820Sjeff mthca_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n", 862219820Sjeff dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, err); 863219820Sjeff if (status) 864219820Sjeff mthca_warn(dev, "MAP_EQ for async EQ %d returned status 0x%02x\n", 865219820Sjeff dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, status); 866219820Sjeff 867219820Sjeff err = mthca_MAP_EQ(dev, MTHCA_CMD_EVENT_MASK, 868219820Sjeff 0, dev->eq_table.eq[MTHCA_EQ_CMD].eqn, &status); 869219820Sjeff if (err) 870219820Sjeff mthca_warn(dev, "MAP_EQ for cmd EQ %d failed (%d)\n", 871219820Sjeff dev->eq_table.eq[MTHCA_EQ_CMD].eqn, err); 872219820Sjeff if (status) 873219820Sjeff mthca_warn(dev, "MAP_EQ for cmd EQ %d returned status 0x%02x\n", 874219820Sjeff dev->eq_table.eq[MTHCA_EQ_CMD].eqn, status); 875219820Sjeff 876219820Sjeff for (i = 0; i < MTHCA_NUM_EQ; ++i) 877219820Sjeff if (mthca_is_memfree(dev)) 878219820Sjeff arbel_eq_req_not(dev, dev->eq_table.eq[i].eqn_mask); 879219820Sjeff else 880219820Sjeff tavor_eq_req_not(dev, dev->eq_table.eq[i].eqn); 881219820Sjeff 882219820Sjeff return 0; 883219820Sjeff 884219820Sjefferr_out_cmd: 885219820Sjeff mthca_free_irqs(dev); 886219820Sjeff mthca_free_eq(dev, &dev->eq_table.eq[MTHCA_EQ_CMD]); 887219820Sjeff 888219820Sjefferr_out_async: 889219820Sjeff mthca_free_eq(dev, &dev->eq_table.eq[MTHCA_EQ_ASYNC]); 890219820Sjeff 891219820Sjefferr_out_comp: 892219820Sjeff mthca_free_eq(dev, &dev->eq_table.eq[MTHCA_EQ_COMP]); 893219820Sjeff 894219820Sjefferr_out_unmap: 895219820Sjeff mthca_unmap_eq_regs(dev); 896219820Sjeff 897219820Sjefferr_out_free: 898219820Sjeff mthca_alloc_cleanup(&dev->eq_table.alloc); 899219820Sjeff return err; 900219820Sjeff} 901219820Sjeff 902219820Sjeffvoid mthca_cleanup_eq_table(struct mthca_dev *dev) 903219820Sjeff{ 904219820Sjeff u8 status; 905219820Sjeff int i; 906219820Sjeff 907219820Sjeff mthca_free_irqs(dev); 908219820Sjeff 909219820Sjeff mthca_MAP_EQ(dev, async_mask(dev), 910219820Sjeff 1, dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn, &status); 911219820Sjeff mthca_MAP_EQ(dev, MTHCA_CMD_EVENT_MASK, 912219820Sjeff 1, dev->eq_table.eq[MTHCA_EQ_CMD].eqn, &status); 913219820Sjeff 914219820Sjeff for (i = 0; i < MTHCA_NUM_EQ; ++i) 915219820Sjeff mthca_free_eq(dev, &dev->eq_table.eq[i]); 916219820Sjeff 917219820Sjeff mthca_unmap_eq_regs(dev); 918219820Sjeff 919219820Sjeff mthca_alloc_cleanup(&dev->eq_table.alloc); 920219820Sjeff} 921