1219820Sjeff/* 2219820Sjeff * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3219820Sjeff * Copyright (c) 2005 Mellanox Technologies. All rights reserved. 4219820Sjeff * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved. 5219820Sjeff * 6219820Sjeff * This software is available to you under a choice of one of two 7219820Sjeff * licenses. You may choose to be licensed under the terms of the GNU 8219820Sjeff * General Public License (GPL) Version 2, available from the file 9219820Sjeff * COPYING in the main directory of this source tree, or the 10219820Sjeff * OpenIB.org BSD license below: 11219820Sjeff * 12219820Sjeff * Redistribution and use in source and binary forms, with or 13219820Sjeff * without modification, are permitted provided that the following 14219820Sjeff * conditions are met: 15219820Sjeff * 16219820Sjeff * - Redistributions of source code must retain the above 17219820Sjeff * copyright notice, this list of conditions and the following 18219820Sjeff * disclaimer. 19219820Sjeff * 20219820Sjeff * - Redistributions in binary form must reproduce the above 21219820Sjeff * copyright notice, this list of conditions and the following 22219820Sjeff * disclaimer in the documentation and/or other materials 23219820Sjeff * provided with the distribution. 24219820Sjeff * 25219820Sjeff * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26219820Sjeff * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27219820Sjeff * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28219820Sjeff * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29219820Sjeff * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30219820Sjeff * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31219820Sjeff * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32219820Sjeff * SOFTWARE. 33219820Sjeff */ 34219820Sjeff 35219820Sjeff#include <linux/completion.h> 36219820Sjeff#include <linux/pci.h> 37219820Sjeff#include <linux/errno.h> 38219820Sjeff#include <linux/sched.h> 39219820Sjeff#include <asm/io.h> 40219820Sjeff#include <rdma/ib_mad.h> 41219820Sjeff 42219820Sjeff#include "mthca_dev.h" 43219820Sjeff#include "mthca_config_reg.h" 44219820Sjeff#include "mthca_cmd.h" 45219820Sjeff#include "mthca_memfree.h" 46219820Sjeff 47219820Sjeff#define CMD_POLL_TOKEN 0xffff 48219820Sjeff 49219820Sjeffenum { 50219820Sjeff HCR_IN_PARAM_OFFSET = 0x00, 51219820Sjeff HCR_IN_MODIFIER_OFFSET = 0x08, 52219820Sjeff HCR_OUT_PARAM_OFFSET = 0x0c, 53219820Sjeff HCR_TOKEN_OFFSET = 0x14, 54219820Sjeff HCR_STATUS_OFFSET = 0x18, 55219820Sjeff 56219820Sjeff HCR_OPMOD_SHIFT = 12, 57219820Sjeff HCA_E_BIT = 22, 58219820Sjeff HCR_GO_BIT = 23 59219820Sjeff}; 60219820Sjeff 61219820Sjeffenum { 62219820Sjeff /* initialization and general commands */ 63219820Sjeff CMD_SYS_EN = 0x1, 64219820Sjeff CMD_SYS_DIS = 0x2, 65219820Sjeff CMD_MAP_FA = 0xfff, 66219820Sjeff CMD_UNMAP_FA = 0xffe, 67219820Sjeff CMD_RUN_FW = 0xff6, 68219820Sjeff CMD_MOD_STAT_CFG = 0x34, 69219820Sjeff CMD_QUERY_DEV_LIM = 0x3, 70219820Sjeff CMD_QUERY_FW = 0x4, 71219820Sjeff CMD_ENABLE_LAM = 0xff8, 72219820Sjeff CMD_DISABLE_LAM = 0xff7, 73219820Sjeff CMD_QUERY_DDR = 0x5, 74219820Sjeff CMD_QUERY_ADAPTER = 0x6, 75219820Sjeff CMD_INIT_HCA = 0x7, 76219820Sjeff CMD_CLOSE_HCA = 0x8, 77219820Sjeff CMD_INIT_IB = 0x9, 78219820Sjeff CMD_CLOSE_IB = 0xa, 79219820Sjeff CMD_QUERY_HCA = 0xb, 80219820Sjeff CMD_SET_IB = 0xc, 81219820Sjeff CMD_ACCESS_DDR = 0x2e, 82219820Sjeff CMD_MAP_ICM = 0xffa, 83219820Sjeff CMD_UNMAP_ICM = 0xff9, 84219820Sjeff CMD_MAP_ICM_AUX = 0xffc, 85219820Sjeff CMD_UNMAP_ICM_AUX = 0xffb, 86219820Sjeff CMD_SET_ICM_SIZE = 0xffd, 87219820Sjeff 88219820Sjeff /* TPT commands */ 89219820Sjeff CMD_SW2HW_MPT = 0xd, 90219820Sjeff CMD_QUERY_MPT = 0xe, 91219820Sjeff CMD_HW2SW_MPT = 0xf, 92219820Sjeff CMD_READ_MTT = 0x10, 93219820Sjeff CMD_WRITE_MTT = 0x11, 94219820Sjeff CMD_SYNC_TPT = 0x2f, 95219820Sjeff 96219820Sjeff /* EQ commands */ 97219820Sjeff CMD_MAP_EQ = 0x12, 98219820Sjeff CMD_SW2HW_EQ = 0x13, 99219820Sjeff CMD_HW2SW_EQ = 0x14, 100219820Sjeff CMD_QUERY_EQ = 0x15, 101219820Sjeff 102219820Sjeff /* CQ commands */ 103219820Sjeff CMD_SW2HW_CQ = 0x16, 104219820Sjeff CMD_HW2SW_CQ = 0x17, 105219820Sjeff CMD_QUERY_CQ = 0x18, 106219820Sjeff CMD_RESIZE_CQ = 0x2c, 107219820Sjeff 108219820Sjeff /* SRQ commands */ 109219820Sjeff CMD_SW2HW_SRQ = 0x35, 110219820Sjeff CMD_HW2SW_SRQ = 0x36, 111219820Sjeff CMD_QUERY_SRQ = 0x37, 112219820Sjeff CMD_ARM_SRQ = 0x40, 113219820Sjeff 114219820Sjeff /* QP/EE commands */ 115219820Sjeff CMD_RST2INIT_QPEE = 0x19, 116219820Sjeff CMD_INIT2RTR_QPEE = 0x1a, 117219820Sjeff CMD_RTR2RTS_QPEE = 0x1b, 118219820Sjeff CMD_RTS2RTS_QPEE = 0x1c, 119219820Sjeff CMD_SQERR2RTS_QPEE = 0x1d, 120219820Sjeff CMD_2ERR_QPEE = 0x1e, 121219820Sjeff CMD_RTS2SQD_QPEE = 0x1f, 122219820Sjeff CMD_SQD2SQD_QPEE = 0x38, 123219820Sjeff CMD_SQD2RTS_QPEE = 0x20, 124219820Sjeff CMD_ERR2RST_QPEE = 0x21, 125219820Sjeff CMD_QUERY_QPEE = 0x22, 126219820Sjeff CMD_INIT2INIT_QPEE = 0x2d, 127219820Sjeff CMD_SUSPEND_QPEE = 0x32, 128219820Sjeff CMD_UNSUSPEND_QPEE = 0x33, 129219820Sjeff /* special QPs and management commands */ 130219820Sjeff CMD_CONF_SPECIAL_QP = 0x23, 131219820Sjeff CMD_MAD_IFC = 0x24, 132219820Sjeff 133219820Sjeff /* multicast commands */ 134219820Sjeff CMD_READ_MGM = 0x25, 135219820Sjeff CMD_WRITE_MGM = 0x26, 136219820Sjeff CMD_MGID_HASH = 0x27, 137219820Sjeff 138219820Sjeff /* miscellaneous commands */ 139219820Sjeff CMD_DIAG_RPRT = 0x30, 140219820Sjeff CMD_NOP = 0x31, 141219820Sjeff 142219820Sjeff /* debug commands */ 143219820Sjeff CMD_QUERY_DEBUG_MSG = 0x2a, 144219820Sjeff CMD_SET_DEBUG_MSG = 0x2b, 145219820Sjeff}; 146219820Sjeff 147219820Sjeff/* 148219820Sjeff * According to Mellanox code, FW may be starved and never complete 149219820Sjeff * commands. So we can't use strict timeouts described in PRM -- we 150219820Sjeff * just arbitrarily select 60 seconds for now. 151219820Sjeff */ 152219820Sjeff#if 0 153219820Sjeff/* 154219820Sjeff * Round up and add 1 to make sure we get the full wait time (since we 155219820Sjeff * will be starting in the middle of a jiffy) 156219820Sjeff */ 157219820Sjeffenum { 158219820Sjeff CMD_TIME_CLASS_A = (HZ + 999) / 1000 + 1, 159219820Sjeff CMD_TIME_CLASS_B = (HZ + 99) / 100 + 1, 160219820Sjeff CMD_TIME_CLASS_C = (HZ + 9) / 10 + 1, 161219820Sjeff CMD_TIME_CLASS_D = 60 * HZ 162219820Sjeff}; 163219820Sjeff#else 164219820Sjeff#define CMD_TIME_CLASS_A (60 * HZ) 165219820Sjeff#define CMD_TIME_CLASS_B (60 * HZ) 166219820Sjeff#define CMD_TIME_CLASS_C (60 * HZ) 167219820Sjeff#define CMD_TIME_CLASS_D (60 * HZ) 168219820Sjeff#endif 169219820Sjeff 170219820Sjeff#define GO_BIT_TIMEOUT (HZ * 10) 171219820Sjeff 172219820Sjeffstruct mthca_cmd_context { 173219820Sjeff struct completion done; 174219820Sjeff int result; 175219820Sjeff int next; 176219820Sjeff u64 out_param; 177219820Sjeff u16 token; 178219820Sjeff u8 status; 179219820Sjeff}; 180219820Sjeff 181219820Sjeffstatic int fw_cmd_doorbell = 0; 182219820Sjeffmodule_param(fw_cmd_doorbell, int, 0644); 183219820SjeffMODULE_PARM_DESC(fw_cmd_doorbell, "post FW commands through doorbell page if nonzero " 184219820Sjeff "(and supported by FW)"); 185219820Sjeff 186219820Sjeffstatic inline int go_bit(struct mthca_dev *dev) 187219820Sjeff{ 188219820Sjeff return readl(dev->hcr + HCR_STATUS_OFFSET) & 189219820Sjeff swab32(1 << HCR_GO_BIT); 190219820Sjeff} 191219820Sjeff 192219820Sjeffstatic void mthca_cmd_post_dbell(struct mthca_dev *dev, 193219820Sjeff u64 in_param, 194219820Sjeff u64 out_param, 195219820Sjeff u32 in_modifier, 196219820Sjeff u8 op_modifier, 197219820Sjeff u16 op, 198219820Sjeff u16 token) 199219820Sjeff{ 200219820Sjeff void __iomem *ptr = dev->cmd.dbell_map; 201219820Sjeff u16 *offs = dev->cmd.dbell_offsets; 202219820Sjeff 203219820Sjeff __raw_writel((__force u32) cpu_to_be32(in_param >> 32), ptr + offs[0]); 204219820Sjeff wmb(); 205219820Sjeff __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), ptr + offs[1]); 206219820Sjeff wmb(); 207219820Sjeff __raw_writel((__force u32) cpu_to_be32(in_modifier), ptr + offs[2]); 208219820Sjeff wmb(); 209219820Sjeff __raw_writel((__force u32) cpu_to_be32(out_param >> 32), ptr + offs[3]); 210219820Sjeff wmb(); 211219820Sjeff __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), ptr + offs[4]); 212219820Sjeff wmb(); 213219820Sjeff __raw_writel((__force u32) cpu_to_be32(token << 16), ptr + offs[5]); 214219820Sjeff wmb(); 215219820Sjeff __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) | 216219820Sjeff (1 << HCA_E_BIT) | 217219820Sjeff (op_modifier << HCR_OPMOD_SHIFT) | 218219820Sjeff op), ptr + offs[6]); 219219820Sjeff wmb(); 220219820Sjeff __raw_writel((__force u32) 0, ptr + offs[7]); 221219820Sjeff wmb(); 222219820Sjeff} 223219820Sjeff 224219820Sjeffstatic int mthca_cmd_post_hcr(struct mthca_dev *dev, 225219820Sjeff u64 in_param, 226219820Sjeff u64 out_param, 227219820Sjeff u32 in_modifier, 228219820Sjeff u8 op_modifier, 229219820Sjeff u16 op, 230219820Sjeff u16 token, 231219820Sjeff int event) 232219820Sjeff{ 233219820Sjeff if (event) { 234219820Sjeff unsigned long end = jiffies + GO_BIT_TIMEOUT; 235219820Sjeff 236219820Sjeff while (go_bit(dev) && time_before(jiffies, end)) 237219820Sjeff sched_yield(); 238219820Sjeff } 239219820Sjeff 240219820Sjeff if (go_bit(dev)) 241219820Sjeff return -EAGAIN; 242219820Sjeff 243219820Sjeff /* 244219820Sjeff * We use writel (instead of something like memcpy_toio) 245219820Sjeff * because writes of less than 32 bits to the HCR don't work 246219820Sjeff * (and some architectures such as ia64 implement memcpy_toio 247219820Sjeff * in terms of writeb). 248219820Sjeff */ 249219820Sjeff __raw_writel((__force u32) cpu_to_be32(in_param >> 32), dev->hcr + 0 * 4); 250219820Sjeff __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), dev->hcr + 1 * 4); 251219820Sjeff __raw_writel((__force u32) cpu_to_be32(in_modifier), dev->hcr + 2 * 4); 252219820Sjeff __raw_writel((__force u32) cpu_to_be32(out_param >> 32), dev->hcr + 3 * 4); 253219820Sjeff __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4); 254219820Sjeff __raw_writel((__force u32) cpu_to_be32(token << 16), dev->hcr + 5 * 4); 255219820Sjeff 256219820Sjeff /* __raw_writel may not order writes. */ 257219820Sjeff wmb(); 258219820Sjeff 259219820Sjeff __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) | 260219820Sjeff (event ? (1 << HCA_E_BIT) : 0) | 261219820Sjeff (op_modifier << HCR_OPMOD_SHIFT) | 262219820Sjeff op), dev->hcr + 6 * 4); 263219820Sjeff 264219820Sjeff return 0; 265219820Sjeff} 266219820Sjeff 267219820Sjeffstatic int mthca_cmd_post(struct mthca_dev *dev, 268219820Sjeff u64 in_param, 269219820Sjeff u64 out_param, 270219820Sjeff u32 in_modifier, 271219820Sjeff u8 op_modifier, 272219820Sjeff u16 op, 273219820Sjeff u16 token, 274219820Sjeff int event) 275219820Sjeff{ 276219820Sjeff int err = 0; 277219820Sjeff 278219820Sjeff mutex_lock(&dev->cmd.hcr_mutex); 279219820Sjeff 280219820Sjeff if (event && dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS && fw_cmd_doorbell) 281219820Sjeff mthca_cmd_post_dbell(dev, in_param, out_param, in_modifier, 282219820Sjeff op_modifier, op, token); 283219820Sjeff else 284219820Sjeff err = mthca_cmd_post_hcr(dev, in_param, out_param, in_modifier, 285219820Sjeff op_modifier, op, token, event); 286219820Sjeff 287219820Sjeff /* 288219820Sjeff * Make sure that our HCR writes don't get mixed in with 289219820Sjeff * writes from another CPU starting a FW command. 290219820Sjeff */ 291219820Sjeff mmiowb(); 292219820Sjeff 293219820Sjeff mutex_unlock(&dev->cmd.hcr_mutex); 294219820Sjeff return err; 295219820Sjeff} 296219820Sjeff 297219820Sjeffstatic int mthca_cmd_poll(struct mthca_dev *dev, 298219820Sjeff u64 in_param, 299219820Sjeff u64 *out_param, 300219820Sjeff int out_is_imm, 301219820Sjeff u32 in_modifier, 302219820Sjeff u8 op_modifier, 303219820Sjeff u16 op, 304219820Sjeff unsigned long timeout, 305219820Sjeff u8 *status) 306219820Sjeff{ 307219820Sjeff int err = 0; 308219820Sjeff unsigned long end; 309219820Sjeff 310219820Sjeff down(&dev->cmd.poll_sem); 311219820Sjeff 312219820Sjeff err = mthca_cmd_post(dev, in_param, 313219820Sjeff out_param ? *out_param : 0, 314219820Sjeff in_modifier, op_modifier, 315219820Sjeff op, CMD_POLL_TOKEN, 0); 316219820Sjeff if (err) 317219820Sjeff goto out; 318219820Sjeff 319219820Sjeff end = timeout + jiffies; 320219820Sjeff while (go_bit(dev) && time_before(jiffies, end)) 321219820Sjeff sched_yield(); 322219820Sjeff 323219820Sjeff if (go_bit(dev)) { 324219820Sjeff err = -EBUSY; 325219820Sjeff goto out; 326219820Sjeff } 327219820Sjeff 328219820Sjeff if (out_is_imm) 329219820Sjeff *out_param = 330219820Sjeff (u64) be32_to_cpu((__force __be32) 331219820Sjeff __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 | 332219820Sjeff (u64) be32_to_cpu((__force __be32) 333219820Sjeff __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET + 4)); 334219820Sjeff 335219820Sjeff *status = be32_to_cpu((__force __be32) __raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24; 336219820Sjeff 337219820Sjeffout: 338219820Sjeff up(&dev->cmd.poll_sem); 339219820Sjeff return err; 340219820Sjeff} 341219820Sjeff 342219820Sjeffvoid mthca_cmd_event(struct mthca_dev *dev, 343219820Sjeff u16 token, 344219820Sjeff u8 status, 345219820Sjeff u64 out_param) 346219820Sjeff{ 347219820Sjeff struct mthca_cmd_context *context = 348219820Sjeff &dev->cmd.context[token & dev->cmd.token_mask]; 349219820Sjeff 350219820Sjeff /* previously timed out command completing at long last */ 351219820Sjeff if (token != context->token) 352219820Sjeff return; 353219820Sjeff 354219820Sjeff context->result = 0; 355219820Sjeff context->status = status; 356219820Sjeff context->out_param = out_param; 357219820Sjeff 358219820Sjeff complete(&context->done); 359219820Sjeff} 360219820Sjeff 361219820Sjeffstatic int mthca_cmd_wait(struct mthca_dev *dev, 362219820Sjeff u64 in_param, 363219820Sjeff u64 *out_param, 364219820Sjeff int out_is_imm, 365219820Sjeff u32 in_modifier, 366219820Sjeff u8 op_modifier, 367219820Sjeff u16 op, 368219820Sjeff unsigned long timeout, 369219820Sjeff u8 *status) 370219820Sjeff{ 371219820Sjeff int err = 0; 372219820Sjeff struct mthca_cmd_context *context; 373219820Sjeff 374219820Sjeff down(&dev->cmd.event_sem); 375219820Sjeff 376219820Sjeff spin_lock(&dev->cmd.context_lock); 377219820Sjeff BUG_ON(dev->cmd.free_head < 0); 378219820Sjeff context = &dev->cmd.context[dev->cmd.free_head]; 379219820Sjeff context->token += dev->cmd.token_mask + 1; 380219820Sjeff dev->cmd.free_head = context->next; 381219820Sjeff spin_unlock(&dev->cmd.context_lock); 382219820Sjeff 383219820Sjeff init_completion(&context->done); 384219820Sjeff 385219820Sjeff err = mthca_cmd_post(dev, in_param, 386219820Sjeff out_param ? *out_param : 0, 387219820Sjeff in_modifier, op_modifier, 388219820Sjeff op, context->token, 1); 389219820Sjeff if (err) 390219820Sjeff goto out; 391219820Sjeff 392219820Sjeff if (!wait_for_completion_timeout(&context->done, timeout)) { 393219820Sjeff err = -EBUSY; 394219820Sjeff goto out; 395219820Sjeff } 396219820Sjeff 397219820Sjeff err = context->result; 398219820Sjeff if (err) 399219820Sjeff goto out; 400219820Sjeff 401219820Sjeff *status = context->status; 402219820Sjeff if (*status) 403219820Sjeff mthca_dbg(dev, "Command %02x completed with status %02x\n", 404219820Sjeff op, *status); 405219820Sjeff 406219820Sjeff if (out_is_imm) 407219820Sjeff *out_param = context->out_param; 408219820Sjeff 409219820Sjeffout: 410219820Sjeff spin_lock(&dev->cmd.context_lock); 411219820Sjeff context->next = dev->cmd.free_head; 412219820Sjeff dev->cmd.free_head = context - dev->cmd.context; 413219820Sjeff spin_unlock(&dev->cmd.context_lock); 414219820Sjeff 415219820Sjeff up(&dev->cmd.event_sem); 416219820Sjeff return err; 417219820Sjeff} 418219820Sjeff 419219820Sjeff/* Invoke a command with an output mailbox */ 420219820Sjeffstatic int mthca_cmd_box(struct mthca_dev *dev, 421219820Sjeff u64 in_param, 422219820Sjeff u64 out_param, 423219820Sjeff u32 in_modifier, 424219820Sjeff u8 op_modifier, 425219820Sjeff u16 op, 426219820Sjeff unsigned long timeout, 427219820Sjeff u8 *status) 428219820Sjeff{ 429219820Sjeff if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS) 430219820Sjeff return mthca_cmd_wait(dev, in_param, &out_param, 0, 431219820Sjeff in_modifier, op_modifier, op, 432219820Sjeff timeout, status); 433219820Sjeff else 434219820Sjeff return mthca_cmd_poll(dev, in_param, &out_param, 0, 435219820Sjeff in_modifier, op_modifier, op, 436219820Sjeff timeout, status); 437219820Sjeff} 438219820Sjeff 439219820Sjeff/* Invoke a command with no output parameter */ 440219820Sjeffstatic int mthca_cmd(struct mthca_dev *dev, 441219820Sjeff u64 in_param, 442219820Sjeff u32 in_modifier, 443219820Sjeff u8 op_modifier, 444219820Sjeff u16 op, 445219820Sjeff unsigned long timeout, 446219820Sjeff u8 *status) 447219820Sjeff{ 448219820Sjeff return mthca_cmd_box(dev, in_param, 0, in_modifier, 449219820Sjeff op_modifier, op, timeout, status); 450219820Sjeff} 451219820Sjeff 452219820Sjeff/* 453219820Sjeff * Invoke a command with an immediate output parameter (and copy the 454219820Sjeff * output into the caller's out_param pointer after the command 455219820Sjeff * executes). 456219820Sjeff */ 457219820Sjeffstatic int mthca_cmd_imm(struct mthca_dev *dev, 458219820Sjeff u64 in_param, 459219820Sjeff u64 *out_param, 460219820Sjeff u32 in_modifier, 461219820Sjeff u8 op_modifier, 462219820Sjeff u16 op, 463219820Sjeff unsigned long timeout, 464219820Sjeff u8 *status) 465219820Sjeff{ 466219820Sjeff if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS) 467219820Sjeff return mthca_cmd_wait(dev, in_param, out_param, 1, 468219820Sjeff in_modifier, op_modifier, op, 469219820Sjeff timeout, status); 470219820Sjeff else 471219820Sjeff return mthca_cmd_poll(dev, in_param, out_param, 1, 472219820Sjeff in_modifier, op_modifier, op, 473219820Sjeff timeout, status); 474219820Sjeff} 475219820Sjeff 476219820Sjeffint mthca_cmd_init(struct mthca_dev *dev) 477219820Sjeff{ 478219820Sjeff mutex_init(&dev->cmd.hcr_mutex); 479219820Sjeff sema_init(&dev->cmd.poll_sem, 1); 480219820Sjeff dev->cmd.flags = 0; 481219820Sjeff 482219820Sjeff dev->hcr = ioremap(pci_resource_start(dev->pdev, 0) + MTHCA_HCR_BASE, 483219820Sjeff MTHCA_HCR_SIZE); 484219820Sjeff if (!dev->hcr) { 485219820Sjeff mthca_err(dev, "Couldn't map command register."); 486219820Sjeff return -ENOMEM; 487219820Sjeff } 488219820Sjeff 489219820Sjeff dev->cmd.pool = pci_pool_create("mthca_cmd", dev->pdev, 490219820Sjeff MTHCA_MAILBOX_SIZE, 491219820Sjeff MTHCA_MAILBOX_SIZE, 0); 492219820Sjeff if (!dev->cmd.pool) { 493219820Sjeff iounmap(dev->hcr); 494219820Sjeff return -ENOMEM; 495219820Sjeff } 496219820Sjeff 497219820Sjeff return 0; 498219820Sjeff} 499219820Sjeff 500219820Sjeffvoid mthca_cmd_cleanup(struct mthca_dev *dev) 501219820Sjeff{ 502219820Sjeff pci_pool_destroy(dev->cmd.pool); 503219820Sjeff iounmap(dev->hcr); 504219820Sjeff if (dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS) 505219820Sjeff iounmap(dev->cmd.dbell_map); 506219820Sjeff} 507219820Sjeff 508219820Sjeff/* 509219820Sjeff * Switch to using events to issue FW commands (should be called after 510219820Sjeff * event queue to command events has been initialized). 511219820Sjeff */ 512219820Sjeffint mthca_cmd_use_events(struct mthca_dev *dev) 513219820Sjeff{ 514219820Sjeff int i; 515219820Sjeff 516219820Sjeff dev->cmd.context = kmalloc(dev->cmd.max_cmds * 517219820Sjeff sizeof (struct mthca_cmd_context), 518219820Sjeff GFP_KERNEL); 519219820Sjeff if (!dev->cmd.context) 520219820Sjeff return -ENOMEM; 521219820Sjeff 522219820Sjeff for (i = 0; i < dev->cmd.max_cmds; ++i) { 523219820Sjeff dev->cmd.context[i].token = i; 524219820Sjeff dev->cmd.context[i].next = i + 1; 525219820Sjeff } 526219820Sjeff 527219820Sjeff dev->cmd.context[dev->cmd.max_cmds - 1].next = -1; 528219820Sjeff dev->cmd.free_head = 0; 529219820Sjeff 530219820Sjeff sema_init(&dev->cmd.event_sem, dev->cmd.max_cmds); 531219820Sjeff spin_lock_init(&dev->cmd.context_lock); 532219820Sjeff 533219820Sjeff for (dev->cmd.token_mask = 1; 534219820Sjeff dev->cmd.token_mask < dev->cmd.max_cmds; 535219820Sjeff dev->cmd.token_mask <<= 1) 536219820Sjeff ; /* nothing */ 537219820Sjeff --dev->cmd.token_mask; 538219820Sjeff 539219820Sjeff dev->cmd.flags |= MTHCA_CMD_USE_EVENTS; 540219820Sjeff 541219820Sjeff down(&dev->cmd.poll_sem); 542219820Sjeff 543219820Sjeff return 0; 544219820Sjeff} 545219820Sjeff 546219820Sjeff/* 547219820Sjeff * Switch back to polling (used when shutting down the device) 548219820Sjeff */ 549219820Sjeffvoid mthca_cmd_use_polling(struct mthca_dev *dev) 550219820Sjeff{ 551219820Sjeff int i; 552219820Sjeff 553219820Sjeff dev->cmd.flags &= ~MTHCA_CMD_USE_EVENTS; 554219820Sjeff 555219820Sjeff for (i = 0; i < dev->cmd.max_cmds; ++i) 556219820Sjeff down(&dev->cmd.event_sem); 557219820Sjeff 558219820Sjeff kfree(dev->cmd.context); 559219820Sjeff 560219820Sjeff up(&dev->cmd.poll_sem); 561219820Sjeff} 562219820Sjeff 563219820Sjeffstruct mthca_mailbox *mthca_alloc_mailbox(struct mthca_dev *dev, 564219820Sjeff gfp_t gfp_mask) 565219820Sjeff{ 566219820Sjeff struct mthca_mailbox *mailbox; 567219820Sjeff 568219820Sjeff mailbox = kmalloc(sizeof *mailbox, gfp_mask); 569219820Sjeff if (!mailbox) 570219820Sjeff return ERR_PTR(-ENOMEM); 571219820Sjeff 572219820Sjeff mailbox->buf = pci_pool_alloc(dev->cmd.pool, gfp_mask, &mailbox->dma); 573219820Sjeff if (!mailbox->buf) { 574219820Sjeff kfree(mailbox); 575219820Sjeff return ERR_PTR(-ENOMEM); 576219820Sjeff } 577219820Sjeff 578219820Sjeff return mailbox; 579219820Sjeff} 580219820Sjeff 581219820Sjeffvoid mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox) 582219820Sjeff{ 583219820Sjeff if (!mailbox) 584219820Sjeff return; 585219820Sjeff 586219820Sjeff pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma); 587219820Sjeff kfree(mailbox); 588219820Sjeff} 589219820Sjeff 590219820Sjeffint mthca_SYS_EN(struct mthca_dev *dev, u8 *status) 591219820Sjeff{ 592219820Sjeff u64 out; 593219820Sjeff int ret; 594219820Sjeff 595219820Sjeff ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, CMD_TIME_CLASS_D, status); 596219820Sjeff 597219820Sjeff if (*status == MTHCA_CMD_STAT_DDR_MEM_ERR) 598219820Sjeff mthca_warn(dev, "SYS_EN DDR error: syn=%x, sock=%d, " 599219820Sjeff "sladdr=%d, SPD source=%s\n", 600219820Sjeff (int) (out >> 6) & 0xf, (int) (out >> 4) & 3, 601219820Sjeff (int) (out >> 1) & 7, (int) out & 1 ? "NVMEM" : "DIMM"); 602219820Sjeff 603219820Sjeff return ret; 604219820Sjeff} 605219820Sjeff 606219820Sjeffint mthca_SYS_DIS(struct mthca_dev *dev, u8 *status) 607219820Sjeff{ 608219820Sjeff return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C, status); 609219820Sjeff} 610219820Sjeff 611219820Sjeffstatic int mthca_map_cmd(struct mthca_dev *dev, u16 op, struct mthca_icm *icm, 612219820Sjeff u64 virt, u8 *status) 613219820Sjeff{ 614219820Sjeff struct mthca_mailbox *mailbox; 615219820Sjeff struct mthca_icm_iter iter; 616219820Sjeff __be64 *pages; 617219820Sjeff int lg; 618219820Sjeff int nent = 0; 619219820Sjeff int i; 620219820Sjeff int err = 0; 621219820Sjeff int ts = 0, tc = 0; 622219820Sjeff 623219820Sjeff mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 624219820Sjeff if (IS_ERR(mailbox)) 625219820Sjeff return PTR_ERR(mailbox); 626219820Sjeff memset(mailbox->buf, 0, MTHCA_MAILBOX_SIZE); 627219820Sjeff pages = mailbox->buf; 628219820Sjeff 629219820Sjeff for (mthca_icm_first(icm, &iter); 630219820Sjeff !mthca_icm_last(&iter); 631219820Sjeff mthca_icm_next(&iter)) { 632219820Sjeff /* 633219820Sjeff * We have to pass pages that are aligned to their 634219820Sjeff * size, so find the least significant 1 in the 635219820Sjeff * address or size and use that as our log2 size. 636219820Sjeff */ 637219820Sjeff lg = ffs(mthca_icm_addr(&iter) | mthca_icm_size(&iter)) - 1; 638219820Sjeff if (lg < MTHCA_ICM_PAGE_SHIFT) { 639219820Sjeff mthca_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n", 640219820Sjeff MTHCA_ICM_PAGE_SIZE, 641219820Sjeff (unsigned long long) mthca_icm_addr(&iter), 642219820Sjeff mthca_icm_size(&iter)); 643219820Sjeff err = -EINVAL; 644219820Sjeff goto out; 645219820Sjeff } 646219820Sjeff for (i = 0; i < mthca_icm_size(&iter) >> lg; ++i) { 647219820Sjeff if (virt != -1) { 648219820Sjeff pages[nent * 2] = cpu_to_be64(virt); 649219820Sjeff virt += 1 << lg; 650219820Sjeff } 651219820Sjeff 652219820Sjeff pages[nent * 2 + 1] = 653219820Sjeff cpu_to_be64((mthca_icm_addr(&iter) + (i << lg)) | 654219820Sjeff (lg - MTHCA_ICM_PAGE_SHIFT)); 655219820Sjeff ts += 1 << (lg - 10); 656219820Sjeff ++tc; 657219820Sjeff 658219820Sjeff if (++nent == MTHCA_MAILBOX_SIZE / 16) { 659219820Sjeff err = mthca_cmd(dev, mailbox->dma, nent, 0, op, 660219820Sjeff CMD_TIME_CLASS_B, status); 661219820Sjeff if (err || *status) 662219820Sjeff goto out; 663219820Sjeff nent = 0; 664219820Sjeff } 665219820Sjeff } 666219820Sjeff } 667219820Sjeff 668219820Sjeff if (nent) 669219820Sjeff err = mthca_cmd(dev, mailbox->dma, nent, 0, op, 670219820Sjeff CMD_TIME_CLASS_B, status); 671219820Sjeff 672219820Sjeff switch (op) { 673219820Sjeff case CMD_MAP_FA: 674219820Sjeff mthca_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts); 675219820Sjeff break; 676219820Sjeff case CMD_MAP_ICM_AUX: 677219820Sjeff mthca_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts); 678219820Sjeff break; 679219820Sjeff case CMD_MAP_ICM: 680219820Sjeff mthca_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n", 681219820Sjeff tc, ts, (unsigned long long) virt - (ts << 10)); 682219820Sjeff break; 683219820Sjeff } 684219820Sjeff 685219820Sjeffout: 686219820Sjeff mthca_free_mailbox(dev, mailbox); 687219820Sjeff return err; 688219820Sjeff} 689219820Sjeff 690219820Sjeffint mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status) 691219820Sjeff{ 692219820Sjeff return mthca_map_cmd(dev, CMD_MAP_FA, icm, -1, status); 693219820Sjeff} 694219820Sjeff 695219820Sjeffint mthca_UNMAP_FA(struct mthca_dev *dev, u8 *status) 696219820Sjeff{ 697219820Sjeff return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_FA, CMD_TIME_CLASS_B, status); 698219820Sjeff} 699219820Sjeff 700219820Sjeffint mthca_RUN_FW(struct mthca_dev *dev, u8 *status) 701219820Sjeff{ 702219820Sjeff return mthca_cmd(dev, 0, 0, 0, CMD_RUN_FW, CMD_TIME_CLASS_A, status); 703219820Sjeff} 704219820Sjeff 705219820Sjeffstatic void mthca_setup_cmd_doorbells(struct mthca_dev *dev, u64 base) 706219820Sjeff{ 707219820Sjeff unsigned long addr; 708219820Sjeff u16 max_off = 0; 709219820Sjeff int i; 710219820Sjeff 711219820Sjeff for (i = 0; i < 8; ++i) 712219820Sjeff max_off = max(max_off, dev->cmd.dbell_offsets[i]); 713219820Sjeff 714219820Sjeff if ((base & PAGE_MASK) != ((base + max_off) & PAGE_MASK)) { 715219820Sjeff mthca_warn(dev, "Firmware doorbell region at 0x%016llx, " 716219820Sjeff "length 0x%x crosses a page boundary\n", 717219820Sjeff (unsigned long long) base, max_off); 718219820Sjeff return; 719219820Sjeff } 720219820Sjeff 721219820Sjeff addr = pci_resource_start(dev->pdev, 2) + 722219820Sjeff ((pci_resource_len(dev->pdev, 2) - 1) & base); 723219820Sjeff dev->cmd.dbell_map = ioremap(addr, max_off + sizeof(u32)); 724219820Sjeff if (!dev->cmd.dbell_map) 725219820Sjeff return; 726219820Sjeff 727219820Sjeff dev->cmd.flags |= MTHCA_CMD_POST_DOORBELLS; 728219820Sjeff mthca_dbg(dev, "Mapped doorbell page for posting FW commands\n"); 729219820Sjeff} 730219820Sjeff 731219820Sjeffint mthca_QUERY_FW(struct mthca_dev *dev, u8 *status) 732219820Sjeff{ 733219820Sjeff struct mthca_mailbox *mailbox; 734219820Sjeff u32 *outbox; 735219820Sjeff u64 base; 736219820Sjeff u32 tmp; 737219820Sjeff int err = 0; 738219820Sjeff u8 lg; 739219820Sjeff int i; 740219820Sjeff 741219820Sjeff#define QUERY_FW_OUT_SIZE 0x100 742219820Sjeff#define QUERY_FW_VER_OFFSET 0x00 743219820Sjeff#define QUERY_FW_MAX_CMD_OFFSET 0x0f 744219820Sjeff#define QUERY_FW_ERR_START_OFFSET 0x30 745219820Sjeff#define QUERY_FW_ERR_SIZE_OFFSET 0x38 746219820Sjeff 747219820Sjeff#define QUERY_FW_CMD_DB_EN_OFFSET 0x10 748219820Sjeff#define QUERY_FW_CMD_DB_OFFSET 0x50 749219820Sjeff#define QUERY_FW_CMD_DB_BASE 0x60 750219820Sjeff 751219820Sjeff#define QUERY_FW_START_OFFSET 0x20 752219820Sjeff#define QUERY_FW_END_OFFSET 0x28 753219820Sjeff 754219820Sjeff#define QUERY_FW_SIZE_OFFSET 0x00 755219820Sjeff#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 756219820Sjeff#define QUERY_FW_EQ_ARM_BASE_OFFSET 0x40 757219820Sjeff#define QUERY_FW_EQ_SET_CI_BASE_OFFSET 0x48 758219820Sjeff 759219820Sjeff mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 760219820Sjeff if (IS_ERR(mailbox)) 761219820Sjeff return PTR_ERR(mailbox); 762219820Sjeff outbox = mailbox->buf; 763219820Sjeff 764219820Sjeff err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_FW, 765219820Sjeff CMD_TIME_CLASS_A, status); 766219820Sjeff 767219820Sjeff if (err) 768219820Sjeff goto out; 769219820Sjeff 770219820Sjeff MTHCA_GET(dev->fw_ver, outbox, QUERY_FW_VER_OFFSET); 771219820Sjeff /* 772219820Sjeff * FW subminor version is at more significant bits than minor 773219820Sjeff * version, so swap here. 774219820Sjeff */ 775219820Sjeff dev->fw_ver = (dev->fw_ver & 0xffff00000000ull) | 776219820Sjeff ((dev->fw_ver & 0xffff0000ull) >> 16) | 777219820Sjeff ((dev->fw_ver & 0x0000ffffull) << 16); 778219820Sjeff 779219820Sjeff MTHCA_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); 780219820Sjeff dev->cmd.max_cmds = 1 << lg; 781219820Sjeff 782219820Sjeff mthca_dbg(dev, "FW version %012llx, max commands %d\n", 783219820Sjeff (unsigned long long) dev->fw_ver, dev->cmd.max_cmds); 784219820Sjeff 785219820Sjeff MTHCA_GET(dev->catas_err.addr, outbox, QUERY_FW_ERR_START_OFFSET); 786219820Sjeff MTHCA_GET(dev->catas_err.size, outbox, QUERY_FW_ERR_SIZE_OFFSET); 787219820Sjeff 788219820Sjeff mthca_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x\n", 789219820Sjeff (unsigned long long) dev->catas_err.addr, dev->catas_err.size); 790219820Sjeff 791219820Sjeff MTHCA_GET(tmp, outbox, QUERY_FW_CMD_DB_EN_OFFSET); 792219820Sjeff if (tmp & 0x1) { 793219820Sjeff mthca_dbg(dev, "FW supports commands through doorbells\n"); 794219820Sjeff 795219820Sjeff MTHCA_GET(base, outbox, QUERY_FW_CMD_DB_BASE); 796219820Sjeff for (i = 0; i < MTHCA_CMD_NUM_DBELL_DWORDS; ++i) 797219820Sjeff MTHCA_GET(dev->cmd.dbell_offsets[i], outbox, 798219820Sjeff QUERY_FW_CMD_DB_OFFSET + (i << 1)); 799219820Sjeff 800219820Sjeff mthca_setup_cmd_doorbells(dev, base); 801219820Sjeff } 802219820Sjeff 803219820Sjeff if (mthca_is_memfree(dev)) { 804219820Sjeff MTHCA_GET(dev->fw.arbel.fw_pages, outbox, QUERY_FW_SIZE_OFFSET); 805219820Sjeff MTHCA_GET(dev->fw.arbel.clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); 806219820Sjeff MTHCA_GET(dev->fw.arbel.eq_arm_base, outbox, QUERY_FW_EQ_ARM_BASE_OFFSET); 807219820Sjeff MTHCA_GET(dev->fw.arbel.eq_set_ci_base, outbox, QUERY_FW_EQ_SET_CI_BASE_OFFSET); 808219820Sjeff mthca_dbg(dev, "FW size %d KB\n", dev->fw.arbel.fw_pages << 2); 809219820Sjeff 810219820Sjeff /* 811219820Sjeff * Round up number of system pages needed in case 812219820Sjeff * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE. 813219820Sjeff */ 814219820Sjeff dev->fw.arbel.fw_pages = 815219820Sjeff ALIGN(dev->fw.arbel.fw_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >> 816219820Sjeff (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT); 817219820Sjeff 818219820Sjeff mthca_dbg(dev, "Clear int @ %llx, EQ arm @ %llx, EQ set CI @ %llx\n", 819219820Sjeff (unsigned long long) dev->fw.arbel.clr_int_base, 820219820Sjeff (unsigned long long) dev->fw.arbel.eq_arm_base, 821219820Sjeff (unsigned long long) dev->fw.arbel.eq_set_ci_base); 822219820Sjeff } else { 823219820Sjeff MTHCA_GET(dev->fw.tavor.fw_start, outbox, QUERY_FW_START_OFFSET); 824219820Sjeff MTHCA_GET(dev->fw.tavor.fw_end, outbox, QUERY_FW_END_OFFSET); 825219820Sjeff 826219820Sjeff mthca_dbg(dev, "FW size %d KB (start %llx, end %llx)\n", 827219820Sjeff (int) ((dev->fw.tavor.fw_end - dev->fw.tavor.fw_start) >> 10), 828219820Sjeff (unsigned long long) dev->fw.tavor.fw_start, 829219820Sjeff (unsigned long long) dev->fw.tavor.fw_end); 830219820Sjeff } 831219820Sjeff 832219820Sjeffout: 833219820Sjeff mthca_free_mailbox(dev, mailbox); 834219820Sjeff return err; 835219820Sjeff} 836219820Sjeff 837219820Sjeffint mthca_ENABLE_LAM(struct mthca_dev *dev, u8 *status) 838219820Sjeff{ 839219820Sjeff struct mthca_mailbox *mailbox; 840219820Sjeff u8 info; 841219820Sjeff u32 *outbox; 842219820Sjeff int err = 0; 843219820Sjeff 844219820Sjeff#define ENABLE_LAM_OUT_SIZE 0x100 845219820Sjeff#define ENABLE_LAM_START_OFFSET 0x00 846219820Sjeff#define ENABLE_LAM_END_OFFSET 0x08 847219820Sjeff#define ENABLE_LAM_INFO_OFFSET 0x13 848219820Sjeff 849219820Sjeff#define ENABLE_LAM_INFO_HIDDEN_FLAG (1 << 4) 850219820Sjeff#define ENABLE_LAM_INFO_ECC_MASK 0x3 851219820Sjeff 852219820Sjeff mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 853219820Sjeff if (IS_ERR(mailbox)) 854219820Sjeff return PTR_ERR(mailbox); 855219820Sjeff outbox = mailbox->buf; 856219820Sjeff 857219820Sjeff err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_ENABLE_LAM, 858219820Sjeff CMD_TIME_CLASS_C, status); 859219820Sjeff 860219820Sjeff if (err) 861219820Sjeff goto out; 862219820Sjeff 863219820Sjeff if (*status == MTHCA_CMD_STAT_LAM_NOT_PRE) 864219820Sjeff goto out; 865219820Sjeff 866219820Sjeff MTHCA_GET(dev->ddr_start, outbox, ENABLE_LAM_START_OFFSET); 867219820Sjeff MTHCA_GET(dev->ddr_end, outbox, ENABLE_LAM_END_OFFSET); 868219820Sjeff MTHCA_GET(info, outbox, ENABLE_LAM_INFO_OFFSET); 869219820Sjeff 870219820Sjeff if (!!(info & ENABLE_LAM_INFO_HIDDEN_FLAG) != 871219820Sjeff !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) { 872219820Sjeff mthca_info(dev, "FW reports that HCA-attached memory " 873219820Sjeff "is %s hidden; does not match PCI config\n", 874219820Sjeff (info & ENABLE_LAM_INFO_HIDDEN_FLAG) ? 875219820Sjeff "" : "not"); 876219820Sjeff } 877219820Sjeff if (info & ENABLE_LAM_INFO_HIDDEN_FLAG) 878219820Sjeff mthca_dbg(dev, "HCA-attached memory is hidden.\n"); 879219820Sjeff 880219820Sjeff mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n", 881219820Sjeff (int) ((dev->ddr_end - dev->ddr_start) >> 10), 882219820Sjeff (unsigned long long) dev->ddr_start, 883219820Sjeff (unsigned long long) dev->ddr_end); 884219820Sjeff 885219820Sjeffout: 886219820Sjeff mthca_free_mailbox(dev, mailbox); 887219820Sjeff return err; 888219820Sjeff} 889219820Sjeff 890219820Sjeffint mthca_DISABLE_LAM(struct mthca_dev *dev, u8 *status) 891219820Sjeff{ 892219820Sjeff return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C, status); 893219820Sjeff} 894219820Sjeff 895219820Sjeffint mthca_QUERY_DDR(struct mthca_dev *dev, u8 *status) 896219820Sjeff{ 897219820Sjeff struct mthca_mailbox *mailbox; 898219820Sjeff u8 info; 899219820Sjeff u32 *outbox; 900219820Sjeff int err = 0; 901219820Sjeff 902219820Sjeff#define QUERY_DDR_OUT_SIZE 0x100 903219820Sjeff#define QUERY_DDR_START_OFFSET 0x00 904219820Sjeff#define QUERY_DDR_END_OFFSET 0x08 905219820Sjeff#define QUERY_DDR_INFO_OFFSET 0x13 906219820Sjeff 907219820Sjeff#define QUERY_DDR_INFO_HIDDEN_FLAG (1 << 4) 908219820Sjeff#define QUERY_DDR_INFO_ECC_MASK 0x3 909219820Sjeff 910219820Sjeff mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 911219820Sjeff if (IS_ERR(mailbox)) 912219820Sjeff return PTR_ERR(mailbox); 913219820Sjeff outbox = mailbox->buf; 914219820Sjeff 915219820Sjeff err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DDR, 916219820Sjeff CMD_TIME_CLASS_A, status); 917219820Sjeff 918219820Sjeff if (err) 919219820Sjeff goto out; 920219820Sjeff 921219820Sjeff MTHCA_GET(dev->ddr_start, outbox, QUERY_DDR_START_OFFSET); 922219820Sjeff MTHCA_GET(dev->ddr_end, outbox, QUERY_DDR_END_OFFSET); 923219820Sjeff MTHCA_GET(info, outbox, QUERY_DDR_INFO_OFFSET); 924219820Sjeff 925219820Sjeff if (!!(info & QUERY_DDR_INFO_HIDDEN_FLAG) != 926219820Sjeff !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) { 927219820Sjeff mthca_info(dev, "FW reports that HCA-attached memory " 928219820Sjeff "is %s hidden; does not match PCI config\n", 929219820Sjeff (info & QUERY_DDR_INFO_HIDDEN_FLAG) ? 930219820Sjeff "" : "not"); 931219820Sjeff } 932219820Sjeff if (info & QUERY_DDR_INFO_HIDDEN_FLAG) 933219820Sjeff mthca_dbg(dev, "HCA-attached memory is hidden.\n"); 934219820Sjeff 935219820Sjeff mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n", 936219820Sjeff (int) ((dev->ddr_end - dev->ddr_start) >> 10), 937219820Sjeff (unsigned long long) dev->ddr_start, 938219820Sjeff (unsigned long long) dev->ddr_end); 939219820Sjeff 940219820Sjeffout: 941219820Sjeff mthca_free_mailbox(dev, mailbox); 942219820Sjeff return err; 943219820Sjeff} 944219820Sjeff 945219820Sjeffint mthca_QUERY_DEV_LIM(struct mthca_dev *dev, 946219820Sjeff struct mthca_dev_lim *dev_lim, u8 *status) 947219820Sjeff{ 948219820Sjeff struct mthca_mailbox *mailbox; 949219820Sjeff u32 *outbox; 950219820Sjeff u8 field; 951219820Sjeff u16 size; 952219820Sjeff u16 stat_rate; 953219820Sjeff int err; 954219820Sjeff 955219820Sjeff#define QUERY_DEV_LIM_OUT_SIZE 0x100 956219820Sjeff#define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET 0x10 957219820Sjeff#define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET 0x11 958219820Sjeff#define QUERY_DEV_LIM_RSVD_QP_OFFSET 0x12 959219820Sjeff#define QUERY_DEV_LIM_MAX_QP_OFFSET 0x13 960219820Sjeff#define QUERY_DEV_LIM_RSVD_SRQ_OFFSET 0x14 961219820Sjeff#define QUERY_DEV_LIM_MAX_SRQ_OFFSET 0x15 962219820Sjeff#define QUERY_DEV_LIM_RSVD_EEC_OFFSET 0x16 963219820Sjeff#define QUERY_DEV_LIM_MAX_EEC_OFFSET 0x17 964219820Sjeff#define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET 0x19 965219820Sjeff#define QUERY_DEV_LIM_RSVD_CQ_OFFSET 0x1a 966219820Sjeff#define QUERY_DEV_LIM_MAX_CQ_OFFSET 0x1b 967219820Sjeff#define QUERY_DEV_LIM_MAX_MPT_OFFSET 0x1d 968219820Sjeff#define QUERY_DEV_LIM_RSVD_EQ_OFFSET 0x1e 969219820Sjeff#define QUERY_DEV_LIM_MAX_EQ_OFFSET 0x1f 970219820Sjeff#define QUERY_DEV_LIM_RSVD_MTT_OFFSET 0x20 971219820Sjeff#define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET 0x21 972219820Sjeff#define QUERY_DEV_LIM_RSVD_MRW_OFFSET 0x22 973219820Sjeff#define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET 0x23 974219820Sjeff#define QUERY_DEV_LIM_MAX_AV_OFFSET 0x27 975219820Sjeff#define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET 0x29 976219820Sjeff#define QUERY_DEV_LIM_MAX_RES_QP_OFFSET 0x2b 977219820Sjeff#define QUERY_DEV_LIM_MAX_RDMA_OFFSET 0x2f 978219820Sjeff#define QUERY_DEV_LIM_RSZ_SRQ_OFFSET 0x33 979219820Sjeff#define QUERY_DEV_LIM_ACK_DELAY_OFFSET 0x35 980219820Sjeff#define QUERY_DEV_LIM_MTU_WIDTH_OFFSET 0x36 981219820Sjeff#define QUERY_DEV_LIM_VL_PORT_OFFSET 0x37 982219820Sjeff#define QUERY_DEV_LIM_MAX_GID_OFFSET 0x3b 983219820Sjeff#define QUERY_DEV_LIM_RATE_SUPPORT_OFFSET 0x3c 984219820Sjeff#define QUERY_DEV_LIM_MAX_PKEY_OFFSET 0x3f 985219820Sjeff#define QUERY_DEV_LIM_FLAGS_OFFSET 0x44 986219820Sjeff#define QUERY_DEV_LIM_RSVD_UAR_OFFSET 0x48 987219820Sjeff#define QUERY_DEV_LIM_UAR_SZ_OFFSET 0x49 988219820Sjeff#define QUERY_DEV_LIM_PAGE_SZ_OFFSET 0x4b 989219820Sjeff#define QUERY_DEV_LIM_MAX_SG_OFFSET 0x51 990219820Sjeff#define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET 0x52 991219820Sjeff#define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET 0x55 992219820Sjeff#define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x56 993219820Sjeff#define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET 0x61 994219820Sjeff#define QUERY_DEV_LIM_RSVD_MCG_OFFSET 0x62 995219820Sjeff#define QUERY_DEV_LIM_MAX_MCG_OFFSET 0x63 996219820Sjeff#define QUERY_DEV_LIM_RSVD_PD_OFFSET 0x64 997219820Sjeff#define QUERY_DEV_LIM_MAX_PD_OFFSET 0x65 998219820Sjeff#define QUERY_DEV_LIM_RSVD_RDD_OFFSET 0x66 999219820Sjeff#define QUERY_DEV_LIM_MAX_RDD_OFFSET 0x67 1000219820Sjeff#define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET 0x80 1001219820Sjeff#define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET 0x82 1002219820Sjeff#define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET 0x84 1003219820Sjeff#define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET 0x86 1004219820Sjeff#define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET 0x88 1005219820Sjeff#define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET 0x8a 1006219820Sjeff#define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET 0x8c 1007219820Sjeff#define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET 0x8e 1008219820Sjeff#define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET 0x90 1009219820Sjeff#define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET 0x92 1010219820Sjeff#define QUERY_DEV_LIM_PBL_SZ_OFFSET 0x96 1011219820Sjeff#define QUERY_DEV_LIM_BMME_FLAGS_OFFSET 0x97 1012219820Sjeff#define QUERY_DEV_LIM_RSVD_LKEY_OFFSET 0x98 1013219820Sjeff#define QUERY_DEV_LIM_LAMR_OFFSET 0x9f 1014219820Sjeff#define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET 0xa0 1015219820Sjeff 1016219820Sjeff mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1017219820Sjeff if (IS_ERR(mailbox)) 1018219820Sjeff return PTR_ERR(mailbox); 1019219820Sjeff outbox = mailbox->buf; 1020219820Sjeff 1021219820Sjeff err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DEV_LIM, 1022219820Sjeff CMD_TIME_CLASS_A, status); 1023219820Sjeff 1024219820Sjeff if (err) 1025219820Sjeff goto out; 1026219820Sjeff 1027219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_QP_OFFSET); 1028219820Sjeff dev_lim->reserved_qps = 1 << (field & 0xf); 1029219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_OFFSET); 1030219820Sjeff dev_lim->max_qps = 1 << (field & 0x1f); 1031219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_SRQ_OFFSET); 1032219820Sjeff dev_lim->reserved_srqs = 1 << (field >> 4); 1033219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_OFFSET); 1034219820Sjeff dev_lim->max_srqs = 1 << (field & 0x1f); 1035219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EEC_OFFSET); 1036219820Sjeff dev_lim->reserved_eecs = 1 << (field & 0xf); 1037219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EEC_OFFSET); 1038219820Sjeff dev_lim->max_eecs = 1 << (field & 0x1f); 1039219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET); 1040219820Sjeff dev_lim->max_cq_sz = 1 << field; 1041219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_CQ_OFFSET); 1042219820Sjeff dev_lim->reserved_cqs = 1 << (field & 0xf); 1043219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_OFFSET); 1044219820Sjeff dev_lim->max_cqs = 1 << (field & 0x1f); 1045219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MPT_OFFSET); 1046219820Sjeff dev_lim->max_mpts = 1 << (field & 0x3f); 1047219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EQ_OFFSET); 1048219820Sjeff dev_lim->reserved_eqs = 1 << (field & 0xf); 1049219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EQ_OFFSET); 1050219820Sjeff dev_lim->max_eqs = 1 << (field & 0x7); 1051219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET); 1052219820Sjeff if (mthca_is_memfree(dev)) 1053219820Sjeff dev_lim->reserved_mtts = ALIGN((1 << (field >> 4)) * sizeof(u64), 1054219820Sjeff dev->limits.mtt_seg_size) / dev->limits.mtt_seg_size; 1055219820Sjeff else 1056219820Sjeff dev_lim->reserved_mtts = 1 << (field >> 4); 1057219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET); 1058219820Sjeff dev_lim->max_mrw_sz = 1 << field; 1059219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MRW_OFFSET); 1060219820Sjeff dev_lim->reserved_mrws = 1 << (field & 0xf); 1061219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET); 1062219820Sjeff dev_lim->max_mtt_seg = 1 << (field & 0x3f); 1063219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_REQ_QP_OFFSET); 1064219820Sjeff dev_lim->max_requester_per_qp = 1 << (field & 0x3f); 1065219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RES_QP_OFFSET); 1066219820Sjeff dev_lim->max_responder_per_qp = 1 << (field & 0x3f); 1067219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDMA_OFFSET); 1068219820Sjeff dev_lim->max_rdma_global = 1 << (field & 0x3f); 1069219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_ACK_DELAY_OFFSET); 1070219820Sjeff dev_lim->local_ca_ack_delay = field & 0x1f; 1071219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MTU_WIDTH_OFFSET); 1072219820Sjeff dev_lim->max_mtu = field >> 4; 1073219820Sjeff dev_lim->max_port_width = field & 0xf; 1074219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_VL_PORT_OFFSET); 1075219820Sjeff dev_lim->max_vl = field >> 4; 1076219820Sjeff dev_lim->num_ports = field & 0xf; 1077219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_GID_OFFSET); 1078219820Sjeff dev_lim->max_gids = 1 << (field & 0xf); 1079219820Sjeff MTHCA_GET(stat_rate, outbox, QUERY_DEV_LIM_RATE_SUPPORT_OFFSET); 1080219820Sjeff dev_lim->stat_rate_support = stat_rate; 1081219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PKEY_OFFSET); 1082219820Sjeff dev_lim->max_pkeys = 1 << (field & 0xf); 1083219820Sjeff MTHCA_GET(dev_lim->flags, outbox, QUERY_DEV_LIM_FLAGS_OFFSET); 1084219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_UAR_OFFSET); 1085219820Sjeff dev_lim->reserved_uars = field >> 4; 1086219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_UAR_SZ_OFFSET); 1087219820Sjeff dev_lim->uar_size = 1 << ((field & 0x3f) + 20); 1088219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_PAGE_SZ_OFFSET); 1089219820Sjeff dev_lim->min_page_sz = 1 << field; 1090219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_OFFSET); 1091219820Sjeff dev_lim->max_sg = field; 1092219820Sjeff 1093219820Sjeff MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET); 1094219820Sjeff dev_lim->max_desc_sz = size; 1095219820Sjeff 1096219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_MCG_OFFSET); 1097219820Sjeff dev_lim->max_qp_per_mcg = 1 << field; 1098219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MCG_OFFSET); 1099219820Sjeff dev_lim->reserved_mgms = field & 0xf; 1100219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MCG_OFFSET); 1101219820Sjeff dev_lim->max_mcgs = 1 << field; 1102219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_PD_OFFSET); 1103219820Sjeff dev_lim->reserved_pds = field >> 4; 1104219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PD_OFFSET); 1105219820Sjeff dev_lim->max_pds = 1 << (field & 0x3f); 1106219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_RDD_OFFSET); 1107219820Sjeff dev_lim->reserved_rdds = field >> 4; 1108219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDD_OFFSET); 1109219820Sjeff dev_lim->max_rdds = 1 << (field & 0x3f); 1110219820Sjeff 1111219820Sjeff MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET); 1112219820Sjeff dev_lim->eec_entry_sz = size; 1113219820Sjeff MTHCA_GET(size, outbox, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET); 1114219820Sjeff dev_lim->qpc_entry_sz = size; 1115219820Sjeff MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET); 1116219820Sjeff dev_lim->eeec_entry_sz = size; 1117219820Sjeff MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET); 1118219820Sjeff dev_lim->eqpc_entry_sz = size; 1119219820Sjeff MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET); 1120219820Sjeff dev_lim->eqc_entry_sz = size; 1121219820Sjeff MTHCA_GET(size, outbox, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET); 1122219820Sjeff dev_lim->cqc_entry_sz = size; 1123219820Sjeff MTHCA_GET(size, outbox, QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET); 1124219820Sjeff dev_lim->srq_entry_sz = size; 1125219820Sjeff MTHCA_GET(size, outbox, QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET); 1126219820Sjeff dev_lim->uar_scratch_entry_sz = size; 1127219820Sjeff 1128219820Sjeff if (mthca_is_memfree(dev)) { 1129219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET); 1130219820Sjeff dev_lim->max_srq_sz = 1 << field; 1131219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET); 1132219820Sjeff dev_lim->max_qp_sz = 1 << field; 1133219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSZ_SRQ_OFFSET); 1134219820Sjeff dev_lim->hca.arbel.resize_srq = field & 1; 1135219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_RQ_OFFSET); 1136219820Sjeff dev_lim->max_sg = min_t(int, field, dev_lim->max_sg); 1137219820Sjeff MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET); 1138219820Sjeff dev_lim->max_desc_sz = min_t(int, size, dev_lim->max_desc_sz); 1139219820Sjeff MTHCA_GET(size, outbox, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET); 1140219820Sjeff dev_lim->mpt_entry_sz = size; 1141219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_PBL_SZ_OFFSET); 1142219820Sjeff dev_lim->hca.arbel.max_pbl_sz = 1 << (field & 0x3f); 1143219820Sjeff MTHCA_GET(dev_lim->hca.arbel.bmme_flags, outbox, 1144219820Sjeff QUERY_DEV_LIM_BMME_FLAGS_OFFSET); 1145219820Sjeff MTHCA_GET(dev_lim->hca.arbel.reserved_lkey, outbox, 1146219820Sjeff QUERY_DEV_LIM_RSVD_LKEY_OFFSET); 1147219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_LAMR_OFFSET); 1148219820Sjeff dev_lim->hca.arbel.lam_required = field & 1; 1149219820Sjeff MTHCA_GET(dev_lim->hca.arbel.max_icm_sz, outbox, 1150219820Sjeff QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET); 1151219820Sjeff 1152219820Sjeff if (dev_lim->hca.arbel.bmme_flags & 1) 1153219820Sjeff mthca_dbg(dev, "Base MM extensions: yes " 1154219820Sjeff "(flags %d, max PBL %d, rsvd L_Key %08x)\n", 1155219820Sjeff dev_lim->hca.arbel.bmme_flags, 1156219820Sjeff dev_lim->hca.arbel.max_pbl_sz, 1157219820Sjeff dev_lim->hca.arbel.reserved_lkey); 1158219820Sjeff else 1159219820Sjeff mthca_dbg(dev, "Base MM extensions: no\n"); 1160219820Sjeff 1161219820Sjeff mthca_dbg(dev, "Max ICM size %lld MB\n", 1162219820Sjeff (unsigned long long) dev_lim->hca.arbel.max_icm_sz >> 20); 1163219820Sjeff } else { 1164219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET); 1165219820Sjeff dev_lim->max_srq_sz = (1 << field) - 1; 1166219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET); 1167219820Sjeff dev_lim->max_qp_sz = (1 << field) - 1; 1168219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_AV_OFFSET); 1169219820Sjeff dev_lim->hca.tavor.max_avs = 1 << (field & 0x3f); 1170219820Sjeff dev_lim->mpt_entry_sz = MTHCA_MPT_ENTRY_SIZE; 1171219820Sjeff } 1172219820Sjeff 1173219820Sjeff mthca_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", 1174219820Sjeff dev_lim->max_qps, dev_lim->reserved_qps, dev_lim->qpc_entry_sz); 1175219820Sjeff mthca_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", 1176219820Sjeff dev_lim->max_srqs, dev_lim->reserved_srqs, dev_lim->srq_entry_sz); 1177219820Sjeff mthca_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", 1178219820Sjeff dev_lim->max_cqs, dev_lim->reserved_cqs, dev_lim->cqc_entry_sz); 1179219820Sjeff mthca_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n", 1180219820Sjeff dev_lim->max_eqs, dev_lim->reserved_eqs, dev_lim->eqc_entry_sz); 1181219820Sjeff mthca_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", 1182219820Sjeff dev_lim->reserved_mrws, dev_lim->reserved_mtts); 1183219820Sjeff mthca_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", 1184219820Sjeff dev_lim->max_pds, dev_lim->reserved_pds, dev_lim->reserved_uars); 1185219820Sjeff mthca_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", 1186219820Sjeff dev_lim->max_pds, dev_lim->reserved_mgms); 1187219820Sjeff mthca_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", 1188219820Sjeff dev_lim->max_cq_sz, dev_lim->max_qp_sz, dev_lim->max_srq_sz); 1189219820Sjeff 1190219820Sjeff mthca_dbg(dev, "Flags: %08x\n", dev_lim->flags); 1191219820Sjeff 1192219820Sjeffout: 1193219820Sjeff mthca_free_mailbox(dev, mailbox); 1194219820Sjeff return err; 1195219820Sjeff} 1196219820Sjeff 1197219820Sjeffstatic void get_board_id(void *vsd, char *board_id) 1198219820Sjeff{ 1199219820Sjeff int i; 1200219820Sjeff 1201219820Sjeff#define VSD_OFFSET_SIG1 0x00 1202219820Sjeff#define VSD_OFFSET_SIG2 0xde 1203219820Sjeff#define VSD_OFFSET_MLX_BOARD_ID 0xd0 1204219820Sjeff#define VSD_OFFSET_TS_BOARD_ID 0x20 1205219820Sjeff 1206219820Sjeff#define VSD_SIGNATURE_TOPSPIN 0x5ad 1207219820Sjeff 1208219820Sjeff memset(board_id, 0, MTHCA_BOARD_ID_LEN); 1209219820Sjeff 1210219820Sjeff if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && 1211219820Sjeff be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { 1212219820Sjeff strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MTHCA_BOARD_ID_LEN); 1213219820Sjeff } else { 1214219820Sjeff /* 1215219820Sjeff * The board ID is a string but the firmware byte 1216219820Sjeff * swaps each 4-byte word before passing it back to 1217219820Sjeff * us. Therefore we need to swab it before printing. 1218219820Sjeff */ 1219219820Sjeff for (i = 0; i < 4; ++i) 1220219820Sjeff ((u32 *) board_id)[i] = 1221219820Sjeff swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4)); 1222219820Sjeff } 1223219820Sjeff} 1224219820Sjeff 1225219820Sjeffint mthca_QUERY_ADAPTER(struct mthca_dev *dev, 1226219820Sjeff struct mthca_adapter *adapter, u8 *status) 1227219820Sjeff{ 1228219820Sjeff struct mthca_mailbox *mailbox; 1229219820Sjeff u32 *outbox; 1230219820Sjeff int err; 1231219820Sjeff 1232219820Sjeff#define QUERY_ADAPTER_OUT_SIZE 0x100 1233219820Sjeff#define QUERY_ADAPTER_VENDOR_ID_OFFSET 0x00 1234219820Sjeff#define QUERY_ADAPTER_DEVICE_ID_OFFSET 0x04 1235219820Sjeff#define QUERY_ADAPTER_REVISION_ID_OFFSET 0x08 1236219820Sjeff#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 1237219820Sjeff#define QUERY_ADAPTER_VSD_OFFSET 0x20 1238219820Sjeff 1239219820Sjeff mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1240219820Sjeff if (IS_ERR(mailbox)) 1241219820Sjeff return PTR_ERR(mailbox); 1242219820Sjeff outbox = mailbox->buf; 1243219820Sjeff 1244219820Sjeff err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_ADAPTER, 1245219820Sjeff CMD_TIME_CLASS_A, status); 1246219820Sjeff 1247219820Sjeff if (err) 1248219820Sjeff goto out; 1249219820Sjeff 1250219820Sjeff if (!mthca_is_memfree(dev)) { 1251219820Sjeff MTHCA_GET(adapter->vendor_id, outbox, 1252219820Sjeff QUERY_ADAPTER_VENDOR_ID_OFFSET); 1253219820Sjeff MTHCA_GET(adapter->device_id, outbox, 1254219820Sjeff QUERY_ADAPTER_DEVICE_ID_OFFSET); 1255219820Sjeff MTHCA_GET(adapter->revision_id, outbox, 1256219820Sjeff QUERY_ADAPTER_REVISION_ID_OFFSET); 1257219820Sjeff } 1258219820Sjeff MTHCA_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); 1259219820Sjeff 1260219820Sjeff get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, 1261219820Sjeff adapter->board_id); 1262219820Sjeff 1263219820Sjeffout: 1264219820Sjeff mthca_free_mailbox(dev, mailbox); 1265219820Sjeff return err; 1266219820Sjeff} 1267219820Sjeff 1268219820Sjeffint mthca_INIT_HCA(struct mthca_dev *dev, 1269219820Sjeff struct mthca_init_hca_param *param, 1270219820Sjeff u8 *status) 1271219820Sjeff{ 1272219820Sjeff struct mthca_mailbox *mailbox; 1273219820Sjeff __be32 *inbox; 1274219820Sjeff int err; 1275219820Sjeff 1276219820Sjeff#define INIT_HCA_IN_SIZE 0x200 1277219820Sjeff#define INIT_HCA_FLAGS1_OFFSET 0x00c 1278219820Sjeff#define INIT_HCA_FLAGS2_OFFSET 0x014 1279219820Sjeff#define INIT_HCA_QPC_OFFSET 0x020 1280219820Sjeff#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) 1281219820Sjeff#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) 1282219820Sjeff#define INIT_HCA_EEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x20) 1283219820Sjeff#define INIT_HCA_LOG_EEC_OFFSET (INIT_HCA_QPC_OFFSET + 0x27) 1284219820Sjeff#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) 1285219820Sjeff#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) 1286219820Sjeff#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) 1287219820Sjeff#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) 1288219820Sjeff#define INIT_HCA_EQPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) 1289219820Sjeff#define INIT_HCA_EEEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) 1290219820Sjeff#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) 1291219820Sjeff#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) 1292219820Sjeff#define INIT_HCA_RDB_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) 1293219820Sjeff#define INIT_HCA_UDAV_OFFSET 0x0b0 1294219820Sjeff#define INIT_HCA_UDAV_LKEY_OFFSET (INIT_HCA_UDAV_OFFSET + 0x0) 1295219820Sjeff#define INIT_HCA_UDAV_PD_OFFSET (INIT_HCA_UDAV_OFFSET + 0x4) 1296219820Sjeff#define INIT_HCA_MCAST_OFFSET 0x0c0 1297219820Sjeff#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) 1298219820Sjeff#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) 1299219820Sjeff#define INIT_HCA_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) 1300219820Sjeff#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) 1301219820Sjeff#define INIT_HCA_TPT_OFFSET 0x0f0 1302219820Sjeff#define INIT_HCA_MPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) 1303219820Sjeff#define INIT_HCA_MTT_SEG_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x09) 1304219820Sjeff#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) 1305219820Sjeff#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) 1306219820Sjeff#define INIT_HCA_UAR_OFFSET 0x120 1307219820Sjeff#define INIT_HCA_UAR_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x00) 1308219820Sjeff#define INIT_HCA_UARC_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x09) 1309219820Sjeff#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) 1310219820Sjeff#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) 1311219820Sjeff#define INIT_HCA_UAR_SCATCH_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x10) 1312219820Sjeff#define INIT_HCA_UAR_CTX_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x18) 1313219820Sjeff 1314219820Sjeff mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1315219820Sjeff if (IS_ERR(mailbox)) 1316219820Sjeff return PTR_ERR(mailbox); 1317219820Sjeff inbox = mailbox->buf; 1318219820Sjeff 1319219820Sjeff memset(inbox, 0, INIT_HCA_IN_SIZE); 1320219820Sjeff 1321219820Sjeff if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT) 1322219820Sjeff MTHCA_PUT(inbox, 0x1, INIT_HCA_FLAGS1_OFFSET); 1323219820Sjeff 1324219820Sjeff#if defined(__LITTLE_ENDIAN) 1325219820Sjeff *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) &= ~cpu_to_be32(1 << 1); 1326219820Sjeff#elif defined(__BIG_ENDIAN) 1327219820Sjeff *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1 << 1); 1328219820Sjeff#else 1329219820Sjeff#error Host endianness not defined 1330219820Sjeff#endif 1331219820Sjeff /* Check port for UD address vector: */ 1332219820Sjeff *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1); 1333219820Sjeff 1334219820Sjeff /* Enable IPoIB checksumming if we can: */ 1335219820Sjeff if (dev->device_cap_flags & IB_DEVICE_UD_IP_CSUM) 1336219820Sjeff *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(7 << 3); 1337219820Sjeff 1338219820Sjeff /* We leave wqe_quota, responder_exu, etc as 0 (default) */ 1339219820Sjeff 1340219820Sjeff /* QPC/EEC/CQC/EQC/RDB attributes */ 1341219820Sjeff 1342219820Sjeff MTHCA_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); 1343219820Sjeff MTHCA_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); 1344219820Sjeff MTHCA_PUT(inbox, param->eec_base, INIT_HCA_EEC_BASE_OFFSET); 1345219820Sjeff MTHCA_PUT(inbox, param->log_num_eecs, INIT_HCA_LOG_EEC_OFFSET); 1346219820Sjeff MTHCA_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); 1347219820Sjeff MTHCA_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); 1348219820Sjeff MTHCA_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); 1349219820Sjeff MTHCA_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); 1350219820Sjeff MTHCA_PUT(inbox, param->eqpc_base, INIT_HCA_EQPC_BASE_OFFSET); 1351219820Sjeff MTHCA_PUT(inbox, param->eeec_base, INIT_HCA_EEEC_BASE_OFFSET); 1352219820Sjeff MTHCA_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); 1353219820Sjeff MTHCA_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); 1354219820Sjeff MTHCA_PUT(inbox, param->rdb_base, INIT_HCA_RDB_BASE_OFFSET); 1355219820Sjeff 1356219820Sjeff /* UD AV attributes */ 1357219820Sjeff 1358219820Sjeff /* multicast attributes */ 1359219820Sjeff 1360219820Sjeff MTHCA_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); 1361219820Sjeff MTHCA_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 1362219820Sjeff MTHCA_PUT(inbox, param->mc_hash_sz, INIT_HCA_MC_HASH_SZ_OFFSET); 1363219820Sjeff MTHCA_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 1364219820Sjeff 1365219820Sjeff /* TPT attributes */ 1366219820Sjeff 1367219820Sjeff MTHCA_PUT(inbox, param->mpt_base, INIT_HCA_MPT_BASE_OFFSET); 1368219820Sjeff if (!mthca_is_memfree(dev)) 1369219820Sjeff MTHCA_PUT(inbox, param->mtt_seg_sz, INIT_HCA_MTT_SEG_SZ_OFFSET); 1370219820Sjeff MTHCA_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); 1371219820Sjeff MTHCA_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); 1372219820Sjeff 1373219820Sjeff /* UAR attributes */ 1374219820Sjeff { 1375219820Sjeff u8 uar_page_sz = PAGE_SHIFT - 12; 1376219820Sjeff MTHCA_PUT(inbox, uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); 1377219820Sjeff } 1378219820Sjeff 1379219820Sjeff MTHCA_PUT(inbox, param->uar_scratch_base, INIT_HCA_UAR_SCATCH_BASE_OFFSET); 1380219820Sjeff 1381219820Sjeff if (mthca_is_memfree(dev)) { 1382219820Sjeff MTHCA_PUT(inbox, param->log_uarc_sz, INIT_HCA_UARC_SZ_OFFSET); 1383219820Sjeff MTHCA_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); 1384219820Sjeff MTHCA_PUT(inbox, param->uarc_base, INIT_HCA_UAR_CTX_BASE_OFFSET); 1385219820Sjeff } 1386219820Sjeff 1387219820Sjeff err = mthca_cmd(dev, mailbox->dma, 0, 0, CMD_INIT_HCA, CMD_TIME_CLASS_D, status); 1388219820Sjeff 1389219820Sjeff mthca_free_mailbox(dev, mailbox); 1390219820Sjeff return err; 1391219820Sjeff} 1392219820Sjeff 1393219820Sjeffint mthca_INIT_IB(struct mthca_dev *dev, 1394219820Sjeff struct mthca_init_ib_param *param, 1395219820Sjeff int port, u8 *status) 1396219820Sjeff{ 1397219820Sjeff struct mthca_mailbox *mailbox; 1398219820Sjeff u32 *inbox; 1399219820Sjeff int err; 1400219820Sjeff u32 flags; 1401219820Sjeff 1402219820Sjeff#define INIT_IB_IN_SIZE 56 1403219820Sjeff#define INIT_IB_FLAGS_OFFSET 0x00 1404219820Sjeff#define INIT_IB_FLAG_SIG (1 << 18) 1405219820Sjeff#define INIT_IB_FLAG_NG (1 << 17) 1406219820Sjeff#define INIT_IB_FLAG_G0 (1 << 16) 1407219820Sjeff#define INIT_IB_VL_SHIFT 4 1408219820Sjeff#define INIT_IB_PORT_WIDTH_SHIFT 8 1409219820Sjeff#define INIT_IB_MTU_SHIFT 12 1410219820Sjeff#define INIT_IB_MAX_GID_OFFSET 0x06 1411219820Sjeff#define INIT_IB_MAX_PKEY_OFFSET 0x0a 1412219820Sjeff#define INIT_IB_GUID0_OFFSET 0x10 1413219820Sjeff#define INIT_IB_NODE_GUID_OFFSET 0x18 1414219820Sjeff#define INIT_IB_SI_GUID_OFFSET 0x20 1415219820Sjeff 1416219820Sjeff mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1417219820Sjeff if (IS_ERR(mailbox)) 1418219820Sjeff return PTR_ERR(mailbox); 1419219820Sjeff inbox = mailbox->buf; 1420219820Sjeff 1421219820Sjeff memset(inbox, 0, INIT_IB_IN_SIZE); 1422219820Sjeff 1423219820Sjeff flags = 0; 1424219820Sjeff flags |= param->set_guid0 ? INIT_IB_FLAG_G0 : 0; 1425219820Sjeff flags |= param->set_node_guid ? INIT_IB_FLAG_NG : 0; 1426219820Sjeff flags |= param->set_si_guid ? INIT_IB_FLAG_SIG : 0; 1427219820Sjeff flags |= param->vl_cap << INIT_IB_VL_SHIFT; 1428219820Sjeff flags |= param->port_width << INIT_IB_PORT_WIDTH_SHIFT; 1429219820Sjeff flags |= param->mtu_cap << INIT_IB_MTU_SHIFT; 1430219820Sjeff MTHCA_PUT(inbox, flags, INIT_IB_FLAGS_OFFSET); 1431219820Sjeff 1432219820Sjeff MTHCA_PUT(inbox, param->gid_cap, INIT_IB_MAX_GID_OFFSET); 1433219820Sjeff MTHCA_PUT(inbox, param->pkey_cap, INIT_IB_MAX_PKEY_OFFSET); 1434219820Sjeff MTHCA_PUT(inbox, param->guid0, INIT_IB_GUID0_OFFSET); 1435219820Sjeff MTHCA_PUT(inbox, param->node_guid, INIT_IB_NODE_GUID_OFFSET); 1436219820Sjeff MTHCA_PUT(inbox, param->si_guid, INIT_IB_SI_GUID_OFFSET); 1437219820Sjeff 1438219820Sjeff err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_INIT_IB, 1439219820Sjeff CMD_TIME_CLASS_A, status); 1440219820Sjeff 1441219820Sjeff mthca_free_mailbox(dev, mailbox); 1442219820Sjeff return err; 1443219820Sjeff} 1444219820Sjeff 1445219820Sjeffint mthca_CLOSE_IB(struct mthca_dev *dev, int port, u8 *status) 1446219820Sjeff{ 1447219820Sjeff return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, CMD_TIME_CLASS_A, status); 1448219820Sjeff} 1449219820Sjeff 1450219820Sjeffint mthca_CLOSE_HCA(struct mthca_dev *dev, int panic, u8 *status) 1451219820Sjeff{ 1452219820Sjeff return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, CMD_TIME_CLASS_C, status); 1453219820Sjeff} 1454219820Sjeff 1455219820Sjeffint mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param, 1456219820Sjeff int port, u8 *status) 1457219820Sjeff{ 1458219820Sjeff struct mthca_mailbox *mailbox; 1459219820Sjeff u32 *inbox; 1460219820Sjeff int err; 1461219820Sjeff u32 flags = 0; 1462219820Sjeff 1463219820Sjeff#define SET_IB_IN_SIZE 0x40 1464219820Sjeff#define SET_IB_FLAGS_OFFSET 0x00 1465219820Sjeff#define SET_IB_FLAG_SIG (1 << 18) 1466219820Sjeff#define SET_IB_FLAG_RQK (1 << 0) 1467219820Sjeff#define SET_IB_CAP_MASK_OFFSET 0x04 1468219820Sjeff#define SET_IB_SI_GUID_OFFSET 0x08 1469219820Sjeff 1470219820Sjeff mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1471219820Sjeff if (IS_ERR(mailbox)) 1472219820Sjeff return PTR_ERR(mailbox); 1473219820Sjeff inbox = mailbox->buf; 1474219820Sjeff 1475219820Sjeff memset(inbox, 0, SET_IB_IN_SIZE); 1476219820Sjeff 1477219820Sjeff flags |= param->set_si_guid ? SET_IB_FLAG_SIG : 0; 1478219820Sjeff flags |= param->reset_qkey_viol ? SET_IB_FLAG_RQK : 0; 1479219820Sjeff MTHCA_PUT(inbox, flags, SET_IB_FLAGS_OFFSET); 1480219820Sjeff 1481219820Sjeff MTHCA_PUT(inbox, param->cap_mask, SET_IB_CAP_MASK_OFFSET); 1482219820Sjeff MTHCA_PUT(inbox, param->si_guid, SET_IB_SI_GUID_OFFSET); 1483219820Sjeff 1484219820Sjeff err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_SET_IB, 1485219820Sjeff CMD_TIME_CLASS_B, status); 1486219820Sjeff 1487219820Sjeff mthca_free_mailbox(dev, mailbox); 1488219820Sjeff return err; 1489219820Sjeff} 1490219820Sjeff 1491219820Sjeffint mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt, u8 *status) 1492219820Sjeff{ 1493219820Sjeff return mthca_map_cmd(dev, CMD_MAP_ICM, icm, virt, status); 1494219820Sjeff} 1495219820Sjeff 1496219820Sjeffint mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt, u8 *status) 1497219820Sjeff{ 1498219820Sjeff struct mthca_mailbox *mailbox; 1499219820Sjeff __be64 *inbox; 1500219820Sjeff int err; 1501219820Sjeff 1502219820Sjeff mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1503219820Sjeff if (IS_ERR(mailbox)) 1504219820Sjeff return PTR_ERR(mailbox); 1505219820Sjeff inbox = mailbox->buf; 1506219820Sjeff 1507219820Sjeff inbox[0] = cpu_to_be64(virt); 1508219820Sjeff inbox[1] = cpu_to_be64(dma_addr); 1509219820Sjeff 1510219820Sjeff err = mthca_cmd(dev, mailbox->dma, 1, 0, CMD_MAP_ICM, 1511219820Sjeff CMD_TIME_CLASS_B, status); 1512219820Sjeff 1513219820Sjeff mthca_free_mailbox(dev, mailbox); 1514219820Sjeff 1515219820Sjeff if (!err) 1516219820Sjeff mthca_dbg(dev, "Mapped page at %llx to %llx for ICM.\n", 1517219820Sjeff (unsigned long long) dma_addr, (unsigned long long) virt); 1518219820Sjeff 1519219820Sjeff return err; 1520219820Sjeff} 1521219820Sjeff 1522219820Sjeffint mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count, u8 *status) 1523219820Sjeff{ 1524219820Sjeff mthca_dbg(dev, "Unmapping %d pages at %llx from ICM.\n", 1525219820Sjeff page_count, (unsigned long long) virt); 1526219820Sjeff 1527219820Sjeff return mthca_cmd(dev, virt, page_count, 0, CMD_UNMAP_ICM, CMD_TIME_CLASS_B, status); 1528219820Sjeff} 1529219820Sjeff 1530219820Sjeffint mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status) 1531219820Sjeff{ 1532219820Sjeff return mthca_map_cmd(dev, CMD_MAP_ICM_AUX, icm, -1, status); 1533219820Sjeff} 1534219820Sjeff 1535219820Sjeffint mthca_UNMAP_ICM_AUX(struct mthca_dev *dev, u8 *status) 1536219820Sjeff{ 1537219820Sjeff return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_ICM_AUX, CMD_TIME_CLASS_B, status); 1538219820Sjeff} 1539219820Sjeff 1540219820Sjeffint mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages, 1541219820Sjeff u8 *status) 1542219820Sjeff{ 1543219820Sjeff int ret = mthca_cmd_imm(dev, icm_size, aux_pages, 0, 0, CMD_SET_ICM_SIZE, 1544219820Sjeff CMD_TIME_CLASS_A, status); 1545219820Sjeff 1546219820Sjeff if (ret || status) 1547219820Sjeff return ret; 1548219820Sjeff 1549219820Sjeff /* 1550219820Sjeff * Round up number of system pages needed in case 1551219820Sjeff * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE. 1552219820Sjeff */ 1553219820Sjeff *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >> 1554219820Sjeff (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT); 1555219820Sjeff 1556219820Sjeff return 0; 1557219820Sjeff} 1558219820Sjeff 1559219820Sjeffint mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1560219820Sjeff int mpt_index, u8 *status) 1561219820Sjeff{ 1562219820Sjeff return mthca_cmd(dev, mailbox->dma, mpt_index, 0, CMD_SW2HW_MPT, 1563219820Sjeff CMD_TIME_CLASS_B, status); 1564219820Sjeff} 1565219820Sjeff 1566219820Sjeffint mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1567219820Sjeff int mpt_index, u8 *status) 1568219820Sjeff{ 1569219820Sjeff return mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index, 1570219820Sjeff !mailbox, CMD_HW2SW_MPT, 1571219820Sjeff CMD_TIME_CLASS_B, status); 1572219820Sjeff} 1573219820Sjeff 1574219820Sjeffint mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1575219820Sjeff int num_mtt, u8 *status) 1576219820Sjeff{ 1577219820Sjeff return mthca_cmd(dev, mailbox->dma, num_mtt, 0, CMD_WRITE_MTT, 1578219820Sjeff CMD_TIME_CLASS_B, status); 1579219820Sjeff} 1580219820Sjeff 1581219820Sjeffint mthca_SYNC_TPT(struct mthca_dev *dev, u8 *status) 1582219820Sjeff{ 1583219820Sjeff return mthca_cmd(dev, 0, 0, 0, CMD_SYNC_TPT, CMD_TIME_CLASS_B, status); 1584219820Sjeff} 1585219820Sjeff 1586219820Sjeffint mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap, 1587219820Sjeff int eq_num, u8 *status) 1588219820Sjeff{ 1589219820Sjeff mthca_dbg(dev, "%s mask %016llx for eqn %d\n", 1590219820Sjeff unmap ? "Clearing" : "Setting", 1591219820Sjeff (unsigned long long) event_mask, eq_num); 1592219820Sjeff return mthca_cmd(dev, event_mask, (unmap << 31) | eq_num, 1593219820Sjeff 0, CMD_MAP_EQ, CMD_TIME_CLASS_B, status); 1594219820Sjeff} 1595219820Sjeff 1596219820Sjeffint mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1597219820Sjeff int eq_num, u8 *status) 1598219820Sjeff{ 1599219820Sjeff return mthca_cmd(dev, mailbox->dma, eq_num, 0, CMD_SW2HW_EQ, 1600219820Sjeff CMD_TIME_CLASS_A, status); 1601219820Sjeff} 1602219820Sjeff 1603219820Sjeffint mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1604219820Sjeff int eq_num, u8 *status) 1605219820Sjeff{ 1606219820Sjeff return mthca_cmd_box(dev, 0, mailbox->dma, eq_num, 0, 1607219820Sjeff CMD_HW2SW_EQ, 1608219820Sjeff CMD_TIME_CLASS_A, status); 1609219820Sjeff} 1610219820Sjeff 1611219820Sjeffint mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1612219820Sjeff int cq_num, u8 *status) 1613219820Sjeff{ 1614219820Sjeff return mthca_cmd(dev, mailbox->dma, cq_num, 0, CMD_SW2HW_CQ, 1615219820Sjeff CMD_TIME_CLASS_A, status); 1616219820Sjeff} 1617219820Sjeff 1618219820Sjeffint mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1619219820Sjeff int cq_num, u8 *status) 1620219820Sjeff{ 1621219820Sjeff return mthca_cmd_box(dev, 0, mailbox->dma, cq_num, 0, 1622219820Sjeff CMD_HW2SW_CQ, 1623219820Sjeff CMD_TIME_CLASS_A, status); 1624219820Sjeff} 1625219820Sjeff 1626219820Sjeffint mthca_RESIZE_CQ(struct mthca_dev *dev, int cq_num, u32 lkey, u8 log_size, 1627219820Sjeff u8 *status) 1628219820Sjeff{ 1629219820Sjeff struct mthca_mailbox *mailbox; 1630219820Sjeff __be32 *inbox; 1631219820Sjeff int err; 1632219820Sjeff 1633219820Sjeff#define RESIZE_CQ_IN_SIZE 0x40 1634219820Sjeff#define RESIZE_CQ_LOG_SIZE_OFFSET 0x0c 1635219820Sjeff#define RESIZE_CQ_LKEY_OFFSET 0x1c 1636219820Sjeff 1637219820Sjeff mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1638219820Sjeff if (IS_ERR(mailbox)) 1639219820Sjeff return PTR_ERR(mailbox); 1640219820Sjeff inbox = mailbox->buf; 1641219820Sjeff 1642219820Sjeff memset(inbox, 0, RESIZE_CQ_IN_SIZE); 1643219820Sjeff /* 1644219820Sjeff * Leave start address fields zeroed out -- mthca assumes that 1645219820Sjeff * MRs for CQs always start at virtual address 0. 1646219820Sjeff */ 1647219820Sjeff MTHCA_PUT(inbox, log_size, RESIZE_CQ_LOG_SIZE_OFFSET); 1648219820Sjeff MTHCA_PUT(inbox, lkey, RESIZE_CQ_LKEY_OFFSET); 1649219820Sjeff 1650219820Sjeff err = mthca_cmd(dev, mailbox->dma, cq_num, 1, CMD_RESIZE_CQ, 1651219820Sjeff CMD_TIME_CLASS_B, status); 1652219820Sjeff 1653219820Sjeff mthca_free_mailbox(dev, mailbox); 1654219820Sjeff return err; 1655219820Sjeff} 1656219820Sjeff 1657219820Sjeffint mthca_SW2HW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1658219820Sjeff int srq_num, u8 *status) 1659219820Sjeff{ 1660219820Sjeff return mthca_cmd(dev, mailbox->dma, srq_num, 0, CMD_SW2HW_SRQ, 1661219820Sjeff CMD_TIME_CLASS_A, status); 1662219820Sjeff} 1663219820Sjeff 1664219820Sjeffint mthca_HW2SW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1665219820Sjeff int srq_num, u8 *status) 1666219820Sjeff{ 1667219820Sjeff return mthca_cmd_box(dev, 0, mailbox->dma, srq_num, 0, 1668219820Sjeff CMD_HW2SW_SRQ, 1669219820Sjeff CMD_TIME_CLASS_A, status); 1670219820Sjeff} 1671219820Sjeff 1672219820Sjeffint mthca_QUERY_SRQ(struct mthca_dev *dev, u32 num, 1673219820Sjeff struct mthca_mailbox *mailbox, u8 *status) 1674219820Sjeff{ 1675219820Sjeff return mthca_cmd_box(dev, 0, mailbox->dma, num, 0, 1676219820Sjeff CMD_QUERY_SRQ, CMD_TIME_CLASS_A, status); 1677219820Sjeff} 1678219820Sjeff 1679219820Sjeffint mthca_ARM_SRQ(struct mthca_dev *dev, int srq_num, int limit, u8 *status) 1680219820Sjeff{ 1681219820Sjeff return mthca_cmd(dev, limit, srq_num, 0, CMD_ARM_SRQ, 1682219820Sjeff CMD_TIME_CLASS_B, status); 1683219820Sjeff} 1684219820Sjeff 1685219820Sjeffint mthca_MODIFY_QP(struct mthca_dev *dev, enum ib_qp_state cur, 1686219820Sjeff enum ib_qp_state next, u32 num, int is_ee, 1687219820Sjeff struct mthca_mailbox *mailbox, u32 optmask, 1688219820Sjeff u8 *status) 1689219820Sjeff{ 1690219820Sjeff static const u16 op[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = { 1691219820Sjeff [IB_QPS_RESET] = { 1692219820Sjeff [IB_QPS_RESET] = CMD_ERR2RST_QPEE, 1693219820Sjeff [IB_QPS_ERR] = CMD_2ERR_QPEE, 1694219820Sjeff [IB_QPS_INIT] = CMD_RST2INIT_QPEE, 1695219820Sjeff }, 1696219820Sjeff [IB_QPS_INIT] = { 1697219820Sjeff [IB_QPS_RESET] = CMD_ERR2RST_QPEE, 1698219820Sjeff [IB_QPS_ERR] = CMD_2ERR_QPEE, 1699219820Sjeff [IB_QPS_INIT] = CMD_INIT2INIT_QPEE, 1700219820Sjeff [IB_QPS_RTR] = CMD_INIT2RTR_QPEE, 1701219820Sjeff }, 1702219820Sjeff [IB_QPS_RTR] = { 1703219820Sjeff [IB_QPS_RESET] = CMD_ERR2RST_QPEE, 1704219820Sjeff [IB_QPS_ERR] = CMD_2ERR_QPEE, 1705219820Sjeff [IB_QPS_RTS] = CMD_RTR2RTS_QPEE, 1706219820Sjeff }, 1707219820Sjeff [IB_QPS_RTS] = { 1708219820Sjeff [IB_QPS_RESET] = CMD_ERR2RST_QPEE, 1709219820Sjeff [IB_QPS_ERR] = CMD_2ERR_QPEE, 1710219820Sjeff [IB_QPS_RTS] = CMD_RTS2RTS_QPEE, 1711219820Sjeff [IB_QPS_SQD] = CMD_RTS2SQD_QPEE, 1712219820Sjeff }, 1713219820Sjeff [IB_QPS_SQD] = { 1714219820Sjeff [IB_QPS_RESET] = CMD_ERR2RST_QPEE, 1715219820Sjeff [IB_QPS_ERR] = CMD_2ERR_QPEE, 1716219820Sjeff [IB_QPS_RTS] = CMD_SQD2RTS_QPEE, 1717219820Sjeff [IB_QPS_SQD] = CMD_SQD2SQD_QPEE, 1718219820Sjeff }, 1719219820Sjeff [IB_QPS_SQE] = { 1720219820Sjeff [IB_QPS_RESET] = CMD_ERR2RST_QPEE, 1721219820Sjeff [IB_QPS_ERR] = CMD_2ERR_QPEE, 1722219820Sjeff [IB_QPS_RTS] = CMD_SQERR2RTS_QPEE, 1723219820Sjeff }, 1724219820Sjeff [IB_QPS_ERR] = { 1725219820Sjeff [IB_QPS_RESET] = CMD_ERR2RST_QPEE, 1726219820Sjeff [IB_QPS_ERR] = CMD_2ERR_QPEE, 1727219820Sjeff } 1728219820Sjeff }; 1729219820Sjeff 1730219820Sjeff u8 op_mod = 0; 1731219820Sjeff int my_mailbox = 0; 1732219820Sjeff int err; 1733219820Sjeff 1734219820Sjeff if (op[cur][next] == CMD_ERR2RST_QPEE) { 1735219820Sjeff op_mod = 3; /* don't write outbox, any->reset */ 1736219820Sjeff 1737219820Sjeff /* For debugging */ 1738219820Sjeff if (!mailbox) { 1739219820Sjeff mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1740219820Sjeff if (!IS_ERR(mailbox)) { 1741219820Sjeff my_mailbox = 1; 1742219820Sjeff op_mod = 2; /* write outbox, any->reset */ 1743219820Sjeff } else 1744219820Sjeff mailbox = NULL; 1745219820Sjeff } 1746219820Sjeff 1747219820Sjeff err = mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, 1748219820Sjeff (!!is_ee << 24) | num, op_mod, 1749219820Sjeff op[cur][next], CMD_TIME_CLASS_C, status); 1750219820Sjeff 1751219820Sjeff if (0 && mailbox) { 1752219820Sjeff int i; 1753219820Sjeff mthca_dbg(dev, "Dumping QP context:\n"); 1754219820Sjeff printk(" %08x\n", be32_to_cpup(mailbox->buf)); 1755219820Sjeff for (i = 0; i < 0x100 / 4; ++i) { 1756219820Sjeff if (i % 8 == 0) 1757219820Sjeff printk("[%02x] ", i * 4); 1758219820Sjeff printk(" %08x", 1759219820Sjeff be32_to_cpu(((__be32 *) mailbox->buf)[i + 2])); 1760219820Sjeff if ((i + 1) % 8 == 0) 1761219820Sjeff printk("\n"); 1762219820Sjeff } 1763219820Sjeff } 1764219820Sjeff 1765219820Sjeff if (my_mailbox) 1766219820Sjeff mthca_free_mailbox(dev, mailbox); 1767219820Sjeff } else { 1768219820Sjeff if (0) { 1769219820Sjeff int i; 1770219820Sjeff mthca_dbg(dev, "Dumping QP context:\n"); 1771219820Sjeff printk(" opt param mask: %08x\n", be32_to_cpup(mailbox->buf)); 1772219820Sjeff for (i = 0; i < 0x100 / 4; ++i) { 1773219820Sjeff if (i % 8 == 0) 1774219820Sjeff printk(" [%02x] ", i * 4); 1775219820Sjeff printk(" %08x", 1776219820Sjeff be32_to_cpu(((__be32 *) mailbox->buf)[i + 2])); 1777219820Sjeff if ((i + 1) % 8 == 0) 1778219820Sjeff printk("\n"); 1779219820Sjeff } 1780219820Sjeff } 1781219820Sjeff 1782219820Sjeff err = mthca_cmd(dev, mailbox->dma, optmask | (!!is_ee << 24) | num, 1783219820Sjeff op_mod, op[cur][next], CMD_TIME_CLASS_C, status); 1784219820Sjeff } 1785219820Sjeff 1786219820Sjeff return err; 1787219820Sjeff} 1788219820Sjeff 1789219820Sjeffint mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee, 1790219820Sjeff struct mthca_mailbox *mailbox, u8 *status) 1791219820Sjeff{ 1792219820Sjeff return mthca_cmd_box(dev, 0, mailbox->dma, (!!is_ee << 24) | num, 0, 1793219820Sjeff CMD_QUERY_QPEE, CMD_TIME_CLASS_A, status); 1794219820Sjeff} 1795219820Sjeff 1796219820Sjeffint mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn, 1797219820Sjeff u8 *status) 1798219820Sjeff{ 1799219820Sjeff u8 op_mod; 1800219820Sjeff 1801219820Sjeff switch (type) { 1802219820Sjeff case IB_QPT_SMI: 1803219820Sjeff op_mod = 0; 1804219820Sjeff break; 1805219820Sjeff case IB_QPT_GSI: 1806219820Sjeff op_mod = 1; 1807219820Sjeff break; 1808219820Sjeff case IB_QPT_RAW_IPV6: 1809219820Sjeff op_mod = 2; 1810219820Sjeff break; 1811219820Sjeff case IB_QPT_RAW_ETY: 1812219820Sjeff op_mod = 3; 1813219820Sjeff break; 1814219820Sjeff default: 1815219820Sjeff return -EINVAL; 1816219820Sjeff } 1817219820Sjeff 1818219820Sjeff return mthca_cmd(dev, 0, qpn, op_mod, CMD_CONF_SPECIAL_QP, 1819219820Sjeff CMD_TIME_CLASS_B, status); 1820219820Sjeff} 1821219820Sjeff 1822219820Sjeffint mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey, 1823219820Sjeff int port, struct ib_wc *in_wc, struct ib_grh *in_grh, 1824219820Sjeff void *in_mad, void *response_mad, u8 *status) 1825219820Sjeff{ 1826219820Sjeff struct mthca_mailbox *inmailbox, *outmailbox; 1827219820Sjeff void *inbox; 1828219820Sjeff int err; 1829219820Sjeff u32 in_modifier = port; 1830219820Sjeff u8 op_modifier = 0; 1831219820Sjeff 1832219820Sjeff#define MAD_IFC_BOX_SIZE 0x400 1833219820Sjeff#define MAD_IFC_MY_QPN_OFFSET 0x100 1834219820Sjeff#define MAD_IFC_RQPN_OFFSET 0x108 1835219820Sjeff#define MAD_IFC_SL_OFFSET 0x10c 1836219820Sjeff#define MAD_IFC_G_PATH_OFFSET 0x10d 1837219820Sjeff#define MAD_IFC_RLID_OFFSET 0x10e 1838219820Sjeff#define MAD_IFC_PKEY_OFFSET 0x112 1839219820Sjeff#define MAD_IFC_GRH_OFFSET 0x140 1840219820Sjeff 1841219820Sjeff inmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1842219820Sjeff if (IS_ERR(inmailbox)) 1843219820Sjeff return PTR_ERR(inmailbox); 1844219820Sjeff inbox = inmailbox->buf; 1845219820Sjeff 1846219820Sjeff outmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1847219820Sjeff if (IS_ERR(outmailbox)) { 1848219820Sjeff mthca_free_mailbox(dev, inmailbox); 1849219820Sjeff return PTR_ERR(outmailbox); 1850219820Sjeff } 1851219820Sjeff 1852219820Sjeff memcpy(inbox, in_mad, 256); 1853219820Sjeff 1854219820Sjeff /* 1855219820Sjeff * Key check traps can't be generated unless we have in_wc to 1856219820Sjeff * tell us where to send the trap. 1857219820Sjeff */ 1858219820Sjeff if (ignore_mkey || !in_wc) 1859219820Sjeff op_modifier |= 0x1; 1860219820Sjeff if (ignore_bkey || !in_wc) 1861219820Sjeff op_modifier |= 0x2; 1862219820Sjeff 1863219820Sjeff if (in_wc) { 1864219820Sjeff u8 val; 1865219820Sjeff 1866219820Sjeff memset(inbox + 256, 0, 256); 1867219820Sjeff 1868219820Sjeff MTHCA_PUT(inbox, in_wc->qp->qp_num, MAD_IFC_MY_QPN_OFFSET); 1869219820Sjeff MTHCA_PUT(inbox, in_wc->src_qp, MAD_IFC_RQPN_OFFSET); 1870219820Sjeff 1871219820Sjeff val = in_wc->sl << 4; 1872219820Sjeff MTHCA_PUT(inbox, val, MAD_IFC_SL_OFFSET); 1873219820Sjeff 1874219820Sjeff val = in_wc->dlid_path_bits | 1875219820Sjeff (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0); 1876219820Sjeff MTHCA_PUT(inbox, val, MAD_IFC_G_PATH_OFFSET); 1877219820Sjeff 1878219820Sjeff MTHCA_PUT(inbox, in_wc->slid, MAD_IFC_RLID_OFFSET); 1879219820Sjeff MTHCA_PUT(inbox, in_wc->pkey_index, MAD_IFC_PKEY_OFFSET); 1880219820Sjeff 1881219820Sjeff if (in_grh) 1882219820Sjeff memcpy(inbox + MAD_IFC_GRH_OFFSET, in_grh, 40); 1883219820Sjeff 1884219820Sjeff op_modifier |= 0x4; 1885219820Sjeff 1886219820Sjeff in_modifier |= in_wc->slid << 16; 1887219820Sjeff } 1888219820Sjeff 1889219820Sjeff err = mthca_cmd_box(dev, inmailbox->dma, outmailbox->dma, 1890219820Sjeff in_modifier, op_modifier, 1891219820Sjeff CMD_MAD_IFC, CMD_TIME_CLASS_C, status); 1892219820Sjeff 1893219820Sjeff if (!err && !*status) 1894219820Sjeff memcpy(response_mad, outmailbox->buf, 256); 1895219820Sjeff 1896219820Sjeff mthca_free_mailbox(dev, inmailbox); 1897219820Sjeff mthca_free_mailbox(dev, outmailbox); 1898219820Sjeff return err; 1899219820Sjeff} 1900219820Sjeff 1901219820Sjeffint mthca_READ_MGM(struct mthca_dev *dev, int index, 1902219820Sjeff struct mthca_mailbox *mailbox, u8 *status) 1903219820Sjeff{ 1904219820Sjeff return mthca_cmd_box(dev, 0, mailbox->dma, index, 0, 1905219820Sjeff CMD_READ_MGM, CMD_TIME_CLASS_A, status); 1906219820Sjeff} 1907219820Sjeff 1908219820Sjeffint mthca_WRITE_MGM(struct mthca_dev *dev, int index, 1909219820Sjeff struct mthca_mailbox *mailbox, u8 *status) 1910219820Sjeff{ 1911219820Sjeff return mthca_cmd(dev, mailbox->dma, index, 0, CMD_WRITE_MGM, 1912219820Sjeff CMD_TIME_CLASS_A, status); 1913219820Sjeff} 1914219820Sjeff 1915219820Sjeffint mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1916219820Sjeff u16 *hash, u8 *status) 1917219820Sjeff{ 1918219820Sjeff u64 imm; 1919219820Sjeff int err; 1920219820Sjeff 1921219820Sjeff err = mthca_cmd_imm(dev, mailbox->dma, &imm, 0, 0, CMD_MGID_HASH, 1922219820Sjeff CMD_TIME_CLASS_A, status); 1923219820Sjeff 1924219820Sjeff *hash = imm; 1925219820Sjeff return err; 1926219820Sjeff} 1927219820Sjeff 1928219820Sjeffint mthca_NOP(struct mthca_dev *dev, u8 *status) 1929219820Sjeff{ 1930219820Sjeff return mthca_cmd(dev, 0, 0x1f, 0, CMD_NOP, msecs_to_jiffies(100), status); 1931219820Sjeff} 1932