1220297Sadrian/*- 2220297Sadrian * Copyright (c) 2010 Aleksandr Rybalko. 3220297Sadrian * All rights reserved. 4220297Sadrian * 5220297Sadrian * Redistribution and use in source and binary forms, with or without 6220297Sadrian * modification, are permitted provided that the following conditions 7220297Sadrian * are met: 8220297Sadrian * 1. Redistributions of source code must retain the above copyright 9220297Sadrian * notice, this list of conditions and the following disclaimer. 10220297Sadrian * 2. Redistributions in binary form must reproduce the above copyright 11220297Sadrian * notice, this list of conditions and the following disclaimer in the 12220297Sadrian * documentation and/or other materials provided with the distribution. 13220297Sadrian * 14220297Sadrian * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15220297Sadrian * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16220297Sadrian * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17220297Sadrian * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18220297Sadrian * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19220297Sadrian * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20220297Sadrian * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21220297Sadrian * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22220297Sadrian * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23220297Sadrian * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24220297Sadrian * SUCH DAMAGE. 25220297Sadrian * 26220297Sadrian * $FreeBSD$ 27220297Sadrian */ 28220297Sadrian 29220297Sadrian#ifndef _RT305XREG_H_ 30220297Sadrian#define _RT305XREG_H_ 31220297Sadrian 32220297Sadrian/* XXX: must move to config */ 33220297Sadrian#define RT305X 1 34220297Sadrian#define RT305XF 1 35220297Sadrian#define RT3052F 1 36220297Sadrian#define __U_BOOT__ 1 37220297Sadrian/* XXX: must move to config */ 38220297Sadrian 39220297Sadrian#ifdef RT3052F 40220297Sadrian#define PLATFORM_COUNTER_FREQ (384 * 1000 * 1000) 41220297Sadrian#endif 42220297Sadrian#ifdef RT3050F 43220297Sadrian#define PLATFORM_COUNTER_FREQ (320 * 1000 * 1000) 44220297Sadrian#endif 45220297Sadrian#ifndef PLATFORM_COUNTER_FREQ 46220297Sadrian#error "Nor RT3052F nor RT3050F defined" 47220297Sadrian#endif 48220297Sadrian 49220297Sadrian#define SYSTEM_CLOCK (PLATFORM_COUNTER_FREQ/3) 50220297Sadrian 51220297Sadrian 52220297Sadrian#define SDRAM_BASE 0x00000000 53220297Sadrian#define SDRAM_END 0x03FFFFFF 54220297Sadrian 55220297Sadrian#define SYSCTL_BASE 0x10000000 56220297Sadrian#define SYSCTL_END 0x100000FF 57220297Sadrian#define TIMER_BASE 0x10000100 58220297Sadrian#define TIMER_END 0x100001FF 59220297Sadrian#define INTCTL_BASE 0x10000200 60220297Sadrian#define INTCTL_END 0x100002FF 61220297Sadrian#define MEMCTRL_BASE 0x10000300 62220297Sadrian#define MEMCTRL_END 0x100003FF /* SDRAM & Flash/SRAM */ 63220297Sadrian#define PCM_BASE 0x10000400 64220297Sadrian#define PCM_END 0x100004FF 65220297Sadrian#define UART_BASE 0x10000500 66220297Sadrian#define UART_END 0x100005FF 67220297Sadrian#define PIO_BASE 0x10000600 68220297Sadrian#define PIO_END 0x100006FF 69220297Sadrian#define GDMA_BASE 0x10000700 70220297Sadrian#define GDMA_END 0x100007FF /* Generic DMA */ 71220297Sadrian#define NANDFC_BASE 0x10000800 72220297Sadrian#define NANDFC_END 0x100008FF /* NAND Flash Controller */ 73220297Sadrian#define I2C_BASE 0x10000900 74220297Sadrian#define I2C_END 0x100009FF 75220297Sadrian#define I2S_BASE 0x10000A00 76220297Sadrian#define I2S_END 0x10000AFF 77220297Sadrian#define SPI_BASE 0x10000B00 78220297Sadrian#define SPI_END 0x10000BFF 79220297Sadrian#define UARTLITE_BASE 0x10000C00 80220297Sadrian#define UARTLITE_END 0x10000CFF 81220297Sadrian 82220297Sadrian#define FRENG_BASE 0x10100000 83220297Sadrian#define FRENG_END 0x1010FFFF /* Frame Engine */ 84220297Sadrian#define ETHSW_BASE 0x10110000 85220297Sadrian#define ETHSW_END 0x10117FFF /* Ethernet Switch */ 86220297Sadrian#define ROM_BASE 0x10118000 87220297Sadrian#define ROM_END 0x10119FFF 88220297Sadrian#define WLAN_BASE 0x10180000 89220297Sadrian#define WLAN_END 0x101BFFFF /* 802.11n MAC/BBP */ 90220297Sadrian#define USB_OTG_BASE 0x101C0000 91220297Sadrian#define USB_OTG_END 0x101FFFFF 92220297Sadrian#define EMEM_BASE 0x1B000000 93220297Sadrian#define EMEM_END 0x1BFFFFFF /* External SRAM/Flash */ 94220297Sadrian#define FLASH_BASE 0x1F000000 95220297Sadrian#define FLASH_END 0x1FFFFFFF /* Flash window */ 96220297Sadrian 97220297Sadrian#define OBIO_MEM_BASE SYSCTL_BASE 98220297Sadrian#define OBIO_MEM_START OBIO_MEM_BASE 99220297Sadrian#define OBIO_MEM_END FLASH_END 100220297Sadrian 101220297Sadrian 102220297Sadrian 103220297Sadrian/* System Control */ 104220297Sadrian#define SYSCTL_CHIPID0_3 0x00 /* 'R''T''3''0' */ 105220297Sadrian#define SYSCTL_CHIPID4_7 0x04 /* '5''2'' '' ' */ 106220297Sadrian#define SYSCTL_SYSCFG 0x10 107220297Sadrian#define SYSCTL_SYSCFG_INIC_EE_SDRAM (1<<29) 108220297Sadrian#define SYSCTL_SYSCFG_INIC_8MB_SDRAM (1<<28) 109220297Sadrian#define SYSCTL_SYSCFG_GE0_MODE_MASK 0x03000000 110220297Sadrian#define SYSCTL_SYSCFG_GE0_MODE_SHIFT 24 111220297Sadrian#define SYSCTL_SYSCFG_GE0_MODE_RGMII 0 /* RGMII Mode */ 112220297Sadrian#define SYSCTL_SYSCFG_GE0_MODE_MII 1 /* MII Mode */ 113220297Sadrian#define SYSCTL_SYSCFG_GE0_MODE_REV_MII 2 /*Reversed MII Mode*/ 114220297Sadrian#define SYSCTL_SYSCFG_BOOT_ADDR_1F00 (1<<22) 115220297Sadrian#define SYSCTL_SYSCFG_BYPASS_PLL (1<<21) 116220297Sadrian#define SYSCTL_SYSCFG_BIG_ENDIAN (1<<20) 117220297Sadrian#define SYSCTL_SYSCFG_CPU_CLK_SEL_384MHZ (1<<18) 118220297Sadrian#define SYSCTL_SYSCFG_BOOT_FROM_MASK 0x00030000 119220297Sadrian#define SYSCTL_SYSCFG_BOOT_FROM_SHIFT 16 120220297Sadrian#define SYSCTL_SYSCFG_BOOT_FROM_FLASH16 0 121220297Sadrian#define SYSCTL_SYSCFG_BOOT_FROM_FLASH8 1 122220297Sadrian#define SYSCTL_SYSCFG_BOOT_FROM_NANDFLASH 2 123220297Sadrian#define SYSCTL_SYSCFG_BOOT_FROM_ROM 3 124220297Sadrian#define SYSCTL_SYSCFG_TEST_CODE_MASK 0x0000ff00 125220297Sadrian#define SYSCTL_SYSCFG_TEST_CODE_SHIFT 8 126220297Sadrian#define SYSCTL_SYSCFG_SRAM_CS_MODE_MASK 0x0000000c 127220297Sadrian#define SYSCTL_SYSCFG_SRAM_CS_MODE_SHIFT 2 128220297Sadrian#define SYSCTL_SYSCFG_SRAM_CS_MODE_SRAM 0 129220297Sadrian#define SYSCTL_SYSCFG_SRAM_CS_MODE_WDOG_RST 1 130220297Sadrian#define SYSCTL_SYSCFG_SRAM_CS_MODE_BT_COEX 2 131220297Sadrian#define SYSCTL_SYSCFG_SDRAM_CLK_DRV (1<<0) /* 8mA/12mA */ 132220297Sadrian 133220297Sadrian#define SYSCTL_TESTSTAT 0x18 134220297Sadrian#define SYSCTL_TESTSTAT2 0x1C 135220297Sadrian 136220297Sadrian#define SYSCTL_CLKCFG0 0x2C 137220297Sadrian#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_MASK 0xc0000000 138220297Sadrian#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_SHIFT 30 139220297Sadrian#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_ZERO_DELAY 0 140220297Sadrian#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_1NS_DELAY 1 141220297Sadrian#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_2NS_DELAY 2 142220297Sadrian#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_3NS_DELAY 3 143220297Sadrian 144220297Sadrian#define SYSCTL_CLKCFG1 0x30 145220297Sadrian#define SYSCTL_CLKCFG1_PBUS_DIV_CLK_BY2 (1<<30) 146220297Sadrian#define SYSCTL_CLKCFG1_OTG_CLK_EN (1<<18) 147220297Sadrian#define SYSCTL_CLKCFG1_I2S_CLK_EN (1<<15) 148220297Sadrian#define SYSCTL_CLKCFG1_I2S_CLK_SEL_EXT (1<<14) 149220297Sadrian#define SYSCTL_CLKCFG1_I2S_CLK_DIV_MASK 0x00003f00 150220297Sadrian#define SYSCTL_CLKCFG1_I2S_CLK_DIV_SHIFT 8 151220297Sadrian#define SYSCTL_CLKCFG1_PCM_CLK_EN (1<<7) 152220297Sadrian#define SYSCTL_CLKCFG1_PCM_CLK_SEL_EXT (1<<6) 153220297Sadrian#define SYSCTL_CLKCFG1_PCM_CLK_DIV_MASK 0x0000003f 154220297Sadrian#define SYSCTL_CLKCFG1_PCM_CLK_DIV_SHIFT 0 155220297Sadrian 156220297Sadrian#define SYSCTL_RSTCTRL 0x34 157220297Sadrian#define SYSCTL_RSTCTRL_ETHSW (1<<23) 158220297Sadrian#define SYSCTL_RSTCTRL_OTG (1<<22) 159220297Sadrian#define SYSCTL_RSTCTRL_FRENG (1<<21) 160220297Sadrian#define SYSCTL_RSTCTRL_WLAN (1<<20) 161220297Sadrian#define SYSCTL_RSTCTRL_UARTL (1<<19) 162220297Sadrian#define SYSCTL_RSTCTRL_SPI (1<<18) 163220297Sadrian#define SYSCTL_RSTCTRL_I2S (1<<17) 164220297Sadrian#define SYSCTL_RSTCTRL_I2C (1<<16) 165220297Sadrian#define SYSCTL_RSTCTRL_DMA (1<<14) 166220297Sadrian#define SYSCTL_RSTCTRL_PIO (1<<13) 167220297Sadrian#define SYSCTL_RSTCTRL_UART (1<<12) 168220297Sadrian#define SYSCTL_RSTCTRL_PCM (1<<11) 169220297Sadrian#define SYSCTL_RSTCTRL_MC (1<<10) 170220297Sadrian#define SYSCTL_RSTCTRL_INTC (1<<9) 171220297Sadrian#define SYSCTL_RSTCTRL_TIMER (1<<8) 172220297Sadrian#define SYSCTL_RSTCTRL_SYS (1<<0) 173220297Sadrian 174220297Sadrian#define SYSCTL_RSTSTAT 0x38 175220297Sadrian#define SYSCTL_RSTSTAT_SWCPURST (1<<3) 176220297Sadrian#define SYSCTL_RSTSTAT_SWSYSRST (1<<2) 177220297Sadrian#define SYSCTL_RSTSTAT_WDRST (1<<1) 178220297Sadrian 179220297Sadrian#define SYSCTL_GPIOMODE 0x60 180220297Sadrian#define SYSCTL_GPIOMODE_RGMII_GPIO_MODE (1<<9) 181220297Sadrian#define SYSCTL_GPIOMODE_SDRAM_GPIO_MODE (1<<8) 182220297Sadrian#define SYSCTL_GPIOMODE_MDIO_GPIO_MODE (1<<7) 183220297Sadrian#define SYSCTL_GPIOMODE_JTAG_GPIO_MODE (1<<6) 184220297Sadrian#define SYSCTL_GPIOMODE_UARTL_GPIO_MODE (1<<5) 185220297Sadrian#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_UARTF (0<<2) 186220297Sadrian#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_PCM_UARTF (1<<2) 187220297Sadrian#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_PCM_I2S (2<<2) 188220297Sadrian#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_I2S_UARTF (3<<2) 189220297Sadrian#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_PCM_GPIO (4<<2) 190220297Sadrian#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO_UARTF (5<<2) 191220297Sadrian#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO_I2S (6<<2) 192220297Sadrian#define SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO (7<<2) 193220297Sadrian#define SYSCTL_GPIOMODE_SPI_GPIO_MODE (1<<1) 194220297Sadrian#define SYSCTL_GPIOMODE_I2C_GPIO_MODE (1<<0) 195220297Sadrian 196220297Sadrian#define SYSCTL_MEMO0 0x68 197220297Sadrian#define SYSCTL_MEMO1 0x6C 198220297Sadrian 199220297Sadrian/* Timer */ 200220297Sadrian#define TIMER_TMRSTAT 0x00 201220297Sadrian#define TIMER_TMRSTAT_TMR1RST (1<<5) 202220297Sadrian#define TIMER_TMRSTAT_TMR0RST (1<<4) 203220297Sadrian#define TIMER_TMRSTAT_TMR1INT (1<<1) 204220297Sadrian#define TIMER_TMRSTAT_TMR0INT (1<<0) 205220297Sadrian#define TIMER_TMR0LOAD 0x10 206220297Sadrian#define TIMER_TMR0VAL 0x14 207220297Sadrian#define TIMER_TMR0CTL 0x18 208220297Sadrian#define TIMER_TMR1LOAD 0x20 209220297Sadrian#define TIMER_TMR1VAL 0x24 210220297Sadrian#define TIMER_TMR1CTL 0x28 211220297Sadrian 212220297Sadrian#define TIMER_TMRLOAD_TMR0LOAD_MASK 0xffff 213220297Sadrian 214220297Sadrian#define TIMER_TMRVAL_TMR0VAL_MASK 0xffff 215220297Sadrian 216220297Sadrian#define TIMER_TMRCTL_ENABLE (1<<7) 217220297Sadrian#define TIMER_TMRCTL_MODE_MASK 0x00000030 218220297Sadrian#define TIMER_TMRCTL_MODE_SHIFT 4 219220297Sadrian#define TIMER_TMRCTL_MODE_FREE 0 220220297Sadrian#define TIMER_TMRCTL_MODE_PERIODIC 1 221220297Sadrian#define TIMER_TMRCTL_MODE_TIMOUT 2 222220297Sadrian#define TIMER_TMRCTL_MODE_TIMOUT3 3 223220297Sadrian#define TIMER_TMRCTL_PRESCALE_MASK 0x0000000f 224220297Sadrian#define TIMER_TMRCTL_PRESCALE_SHIFT 0 225220297Sadrian#define TIMER_TMRCTL_PRESCALE_NONE 0 226220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_4 1 227220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_8 2 228220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_16 3 229220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_32 4 230220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_64 5 231220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_128 6 232220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_256 7 233220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_512 8 234220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_1K 9 235220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_2K 10 236220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_4K 11 237220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_8K 12 238220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_16K 13 239220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_32K 14 240220297Sadrian#define TIMER_TMRCTL_PRESCALE_BY_64K 15 241220297Sadrian 242220297Sadrian/* Interrupt Controller */ 243220297Sadrian#define IC_IRQ0STAT 0x00 244220297Sadrian#define IC_IRQ1STAT 0x04 245220297Sadrian#define IC_INTTYPE 0x20 246220297Sadrian#define IC_INTRAW 0x30 247220297Sadrian#define IC_INT_ENA 0x34 248220297Sadrian#define IC_INT_DIS 0x38 249220297Sadrian 250220297Sadrian#define IC_OTG 18 251220297Sadrian#define IC_ETHSW 17 252220297Sadrian#define IC_UARTLITE 12 253220297Sadrian#define IC_I2S 10 254220297Sadrian#define IC_PERFC 9 255220297Sadrian#define IC_NAND 8 256220297Sadrian#define IC_DMA 7 257220297Sadrian#define IC_PIO 6 258220297Sadrian#define IC_UART 5 259220297Sadrian#define IC_PCM 4 260220297Sadrian#define IC_ILL_ACCESS 3 261220297Sadrian#define IC_WDTIMER 2 262220297Sadrian#define IC_TIMER0 1 263220297Sadrian#define IC_SYSCTL 0 264220297Sadrian 265220297Sadrian#define IC_LINE_GLOBAL (1<<31) /* Only for DIS/ENA regs */ 266220297Sadrian#define IC_LINE_OTG (1<<18) 267220297Sadrian#define IC_LINE_ETHSW (1<<17) 268220297Sadrian#define IC_LINE_UARTLITE (1<<12) 269220297Sadrian#define IC_LINE_I2S (1<<10) 270220297Sadrian#define IC_LINE_PERFC (1<<9) 271220297Sadrian#define IC_LINE_NAND (1<<8) 272220297Sadrian#define IC_LINE_DMA (1<<7) 273220297Sadrian#define IC_LINE_PIO (1<<6) 274220297Sadrian#define IC_LINE_UART (1<<5) 275220297Sadrian#define IC_LINE_PCM (1<<4) 276220297Sadrian#define IC_LINE_ILL_ACCESS (1<<3) 277220297Sadrian#define IC_LINE_WDTIMER (1<<2) 278220297Sadrian#define IC_LINE_TIMER0 (1<<1) 279220297Sadrian#define IC_LINE_SYSCTL (1<<0) 280220297Sadrian 281220297Sadrian#define IC_INT_MASK 0x000617ff 282220297Sadrian 283220297Sadrian/* GPIO */ 284220297Sadrian 285220297Sadrian#define GPIO23_00_INT 0x00 /* Programmed I/O Int Status */ 286220297Sadrian#define GPIO23_00_EDGE 0x04 /* Programmed I/O Edge Status */ 287220297Sadrian#define GPIO23_00_RENA 0x08 /* Programmed I/O Int on Rising */ 288220297Sadrian#define GPIO23_00_FENA 0x0C /* Programmed I/O Int on Falling */ 289220297Sadrian#define GPIO23_00_DATA 0x20 /* Programmed I/O Data */ 290220297Sadrian#define GPIO23_00_DIR 0x24 /* Programmed I/O Direction */ 291220297Sadrian#define GPIO23_00_POL 0x28 /* Programmed I/O Pin Polarity */ 292220297Sadrian#define GPIO23_00_SET 0x2C /* Set PIO Data Bit */ 293220297Sadrian#define GPIO23_00_RESET 0x30 /* Clear PIO Data bit */ 294220297Sadrian#define GPIO23_00_TOG 0x34 /* Toggle PIO Data bit */ 295220297Sadrian 296220297Sadrian#define GPIO39_24_INT 0x38 297220297Sadrian#define GPIO39_24_EDGE 0x3c 298220297Sadrian#define GPIO39_24_RENA 0x40 299220297Sadrian#define GPIO39_24_FENA 0x44 300220297Sadrian#define GPIO39_24_DATA 0x48 301220297Sadrian#define GPIO39_24_DIR 0x4c 302220297Sadrian#define GPIO39_24_POL 0x50 303220297Sadrian#define GPIO39_24_SET 0x54 304220297Sadrian#define GPIO39_24_RESET 0x58 305220297Sadrian#define GPIO39_24_TOG 0x5c 306220297Sadrian 307220297Sadrian#define GPIO51_40_INT 0x60 308220297Sadrian#define GPIO51_40_EDGE 0x64 309220297Sadrian#define GPIO51_40_RENA 0x68 310220297Sadrian#define GPIO51_40_FENA 0x6C 311220297Sadrian#define GPIO51_40_DATA 0x70 312220297Sadrian#define GPIO51_40_DIR 0x74 313220297Sadrian#define GPIO51_40_POL 0x78 314220297Sadrian#define GPIO51_40_SET 0x7C 315220297Sadrian#define GPIO51_40_RESET 0x80 316220297Sadrian#define GPIO51_40_TOG 0x84 317220297Sadrian 318220297Sadrian 319220297Sadrian 320220297Sadrian 321220297Sadrian#define GDMA_CHANNEL_REQ0 0 322220297Sadrian#define GDMA_CHANNEL_REQ1 1 /* (NAND-flash) */ 323220297Sadrian#define GDMA_CHANNEL_REQ2 2 /* (I2S) */ 324220297Sadrian#define GDMA_CHANNEL_REQ3 3 /* (PCM0-RX) */ 325220297Sadrian#define GDMA_CHANNEL_REQ4 4 /* (PCM1-RX) */ 326220297Sadrian#define GDMA_CHANNEL_REQ5 5 /* (PCM0-TX) */ 327220297Sadrian#define GDMA_CHANNEL_REQ6 6 /* (PCM1-TX) */ 328220297Sadrian#define GDMA_CHANNEL_REQ7 7 329220297Sadrian#define GDMA_CHANNEL_MEM 8 330220297Sadrian 331220297Sadrian/* Generic DMA Controller */ 332220297Sadrian/* GDMA Channel n Source Address */ 333220297Sadrian#define GDMASA(n) (0x00 + 0x10*n) 334220297Sadrian /* GDMA Channel n Destination Address */ 335220297Sadrian#define GDMADA(n) (0x04 + 0x10*n) 336220297Sadrian /* GDMA Channel n Control Register 0 */ 337220297Sadrian#define GDMACT0(n) (0x08 + 0x10*n) 338220297Sadrian 339220297Sadrian#define GDMACT0_TR_COUNT_MASK 0x0fff0000 340220297Sadrian#define GDMACT0_TR_COUNT_SHIFT 16 341220297Sadrian#define GDMACT0_SRC_CHAN_SHIFT 12 342220297Sadrian#define GDMACT0_SRC_CHAN_MASK 0x0000f000 343220297Sadrian#define GDMACT0_DST_CHAN_SHIFT 8 344220297Sadrian#define GDMACT0_DST_CHAN_MASK 0x00000f00 345220297Sadrian#define GDMACT0_SRC_BURST_MODE (1<<7) 346220297Sadrian#define GDMACT0_DST_BURST_MODE (1<<6) 347220297Sadrian#define GDMACT0_BURST_SIZE_SHIFT 3 348220297Sadrian#define GDMACT0_BURST_SIZE_MASK 0x00000038 349220297Sadrian#define GDMACT0_BURST_SIZE_1 0 350220297Sadrian#define GDMACT0_BURST_SIZE_2 1 351220297Sadrian#define GDMACT0_BURST_SIZE_4 2 352220297Sadrian#define GDMACT0_BURST_SIZE_8 3 353220297Sadrian#define GDMACT0_BURST_SIZE_16 4 354220297Sadrian 355220297Sadrian#define GDMACT0_DONE_INT_EN (1<<2) 356220297Sadrian#define GDMACT0_CHAN_EN (1<<1) 357220297Sadrian/* 358220297Sadrian * In software mode, the data transfer will start when the Channel Enable bit 359220297Sadrian * is set. 360220297Sadrian * In hardware mode, the data transfer will start when the DMA Request is 361220297Sadrian * asserted. 362220297Sadrian*/ 363220297Sadrian#define GDMACT0_SWMODE (1<<0) 364220297Sadrian 365220297Sadrian 366220297Sadrian 367220297Sadrian 368220297Sadrian#endif /* _RT305XREG_H_ */ 369