1198160Srrs/*- 2198160Srrs * Copyright (c) 2003-2009 RMI Corporation 3198160Srrs * All rights reserved. 4198160Srrs * 5198160Srrs * Redistribution and use in source and binary forms, with or without 6198160Srrs * modification, are permitted provided that the following conditions 7198160Srrs * are met: 8198160Srrs * 1. Redistributions of source code must retain the above copyright 9198160Srrs * notice, this list of conditions and the following disclaimer. 10198160Srrs * 2. Redistributions in binary form must reproduce the above copyright 11198160Srrs * notice, this list of conditions and the following disclaimer in the 12198160Srrs * documentation and/or other materials provided with the distribution. 13198160Srrs * 3. Neither the name of RMI Corporation, nor the names of its contributors, 14198160Srrs * may be used to endorse or promote products derived from this software 15198160Srrs * without specific prior written permission. 16198160Srrs * 17198160Srrs * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18198160Srrs * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19198160Srrs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20198160Srrs * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21198160Srrs * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22198160Srrs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23198160Srrs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24198160Srrs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25198160Srrs * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26198160Srrs * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27198160Srrs * SUCH DAMAGE. 28198160Srrs * 29211994Sjchandra * RMI_BSD 30211994Sjchandra * $FreeBSD$ 31211994Sjchandra */ 32198160Srrs#ifndef _RMI_IOMAP_H_ 33198160Srrs#define _RMI_IOMAP_H_ 34198160Srrs 35198160Srrs#include <machine/endian.h> 36198956Srrs#define XLR_DEVICE_REGISTER_BASE 0x1EF00000 37198160Srrs#define DEFAULT_XLR_IO_BASE 0xffffffffbef00000ULL 38198160Srrs#define XLR_IO_SIZE 0x1000 39198160Srrs 40198160Srrs#define XLR_IO_BRIDGE_OFFSET 0x00000 41198160Srrs 42198160Srrs#define XLR_IO_DDR2_CHN0_OFFSET 0x01000 43198160Srrs#define XLR_IO_DDR2_CHN1_OFFSET 0x02000 44198160Srrs#define XLR_IO_DDR2_CHN2_OFFSET 0x03000 45198160Srrs#define XLR_IO_DDR2_CHN3_OFFSET 0x04000 46198160Srrs 47198160Srrs#define XLR_IO_RLD2_CHN0_OFFSET 0x05000 48198160Srrs#define XLR_IO_RLD2_CHN1_OFFSET 0x06000 49198160Srrs 50198160Srrs#define XLR_IO_SRAM_OFFSET 0x07000 51198160Srrs 52198160Srrs#define XLR_IO_PIC_OFFSET 0x08000 53198160Srrs#define XLR_IO_PCIX_OFFSET 0x09000 54198160Srrs#define XLR_IO_HT_OFFSET 0x0A000 55198160Srrs 56198160Srrs#define XLR_IO_SECURITY_OFFSET 0x0B000 57198160Srrs 58198160Srrs#define XLR_IO_GMAC_0_OFFSET 0x0C000 59198160Srrs#define XLR_IO_GMAC_1_OFFSET 0x0D000 60198160Srrs#define XLR_IO_GMAC_2_OFFSET 0x0E000 61198160Srrs#define XLR_IO_GMAC_3_OFFSET 0x0F000 62198160Srrs 63198160Srrs#define XLR_IO_SPI4_0_OFFSET 0x10000 64198160Srrs#define XLR_IO_XGMAC_0_OFFSET 0x11000 65198160Srrs#define XLR_IO_SPI4_1_OFFSET 0x12000 66198160Srrs#define XLR_IO_XGMAC_1_OFFSET 0x13000 67198160Srrs 68198160Srrs#define XLR_IO_UART_0_OFFSET 0x14000 69198160Srrs#define XLR_IO_UART_1_OFFSET 0x15000 70198956Srrs#define XLR_UART0ADDR (XLR_IO_UART_0_OFFSET+XLR_DEVICE_REGISTER_BASE) 71198160Srrs 72198956Srrs 73198956Srrs 74198160Srrs#define XLR_IO_I2C_0_OFFSET 0x16000 75198160Srrs#define XLR_IO_I2C_1_OFFSET 0x17000 76198160Srrs 77198160Srrs#define XLR_IO_GPIO_OFFSET 0x18000 78198160Srrs 79198160Srrs#define XLR_IO_FLASH_OFFSET 0x19000 80198160Srrs 81198160Srrs#define XLR_IO_TB_OFFSET 0x1C000 82198160Srrs 83198160Srrs#define XLR_IO_GMAC_4_OFFSET 0x20000 84198160Srrs#define XLR_IO_GMAC_5_OFFSET 0x21000 85198160Srrs#define XLR_IO_GMAC_6_OFFSET 0x22000 86198160Srrs#define XLR_IO_GMAC_7_OFFSET 0x23000 87198160Srrs 88198160Srrs#define XLR_IO_PCIE_0_OFFSET 0x1E000 89198160Srrs#define XLR_IO_PCIE_1_OFFSET 0x1F000 90198160Srrs 91198160Srrs#define XLR_IO_USB_0_OFFSET 0x24000 92198160Srrs#define XLR_IO_USB_1_OFFSET 0x25000 93198160Srrs 94198160Srrs#define XLR_IO_COMP_OFFSET 0x1d000 95198160Srrs 96198160Srrs/* Base Address (Virtual) of the PCI Config address space 97198160Srrs * For now, choose 256M phys in kseg1 = 0xA0000000 + (1<<28) 98198160Srrs * Config space spans 256 (num of buses) * 256 (num functions) * 256 bytes 99198160Srrs * ie 1<<24 = 16M 100198625Srrs */ 101198160Srrs#define DEFAULT_PCI_CONFIG_BASE 0x18000000 102198160Srrs#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000 103198160Srrs#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000 104198160Srrs 105198160Srrstypedef volatile __uint32_t xlr_reg_t; 106198160Srrsextern unsigned long xlr_io_base; 107198160Srrs 108198160Srrs#define xlr_io_mmio(offset) ((xlr_reg_t *)(xlr_io_base+(offset))) 109198160Srrs 110198160Srrs#define xlr_read_reg(base, offset) (__ntohl((base)[(offset)])) 111198160Srrs#define xlr_write_reg(base, offset, value) ((base)[(offset)] = __htonl((value))) 112198160Srrs 113198160Srrsextern void on_chip_init(void); 114198160Srrs 115198625Srrs#endif /* _RMI_IOMAP_H_ */ 116