1211946Sjchandra/*- 2211946Sjchandra * Copyright (c) 2003-2009 RMI Corporation 3211946Sjchandra * All rights reserved. 4211946Sjchandra * 5211946Sjchandra * Redistribution and use in source and binary forms, with or without 6211946Sjchandra * modification, are permitted provided that the following conditions 7211946Sjchandra * are met: 8211946Sjchandra * 1. Redistributions of source code must retain the above copyright 9211946Sjchandra * notice, this list of conditions and the following disclaimer. 10211946Sjchandra * 2. Redistributions in binary form must reproduce the above copyright 11211946Sjchandra * notice, this list of conditions and the following disclaimer in the 12211946Sjchandra * documentation and/or other materials provided with the distribution. 13211946Sjchandra * 3. Neither the name of RMI Corporation, nor the names of its contributors, 14211946Sjchandra * may be used to endorse or promote products derived from this software 15211946Sjchandra * without specific prior written permission. 16211946Sjchandra * 17211946Sjchandra * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18211946Sjchandra * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19211946Sjchandra * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20211946Sjchandra * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21211946Sjchandra * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22211946Sjchandra * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23211946Sjchandra * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24211946Sjchandra * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25211946Sjchandra * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26211946Sjchandra * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27211946Sjchandra * SUCH DAMAGE. 28211946Sjchandra * $FreeBSD$ 29211946Sjchandra * 30211946Sjchandra * RMI_BSD 31211946Sjchandra */ 32211946Sjchandra 33211946Sjchandra/* #define MAC_SPLIT_MODE */ 34211946Sjchandra 35211946Sjchandra#define MAC_SPACING 0x400 36211946Sjchandra#define XGMAC_SPACING 0x400 37211946Sjchandra 38211946Sjchandra/* PE-MCXMAC register and bit field definitions */ 39211946Sjchandra#define R_MAC_CONFIG_1 0x00 40211946Sjchandra#define O_MAC_CONFIG_1__srst 31 41211946Sjchandra#define O_MAC_CONFIG_1__simr 30 42211946Sjchandra#define O_MAC_CONFIG_1__hrrmc 18 43211946Sjchandra#define W_MAC_CONFIG_1__hrtmc 2 44211946Sjchandra#define O_MAC_CONFIG_1__hrrfn 16 45211946Sjchandra#define W_MAC_CONFIG_1__hrtfn 2 46211946Sjchandra#define O_MAC_CONFIG_1__intlb 8 47211946Sjchandra#define O_MAC_CONFIG_1__rxfc 5 48211946Sjchandra#define O_MAC_CONFIG_1__txfc 4 49211946Sjchandra#define O_MAC_CONFIG_1__srxen 3 50211946Sjchandra#define O_MAC_CONFIG_1__rxen 2 51211946Sjchandra#define O_MAC_CONFIG_1__stxen 1 52211946Sjchandra#define O_MAC_CONFIG_1__txen 0 53211946Sjchandra#define R_MAC_CONFIG_2 0x01 54211946Sjchandra#define O_MAC_CONFIG_2__prlen 12 55211946Sjchandra#define W_MAC_CONFIG_2__prlen 4 56211946Sjchandra#define O_MAC_CONFIG_2__speed 8 57211946Sjchandra#define W_MAC_CONFIG_2__speed 2 58211946Sjchandra#define O_MAC_CONFIG_2__hugen 5 59211946Sjchandra#define O_MAC_CONFIG_2__flchk 4 60211946Sjchandra#define O_MAC_CONFIG_2__crce 1 61211946Sjchandra#define O_MAC_CONFIG_2__fulld 0 62211946Sjchandra#define R_IPG_IFG 0x02 63211946Sjchandra#define O_IPG_IFG__ipgr1 24 64211946Sjchandra#define W_IPG_IFG__ipgr1 7 65211946Sjchandra#define O_IPG_IFG__ipgr2 16 66211946Sjchandra#define W_IPG_IFG__ipgr2 7 67211946Sjchandra#define O_IPG_IFG__mifg 8 68211946Sjchandra#define W_IPG_IFG__mifg 8 69211946Sjchandra#define O_IPG_IFG__ipgt 0 70211946Sjchandra#define W_IPG_IFG__ipgt 7 71211946Sjchandra#define R_HALF_DUPLEX 0x03 72211946Sjchandra#define O_HALF_DUPLEX__abebt 24 73211946Sjchandra#define W_HALF_DUPLEX__abebt 4 74211946Sjchandra#define O_HALF_DUPLEX__abebe 19 75211946Sjchandra#define O_HALF_DUPLEX__bpnb 18 76211946Sjchandra#define O_HALF_DUPLEX__nobo 17 77211946Sjchandra#define O_HALF_DUPLEX__edxsdfr 16 78211946Sjchandra#define O_HALF_DUPLEX__retry 12 79211946Sjchandra#define W_HALF_DUPLEX__retry 4 80211946Sjchandra#define O_HALF_DUPLEX__lcol 0 81211946Sjchandra#define W_HALF_DUPLEX__lcol 10 82211946Sjchandra#define R_MAXIMUM_FRAME_LENGTH 0x04 83211946Sjchandra#define O_MAXIMUM_FRAME_LENGTH__maxf 0 84211946Sjchandra#define W_MAXIMUM_FRAME_LENGTH__maxf 16 85211946Sjchandra#define R_TEST 0x07 86211946Sjchandra#define O_TEST__mbof 3 87211946Sjchandra#define O_TEST__rthdf 2 88211946Sjchandra#define O_TEST__tpause 1 89211946Sjchandra#define O_TEST__sstct 0 90211946Sjchandra#define R_MII_MGMT_CONFIG 0x08 91211946Sjchandra#define O_MII_MGMT_CONFIG__scinc 5 92211946Sjchandra#define O_MII_MGMT_CONFIG__spre 4 93211946Sjchandra#define O_MII_MGMT_CONFIG__clks 3 94211946Sjchandra#define W_MII_MGMT_CONFIG__clks 3 95211946Sjchandra#define R_MII_MGMT_COMMAND 0x09 96211946Sjchandra#define O_MII_MGMT_COMMAND__scan 1 97211946Sjchandra#define O_MII_MGMT_COMMAND__rstat 0 98211946Sjchandra#define R_MII_MGMT_ADDRESS 0x0A 99211946Sjchandra#define O_MII_MGMT_ADDRESS__fiad 8 100211946Sjchandra#define W_MII_MGMT_ADDRESS__fiad 5 101211946Sjchandra#define O_MII_MGMT_ADDRESS__fgad 5 102211946Sjchandra#define W_MII_MGMT_ADDRESS__fgad 0 103211946Sjchandra#define R_MII_MGMT_WRITE_DATA 0x0B 104211946Sjchandra#define O_MII_MGMT_WRITE_DATA__ctld 0 105211946Sjchandra#define W_MII_MGMT_WRITE_DATA__ctld 16 106211946Sjchandra#define R_MII_MGMT_STATUS 0x0C 107211946Sjchandra#define R_MII_MGMT_INDICATORS 0x0D 108211946Sjchandra#define O_MII_MGMT_INDICATORS__nvalid 2 109211946Sjchandra#define O_MII_MGMT_INDICATORS__scan 1 110211946Sjchandra#define O_MII_MGMT_INDICATORS__busy 0 111211946Sjchandra#define R_INTERFACE_CONTROL 0x0E 112211946Sjchandra#define O_INTERFACE_CONTROL__hrstint 31 113211946Sjchandra#define O_INTERFACE_CONTROL__tbimode 27 114211946Sjchandra#define O_INTERFACE_CONTROL__ghdmode 26 115211946Sjchandra#define O_INTERFACE_CONTROL__lhdmode 25 116211946Sjchandra#define O_INTERFACE_CONTROL__phymod 24 117211946Sjchandra#define O_INTERFACE_CONTROL__hrrmi 23 118211946Sjchandra#define O_INTERFACE_CONTROL__rspd 16 119211946Sjchandra#define O_INTERFACE_CONTROL__hr100 15 120211946Sjchandra#define O_INTERFACE_CONTROL__frcq 10 121211946Sjchandra#define O_INTERFACE_CONTROL__nocfr 9 122211946Sjchandra#define O_INTERFACE_CONTROL__dlfct 8 123211946Sjchandra#define O_INTERFACE_CONTROL__enjab 0 124211946Sjchandra#define R_INTERFACE_STATUS 0x0F 125211946Sjchandra#define O_INTERFACE_STATUS__xsdfr 9 126211946Sjchandra#define O_INTERFACE_STATUS__ssrr 8 127211946Sjchandra#define W_INTERFACE_STATUS__ssrr 5 128211946Sjchandra#define O_INTERFACE_STATUS__miilf 3 129211946Sjchandra#define O_INTERFACE_STATUS__locar 2 130211946Sjchandra#define O_INTERFACE_STATUS__sqerr 1 131211946Sjchandra#define O_INTERFACE_STATUS__jabber 0 132211946Sjchandra#define R_STATION_ADDRESS_LS 0x10 133211946Sjchandra#define R_STATION_ADDRESS_MS 0x11 134211946Sjchandra 135211946Sjchandra/* A-XGMAC register and bit field definitions */ 136211946Sjchandra#define R_XGMAC_CONFIG_0 0x00 137211946Sjchandra#define O_XGMAC_CONFIG_0__hstmacrst 31 138211946Sjchandra#define O_XGMAC_CONFIG_0__hstrstrctl 23 139211946Sjchandra#define O_XGMAC_CONFIG_0__hstrstrfn 22 140211946Sjchandra#define O_XGMAC_CONFIG_0__hstrsttctl 18 141211946Sjchandra#define O_XGMAC_CONFIG_0__hstrsttfn 17 142211946Sjchandra#define O_XGMAC_CONFIG_0__hstrstmiim 16 143211946Sjchandra#define O_XGMAC_CONFIG_0__hstloopback 8 144211946Sjchandra#define R_XGMAC_CONFIG_1 0x01 145211946Sjchandra#define O_XGMAC_CONFIG_1__hsttctlen 31 146211946Sjchandra#define O_XGMAC_CONFIG_1__hsttfen 30 147211946Sjchandra#define O_XGMAC_CONFIG_1__hstrctlen 29 148211946Sjchandra#define O_XGMAC_CONFIG_1__hstrfen 28 149211946Sjchandra#define O_XGMAC_CONFIG_1__tfen 26 150211946Sjchandra#define O_XGMAC_CONFIG_1__rfen 24 151211946Sjchandra#define O_XGMAC_CONFIG_1__hstrctlshrtp 12 152211946Sjchandra#define O_XGMAC_CONFIG_1__hstdlyfcstx 10 153211946Sjchandra#define W_XGMAC_CONFIG_1__hstdlyfcstx 2 154211946Sjchandra#define O_XGMAC_CONFIG_1__hstdlyfcsrx 8 155211946Sjchandra#define W_XGMAC_CONFIG_1__hstdlyfcsrx 2 156211946Sjchandra#define O_XGMAC_CONFIG_1__hstppen 7 157211946Sjchandra#define O_XGMAC_CONFIG_1__hstbytswp 6 158211946Sjchandra#define O_XGMAC_CONFIG_1__hstdrplt64 5 159211946Sjchandra#define O_XGMAC_CONFIG_1__hstprmscrx 4 160211946Sjchandra#define O_XGMAC_CONFIG_1__hstlenchk 3 161211946Sjchandra#define O_XGMAC_CONFIG_1__hstgenfcs 2 162211946Sjchandra#define O_XGMAC_CONFIG_1__hstpadmode 0 163211946Sjchandra#define W_XGMAC_CONFIG_1__hstpadmode 2 164211946Sjchandra#define R_XGMAC_CONFIG_2 0x02 165211946Sjchandra#define O_XGMAC_CONFIG_2__hsttctlfrcp 31 166211946Sjchandra#define O_XGMAC_CONFIG_2__hstmlnkflth 27 167211946Sjchandra#define O_XGMAC_CONFIG_2__hstalnkflth 26 168211946Sjchandra#define O_XGMAC_CONFIG_2__rflnkflt 24 169211946Sjchandra#define W_XGMAC_CONFIG_2__rflnkflt 2 170211946Sjchandra#define O_XGMAC_CONFIG_2__hstipgextmod 16 171211946Sjchandra#define W_XGMAC_CONFIG_2__hstipgextmod 5 172211946Sjchandra#define O_XGMAC_CONFIG_2__hstrctlfrcp 15 173211946Sjchandra#define O_XGMAC_CONFIG_2__hstipgexten 5 174211946Sjchandra#define O_XGMAC_CONFIG_2__hstmipgext 0 175211946Sjchandra#define W_XGMAC_CONFIG_2__hstmipgext 5 176211946Sjchandra#define R_XGMAC_CONFIG_3 0x03 177211946Sjchandra#define O_XGMAC_CONFIG_3__hstfltrfrm 31 178211946Sjchandra#define W_XGMAC_CONFIG_3__hstfltrfrm 16 179211946Sjchandra#define O_XGMAC_CONFIG_3__hstfltrfrmdc 15 180211946Sjchandra#define W_XGMAC_CONFIG_3__hstfltrfrmdc 16 181211946Sjchandra#define R_XGMAC_STATION_ADDRESS_LS 0x04 182211946Sjchandra#define O_XGMAC_STATION_ADDRESS_LS__hstmacadr0 0 183211946Sjchandra#define W_XGMAC_STATION_ADDRESS_LS__hstmacadr0 32 184211946Sjchandra#define R_XGMAC_STATION_ADDRESS_MS 0x05 185211946Sjchandra#define R_XGMAC_MAX_FRAME_LEN 0x08 186211946Sjchandra#define O_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx 16 187211946Sjchandra#define W_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx 14 188211946Sjchandra#define O_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx 0 189211946Sjchandra#define W_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx 16 190211946Sjchandra#define R_XGMAC_REV_LEVEL 0x0B 191211946Sjchandra#define O_XGMAC_REV_LEVEL__revlvl 0 192211946Sjchandra#define W_XGMAC_REV_LEVEL__revlvl 15 193211946Sjchandra#define R_XGMAC_MIIM_COMMAND 0x10 194211946Sjchandra#define O_XGMAC_MIIM_COMMAND__hstldcmd 3 195211946Sjchandra#define O_XGMAC_MIIM_COMMAND__hstmiimcmd 0 196211946Sjchandra#define W_XGMAC_MIIM_COMMAND__hstmiimcmd 3 197211946Sjchandra#define R_XGMAC_MIIM_FILED 0x11 198211946Sjchandra#define O_XGMAC_MIIM_FILED__hststfield 30 199211946Sjchandra#define W_XGMAC_MIIM_FILED__hststfield 2 200211946Sjchandra#define O_XGMAC_MIIM_FILED__hstopfield 28 201211946Sjchandra#define W_XGMAC_MIIM_FILED__hstopfield 2 202211946Sjchandra#define O_XGMAC_MIIM_FILED__hstphyadx 23 203211946Sjchandra#define W_XGMAC_MIIM_FILED__hstphyadx 5 204211946Sjchandra#define O_XGMAC_MIIM_FILED__hstregadx 18 205211946Sjchandra#define W_XGMAC_MIIM_FILED__hstregadx 5 206211946Sjchandra#define O_XGMAC_MIIM_FILED__hsttafield 16 207211946Sjchandra#define W_XGMAC_MIIM_FILED__hsttafield 2 208211946Sjchandra#define O_XGMAC_MIIM_FILED__miimrddat 0 209211946Sjchandra#define W_XGMAC_MIIM_FILED__miimrddat 16 210211946Sjchandra#define R_XGMAC_MIIM_CONFIG 0x12 211211946Sjchandra#define O_XGMAC_MIIM_CONFIG__hstnopram 7 212211946Sjchandra#define O_XGMAC_MIIM_CONFIG__hstclkdiv 0 213211946Sjchandra#define W_XGMAC_MIIM_CONFIG__hstclkdiv 7 214211946Sjchandra#define R_XGMAC_MIIM_LINK_FAIL_VECTOR 0x13 215211946Sjchandra#define O_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec 0 216211946Sjchandra#define W_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec 32 217211946Sjchandra#define R_XGMAC_MIIM_INDICATOR 0x14 218211946Sjchandra#define O_XGMAC_MIIM_INDICATOR__miimphylf 4 219211946Sjchandra#define O_XGMAC_MIIM_INDICATOR__miimmoncplt 3 220211946Sjchandra#define O_XGMAC_MIIM_INDICATOR__miimmonvld 2 221211946Sjchandra#define O_XGMAC_MIIM_INDICATOR__miimmon 1 222211946Sjchandra#define O_XGMAC_MIIM_INDICATOR__miimbusy 0 223211946Sjchandra 224211946Sjchandra/* GMAC stats registers */ 225211946Sjchandra#define R_RBYT 0x27 226211946Sjchandra#define R_RPKT 0x28 227211946Sjchandra#define R_RFCS 0x29 228211946Sjchandra#define R_RMCA 0x2A 229211946Sjchandra#define R_RBCA 0x2B 230211946Sjchandra#define R_RXCF 0x2C 231211946Sjchandra#define R_RXPF 0x2D 232211946Sjchandra#define R_RXUO 0x2E 233211946Sjchandra#define R_RALN 0x2F 234211946Sjchandra#define R_RFLR 0x30 235211946Sjchandra#define R_RCDE 0x31 236211946Sjchandra#define R_RCSE 0x32 237211946Sjchandra#define R_RUND 0x33 238211946Sjchandra#define R_ROVR 0x34 239211946Sjchandra#define R_TBYT 0x38 240211946Sjchandra#define R_TPKT 0x39 241211946Sjchandra#define R_TMCA 0x3A 242211946Sjchandra#define R_TBCA 0x3B 243211946Sjchandra#define R_TXPF 0x3C 244211946Sjchandra#define R_TDFR 0x3D 245211946Sjchandra#define R_TEDF 0x3E 246211946Sjchandra#define R_TSCL 0x3F 247211946Sjchandra#define R_TMCL 0x40 248211946Sjchandra#define R_TLCL 0x41 249211946Sjchandra#define R_TXCL 0x42 250211946Sjchandra#define R_TNCL 0x43 251211946Sjchandra#define R_TJBR 0x46 252211946Sjchandra#define R_TFCS 0x47 253211946Sjchandra#define R_TXCF 0x48 254211946Sjchandra#define R_TOVR 0x49 255211946Sjchandra#define R_TUND 0x4A 256211946Sjchandra#define R_TFRG 0x4B 257211946Sjchandra 258211946Sjchandra/* Glue logic register and bit field definitions */ 259211946Sjchandra#define R_MAC_ADDR0 0x50 260211946Sjchandra#define R_MAC_ADDR1 0x52 261211946Sjchandra#define R_MAC_ADDR2 0x54 262211946Sjchandra#define R_MAC_ADDR3 0x56 263211946Sjchandra#define R_MAC_ADDR_MASK2 0x58 264211946Sjchandra#define R_MAC_ADDR_MASK3 0x5A 265211946Sjchandra#define R_MAC_FILTER_CONFIG 0x5C 266211946Sjchandra#define O_MAC_FILTER_CONFIG__BROADCAST_EN 10 267211946Sjchandra#define O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN 9 268211946Sjchandra#define O_MAC_FILTER_CONFIG__ALL_MCAST_EN 8 269211946Sjchandra#define O_MAC_FILTER_CONFIG__ALL_UCAST_EN 7 270211946Sjchandra#define O_MAC_FILTER_CONFIG__HASH_MCAST_EN 6 271211946Sjchandra#define O_MAC_FILTER_CONFIG__HASH_UCAST_EN 5 272211946Sjchandra#define O_MAC_FILTER_CONFIG__ADDR_MATCH_DISC 4 273211946Sjchandra#define O_MAC_FILTER_CONFIG__MAC_ADDR3_VALID 3 274211946Sjchandra#define O_MAC_FILTER_CONFIG__MAC_ADDR2_VALID 2 275211946Sjchandra#define O_MAC_FILTER_CONFIG__MAC_ADDR1_VALID 1 276211946Sjchandra#define O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID 0 277211946Sjchandra#define R_HASH_TABLE_VECTOR 0x30 278211946Sjchandra#define R_TX_CONTROL 0x0A0 279211946Sjchandra#define O_TX_CONTROL__Tx15Halt 31 280211946Sjchandra#define O_TX_CONTROL__Tx14Halt 30 281211946Sjchandra#define O_TX_CONTROL__Tx13Halt 29 282211946Sjchandra#define O_TX_CONTROL__Tx12Halt 28 283211946Sjchandra#define O_TX_CONTROL__Tx11Halt 27 284211946Sjchandra#define O_TX_CONTROL__Tx10Halt 26 285211946Sjchandra#define O_TX_CONTROL__Tx9Halt 25 286211946Sjchandra#define O_TX_CONTROL__Tx8Halt 24 287211946Sjchandra#define O_TX_CONTROL__Tx7Halt 23 288211946Sjchandra#define O_TX_CONTROL__Tx6Halt 22 289211946Sjchandra#define O_TX_CONTROL__Tx5Halt 21 290211946Sjchandra#define O_TX_CONTROL__Tx4Halt 20 291211946Sjchandra#define O_TX_CONTROL__Tx3Halt 19 292211946Sjchandra#define O_TX_CONTROL__Tx2Halt 18 293211946Sjchandra#define O_TX_CONTROL__Tx1Halt 17 294211946Sjchandra#define O_TX_CONTROL__Tx0Halt 16 295211946Sjchandra#define O_TX_CONTROL__TxIdle 15 296211946Sjchandra#define O_TX_CONTROL__TxEnable 14 297211946Sjchandra#define O_TX_CONTROL__TxThreshold 0 298211946Sjchandra#define W_TX_CONTROL__TxThreshold 14 299211946Sjchandra#define R_RX_CONTROL 0x0A1 300211946Sjchandra#define O_RX_CONTROL__RGMII 10 301211946Sjchandra#define O_RX_CONTROL__SoftReset 2 302211946Sjchandra#define O_RX_CONTROL__RxHalt 1 303211946Sjchandra#define O_RX_CONTROL__RxEnable 0 304211946Sjchandra#define R_DESC_PACK_CTRL 0x0A2 305211946Sjchandra#define O_DESC_PACK_CTRL__ByteOffset 17 306211946Sjchandra#define W_DESC_PACK_CTRL__ByteOffset 3 307211946Sjchandra#define O_DESC_PACK_CTRL__PrePadEnable 16 308211946Sjchandra#define O_DESC_PACK_CTRL__MaxEntry 14 309211946Sjchandra#define W_DESC_PACK_CTRL__MaxEntry 2 310211946Sjchandra#define O_DESC_PACK_CTRL__RegularSize 0 311211946Sjchandra#define W_DESC_PACK_CTRL__RegularSize 14 312211946Sjchandra#define R_STATCTRL 0x0A3 313211946Sjchandra#define O_STATCTRL__OverFlowEn 4 314211946Sjchandra#define O_STATCTRL__GIG 3 315211946Sjchandra#define O_STATCTRL__Sten 2 316211946Sjchandra#define O_STATCTRL__ClrCnt 1 317211946Sjchandra#define O_STATCTRL__AutoZ 0 318211946Sjchandra#define R_L2ALLOCCTRL 0x0A4 319211946Sjchandra#define O_L2ALLOCCTRL__TxL2Allocate 9 320211946Sjchandra#define W_L2ALLOCCTRL__TxL2Allocate 9 321211946Sjchandra#define O_L2ALLOCCTRL__RxL2Allocate 0 322211946Sjchandra#define W_L2ALLOCCTRL__RxL2Allocate 9 323211946Sjchandra#define R_INTMASK 0x0A5 324211946Sjchandra#define O_INTMASK__Spi4TxError 28 325211946Sjchandra#define O_INTMASK__Spi4RxError 27 326211946Sjchandra#define O_INTMASK__RGMIIHalfDupCollision 27 327211946Sjchandra#define O_INTMASK__Abort 26 328211946Sjchandra#define O_INTMASK__Underrun 25 329211946Sjchandra#define O_INTMASK__DiscardPacket 24 330211946Sjchandra#define O_INTMASK__AsyncFifoFull 23 331211946Sjchandra#define O_INTMASK__TagFull 22 332211946Sjchandra#define O_INTMASK__Class3Full 21 333211946Sjchandra#define O_INTMASK__C3EarlyFull 20 334211946Sjchandra#define O_INTMASK__Class2Full 19 335211946Sjchandra#define O_INTMASK__C2EarlyFull 18 336211946Sjchandra#define O_INTMASK__Class1Full 17 337211946Sjchandra#define O_INTMASK__C1EarlyFull 16 338211946Sjchandra#define O_INTMASK__Class0Full 15 339211946Sjchandra#define O_INTMASK__C0EarlyFull 14 340211946Sjchandra#define O_INTMASK__RxDataFull 13 341211946Sjchandra#define O_INTMASK__RxEarlyFull 12 342211946Sjchandra#define O_INTMASK__RFreeEmpty 9 343211946Sjchandra#define O_INTMASK__RFEarlyEmpty 8 344211946Sjchandra#define O_INTMASK__P2PSpillEcc 7 345211946Sjchandra#define O_INTMASK__FreeDescFull 5 346211946Sjchandra#define O_INTMASK__FreeEarlyFull 4 347211946Sjchandra#define O_INTMASK__TxFetchError 3 348211946Sjchandra#define O_INTMASK__StatCarry 2 349211946Sjchandra#define O_INTMASK__MDInt 1 350211946Sjchandra#define O_INTMASK__TxIllegal 0 351211946Sjchandra#define R_INTREG 0x0A6 352211946Sjchandra#define O_INTREG__Spi4TxError 28 353211946Sjchandra#define O_INTREG__Spi4RxError 27 354211946Sjchandra#define O_INTREG__RGMIIHalfDupCollision 27 355211946Sjchandra#define O_INTREG__Abort 26 356211946Sjchandra#define O_INTREG__Underrun 25 357211946Sjchandra#define O_INTREG__DiscardPacket 24 358211946Sjchandra#define O_INTREG__AsyncFifoFull 23 359211946Sjchandra#define O_INTREG__TagFull 22 360211946Sjchandra#define O_INTREG__Class3Full 21 361211946Sjchandra#define O_INTREG__C3EarlyFull 20 362211946Sjchandra#define O_INTREG__Class2Full 19 363211946Sjchandra#define O_INTREG__C2EarlyFull 18 364211946Sjchandra#define O_INTREG__Class1Full 17 365211946Sjchandra#define O_INTREG__C1EarlyFull 16 366211946Sjchandra#define O_INTREG__Class0Full 15 367211946Sjchandra#define O_INTREG__C0EarlyFull 14 368211946Sjchandra#define O_INTREG__RxDataFull 13 369211946Sjchandra#define O_INTREG__RxEarlyFull 12 370211946Sjchandra#define O_INTREG__RFreeEmpty 9 371211946Sjchandra#define O_INTREG__RFEarlyEmpty 8 372211946Sjchandra#define O_INTREG__P2PSpillEcc 7 373211946Sjchandra#define O_INTREG__FreeDescFull 5 374211946Sjchandra#define O_INTREG__FreeEarlyFull 4 375211946Sjchandra#define O_INTREG__TxFetchError 3 376211946Sjchandra#define O_INTREG__StatCarry 2 377211946Sjchandra#define O_INTREG__MDInt 1 378211946Sjchandra#define O_INTREG__TxIllegal 0 379211946Sjchandra#define R_TXRETRY 0x0A7 380211946Sjchandra#define O_TXRETRY__CollisionRetry 6 381211946Sjchandra#define O_TXRETRY__BusErrorRetry 5 382211946Sjchandra#define O_TXRETRY__UnderRunRetry 4 383211946Sjchandra#define O_TXRETRY__Retries 0 384211946Sjchandra#define W_TXRETRY__Retries 4 385211946Sjchandra#define R_CORECONTROL 0x0A8 386211946Sjchandra#define O_CORECONTROL__ErrorThread 4 387211946Sjchandra#define W_CORECONTROL__ErrorThread 7 388211946Sjchandra#define O_CORECONTROL__Shutdown 2 389211946Sjchandra#define O_CORECONTROL__Speed 0 390211946Sjchandra#define W_CORECONTROL__Speed 2 391211946Sjchandra#define R_BYTEOFFSET0 0x0A9 392211946Sjchandra#define R_BYTEOFFSET1 0x0AA 393211946Sjchandra#define R_L2TYPE_0 0x0F0 394211946Sjchandra#define O_L2TYPE__ExtraHdrProtoSize 26 395211946Sjchandra#define W_L2TYPE__ExtraHdrProtoSize 5 396211946Sjchandra#define O_L2TYPE__ExtraHdrProtoOffset 20 397211946Sjchandra#define W_L2TYPE__ExtraHdrProtoOffset 6 398211946Sjchandra#define O_L2TYPE__ExtraHeaderSize 14 399211946Sjchandra#define W_L2TYPE__ExtraHeaderSize 6 400211946Sjchandra#define O_L2TYPE__ProtoOffset 8 401211946Sjchandra#define W_L2TYPE__ProtoOffset 6 402211946Sjchandra#define O_L2TYPE__L2HdrOffset 2 403211946Sjchandra#define W_L2TYPE__L2HdrOffset 6 404211946Sjchandra#define O_L2TYPE__L2Proto 0 405211946Sjchandra#define W_L2TYPE__L2Proto 2 406211946Sjchandra#define R_L2TYPE_1 0xF0 407211946Sjchandra#define R_L2TYPE_2 0xF0 408211946Sjchandra#define R_L2TYPE_3 0xF0 409211946Sjchandra#define R_PARSERCONFIGREG 0x100 410211946Sjchandra#define O_PARSERCONFIGREG__CRCHashPoly 8 411211946Sjchandra#define W_PARSERCONFIGREG__CRCHashPoly 7 412211946Sjchandra#define O_PARSERCONFIGREG__PrePadOffset 4 413211946Sjchandra#define W_PARSERCONFIGREG__PrePadOffset 4 414211946Sjchandra#define O_PARSERCONFIGREG__UseCAM 2 415211946Sjchandra#define O_PARSERCONFIGREG__UseHASH 1 416211946Sjchandra#define O_PARSERCONFIGREG__UseProto 0 417211946Sjchandra#define R_L3CTABLE 0x140 418211946Sjchandra#define O_L3CTABLE__Offset0 25 419211946Sjchandra#define W_L3CTABLE__Offset0 7 420211946Sjchandra#define O_L3CTABLE__Len0 21 421211946Sjchandra#define W_L3CTABLE__Len0 4 422211946Sjchandra#define O_L3CTABLE__Offset1 14 423211946Sjchandra#define W_L3CTABLE__Offset1 7 424211946Sjchandra#define O_L3CTABLE__Len1 10 425211946Sjchandra#define W_L3CTABLE__Len1 4 426211946Sjchandra#define O_L3CTABLE__Offset2 4 427211946Sjchandra#define W_L3CTABLE__Offset2 6 428211946Sjchandra#define O_L3CTABLE__Len2 0 429211946Sjchandra#define W_L3CTABLE__Len2 4 430211946Sjchandra#define O_L3CTABLE__L3HdrOffset 26 431211946Sjchandra#define W_L3CTABLE__L3HdrOffset 6 432211946Sjchandra#define O_L3CTABLE__L4ProtoOffset 20 433211946Sjchandra#define W_L3CTABLE__L4ProtoOffset 6 434211946Sjchandra#define O_L3CTABLE__IPChksumCompute 19 435211946Sjchandra#define O_L3CTABLE__L4Classify 18 436211946Sjchandra#define O_L3CTABLE__L2Proto 16 437211946Sjchandra#define W_L3CTABLE__L2Proto 2 438211946Sjchandra#define O_L3CTABLE__L3ProtoKey 0 439211946Sjchandra#define W_L3CTABLE__L3ProtoKey 16 440211946Sjchandra#define R_L4CTABLE 0x160 441211946Sjchandra#define O_L4CTABLE__Offset0 21 442211946Sjchandra#define W_L4CTABLE__Offset0 6 443211946Sjchandra#define O_L4CTABLE__Len0 17 444211946Sjchandra#define W_L4CTABLE__Len0 4 445211946Sjchandra#define O_L4CTABLE__Offset1 11 446211946Sjchandra#define W_L4CTABLE__Offset1 6 447211946Sjchandra#define O_L4CTABLE__Len1 7 448211946Sjchandra#define W_L4CTABLE__Len1 4 449211946Sjchandra#define O_L4CTABLE__TCPChksumEnable 0 450211946Sjchandra#define R_CAM4X128TABLE 0x172 451211946Sjchandra#define O_CAM4X128TABLE__ClassId 7 452211946Sjchandra#define W_CAM4X128TABLE__ClassId 2 453211946Sjchandra#define O_CAM4X128TABLE__BucketId 1 454211946Sjchandra#define W_CAM4X128TABLE__BucketId 6 455211946Sjchandra#define O_CAM4X128TABLE__UseBucket 0 456211946Sjchandra#define R_CAM4X128KEY 0x180 457211946Sjchandra#define R_TRANSLATETABLE 0x1A0 458211946Sjchandra#define R_DMACR0 0x200 459211946Sjchandra#define O_DMACR0__Data0WrMaxCr 27 460211946Sjchandra#define W_DMACR0__Data0WrMaxCr 3 461211946Sjchandra#define O_DMACR0__Data0RdMaxCr 24 462211946Sjchandra#define W_DMACR0__Data0RdMaxCr 3 463211946Sjchandra#define O_DMACR0__Data1WrMaxCr 21 464211946Sjchandra#define W_DMACR0__Data1WrMaxCr 3 465211946Sjchandra#define O_DMACR0__Data1RdMaxCr 18 466211946Sjchandra#define W_DMACR0__Data1RdMaxCr 3 467211946Sjchandra#define O_DMACR0__Data2WrMaxCr 15 468211946Sjchandra#define W_DMACR0__Data2WrMaxCr 3 469211946Sjchandra#define O_DMACR0__Data2RdMaxCr 12 470211946Sjchandra#define W_DMACR0__Data2RdMaxCr 3 471211946Sjchandra#define O_DMACR0__Data3WrMaxCr 9 472211946Sjchandra#define W_DMACR0__Data3WrMaxCr 3 473211946Sjchandra#define O_DMACR0__Data3RdMaxCr 6 474211946Sjchandra#define W_DMACR0__Data3RdMaxCr 3 475211946Sjchandra#define O_DMACR0__Data4WrMaxCr 3 476211946Sjchandra#define W_DMACR0__Data4WrMaxCr 3 477211946Sjchandra#define O_DMACR0__Data4RdMaxCr 0 478211946Sjchandra#define W_DMACR0__Data4RdMaxCr 3 479211946Sjchandra#define R_DMACR1 0x201 480211946Sjchandra#define O_DMACR1__Data5WrMaxCr 27 481211946Sjchandra#define W_DMACR1__Data5WrMaxCr 3 482211946Sjchandra#define O_DMACR1__Data5RdMaxCr 24 483211946Sjchandra#define W_DMACR1__Data5RdMaxCr 3 484211946Sjchandra#define O_DMACR1__Data6WrMaxCr 21 485211946Sjchandra#define W_DMACR1__Data6WrMaxCr 3 486211946Sjchandra#define O_DMACR1__Data6RdMaxCr 18 487211946Sjchandra#define W_DMACR1__Data6RdMaxCr 3 488211946Sjchandra#define O_DMACR1__Data7WrMaxCr 15 489211946Sjchandra#define W_DMACR1__Data7WrMaxCr 3 490211946Sjchandra#define O_DMACR1__Data7RdMaxCr 12 491211946Sjchandra#define W_DMACR1__Data7RdMaxCr 3 492211946Sjchandra#define O_DMACR1__Data8WrMaxCr 9 493211946Sjchandra#define W_DMACR1__Data8WrMaxCr 3 494211946Sjchandra#define O_DMACR1__Data8RdMaxCr 6 495211946Sjchandra#define W_DMACR1__Data8RdMaxCr 3 496211946Sjchandra#define O_DMACR1__Data9WrMaxCr 3 497211946Sjchandra#define W_DMACR1__Data9WrMaxCr 3 498211946Sjchandra#define O_DMACR1__Data9RdMaxCr 0 499211946Sjchandra#define W_DMACR1__Data9RdMaxCr 3 500211946Sjchandra#define R_DMACR2 0x202 501211946Sjchandra#define O_DMACR2__Data10WrMaxCr 27 502211946Sjchandra#define W_DMACR2__Data10WrMaxCr 3 503211946Sjchandra#define O_DMACR2__Data10RdMaxCr 24 504211946Sjchandra#define W_DMACR2__Data10RdMaxCr 3 505211946Sjchandra#define O_DMACR2__Data11WrMaxCr 21 506211946Sjchandra#define W_DMACR2__Data11WrMaxCr 3 507211946Sjchandra#define O_DMACR2__Data11RdMaxCr 18 508211946Sjchandra#define W_DMACR2__Data11RdMaxCr 3 509211946Sjchandra#define O_DMACR2__Data12WrMaxCr 15 510211946Sjchandra#define W_DMACR2__Data12WrMaxCr 3 511211946Sjchandra#define O_DMACR2__Data12RdMaxCr 12 512211946Sjchandra#define W_DMACR2__Data12RdMaxCr 3 513211946Sjchandra#define O_DMACR2__Data13WrMaxCr 9 514211946Sjchandra#define W_DMACR2__Data13WrMaxCr 3 515211946Sjchandra#define O_DMACR2__Data13RdMaxCr 6 516211946Sjchandra#define W_DMACR2__Data13RdMaxCr 3 517211946Sjchandra#define O_DMACR2__Data14WrMaxCr 3 518211946Sjchandra#define W_DMACR2__Data14WrMaxCr 3 519211946Sjchandra#define O_DMACR2__Data14RdMaxCr 0 520211946Sjchandra#define W_DMACR2__Data14RdMaxCr 3 521211946Sjchandra#define R_DMACR3 0x203 522211946Sjchandra#define O_DMACR3__Data15WrMaxCr 27 523211946Sjchandra#define W_DMACR3__Data15WrMaxCr 3 524211946Sjchandra#define O_DMACR3__Data15RdMaxCr 24 525211946Sjchandra#define W_DMACR3__Data15RdMaxCr 3 526211946Sjchandra#define O_DMACR3__SpClassWrMaxCr 21 527211946Sjchandra#define W_DMACR3__SpClassWrMaxCr 3 528211946Sjchandra#define O_DMACR3__SpClassRdMaxCr 18 529211946Sjchandra#define W_DMACR3__SpClassRdMaxCr 3 530211946Sjchandra#define O_DMACR3__JumFrInWrMaxCr 15 531211946Sjchandra#define W_DMACR3__JumFrInWrMaxCr 3 532211946Sjchandra#define O_DMACR3__JumFrInRdMaxCr 12 533211946Sjchandra#define W_DMACR3__JumFrInRdMaxCr 3 534211946Sjchandra#define O_DMACR3__RegFrInWrMaxCr 9 535211946Sjchandra#define W_DMACR3__RegFrInWrMaxCr 3 536211946Sjchandra#define O_DMACR3__RegFrInRdMaxCr 6 537211946Sjchandra#define W_DMACR3__RegFrInRdMaxCr 3 538211946Sjchandra#define O_DMACR3__FrOutWrMaxCr 3 539211946Sjchandra#define W_DMACR3__FrOutWrMaxCr 3 540211946Sjchandra#define O_DMACR3__FrOutRdMaxCr 0 541211946Sjchandra#define W_DMACR3__FrOutRdMaxCr 3 542211946Sjchandra#define R_REG_FRIN_SPILL_MEM_START_0 0x204 543211946Sjchandra#define O_REG_FRIN_SPILL_MEM_START_0__RegFrInSpillMemStart0 0 544211946Sjchandra#define W_REG_FRIN_SPILL_MEM_START_0__RegFrInSpillMemStart0 32 545211946Sjchandra#define R_REG_FRIN_SPILL_MEM_START_1 0x205 546211946Sjchandra#define O_REG_FRIN_SPILL_MEM_START_1__RegFrInSpillMemStart1 0 547211946Sjchandra#define W_REG_FRIN_SPILL_MEM_START_1__RegFrInSpillMemStart1 3 548211946Sjchandra#define R_REG_FRIN_SPILL_MEM_SIZE 0x206 549211946Sjchandra#define O_REG_FRIN_SPILL_MEM_SIZE__RegFrInSpillMemSize 0 550211946Sjchandra#define W_REG_FRIN_SPILL_MEM_SIZE__RegFrInSpillMemSize 32 551211946Sjchandra#define R_FROUT_SPILL_MEM_START_0 0x207 552211946Sjchandra#define O_FROUT_SPILL_MEM_START_0__FrOutSpillMemStart0 0 553211946Sjchandra#define W_FROUT_SPILL_MEM_START_0__FrOutSpillMemStart0 32 554211946Sjchandra#define R_FROUT_SPILL_MEM_START_1 0x208 555211946Sjchandra#define O_FROUT_SPILL_MEM_START_1__FrOutSpillMemStart1 0 556211946Sjchandra#define W_FROUT_SPILL_MEM_START_1__FrOutSpillMemStart1 3 557211946Sjchandra#define R_FROUT_SPILL_MEM_SIZE 0x209 558211946Sjchandra#define O_FROUT_SPILL_MEM_SIZE__FrOutSpillMemSize 0 559211946Sjchandra#define W_FROUT_SPILL_MEM_SIZE__FrOutSpillMemSize 32 560211946Sjchandra#define R_CLASS0_SPILL_MEM_START_0 0x20A 561211946Sjchandra#define O_CLASS0_SPILL_MEM_START_0__Class0SpillMemStart0 0 562211946Sjchandra#define W_CLASS0_SPILL_MEM_START_0__Class0SpillMemStart0 32 563211946Sjchandra#define R_CLASS0_SPILL_MEM_START_1 0x20B 564211946Sjchandra#define O_CLASS0_SPILL_MEM_START_1__Class0SpillMemStart1 0 565211946Sjchandra#define W_CLASS0_SPILL_MEM_START_1__Class0SpillMemStart1 3 566211946Sjchandra#define R_CLASS0_SPILL_MEM_SIZE 0x20C 567211946Sjchandra#define O_CLASS0_SPILL_MEM_SIZE__Class0SpillMemSize 0 568211946Sjchandra#define W_CLASS0_SPILL_MEM_SIZE__Class0SpillMemSize 32 569211946Sjchandra#define R_JUMFRIN_SPILL_MEM_START_0 0x20D 570211946Sjchandra#define O_JUMFRIN_SPILL_MEM_START_0__JumFrInSpillMemStar0 0 571211946Sjchandra#define W_JUMFRIN_SPILL_MEM_START_0__JumFrInSpillMemStar0 32 572211946Sjchandra#define R_JUMFRIN_SPILL_MEM_START_1 0x20E 573211946Sjchandra#define O_JUMFRIN_SPILL_MEM_START_1__JumFrInSpillMemStart1 0 574211946Sjchandra#define W_JUMFRIN_SPILL_MEM_START_1__JumFrInSpillMemStart1 3 575211946Sjchandra#define R_JUMFRIN_SPILL_MEM_SIZE 0x20F 576211946Sjchandra#define O_JUMFRIN_SPILL_MEM_SIZE__JumFrInSpillMemSize 0 577211946Sjchandra#define W_JUMFRIN_SPILL_MEM_SIZE__JumFrInSpillMemSize 32 578211946Sjchandra#define R_CLASS1_SPILL_MEM_START_0 0x210 579211946Sjchandra#define O_CLASS1_SPILL_MEM_START_0__Class1SpillMemStart0 0 580211946Sjchandra#define W_CLASS1_SPILL_MEM_START_0__Class1SpillMemStart0 32 581211946Sjchandra#define R_CLASS1_SPILL_MEM_START_1 0x211 582211946Sjchandra#define O_CLASS1_SPILL_MEM_START_1__Class1SpillMemStart1 0 583211946Sjchandra#define W_CLASS1_SPILL_MEM_START_1__Class1SpillMemStart1 3 584211946Sjchandra#define R_CLASS1_SPILL_MEM_SIZE 0x212 585211946Sjchandra#define O_CLASS1_SPILL_MEM_SIZE__Class1SpillMemSize 0 586211946Sjchandra#define W_CLASS1_SPILL_MEM_SIZE__Class1SpillMemSize 32 587211946Sjchandra#define R_CLASS2_SPILL_MEM_START_0 0x213 588211946Sjchandra#define O_CLASS2_SPILL_MEM_START_0__Class2SpillMemStart0 0 589211946Sjchandra#define W_CLASS2_SPILL_MEM_START_0__Class2SpillMemStart0 32 590211946Sjchandra#define R_CLASS2_SPILL_MEM_START_1 0x214 591211946Sjchandra#define O_CLASS2_SPILL_MEM_START_1__Class2SpillMemStart1 0 592211946Sjchandra#define W_CLASS2_SPILL_MEM_START_1__Class2SpillMemStart1 3 593211946Sjchandra#define R_CLASS2_SPILL_MEM_SIZE 0x215 594211946Sjchandra#define O_CLASS2_SPILL_MEM_SIZE__Class2SpillMemSize 0 595211946Sjchandra#define W_CLASS2_SPILL_MEM_SIZE__Class2SpillMemSize 32 596211946Sjchandra#define R_CLASS3_SPILL_MEM_START_0 0x216 597211946Sjchandra#define O_CLASS3_SPILL_MEM_START_0__Class3SpillMemStart0 0 598211946Sjchandra#define W_CLASS3_SPILL_MEM_START_0__Class3SpillMemStart0 32 599211946Sjchandra#define R_CLASS3_SPILL_MEM_START_1 0x217 600211946Sjchandra#define O_CLASS3_SPILL_MEM_START_1__Class3SpillMemStart1 0 601211946Sjchandra#define W_CLASS3_SPILL_MEM_START_1__Class3SpillMemStart1 3 602211946Sjchandra#define R_CLASS3_SPILL_MEM_SIZE 0x218 603211946Sjchandra#define O_CLASS3_SPILL_MEM_SIZE__Class3SpillMemSize 0 604211946Sjchandra#define W_CLASS3_SPILL_MEM_SIZE__Class3SpillMemSize 32 605211946Sjchandra#define R_REG_FRIN1_SPILL_MEM_START_0 0x219 606211946Sjchandra#define R_REG_FRIN1_SPILL_MEM_START_1 0x21a 607211946Sjchandra#define R_REG_FRIN1_SPILL_MEM_SIZE 0x21b 608211946Sjchandra#define R_SPIHNGY0 0x219 609211946Sjchandra#define O_SPIHNGY0__EG_HNGY_THRESH_0 24 610211946Sjchandra#define W_SPIHNGY0__EG_HNGY_THRESH_0 7 611211946Sjchandra#define O_SPIHNGY0__EG_HNGY_THRESH_1 16 612211946Sjchandra#define W_SPIHNGY0__EG_HNGY_THRESH_1 7 613211946Sjchandra#define O_SPIHNGY0__EG_HNGY_THRESH_2 8 614211946Sjchandra#define W_SPIHNGY0__EG_HNGY_THRESH_2 7 615211946Sjchandra#define O_SPIHNGY0__EG_HNGY_THRESH_3 0 616211946Sjchandra#define W_SPIHNGY0__EG_HNGY_THRESH_3 7 617211946Sjchandra#define R_SPIHNGY1 0x21A 618211946Sjchandra#define O_SPIHNGY1__EG_HNGY_THRESH_4 24 619211946Sjchandra#define W_SPIHNGY1__EG_HNGY_THRESH_4 7 620211946Sjchandra#define O_SPIHNGY1__EG_HNGY_THRESH_5 16 621211946Sjchandra#define W_SPIHNGY1__EG_HNGY_THRESH_5 7 622211946Sjchandra#define O_SPIHNGY1__EG_HNGY_THRESH_6 8 623211946Sjchandra#define W_SPIHNGY1__EG_HNGY_THRESH_6 7 624211946Sjchandra#define O_SPIHNGY1__EG_HNGY_THRESH_7 0 625211946Sjchandra#define W_SPIHNGY1__EG_HNGY_THRESH_7 7 626211946Sjchandra#define R_SPIHNGY2 0x21B 627211946Sjchandra#define O_SPIHNGY2__EG_HNGY_THRESH_8 24 628211946Sjchandra#define W_SPIHNGY2__EG_HNGY_THRESH_8 7 629211946Sjchandra#define O_SPIHNGY2__EG_HNGY_THRESH_9 16 630211946Sjchandra#define W_SPIHNGY2__EG_HNGY_THRESH_9 7 631211946Sjchandra#define O_SPIHNGY2__EG_HNGY_THRESH_10 8 632211946Sjchandra#define W_SPIHNGY2__EG_HNGY_THRESH_10 7 633211946Sjchandra#define O_SPIHNGY2__EG_HNGY_THRESH_11 0 634211946Sjchandra#define W_SPIHNGY2__EG_HNGY_THRESH_11 7 635211946Sjchandra#define R_SPIHNGY3 0x21C 636211946Sjchandra#define O_SPIHNGY3__EG_HNGY_THRESH_12 24 637211946Sjchandra#define W_SPIHNGY3__EG_HNGY_THRESH_12 7 638211946Sjchandra#define O_SPIHNGY3__EG_HNGY_THRESH_13 16 639211946Sjchandra#define W_SPIHNGY3__EG_HNGY_THRESH_13 7 640211946Sjchandra#define O_SPIHNGY3__EG_HNGY_THRESH_14 8 641211946Sjchandra#define W_SPIHNGY3__EG_HNGY_THRESH_14 7 642211946Sjchandra#define O_SPIHNGY3__EG_HNGY_THRESH_15 0 643211946Sjchandra#define W_SPIHNGY3__EG_HNGY_THRESH_15 7 644211946Sjchandra#define R_SPISTRV0 0x21D 645211946Sjchandra#define O_SPISTRV0__EG_STRV_THRESH_0 24 646211946Sjchandra#define W_SPISTRV0__EG_STRV_THRESH_0 7 647211946Sjchandra#define O_SPISTRV0__EG_STRV_THRESH_1 16 648211946Sjchandra#define W_SPISTRV0__EG_STRV_THRESH_1 7 649211946Sjchandra#define O_SPISTRV0__EG_STRV_THRESH_2 8 650211946Sjchandra#define W_SPISTRV0__EG_STRV_THRESH_2 7 651211946Sjchandra#define O_SPISTRV0__EG_STRV_THRESH_3 0 652211946Sjchandra#define W_SPISTRV0__EG_STRV_THRESH_3 7 653211946Sjchandra#define R_SPISTRV1 0x21E 654211946Sjchandra#define O_SPISTRV1__EG_STRV_THRESH_4 24 655211946Sjchandra#define W_SPISTRV1__EG_STRV_THRESH_4 7 656211946Sjchandra#define O_SPISTRV1__EG_STRV_THRESH_5 16 657211946Sjchandra#define W_SPISTRV1__EG_STRV_THRESH_5 7 658211946Sjchandra#define O_SPISTRV1__EG_STRV_THRESH_6 8 659211946Sjchandra#define W_SPISTRV1__EG_STRV_THRESH_6 7 660211946Sjchandra#define O_SPISTRV1__EG_STRV_THRESH_7 0 661211946Sjchandra#define W_SPISTRV1__EG_STRV_THRESH_7 7 662211946Sjchandra#define R_SPISTRV2 0x21F 663211946Sjchandra#define O_SPISTRV2__EG_STRV_THRESH_8 24 664211946Sjchandra#define W_SPISTRV2__EG_STRV_THRESH_8 7 665211946Sjchandra#define O_SPISTRV2__EG_STRV_THRESH_9 16 666211946Sjchandra#define W_SPISTRV2__EG_STRV_THRESH_9 7 667211946Sjchandra#define O_SPISTRV2__EG_STRV_THRESH_10 8 668211946Sjchandra#define W_SPISTRV2__EG_STRV_THRESH_10 7 669211946Sjchandra#define O_SPISTRV2__EG_STRV_THRESH_11 0 670211946Sjchandra#define W_SPISTRV2__EG_STRV_THRESH_11 7 671211946Sjchandra#define R_SPISTRV3 0x220 672211946Sjchandra#define O_SPISTRV3__EG_STRV_THRESH_12 24 673211946Sjchandra#define W_SPISTRV3__EG_STRV_THRESH_12 7 674211946Sjchandra#define O_SPISTRV3__EG_STRV_THRESH_13 16 675211946Sjchandra#define W_SPISTRV3__EG_STRV_THRESH_13 7 676211946Sjchandra#define O_SPISTRV3__EG_STRV_THRESH_14 8 677211946Sjchandra#define W_SPISTRV3__EG_STRV_THRESH_14 7 678211946Sjchandra#define O_SPISTRV3__EG_STRV_THRESH_15 0 679211946Sjchandra#define W_SPISTRV3__EG_STRV_THRESH_15 7 680211946Sjchandra#define R_TXDATAFIFO0 0x221 681211946Sjchandra#define O_TXDATAFIFO0__Tx0DataFifoStart 24 682211946Sjchandra#define W_TXDATAFIFO0__Tx0DataFifoStart 7 683211946Sjchandra#define O_TXDATAFIFO0__Tx0DataFifoSize 16 684211946Sjchandra#define W_TXDATAFIFO0__Tx0DataFifoSize 7 685211946Sjchandra#define O_TXDATAFIFO0__Tx1DataFifoStart 8 686211946Sjchandra#define W_TXDATAFIFO0__Tx1DataFifoStart 7 687211946Sjchandra#define O_TXDATAFIFO0__Tx1DataFifoSize 0 688211946Sjchandra#define W_TXDATAFIFO0__Tx1DataFifoSize 7 689211946Sjchandra#define R_TXDATAFIFO1 0x222 690211946Sjchandra#define O_TXDATAFIFO1__Tx2DataFifoStart 24 691211946Sjchandra#define W_TXDATAFIFO1__Tx2DataFifoStart 7 692211946Sjchandra#define O_TXDATAFIFO1__Tx2DataFifoSize 16 693211946Sjchandra#define W_TXDATAFIFO1__Tx2DataFifoSize 7 694211946Sjchandra#define O_TXDATAFIFO1__Tx3DataFifoStart 8 695211946Sjchandra#define W_TXDATAFIFO1__Tx3DataFifoStart 7 696211946Sjchandra#define O_TXDATAFIFO1__Tx3DataFifoSize 0 697211946Sjchandra#define W_TXDATAFIFO1__Tx3DataFifoSize 7 698211946Sjchandra#define R_TXDATAFIFO2 0x223 699211946Sjchandra#define O_TXDATAFIFO2__Tx4DataFifoStart 24 700211946Sjchandra#define W_TXDATAFIFO2__Tx4DataFifoStart 7 701211946Sjchandra#define O_TXDATAFIFO2__Tx4DataFifoSize 16 702211946Sjchandra#define W_TXDATAFIFO2__Tx4DataFifoSize 7 703211946Sjchandra#define O_TXDATAFIFO2__Tx5DataFifoStart 8 704211946Sjchandra#define W_TXDATAFIFO2__Tx5DataFifoStart 7 705211946Sjchandra#define O_TXDATAFIFO2__Tx5DataFifoSize 0 706211946Sjchandra#define W_TXDATAFIFO2__Tx5DataFifoSize 7 707211946Sjchandra#define R_TXDATAFIFO3 0x224 708211946Sjchandra#define O_TXDATAFIFO3__Tx6DataFifoStart 24 709211946Sjchandra#define W_TXDATAFIFO3__Tx6DataFifoStart 7 710211946Sjchandra#define O_TXDATAFIFO3__Tx6DataFifoSize 16 711211946Sjchandra#define W_TXDATAFIFO3__Tx6DataFifoSize 7 712211946Sjchandra#define O_TXDATAFIFO3__Tx7DataFifoStart 8 713211946Sjchandra#define W_TXDATAFIFO3__Tx7DataFifoStart 7 714211946Sjchandra#define O_TXDATAFIFO3__Tx7DataFifoSize 0 715211946Sjchandra#define W_TXDATAFIFO3__Tx7DataFifoSize 7 716211946Sjchandra#define R_TXDATAFIFO4 0x225 717211946Sjchandra#define O_TXDATAFIFO4__Tx8DataFifoStart 24 718211946Sjchandra#define W_TXDATAFIFO4__Tx8DataFifoStart 7 719211946Sjchandra#define O_TXDATAFIFO4__Tx8DataFifoSize 16 720211946Sjchandra#define W_TXDATAFIFO4__Tx8DataFifoSize 7 721211946Sjchandra#define O_TXDATAFIFO4__Tx9DataFifoStart 8 722211946Sjchandra#define W_TXDATAFIFO4__Tx9DataFifoStart 7 723211946Sjchandra#define O_TXDATAFIFO4__Tx9DataFifoSize 0 724211946Sjchandra#define W_TXDATAFIFO4__Tx9DataFifoSize 7 725211946Sjchandra#define R_TXDATAFIFO5 0x226 726211946Sjchandra#define O_TXDATAFIFO5__Tx10DataFifoStart 24 727211946Sjchandra#define W_TXDATAFIFO5__Tx10DataFifoStart 7 728211946Sjchandra#define O_TXDATAFIFO5__Tx10DataFifoSize 16 729211946Sjchandra#define W_TXDATAFIFO5__Tx10DataFifoSize 7 730211946Sjchandra#define O_TXDATAFIFO5__Tx11DataFifoStart 8 731211946Sjchandra#define W_TXDATAFIFO5__Tx11DataFifoStart 7 732211946Sjchandra#define O_TXDATAFIFO5__Tx11DataFifoSize 0 733211946Sjchandra#define W_TXDATAFIFO5__Tx11DataFifoSize 7 734211946Sjchandra#define R_TXDATAFIFO6 0x227 735211946Sjchandra#define O_TXDATAFIFO6__Tx12DataFifoStart 24 736211946Sjchandra#define W_TXDATAFIFO6__Tx12DataFifoStart 7 737211946Sjchandra#define O_TXDATAFIFO6__Tx12DataFifoSize 16 738211946Sjchandra#define W_TXDATAFIFO6__Tx12DataFifoSize 7 739211946Sjchandra#define O_TXDATAFIFO6__Tx13DataFifoStart 8 740211946Sjchandra#define W_TXDATAFIFO6__Tx13DataFifoStart 7 741211946Sjchandra#define O_TXDATAFIFO6__Tx13DataFifoSize 0 742211946Sjchandra#define W_TXDATAFIFO6__Tx13DataFifoSize 7 743211946Sjchandra#define R_TXDATAFIFO7 0x228 744211946Sjchandra#define O_TXDATAFIFO7__Tx14DataFifoStart 24 745211946Sjchandra#define W_TXDATAFIFO7__Tx14DataFifoStart 7 746211946Sjchandra#define O_TXDATAFIFO7__Tx14DataFifoSize 16 747211946Sjchandra#define W_TXDATAFIFO7__Tx14DataFifoSize 7 748211946Sjchandra#define O_TXDATAFIFO7__Tx15DataFifoStart 8 749211946Sjchandra#define W_TXDATAFIFO7__Tx15DataFifoStart 7 750211946Sjchandra#define O_TXDATAFIFO7__Tx15DataFifoSize 0 751211946Sjchandra#define W_TXDATAFIFO7__Tx15DataFifoSize 7 752211946Sjchandra#define R_RXDATAFIFO0 0x229 753211946Sjchandra#define O_RXDATAFIFO0__Rx0DataFifoStart 24 754211946Sjchandra#define W_RXDATAFIFO0__Rx0DataFifoStart 7 755211946Sjchandra#define O_RXDATAFIFO0__Rx0DataFifoSize 16 756211946Sjchandra#define W_RXDATAFIFO0__Rx0DataFifoSize 7 757211946Sjchandra#define O_RXDATAFIFO0__Rx1DataFifoStart 8 758211946Sjchandra#define W_RXDATAFIFO0__Rx1DataFifoStart 7 759211946Sjchandra#define O_RXDATAFIFO0__Rx1DataFifoSize 0 760211946Sjchandra#define W_RXDATAFIFO0__Rx1DataFifoSize 7 761211946Sjchandra#define R_RXDATAFIFO1 0x22A 762211946Sjchandra#define O_RXDATAFIFO1__Rx2DataFifoStart 24 763211946Sjchandra#define W_RXDATAFIFO1__Rx2DataFifoStart 7 764211946Sjchandra#define O_RXDATAFIFO1__Rx2DataFifoSize 16 765211946Sjchandra#define W_RXDATAFIFO1__Rx2DataFifoSize 7 766211946Sjchandra#define O_RXDATAFIFO1__Rx3DataFifoStart 8 767211946Sjchandra#define W_RXDATAFIFO1__Rx3DataFifoStart 7 768211946Sjchandra#define O_RXDATAFIFO1__Rx3DataFifoSize 0 769211946Sjchandra#define W_RXDATAFIFO1__Rx3DataFifoSize 7 770211946Sjchandra#define R_RXDATAFIFO2 0x22B 771211946Sjchandra#define O_RXDATAFIFO2__Rx4DataFifoStart 24 772211946Sjchandra#define W_RXDATAFIFO2__Rx4DataFifoStart 7 773211946Sjchandra#define O_RXDATAFIFO2__Rx4DataFifoSize 16 774211946Sjchandra#define W_RXDATAFIFO2__Rx4DataFifoSize 7 775211946Sjchandra#define O_RXDATAFIFO2__Rx5DataFifoStart 8 776211946Sjchandra#define W_RXDATAFIFO2__Rx5DataFifoStart 7 777211946Sjchandra#define O_RXDATAFIFO2__Rx5DataFifoSize 0 778211946Sjchandra#define W_RXDATAFIFO2__Rx5DataFifoSize 7 779211946Sjchandra#define R_RXDATAFIFO3 0x22C 780211946Sjchandra#define O_RXDATAFIFO3__Rx6DataFifoStart 24 781211946Sjchandra#define W_RXDATAFIFO3__Rx6DataFifoStart 7 782211946Sjchandra#define O_RXDATAFIFO3__Rx6DataFifoSize 16 783211946Sjchandra#define W_RXDATAFIFO3__Rx6DataFifoSize 7 784211946Sjchandra#define O_RXDATAFIFO3__Rx7DataFifoStart 8 785211946Sjchandra#define W_RXDATAFIFO3__Rx7DataFifoStart 7 786211946Sjchandra#define O_RXDATAFIFO3__Rx7DataFifoSize 0 787211946Sjchandra#define W_RXDATAFIFO3__Rx7DataFifoSize 7 788211946Sjchandra#define R_RXDATAFIFO4 0x22D 789211946Sjchandra#define O_RXDATAFIFO4__Rx8DataFifoStart 24 790211946Sjchandra#define W_RXDATAFIFO4__Rx8DataFifoStart 7 791211946Sjchandra#define O_RXDATAFIFO4__Rx8DataFifoSize 16 792211946Sjchandra#define W_RXDATAFIFO4__Rx8DataFifoSize 7 793211946Sjchandra#define O_RXDATAFIFO4__Rx9DataFifoStart 8 794211946Sjchandra#define W_RXDATAFIFO4__Rx9DataFifoStart 7 795211946Sjchandra#define O_RXDATAFIFO4__Rx9DataFifoSize 0 796211946Sjchandra#define W_RXDATAFIFO4__Rx9DataFifoSize 7 797211946Sjchandra#define R_RXDATAFIFO5 0x22E 798211946Sjchandra#define O_RXDATAFIFO5__Rx10DataFifoStart 24 799211946Sjchandra#define W_RXDATAFIFO5__Rx10DataFifoStart 7 800211946Sjchandra#define O_RXDATAFIFO5__Rx10DataFifoSize 16 801211946Sjchandra#define W_RXDATAFIFO5__Rx10DataFifoSize 7 802211946Sjchandra#define O_RXDATAFIFO5__Rx11DataFifoStart 8 803211946Sjchandra#define W_RXDATAFIFO5__Rx11DataFifoStart 7 804211946Sjchandra#define O_RXDATAFIFO5__Rx11DataFifoSize 0 805211946Sjchandra#define W_RXDATAFIFO5__Rx11DataFifoSize 7 806211946Sjchandra#define R_RXDATAFIFO6 0x22F 807211946Sjchandra#define O_RXDATAFIFO6__Rx12DataFifoStart 24 808211946Sjchandra#define W_RXDATAFIFO6__Rx12DataFifoStart 7 809211946Sjchandra#define O_RXDATAFIFO6__Rx12DataFifoSize 16 810211946Sjchandra#define W_RXDATAFIFO6__Rx12DataFifoSize 7 811211946Sjchandra#define O_RXDATAFIFO6__Rx13DataFifoStart 8 812211946Sjchandra#define W_RXDATAFIFO6__Rx13DataFifoStart 7 813211946Sjchandra#define O_RXDATAFIFO6__Rx13DataFifoSize 0 814211946Sjchandra#define W_RXDATAFIFO6__Rx13DataFifoSize 7 815211946Sjchandra#define R_RXDATAFIFO7 0x230 816211946Sjchandra#define O_RXDATAFIFO7__Rx14DataFifoStart 24 817211946Sjchandra#define W_RXDATAFIFO7__Rx14DataFifoStart 7 818211946Sjchandra#define O_RXDATAFIFO7__Rx14DataFifoSize 16 819211946Sjchandra#define W_RXDATAFIFO7__Rx14DataFifoSize 7 820211946Sjchandra#define O_RXDATAFIFO7__Rx15DataFifoStart 8 821211946Sjchandra#define W_RXDATAFIFO7__Rx15DataFifoStart 7 822211946Sjchandra#define O_RXDATAFIFO7__Rx15DataFifoSize 0 823211946Sjchandra#define W_RXDATAFIFO7__Rx15DataFifoSize 7 824211946Sjchandra#define R_XGMACPADCALIBRATION 0x231 825211946Sjchandra#define R_FREEQCARVE 0x233 826211946Sjchandra#define R_SPI4STATICDELAY0 0x240 827211946Sjchandra#define O_SPI4STATICDELAY0__DataLine7 28 828211946Sjchandra#define W_SPI4STATICDELAY0__DataLine7 4 829211946Sjchandra#define O_SPI4STATICDELAY0__DataLine6 24 830211946Sjchandra#define W_SPI4STATICDELAY0__DataLine6 4 831211946Sjchandra#define O_SPI4STATICDELAY0__DataLine5 20 832211946Sjchandra#define W_SPI4STATICDELAY0__DataLine5 4 833211946Sjchandra#define O_SPI4STATICDELAY0__DataLine4 16 834211946Sjchandra#define W_SPI4STATICDELAY0__DataLine4 4 835211946Sjchandra#define O_SPI4STATICDELAY0__DataLine3 12 836211946Sjchandra#define W_SPI4STATICDELAY0__DataLine3 4 837211946Sjchandra#define O_SPI4STATICDELAY0__DataLine2 8 838211946Sjchandra#define W_SPI4STATICDELAY0__DataLine2 4 839211946Sjchandra#define O_SPI4STATICDELAY0__DataLine1 4 840211946Sjchandra#define W_SPI4STATICDELAY0__DataLine1 4 841211946Sjchandra#define O_SPI4STATICDELAY0__DataLine0 0 842211946Sjchandra#define W_SPI4STATICDELAY0__DataLine0 4 843211946Sjchandra#define R_SPI4STATICDELAY1 0x241 844211946Sjchandra#define O_SPI4STATICDELAY1__DataLine15 28 845211946Sjchandra#define W_SPI4STATICDELAY1__DataLine15 4 846211946Sjchandra#define O_SPI4STATICDELAY1__DataLine14 24 847211946Sjchandra#define W_SPI4STATICDELAY1__DataLine14 4 848211946Sjchandra#define O_SPI4STATICDELAY1__DataLine13 20 849211946Sjchandra#define W_SPI4STATICDELAY1__DataLine13 4 850211946Sjchandra#define O_SPI4STATICDELAY1__DataLine12 16 851211946Sjchandra#define W_SPI4STATICDELAY1__DataLine12 4 852211946Sjchandra#define O_SPI4STATICDELAY1__DataLine11 12 853211946Sjchandra#define W_SPI4STATICDELAY1__DataLine11 4 854211946Sjchandra#define O_SPI4STATICDELAY1__DataLine10 8 855211946Sjchandra#define W_SPI4STATICDELAY1__DataLine10 4 856211946Sjchandra#define O_SPI4STATICDELAY1__DataLine9 4 857211946Sjchandra#define W_SPI4STATICDELAY1__DataLine9 4 858211946Sjchandra#define O_SPI4STATICDELAY1__DataLine8 0 859211946Sjchandra#define W_SPI4STATICDELAY1__DataLine8 4 860211946Sjchandra#define R_SPI4STATICDELAY2 0x242 861211946Sjchandra#define O_SPI4STATICDELAY0__TxStat1 8 862211946Sjchandra#define W_SPI4STATICDELAY0__TxStat1 4 863211946Sjchandra#define O_SPI4STATICDELAY0__TxStat0 4 864211946Sjchandra#define W_SPI4STATICDELAY0__TxStat0 4 865211946Sjchandra#define O_SPI4STATICDELAY0__RxControl 0 866211946Sjchandra#define W_SPI4STATICDELAY0__RxControl 4 867211946Sjchandra#define R_SPI4CONTROL 0x243 868211946Sjchandra#define O_SPI4CONTROL__StaticDelay 2 869211946Sjchandra#define O_SPI4CONTROL__LVDS_LVTTL 1 870211946Sjchandra#define O_SPI4CONTROL__SPI4Enable 0 871211946Sjchandra#define R_CLASSWATERMARKS 0x244 872211946Sjchandra#define O_CLASSWATERMARKS__Class0Watermark 24 873211946Sjchandra#define W_CLASSWATERMARKS__Class0Watermark 5 874211946Sjchandra#define O_CLASSWATERMARKS__Class1Watermark 16 875211946Sjchandra#define W_CLASSWATERMARKS__Class1Watermark 5 876211946Sjchandra#define O_CLASSWATERMARKS__Class3Watermark 0 877211946Sjchandra#define W_CLASSWATERMARKS__Class3Watermark 5 878211946Sjchandra#define R_RXWATERMARKS1 0x245 879211946Sjchandra#define O_RXWATERMARKS__Rx0DataWatermark 24 880211946Sjchandra#define W_RXWATERMARKS__Rx0DataWatermark 7 881211946Sjchandra#define O_RXWATERMARKS__Rx1DataWatermark 16 882211946Sjchandra#define W_RXWATERMARKS__Rx1DataWatermark 7 883211946Sjchandra#define O_RXWATERMARKS__Rx3DataWatermark 0 884211946Sjchandra#define W_RXWATERMARKS__Rx3DataWatermark 7 885211946Sjchandra#define R_RXWATERMARKS2 0x246 886211946Sjchandra#define O_RXWATERMARKS__Rx4DataWatermark 24 887211946Sjchandra#define W_RXWATERMARKS__Rx4DataWatermark 7 888211946Sjchandra#define O_RXWATERMARKS__Rx5DataWatermark 16 889211946Sjchandra#define W_RXWATERMARKS__Rx5DataWatermark 7 890211946Sjchandra#define O_RXWATERMARKS__Rx6DataWatermark 8 891211946Sjchandra#define W_RXWATERMARKS__Rx6DataWatermark 7 892211946Sjchandra#define O_RXWATERMARKS__Rx7DataWatermark 0 893211946Sjchandra#define W_RXWATERMARKS__Rx7DataWatermark 7 894211946Sjchandra#define R_RXWATERMARKS3 0x247 895211946Sjchandra#define O_RXWATERMARKS__Rx8DataWatermark 24 896211946Sjchandra#define W_RXWATERMARKS__Rx8DataWatermark 7 897211946Sjchandra#define O_RXWATERMARKS__Rx9DataWatermark 16 898211946Sjchandra#define W_RXWATERMARKS__Rx9DataWatermark 7 899211946Sjchandra#define O_RXWATERMARKS__Rx10DataWatermark 8 900211946Sjchandra#define W_RXWATERMARKS__Rx10DataWatermark 7 901211946Sjchandra#define O_RXWATERMARKS__Rx11DataWatermark 0 902211946Sjchandra#define W_RXWATERMARKS__Rx11DataWatermark 7 903211946Sjchandra#define R_RXWATERMARKS4 0x248 904211946Sjchandra#define O_RXWATERMARKS__Rx12DataWatermark 24 905211946Sjchandra#define W_RXWATERMARKS__Rx12DataWatermark 7 906211946Sjchandra#define O_RXWATERMARKS__Rx13DataWatermark 16 907211946Sjchandra#define W_RXWATERMARKS__Rx13DataWatermark 7 908211946Sjchandra#define O_RXWATERMARKS__Rx14DataWatermark 8 909211946Sjchandra#define W_RXWATERMARKS__Rx14DataWatermark 7 910211946Sjchandra#define O_RXWATERMARKS__Rx15DataWatermark 0 911211946Sjchandra#define W_RXWATERMARKS__Rx15DataWatermark 7 912211946Sjchandra#define R_FREEWATERMARKS 0x249 913211946Sjchandra#define O_FREEWATERMARKS__FreeOutWatermark 16 914211946Sjchandra#define W_FREEWATERMARKS__FreeOutWatermark 16 915211946Sjchandra#define O_FREEWATERMARKS__JumFrWatermark 8 916211946Sjchandra#define W_FREEWATERMARKS__JumFrWatermark 7 917211946Sjchandra#define O_FREEWATERMARKS__RegFrWatermark 0 918211946Sjchandra#define W_FREEWATERMARKS__RegFrWatermark 7 919211946Sjchandra#define R_EGRESSFIFOCARVINGSLOTS 0x24a 920211946Sjchandra 921211946Sjchandra#define CTRL_RES0 0 922211946Sjchandra#define CTRL_RES1 1 923211946Sjchandra#define CTRL_REG_FREE 2 924211946Sjchandra#define CTRL_JUMBO_FREE 3 925211946Sjchandra#define CTRL_CONT 4 926211946Sjchandra#define CTRL_EOP 5 927211946Sjchandra#define CTRL_START 6 928211946Sjchandra#define CTRL_SNGL 7 929211946Sjchandra 930211946Sjchandra#define CTRL_B0_NOT_EOP 0 931211946Sjchandra#define CTRL_B0_EOP 1 932211946Sjchandra 933211946Sjchandra#define R_ROUND_ROBIN_TABLE 0 934211946Sjchandra#define R_PDE_CLASS_0 0x300 935211946Sjchandra#define R_PDE_CLASS_1 0x302 936211946Sjchandra#define R_PDE_CLASS_2 0x304 937211946Sjchandra#define R_PDE_CLASS_3 0x306 938211946Sjchandra 939211946Sjchandra#define R_MSG_TX_THRESHOLD 0x308 940211946Sjchandra 941211946Sjchandra#define R_GMAC_JFR0_BUCKET_SIZE 0x320 942211946Sjchandra#define R_GMAC_RFR0_BUCKET_SIZE 0x321 943211946Sjchandra#define R_GMAC_TX0_BUCKET_SIZE 0x322 944211946Sjchandra#define R_GMAC_TX1_BUCKET_SIZE 0x323 945211946Sjchandra#define R_GMAC_TX2_BUCKET_SIZE 0x324 946211946Sjchandra#define R_GMAC_TX3_BUCKET_SIZE 0x325 947211946Sjchandra#define R_GMAC_JFR1_BUCKET_SIZE 0x326 948211946Sjchandra#define R_GMAC_RFR1_BUCKET_SIZE 0x327 949211946Sjchandra 950211946Sjchandra#define R_XGS_TX0_BUCKET_SIZE 0x320 951211946Sjchandra#define R_XGS_TX1_BUCKET_SIZE 0x321 952211946Sjchandra#define R_XGS_TX2_BUCKET_SIZE 0x322 953211946Sjchandra#define R_XGS_TX3_BUCKET_SIZE 0x323 954211946Sjchandra#define R_XGS_TX4_BUCKET_SIZE 0x324 955211946Sjchandra#define R_XGS_TX5_BUCKET_SIZE 0x325 956211946Sjchandra#define R_XGS_TX6_BUCKET_SIZE 0x326 957211946Sjchandra#define R_XGS_TX7_BUCKET_SIZE 0x327 958211946Sjchandra#define R_XGS_TX8_BUCKET_SIZE 0x328 959211946Sjchandra#define R_XGS_TX9_BUCKET_SIZE 0x329 960211946Sjchandra#define R_XGS_TX10_BUCKET_SIZE 0x32A 961211946Sjchandra#define R_XGS_TX11_BUCKET_SIZE 0x32B 962211946Sjchandra#define R_XGS_TX12_BUCKET_SIZE 0x32C 963211946Sjchandra#define R_XGS_TX13_BUCKET_SIZE 0x32D 964211946Sjchandra#define R_XGS_TX14_BUCKET_SIZE 0x32E 965211946Sjchandra#define R_XGS_TX15_BUCKET_SIZE 0x32F 966211946Sjchandra#define R_XGS_JFR_BUCKET_SIZE 0x330 967211946Sjchandra#define R_XGS_RFR_BUCKET_SIZE 0x331 968211946Sjchandra 969211946Sjchandra#define R_CC_CPU0_0 0x380 970211946Sjchandra#define R_CC_CPU1_0 0x388 971211946Sjchandra#define R_CC_CPU2_0 0x390 972211946Sjchandra#define R_CC_CPU3_0 0x398 973211946Sjchandra#define R_CC_CPU4_0 0x3a0 974211946Sjchandra#define R_CC_CPU5_0 0x3a8 975211946Sjchandra#define R_CC_CPU6_0 0x3b0 976211946Sjchandra#define R_CC_CPU7_0 0x3b8 977211946Sjchandra 978211946Sjchandra#define XLR_GMAC_BLK_SZ (XLR_IO_GMAC_1_OFFSET - \ 979211946Sjchandra XLR_IO_GMAC_0_OFFSET) 980211946Sjchandra 981211946Sjchandra/* Constants used for configuring the devices */ 982211946Sjchandra 983211946Sjchandra#define RGE_TX_THRESHOLD 1024 984211946Sjchandra#define RGE_TX_Q_SIZE 1024 985211946Sjchandra 986211946Sjchandra#define MAC_B2B_IPG 88 987211946Sjchandra 988215939Sjchandra#define NLGE_PREPAD_LEN 32 989215939Sjchandra 990211946Sjchandra/* frame sizes need to be cacheline aligned */ 991215939Sjchandra#define MAX_FRAME_SIZE (1536 + NLGE_PREPAD_LEN) 992211946Sjchandra#define MAX_FRAME_SIZE_JUMBO 9216 993211946Sjchandra#define RGE_TX_THRESHOLD_BYTES ETHER_MAX_LEN 994211946Sjchandra 995211946Sjchandra#define MAC_SKB_BACK_PTR_SIZE SMP_CACHE_BYTES 996211946Sjchandra#define MAC_PREPAD 0 997211946Sjchandra#define BYTE_OFFSET 2 998211946Sjchandra#define XLR_RX_BUF_SIZE (MAX_FRAME_SIZE + BYTE_OFFSET + \ 999211946Sjchandra MAC_PREPAD + MAC_SKB_BACK_PTR_SIZE + SMP_CACHE_BYTES) 1000211946Sjchandra#define MAC_CRC_LEN 4 1001211946Sjchandra#define MAX_NUM_MSGRNG_STN_CC 128 1002211946Sjchandra#define MAX_MSG_SND_ATTEMPTS 100 /* 13 stns x 4 entry msg/stn + 1003211946Sjchandra headroom */ 1004211946Sjchandra 1005211946Sjchandra#define MAC_FRIN_TO_BE_SENT_THRESHOLD 16 1006211946Sjchandra 1007211946Sjchandra#define MAX_NUM_DESC_SPILL 1024 1008211946Sjchandra#define MAX_FRIN_SPILL (MAX_NUM_DESC_SPILL << 2) 1009211946Sjchandra#define MAX_FROUT_SPILL (MAX_NUM_DESC_SPILL << 2) 1010211946Sjchandra#define MAX_CLASS_0_SPILL (MAX_NUM_DESC_SPILL << 2) 1011211946Sjchandra#define MAX_CLASS_1_SPILL (MAX_NUM_DESC_SPILL << 2) 1012211946Sjchandra#define MAX_CLASS_2_SPILL (MAX_NUM_DESC_SPILL << 2) 1013211946Sjchandra#define MAX_CLASS_3_SPILL (MAX_NUM_DESC_SPILL << 2) 1014211946Sjchandra 1015211946Sjchandra#define XLR_MAX_CORE 8 1016211946Sjchandra 1017211946Sjchandra#define XLR_MAX_NLNA 3 1018211946Sjchandra#define XLR_MAX_MACS 8 1019211946Sjchandra#define XLR_MAX_TX_FRAGS 14 1020211946Sjchandra#define MAX_P2D_DESC_PER_PORT 512 1021211946Sjchandra 1022211946Sjchandra#define PHY_STATUS_RETRIES 25000 1023211946Sjchandra 1024211946Sjchandra/* Structs representing hardware data structures */ 1025211946Sjchandrastruct size_1_desc { 1026211946Sjchandra uint64_t entry0; 1027211946Sjchandra}; 1028211946Sjchandra 1029211946Sjchandrastruct size_2_desc { 1030211946Sjchandra uint64_t entry0; 1031211946Sjchandra uint64_t entry1; 1032211946Sjchandra}; 1033211946Sjchandra 1034211946Sjchandrastruct size_3_desc { 1035211946Sjchandra uint64_t entry0; 1036211946Sjchandra uint64_t entry1; 1037211946Sjchandra uint64_t entry2; 1038211946Sjchandra}; 1039211946Sjchandra 1040211946Sjchandrastruct size_4_desc { 1041211946Sjchandra uint64_t entry0; 1042211946Sjchandra uint64_t entry1; 1043211946Sjchandra uint64_t entry2; 1044211946Sjchandra uint64_t entry3; 1045211946Sjchandra}; 1046211946Sjchandra 1047211946Sjchandrastruct fr_desc { 1048211946Sjchandra struct size_1_desc d1; 1049211946Sjchandra}; 1050211946Sjchandra 1051211946Sjchandraunion rx_tx_desc { 1052211946Sjchandra struct size_2_desc d2; 1053211946Sjchandra /* struct size_3_desc d3; */ 1054211946Sjchandra /* struct size_4_desc d4; */ 1055211946Sjchandra}; 1056211946Sjchandra 1057211946Sjchandra 1058211946Sjchandraextern unsigned char xlr_base_mac_addr[]; 1059211946Sjchandra 1060211946Sjchandra/* Driver data structures and enums */ 1061211946Sjchandra 1062211946Sjchandratypedef enum { 1063211946Sjchandra xlr_mac_speed_10, xlr_mac_speed_100, 1064211946Sjchandra xlr_mac_speed_1000, xlr_mac_speed_rsvd 1065211946Sjchandra} xlr_mac_speed_t; 1066211946Sjchandra 1067211946Sjchandratypedef enum { 1068211946Sjchandra xlr_mac_duplex_auto, xlr_mac_duplex_half, 1069211946Sjchandra xlr_mac_duplex_full 1070211946Sjchandra} xlr_mac_duplex_t; 1071211946Sjchandra 1072211946Sjchandratypedef enum { 1073211946Sjchandra xlr_mac_link_down, 1074211946Sjchandra xlr_mac_link_up, 1075211946Sjchandra} xlr_mac_link_t; 1076211946Sjchandra 1077211946Sjchandratypedef enum { 1078211946Sjchandra xlr_mac_fc_auto, xlr_mac_fc_disabled, xlr_mac_fc_frame, 1079211946Sjchandra xlr_mac_fc_collision, xlr_mac_fc_carrier 1080211946Sjchandra} xlr_mac_fc_t; 1081211946Sjchandra 1082211946Sjchandraenum { 1083211946Sjchandra SGMII_SPEED_10 = 0x00000000, 1084211946Sjchandra SGMII_SPEED_100 = 0x02000000, 1085211946Sjchandra SGMII_SPEED_1000 = 0x04000000, 1086211946Sjchandra}; 1087211946Sjchandra 1088211946Sjchandrastruct nlge_softc; 1089211946Sjchandra 1090211946Sjchandra/* 1091211946Sjchandra * A data-structure to hold a set of related ports. The "sense" in which they 1092211946Sjchandra * are related is defined by the user of this data-structure. 1093211946Sjchandra * 1094211946Sjchandra * One example: a set of ports that are controlled thru a single MDIO line. 1095211946Sjchandra */ 1096211946Sjchandrastruct nlge_port_set { 1097211946Sjchandra struct nlge_softc **port_vec; 1098211946Sjchandra uint32_t vec_sz; 1099211946Sjchandra}; 1100211946Sjchandra 1101211946Sjchandra/* 1102211946Sjchandra * nlna_softc has Network Accelerator (NA) attributes that are necessary to 1103211946Sjchandra * configure the h/w registers of this block. All the commmon configuration 1104211946Sjchandra * for a set of GMAC ports controlled by an NA is done from here. 1105211946Sjchandra */ 1106211946Sjchandrastruct nlna_softc { 1107213475Sjchandra device_t nlna_dev; 1108211946Sjchandra 1109213475Sjchandra uint32_t num_ports; 1110213475Sjchandra int na_type; 1111213475Sjchandra int mac_type; 1112213475Sjchandra xlr_reg_t *base; 1113211946Sjchandra 1114211946Sjchandra struct fr_desc *frin_spill; 1115211946Sjchandra struct fr_desc *frout_spill; 1116211946Sjchandra union rx_tx_desc *class_0_spill; 1117211946Sjchandra union rx_tx_desc *class_1_spill; 1118211946Sjchandra union rx_tx_desc *class_2_spill; 1119211946Sjchandra union rx_tx_desc *class_3_spill; 1120211946Sjchandra uint32_t rfrbucket; 1121211946Sjchandra uint32_t station_id; 1122211946Sjchandra 1123211946Sjchandra struct nlge_softc *child_sc[XLR_MAX_MACS]; 1124211946Sjchandra 1125211946Sjchandra /* 1126211946Sjchandra * Set of ports controlled/configured by the MII line 1127211946Sjchandra * of this network accelerator. 1128211946Sjchandra */ 1129211946Sjchandra struct nlge_port_set mdio_set; 1130211946Sjchandra struct nlge_softc *mdio_sc[XLR_MAX_MACS]; 1131211946Sjchandra}; 1132211946Sjchandra 1133211946Sjchandrastruct nlge_softc { 1134211946Sjchandra struct ifnet *nlge_if; /* should be first member - cf. 1135211946Sjchandra mii.c:miibus_attach() */ 1136211946Sjchandra struct mii_data nlge_mii; 1137211946Sjchandra struct nlge_port_set *mdio_pset; 1138213475Sjchandra device_t nlge_dev; 1139211946Sjchandra device_t mii_bus; 1140213475Sjchandra xlr_reg_t *base; 1141213475Sjchandra xlr_reg_t *mii_base; 1142213475Sjchandra xlr_reg_t *pcs_addr; 1143213475Sjchandra xlr_reg_t *serdes_addr; 1144213475Sjchandra int port_type; 1145213475Sjchandra int if_flags; 1146211946Sjchandra xlr_mac_speed_t speed; 1147211946Sjchandra xlr_mac_duplex_t duplex; 1148211946Sjchandra xlr_mac_link_t link; 1149211946Sjchandra xlr_mac_fc_t flow_ctrl; 1150213475Sjchandra uint32_t id; 1151213475Sjchandra uint32_t instance; 1152211946Sjchandra uint32_t phy_addr; 1153211946Sjchandra uint32_t tx_bucket_id; 1154211946Sjchandra uint8_t dev_addr[ETHER_ADDR_LEN]; 1155211946Sjchandra struct mtx sc_lock; 1156211946Sjchandra}; 1157211946Sjchandra 1158211946Sjchandra 1159211946Sjchandrastruct nlge_tx_desc { 1160211946Sjchandra uint64_t frag[XLR_MAX_TX_FRAGS + 2]; 1161211946Sjchandra}; 1162211946Sjchandra 1163211946Sjchandra#define MAX_TX_RING_SIZE (XLR_MAX_MACS * MAX_P2D_DESC_PER_PORT *\ 1164211946Sjchandra sizeof(struct p2d_tx_desc)) 1165211946Sjchandra 1166211946Sjchandra#define NLGE_WRITE(base, off, val) xlr_write_reg(base, off, val) 1167211946Sjchandra#define NLGE_READ(base, off) xlr_read_reg(base, off) 1168211946Sjchandra#define NLGE_UPDATE(base, off, val, mask) \ 1169211946Sjchandra do { \ 1170211946Sjchandra uint32_t rd_val, wrt_val; \ 1171211946Sjchandra rd_val = NLGE_READ(base, off); \ 1172211946Sjchandra wrt_val = (rd_val & ~mask) | (val & mask); \ 1173211946Sjchandra NLGE_WRITE(base, off, wrt_val); \ 1174211946Sjchandra } while (0) 1175211946Sjchandra 1176211946Sjchandra#define NLGE_LOCK_INIT(_sc, _name) \ 1177211946Sjchandra mtx_init(&(_sc)->sc_lock, _name, MTX_NETWORK_LOCK, MTX_DEF) 1178211946Sjchandra#define NLGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_lock) 1179211946Sjchandra#define NLGE_LOCK(_sc) mtx_lock(&(_sc)->sc_lock) 1180211946Sjchandra#define NLGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_lock) 1181211946Sjchandra#define NLGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_lock, MA_OWNED) 1182211946Sjchandra 1183