1198160Srrs/********************************************************************* 2198160Srrs * 3198160Srrs * Copyright 2003-2006 Raza Microelectronics, Inc. (RMI). All rights 4198160Srrs * reserved. 5198160Srrs * 6198160Srrs * Redistribution and use in source and binary forms, with or without 7198160Srrs * modification, are permitted provided that the following conditions 8198160Srrs * are met: 9198160Srrs * 10198160Srrs * 1. Redistributions of source code must retain the above copyright 11198160Srrs * notice, this list of conditions and the following disclaimer. 12198160Srrs * 2. Redistributions in binary form must reproduce the above copyright 13198160Srrs * notice, this list of conditions and the following disclaimer in 14198160Srrs * the documentation and/or other materials provided with the 15198160Srrs * distribution. 16198160Srrs * 17198160Srrs * THIS SOFTWARE IS PROVIDED BY Raza Microelectronics, Inc. ``AS IS'' AND 18198160Srrs * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19198160Srrs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20198160Srrs * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE 21198160Srrs * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22198160Srrs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23198160Srrs * SUBSTITUTE GOODS OR SERVICES, LOSS OF USE, DATA, OR PROFITS, OR BUSINESS 24198160Srrs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25198160Srrs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26198160Srrs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27198160Srrs * THE POSSIBILITY OF SUCH DAMAGE. 28198160Srrs * 29198160Srrs * *****************************RMI_2**********************************/ 30204137Srrs#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 31204137Srrs__FBSDID("$FreeBSD$"); 32198160Srrs#include <sys/param.h> 33198160Srrs#include <sys/systm.h> 34198160Srrs#include <sys/bus.h> 35198160Srrs#include <sys/kernel.h> 36198160Srrs#include <sys/lock.h> 37198160Srrs#include <sys/mutex.h> 38198160Srrs 39198160Srrs#include <machine/cpufunc.h> 40198607Srrs#include <mips/rmi/msgring.h> 41211994Sjchandra#include <mips/rmi/rmi_boot_info.h> 42198607Srrs#include <mips/rmi/board.h> 43198607Srrs#include <mips/rmi/pic.h> 44198160Srrs 45216390Sjchandra#define XLR_I2C_RTC_ADDR 0xd0 46216390Sjchandra#define XLR_I2C_EEPROM_ADDR 0xa0 47216390Sjchandra#define XLR_I2C_TEMPSENSOR_ADDR 0x98 48216390Sjchandra#define XLR_I2C_ATX8_TEMPSENSOR_ADDR 0x9a 49216390Sjchandra 50211946Sjchandrastruct stn_cc *xlr_core_cc_configs[] = { &cc_table_cpu_0, &cc_table_cpu_1, 51211946Sjchandra &cc_table_cpu_2, &cc_table_cpu_3, &cc_table_cpu_4, &cc_table_cpu_5, 52211946Sjchandra &cc_table_cpu_6, &cc_table_cpu_7}; 53198160Srrs 54211946Sjchandrastruct stn_cc *xls_core_cc_configs[] = { &xls_cc_table_cpu_0, &xls_cc_table_cpu_1, 55211946Sjchandra &xls_cc_table_cpu_2, &xls_cc_table_cpu_3 }; 56198160Srrs 57198160Srrsstruct xlr_board_info xlr_board_info; 58198160Srrs 59211923Sjchandrastatic int 60211923Sjchandraxlr_pcmcia_present(void) 61211923Sjchandra{ 62211923Sjchandra xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET); 63211923Sjchandra uint32_t resetconf; 64211923Sjchandra 65211923Sjchandra resetconf = xlr_read_reg(mmio, 21); 66211923Sjchandra return ((resetconf & 0x4000) != 0); 67211923Sjchandra} 68211923Sjchandra 69211946Sjchandrastatic void 70213448Sjchandraxlr_chip_specific_overrides(struct xlr_board_info* board) 71213448Sjchandra{ 72213448Sjchandra struct xlr_gmac_block_t *blk0, *blk1, *blk2; 73213448Sjchandra uint32_t chipid; 74213448Sjchandra uint32_t revision; 75213448Sjchandra 76213448Sjchandra blk0 = &board->gmac_block[0]; 77213448Sjchandra blk1 = &board->gmac_block[1]; 78213448Sjchandra blk2 = &board->gmac_block[2]; 79213448Sjchandra 80213448Sjchandra chipid = xlr_processor_id(); 81213448Sjchandra revision = xlr_revision(); 82213448Sjchandra 83213448Sjchandra if (revision == 0x04) { /* B2 */ 84213448Sjchandra switch (chipid) { 85213448Sjchandra case 0x07: /* XLR 508 */ 86213448Sjchandra case 0x08: /* XLR 516 */ 87213448Sjchandra case 0x09: /* XLR 532 */ 88213448Sjchandra /* NA[12] not available */ 89213448Sjchandra memset(blk1, 0, sizeof(*blk1)); 90213448Sjchandra memset(blk2, 0, sizeof(*blk2)); 91213448Sjchandra break; 92213448Sjchandra case 0x06: /* XLR 308 */ 93213448Sjchandra /* NA0 has 3 ports */ 94213448Sjchandra blk0->gmac_port[3].valid = 0; 95213448Sjchandra blk0->num_ports--; 96213448Sjchandra /* NA[12] not available */ 97213448Sjchandra memset(blk1, 0, sizeof(*blk1)); 98213448Sjchandra memset(blk2, 0, sizeof(*blk2)); 99213448Sjchandra break; 100213448Sjchandra default: 101213448Sjchandra break; 102213448Sjchandra } 103213448Sjchandra } else if (revision == 0x91) { /* C4 */ 104213448Sjchandra switch (chipid) { 105213448Sjchandra case 0x0B: /* XLR 508 */ 106213448Sjchandra case 0x0A: /* XLR 516 */ 107213448Sjchandra case 0x08: /* XLR 532 */ 108213448Sjchandra /* NA[12] not available */ 109213448Sjchandra memset(blk1, 0, sizeof(*blk1)); 110213448Sjchandra memset(blk2, 0, sizeof(*blk2)); 111213448Sjchandra break; 112213448Sjchandra case 0x0F: /* XLR 308 */ 113213448Sjchandra /* NA0 has 3 ports */ 114213448Sjchandra blk0->gmac_port[3].valid = 0; 115213448Sjchandra blk0->num_ports--; 116213448Sjchandra /* NA[12] not available */ 117213448Sjchandra memset(blk1, 0, sizeof(*blk1)); 118213448Sjchandra memset(blk2, 0, sizeof(*blk2)); 119213448Sjchandra break; 120213448Sjchandra default: 121213448Sjchandra break; 122213448Sjchandra } 123213448Sjchandra } else { /* other pre-production silicon */ 124213448Sjchandra switch (chipid) { 125213448Sjchandra /* XLR 5xx */ 126213448Sjchandra case 0x0B: 127213448Sjchandra case 0x0A: 128213448Sjchandra case 0x07: 129213448Sjchandra case 0x08: 130213448Sjchandra case 0x09: 131213448Sjchandra /* NA[12] not available */ 132213448Sjchandra memset(blk1, 0, sizeof(*blk1)); 133213448Sjchandra memset(blk2, 0, sizeof(*blk2)); 134213448Sjchandra break; 135213448Sjchandra /* XLR 3xx */ 136213448Sjchandra case 0x0F: 137213448Sjchandra case 0x06: 138213448Sjchandra /* NA0 has 3 ports */ 139213448Sjchandra blk0->gmac_port[3].valid = 0; 140213448Sjchandra blk0->num_ports--; 141213448Sjchandra /* NA[12] not available */ 142213448Sjchandra memset(blk1, 0, sizeof(*blk1)); 143213448Sjchandra memset(blk2, 0, sizeof(*blk2)); 144213448Sjchandra break; 145213448Sjchandra default: 146213448Sjchandra break; 147213448Sjchandra } 148213448Sjchandra } 149213448Sjchandra} 150213448Sjchandra 151213448Sjchandrastatic void 152211946Sjchandraxlr_board_specific_overrides(struct xlr_board_info* board) 153211946Sjchandra{ 154211946Sjchandra struct xlr_gmac_block_t *blk1, *blk2; 155211946Sjchandra 156211946Sjchandra blk1 = &board->gmac_block[1]; 157211946Sjchandra blk2 = &board->gmac_block[2]; 158211946Sjchandra 159211946Sjchandra switch (xlr_boot1_info.board_major_version) { 160211946Sjchandra case RMI_XLR_BOARD_ARIZONA_I: 161211946Sjchandra /* ATX-I has SPI-4, not XGMAC */ 162211946Sjchandra blk1->type = XLR_SPI4; 163211946Sjchandra blk1->enabled = 0; /* nlge does not 164211946Sjchandra support SPI-4 */ 165211946Sjchandra blk2->type = XLR_SPI4; 166211946Sjchandra blk2->enabled = 0; 167211946Sjchandra break; 168211946Sjchandra 169211946Sjchandra case RMI_XLR_BOARD_ARIZONA_II: 170211946Sjchandra /* XGMII_A --> VSC7281, XGMII_B --> VSC7281 */ 171211946Sjchandra blk1->enabled = 1; 172211946Sjchandra blk1->num_ports = 1; 173211946Sjchandra blk1->gmac_port[0].valid = 1; 174211946Sjchandra 175211946Sjchandra blk2->enabled = 1; 176211946Sjchandra blk2->num_ports = 1; 177211946Sjchandra blk2->gmac_port[0].valid = 1; 178211946Sjchandra default: 179211946Sjchandra break; 180211946Sjchandra } 181211946Sjchandra} 182211946Sjchandra 183211946Sjchandrastatic int 184211946Sjchandraquad0_xaui(void) 185211946Sjchandra{ 186211946Sjchandra xlr_reg_t *gpio_mmio = 187211946Sjchandra (unsigned int *)(DEFAULT_XLR_IO_BASE + XLR_IO_GPIO_OFFSET); 188211946Sjchandra uint32_t bit24; 189211946Sjchandra 190211946Sjchandra bit24 = (xlr_read_reg(gpio_mmio, 0x15) >> 24) & 0x1; 191211946Sjchandra return (bit24); 192211946Sjchandra} 193211946Sjchandra 194211946Sjchandrastatic int 195211946Sjchandraquad1_xaui(void) 196211946Sjchandra{ 197211946Sjchandra xlr_reg_t *gpio_mmio = 198211946Sjchandra (unsigned int *)(DEFAULT_XLR_IO_BASE + XLR_IO_GPIO_OFFSET); 199211946Sjchandra uint32_t bit25; 200211946Sjchandra 201211946Sjchandra bit25 = (xlr_read_reg(gpio_mmio, 0x15) >> 25) & 0x1; 202211946Sjchandra return (bit25); 203211946Sjchandra} 204211946Sjchandra 205211946Sjchandrastatic void 206213448Sjchandraxls_chip_specific_overrides(struct xlr_board_info* board) 207213448Sjchandra{ 208213448Sjchandra struct xlr_gmac_block_t *blk0, *blk1; 209213448Sjchandra uint32_t chipid; 210213448Sjchandra 211213448Sjchandra blk0 = &board->gmac_block[0]; 212213448Sjchandra blk1 = &board->gmac_block[1]; 213213448Sjchandra chipid = xlr_processor_id(); 214213448Sjchandra 215213448Sjchandra switch (chipid) { 216213448Sjchandra case 0x8E: /* XLS208 */ 217213448Sjchandra case 0x8F: /* XLS204 */ 218213448Sjchandra /* NA1 is not available */ 219213448Sjchandra memset(blk1, 0, sizeof(*blk1)); 220213448Sjchandra break; 221213448Sjchandra case 0xCE: /* XLS108 */ 222213448Sjchandra case 0xCF: /* XLS104 */ 223213448Sjchandra /* NA0 has 3 ports */ 224213448Sjchandra blk0->gmac_port[3].valid = 0; 225213448Sjchandra blk0->num_ports--; 226213448Sjchandra /* NA1 is not available */ 227213448Sjchandra memset(blk1, 0, sizeof(*blk1)); 228213448Sjchandra break; 229213448Sjchandra default: 230213448Sjchandra break; 231213448Sjchandra } 232213448Sjchandra} 233213448Sjchandra 234213448Sjchandrastatic void 235211946Sjchandraxls_board_specific_overrides(struct xlr_board_info* board) 236211946Sjchandra{ 237211946Sjchandra struct xlr_gmac_block_t *blk0, *blk1; 238211946Sjchandra int i; 239216390Sjchandra struct xlr_i2c_dev_t* iic_blk; 240211946Sjchandra 241211946Sjchandra blk0 = &board->gmac_block[0]; 242211946Sjchandra blk1 = &board->gmac_block[1]; 243211946Sjchandra 244211946Sjchandra switch (xlr_boot1_info.board_major_version) { 245211946Sjchandra case RMI_XLR_BOARD_ARIZONA_VI: 246211946Sjchandra blk0->mode = XLR_PORT0_RGMII; 247211946Sjchandra blk0->gmac_port[0].type = XLR_RGMII; 248211946Sjchandra blk0->gmac_port[0].phy_addr = 0; 249211946Sjchandra blk0->gmac_port[0].mii_addr = XLR_IO_GMAC_4_OFFSET; 250211946Sjchandra /* Because of the Octal PHY, SGMII Quad1 is MII is also bound 251211946Sjchandra * to the PHY attached to SGMII0_MDC/MDIO/MDINT. */ 252211946Sjchandra for (i = 0; i < 4; i++) { 253211946Sjchandra blk1->gmac_port[i].mii_addr = XLR_IO_GMAC_0_OFFSET; 254211946Sjchandra blk1->gmac_port[i].serdes_addr = XLR_IO_GMAC_0_OFFSET; 255211946Sjchandra } 256211946Sjchandra blk1->gmac_port[1].mii_addr = XLR_IO_GMAC_0_OFFSET; 257211946Sjchandra blk1->gmac_port[2].mii_addr = XLR_IO_GMAC_0_OFFSET; 258211946Sjchandra blk1->gmac_port[3].mii_addr = XLR_IO_GMAC_0_OFFSET; 259211946Sjchandra 260211946Sjchandra blk1->gmac_port[1].serdes_addr = XLR_IO_GMAC_0_OFFSET; 261211946Sjchandra blk1->gmac_port[2].serdes_addr = XLR_IO_GMAC_0_OFFSET; 262211946Sjchandra blk1->gmac_port[3].serdes_addr = XLR_IO_GMAC_0_OFFSET; 263211946Sjchandra 264211946Sjchandra /* RGMII MDIO interrupt is thru NA1 and SGMII MDIO 265211946Sjchandra * interrupts for ports in blk1 are from NA0 */ 266211946Sjchandra blk0->gmac_port[0].mdint_id = 1; 267211946Sjchandra 268211946Sjchandra blk1->gmac_port[0].mdint_id = 0; 269211946Sjchandra blk1->gmac_port[1].mdint_id = 0; 270211946Sjchandra blk1->gmac_port[2].mdint_id = 0; 271211946Sjchandra blk1->gmac_port[3].mdint_id = 0; 272212045Sjchandra 273212045Sjchandra /* If we have a 4xx lite chip, don't enable the 274212045Sjchandra * GMACs which are disabled in hardware */ 275212045Sjchandra if (xlr_is_xls4xx_lite()) { 276212045Sjchandra xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET); 277212045Sjchandra uint32_t tmp; 278212045Sjchandra 279212045Sjchandra /* Port 6 & 7 are not enabled on the condor 4xx, figure 280212045Sjchandra * this out from the GPIO fuse bank */ 281212045Sjchandra tmp = xlr_read_reg(mmio, 35); 282212045Sjchandra if ((tmp & (3 << 28)) != 0) { 283212045Sjchandra blk1->enabled = 0x3; 284212045Sjchandra blk1->gmac_port[2].valid = 0; 285212045Sjchandra blk1->gmac_port[3].valid = 0; 286212045Sjchandra blk1->num_ports = 2; 287212045Sjchandra } 288212045Sjchandra } 289211946Sjchandra break; 290211946Sjchandra 291211946Sjchandra case RMI_XLR_BOARD_ARIZONA_VIII: 292216390Sjchandra iic_blk = &xlr_board_info.xlr_i2c_device[I2C_THERMAL]; 293216390Sjchandra if (iic_blk->enabled) { 294216390Sjchandra iic_blk->addr = XLR_I2C_ATX8_TEMPSENSOR_ADDR; 295216390Sjchandra } 296216390Sjchandra if (blk1->enabled) { 297213448Sjchandra /* There is just one Octal PHY on the board and it is 298213448Sjchandra * connected to the MII interface for NA Quad 0. */ 299214107Sjchandra for (i = 0; i < 4; i++) { 300214107Sjchandra blk1->gmac_port[i].mii_addr = 301214107Sjchandra XLR_IO_GMAC_0_OFFSET; 302214107Sjchandra blk1->gmac_port[i].mdint_id = 0; 303214107Sjchandra } 304211946Sjchandra } 305211946Sjchandra break; 306211946Sjchandra 307211946Sjchandra case RMI_XLR_BOARD_ARIZONA_XI: 308211946Sjchandra case RMI_XLR_BOARD_ARIZONA_XII: 309211946Sjchandra if (quad0_xaui()) { /* GMAC ports 0-3 are set to XAUI */ 310211946Sjchandra /* only GMAC0 is active i.e, the 0-th port on this quad. 311211946Sjchandra * Disable all the other 7 possible ports. */ 312211946Sjchandra for (i = 1; i < MAX_NA_PORTS; i++) { 313211946Sjchandra memset(&blk0->gmac_port[i], 0, 314211946Sjchandra sizeof(blk0->gmac_port[i])); 315211946Sjchandra } 316211946Sjchandra /* Setup for XAUI on N/w Acc0: gmac0 */ 317211946Sjchandra blk0->type = XLR_XGMAC; 318211946Sjchandra blk0->mode = XLR_XAUI; 319211946Sjchandra blk0->num_ports = 1; 320211946Sjchandra blk0->gmac_port[0].type = XLR_XAUI; 321211946Sjchandra blk1->gmac_port[0].phy_addr = 16; 322211946Sjchandra blk0->gmac_port[0].tx_bucket_id = blk0->station_txbase; 323211946Sjchandra /* Other addresses etc need not be modified as XAUI_0 324211946Sjchandra * shares its addresses with SGMII GMAC_0, which was 325211946Sjchandra * set in the caller. */ 326211946Sjchandra } 327211946Sjchandra else { 328211946Sjchandra blk0->num_ports = 1; /* only 1 RGMII port */ 329211946Sjchandra blk0->mode = XLR_PORT0_RGMII; 330211946Sjchandra blk0->gmac_port[0].type = XLR_RGMII; 331211946Sjchandra blk0->gmac_port[0].phy_addr = 0; 332211946Sjchandra blk0->gmac_port[0].mii_addr = XLR_IO_GMAC_0_OFFSET; 333211946Sjchandra } 334211946Sjchandra 335211946Sjchandra if (quad1_xaui()) { /* GMAC ports 4-7 are used for XAUI */ 336211946Sjchandra /* only GMAC4 is active i.e, the 0-th port on this quad. 337211946Sjchandra * Disable all the other 7 possible ports. */ 338211946Sjchandra for (i = 1; i < MAX_NA_PORTS; i++) { 339211946Sjchandra memset(&blk1->gmac_port[i], 0, 340211946Sjchandra sizeof(blk1->gmac_port[i])); 341211946Sjchandra } 342211946Sjchandra /* Setup for XAUI on N/w Acc1: gmac4 */ 343211946Sjchandra blk1->type = XLR_XGMAC; 344211946Sjchandra blk1->mode = XLR_XAUI; 345211946Sjchandra blk1->num_ports = 1; 346211946Sjchandra /* XAUI and SGMII ports share FMN buckets on N/w Acc 1; 347211946Sjchandra so, station_txbase, station_rfr need not be 348211946Sjchandra patched up. */ 349211946Sjchandra blk1->gmac_port[0].type = XLR_XAUI; 350211946Sjchandra blk1->gmac_port[0].phy_addr = 16; 351211946Sjchandra blk1->gmac_port[0].tx_bucket_id = blk1->station_txbase; 352211946Sjchandra /* Other addresses etc need not be modified as XAUI_1 353211946Sjchandra * shares its addresses with SGMII GMAC_4, which was 354211946Sjchandra * set in the caller. */ 355211946Sjchandra } 356211946Sjchandra break; 357211946Sjchandra 358211946Sjchandra default: 359211946Sjchandra break; 360211946Sjchandra } 361211946Sjchandra} 362211946Sjchandra 363198160Srrs/* 364198625Srrs * All our knowledge of chip and board that cannot be detected by probing 365198160Srrs * at run-time goes here 366198160Srrs */ 367198625Srrsint 368198625Srrsxlr_board_info_setup() 369198160Srrs{ 370211946Sjchandra struct xlr_gmac_block_t *blk0, *blk1, *blk2; 371216390Sjchandra struct xlr_i2c_dev_t* iic_blk; 372211946Sjchandra int i; 373204137Srrs 374211946Sjchandra /* This setup code is long'ish because the same base driver 375211946Sjchandra * (if_nlge.c) is used for different: 376211946Sjchandra * - CPUs (XLR/XLS) 377211946Sjchandra * - boards (for each CPU, multiple board configs are possible 378211946Sjchandra * and available). 379211946Sjchandra * 380211946Sjchandra * At the time of writing, there are atleast 12 boards, 4 with XLR 381211946Sjchandra * and 8 with XLS. This means that the base driver needs to work with 382211946Sjchandra * 12 different configurations, with varying levels of differences. 383211946Sjchandra * To accomodate the different configs, the xlr_board_info struct 384211946Sjchandra * has various attributes for paramters that could be different. 385211946Sjchandra * These attributes are setup here and can be used directly in the 386211946Sjchandra * base driver. 387211946Sjchandra * It was seen that the setup code is not entirely trivial and 388211946Sjchandra * it is possible to organize it in different ways. In the following, 389211946Sjchandra * we choose an approach that sacrifices code-compactness/speed for 390211946Sjchandra * readability. This is because configuration code executes once 391211946Sjchandra * per reboot and hence has a minimal performance impact. 392211946Sjchandra * On the other hand, driver debugging/enhancements require 393211946Sjchandra * that different engineers can quickly comprehend the setup 394211946Sjchandra * sequence. Hence, readability is seen as the key requirement for 395211946Sjchandra * this code. It is for the reader to decide how much of this 396211946Sjchandra * requirement is met with the current code organization !! 397211946Sjchandra * 398211946Sjchandra * The initialization is organized thus: 399211946Sjchandra * 400211946Sjchandra * if (CPU is XLS) { 401211946Sjchandra * // initialize per XLS architecture 402211946Sjchandra * // default inits (per chip spec) 403213448Sjchandra * // chip-specific overrides 404211946Sjchandra * // board-specific overrides 405211946Sjchandra * } else if (CPU is XLR) { 406211946Sjchandra * // initialize per XLR architecture 407211946Sjchandra * // default inits (per chip spec) 408213448Sjchandra * // chip-specific overrides 409211946Sjchandra * // board-specific overrides 410211946Sjchandra * } 411211946Sjchandra * 412213448Sjchandra * For each CPU family, all the default initializations 413213448Sjchandra * are done for a fully-loaded device of that family. 414213448Sjchandra * This configuration is then adjusted for the actual 415213448Sjchandra * chip id. This is followed up with board specific 416213448Sjchandra * overrides. 417211946Sjchandra */ 418211946Sjchandra 419211946Sjchandra /* start with a clean slate */ 420211946Sjchandra memset(&xlr_board_info, 0, sizeof(xlr_board_info)); 421211946Sjchandra xlr_board_info.ata = xlr_pcmcia_present(); 422211946Sjchandra 423211946Sjchandra blk0 = &xlr_board_info.gmac_block[0]; 424211946Sjchandra blk1 = &xlr_board_info.gmac_block[1]; 425211946Sjchandra blk2 = &xlr_board_info.gmac_block[2]; 426216390Sjchandra 427216390Sjchandra iic_blk = xlr_board_info.xlr_i2c_device; 428216390Sjchandra iic_blk[I2C_RTC].enabled = 1; 429216390Sjchandra iic_blk[I2C_RTC].addr = XLR_I2C_RTC_ADDR; 430216390Sjchandra iic_blk[I2C_THERMAL].enabled = 1; 431216390Sjchandra iic_blk[I2C_THERMAL].addr = XLR_I2C_TEMPSENSOR_ADDR; 432216390Sjchandra iic_blk[I2C_EEPROM].enabled = 1; 433216390Sjchandra iic_blk[I2C_EEPROM].addr = XLR_I2C_EEPROM_ADDR; 434211946Sjchandra 435198160Srrs if (xlr_is_xls()) { 436198160Srrs xlr_board_info.is_xls = 1; 437198160Srrs xlr_board_info.nr_cpus = 8; 438198160Srrs xlr_board_info.usb = 1; 439209318Sjchandra /* Board version 8 has NAND flash */ 440198160Srrs xlr_board_info.cfi = 441198625Srrs (xlr_boot1_info.board_major_version != RMI_XLR_BOARD_ARIZONA_VIII); 442198160Srrs xlr_board_info.pci_irq = 0; 443198160Srrs xlr_board_info.credit_configs = xls_core_cc_configs; 444211946Sjchandra xlr_board_info.bucket_sizes = &xls_bucket_sizes; 445211946Sjchandra xlr_board_info.gmacports = MAX_NA_PORTS; 446198160Srrs 447211946Sjchandra /* ---------------- Network Acc 0 ---------------- */ 448198160Srrs 449211946Sjchandra blk0->type = XLR_GMAC; 450211946Sjchandra blk0->enabled = 0xf; 451211946Sjchandra blk0->credit_config = &xls_cc_table_gmac0; 452213377Sjchandra blk0->station_id = MSGRNG_STNID_GMAC; 453211946Sjchandra blk0->station_txbase = MSGRNG_STNID_GMACTX0; 454211946Sjchandra blk0->station_rfr = MSGRNG_STNID_GMACRFR_0; 455211946Sjchandra blk0->mode = XLR_SGMII; 456211946Sjchandra blk0->baseaddr = XLR_IO_GMAC_0_OFFSET; 457211946Sjchandra blk0->baseirq = PIC_GMAC_0_IRQ; 458211946Sjchandra blk0->baseinst = 0; 459204137Srrs 460211946Sjchandra /* By default, assume SGMII is setup. But this can change based 461211946Sjchandra on board-specific or setting-specific info. */ 462211946Sjchandra for (i = 0; i < 4; i++) { 463211946Sjchandra blk0->gmac_port[i].valid = 1; 464211946Sjchandra blk0->gmac_port[i].instance = i + blk0->baseinst; 465211946Sjchandra blk0->gmac_port[i].type = XLR_SGMII; 466211946Sjchandra blk0->gmac_port[i].phy_addr = i + 16; 467211946Sjchandra blk0->gmac_port[i].tx_bucket_id = 468211946Sjchandra blk0->station_txbase + i; 469211946Sjchandra blk0->gmac_port[i].mdint_id = 0; 470211946Sjchandra blk0->num_ports++; 471211946Sjchandra blk0->gmac_port[i].base_addr = XLR_IO_GMAC_0_OFFSET + i * 0x1000; 472211946Sjchandra blk0->gmac_port[i].mii_addr = XLR_IO_GMAC_0_OFFSET; 473211946Sjchandra blk0->gmac_port[i].pcs_addr = XLR_IO_GMAC_0_OFFSET; 474211946Sjchandra blk0->gmac_port[i].serdes_addr = XLR_IO_GMAC_0_OFFSET; 475204137Srrs } 476198160Srrs 477211946Sjchandra /* ---------------- Network Acc 1 ---------------- */ 478211946Sjchandra blk1->type = XLR_GMAC; 479211946Sjchandra blk1->enabled = 0xf; 480211946Sjchandra blk1->credit_config = &xls_cc_table_gmac1; 481213377Sjchandra blk1->station_id = MSGRNG_STNID_GMAC1; 482211946Sjchandra blk1->station_txbase = MSGRNG_STNID_GMAC1_TX0; 483211946Sjchandra blk1->station_rfr = MSGRNG_STNID_GMAC1_FR_0; 484211946Sjchandra blk1->mode = XLR_SGMII; 485211946Sjchandra blk1->baseaddr = XLR_IO_GMAC_4_OFFSET; 486211946Sjchandra blk1->baseirq = PIC_XGS_0_IRQ; 487211946Sjchandra blk1->baseinst = 4; 488211946Sjchandra 489211946Sjchandra for (i = 0; i < 4; i++) { 490211946Sjchandra blk1->gmac_port[i].valid = 1; 491211946Sjchandra blk1->gmac_port[i].instance = i + blk1->baseinst; 492211946Sjchandra blk1->gmac_port[i].type = XLR_SGMII; 493211946Sjchandra blk1->gmac_port[i].phy_addr = i + 20; 494211946Sjchandra blk1->gmac_port[i].tx_bucket_id = 495211946Sjchandra blk1->station_txbase + i; 496211946Sjchandra blk1->gmac_port[i].mdint_id = 1; 497211946Sjchandra blk1->num_ports++; 498211946Sjchandra blk1->gmac_port[i].base_addr = XLR_IO_GMAC_4_OFFSET + i * 0x1000; 499211946Sjchandra blk1->gmac_port[i].mii_addr = XLR_IO_GMAC_4_OFFSET; 500211946Sjchandra blk1->gmac_port[i].pcs_addr = XLR_IO_GMAC_4_OFFSET; 501211946Sjchandra blk1->gmac_port[i].serdes_addr = XLR_IO_GMAC_0_OFFSET; 502211946Sjchandra } 503211946Sjchandra 504211946Sjchandra /* ---------------- Network Acc 2 ---------------- */ 505211946Sjchandra xlr_board_info.gmac_block[2].enabled = 0; /* disabled on XLS */ 506211946Sjchandra 507213448Sjchandra xls_chip_specific_overrides(&xlr_board_info); 508211946Sjchandra xls_board_specific_overrides(&xlr_board_info); 509211946Sjchandra 510211946Sjchandra } else { /* XLR */ 511198160Srrs xlr_board_info.is_xls = 0; 512198160Srrs xlr_board_info.nr_cpus = 32; 513198160Srrs xlr_board_info.usb = 0; 514198160Srrs xlr_board_info.cfi = 1; 515198160Srrs xlr_board_info.pci_irq = 0; 516198160Srrs xlr_board_info.credit_configs = xlr_core_cc_configs; 517211946Sjchandra xlr_board_info.bucket_sizes = &bucket_sizes; 518211946Sjchandra xlr_board_info.gmacports = 4; 519198160Srrs 520211946Sjchandra /* ---------------- GMAC0 ---------------- */ 521211946Sjchandra blk0->type = XLR_GMAC; 522211946Sjchandra blk0->enabled = 0xf; 523211946Sjchandra blk0->credit_config = &cc_table_gmac; 524213377Sjchandra blk0->station_id = MSGRNG_STNID_GMAC; 525211946Sjchandra blk0->station_txbase = MSGRNG_STNID_GMACTX0; 526211946Sjchandra blk0->station_rfr = MSGRNG_STNID_GMACRFR_0; 527211946Sjchandra blk0->mode = XLR_RGMII; 528211946Sjchandra blk0->baseaddr = XLR_IO_GMAC_0_OFFSET; 529211946Sjchandra blk0->baseirq = PIC_GMAC_0_IRQ; 530211946Sjchandra blk0->baseinst = 0; 531198160Srrs 532211946Sjchandra /* first, do the common/easy stuff for all the ports */ 533211946Sjchandra for (i = 0; i < 4; i++) { 534211946Sjchandra blk0->gmac_port[i].valid = 1; 535211946Sjchandra blk0->gmac_port[i].instance = i + blk0->baseinst; 536211946Sjchandra blk0->gmac_port[i].type = XLR_RGMII; 537211946Sjchandra blk0->gmac_port[i].phy_addr = i; 538211946Sjchandra blk0->gmac_port[i].tx_bucket_id = 539211946Sjchandra blk0->station_txbase + i; 540211946Sjchandra blk0->gmac_port[i].mdint_id = 0; 541211946Sjchandra blk0->gmac_port[i].base_addr = XLR_IO_GMAC_0_OFFSET + i * 0x1000; 542211946Sjchandra blk0->gmac_port[i].mii_addr = XLR_IO_GMAC_0_OFFSET; 543211946Sjchandra /* RGMII ports, no PCS/SERDES */ 544211946Sjchandra blk0->num_ports++; 545211946Sjchandra } 546198160Srrs 547211946Sjchandra /* ---------------- XGMAC0 ---------------- */ 548211946Sjchandra blk1->type = XLR_XGMAC; 549211946Sjchandra blk1->mode = XLR_XGMII; 550211946Sjchandra blk1->enabled = 0; 551211946Sjchandra blk1->credit_config = &cc_table_xgs_0; 552211946Sjchandra blk1->station_txbase = MSGRNG_STNID_XGS0_TX; 553211946Sjchandra blk1->station_rfr = MSGRNG_STNID_XMAC0RFR; 554213377Sjchandra blk1->station_id = MSGRNG_STNID_XGS0FR; 555211946Sjchandra blk1->baseaddr = XLR_IO_XGMAC_0_OFFSET; 556211946Sjchandra blk1->baseirq = PIC_XGS_0_IRQ; 557211946Sjchandra blk1->baseinst = 4; 558211946Sjchandra 559211946Sjchandra blk1->gmac_port[0].type = XLR_XGMII; 560211946Sjchandra blk1->gmac_port[0].instance = 0; 561211946Sjchandra blk1->gmac_port[0].phy_addr = 0; 562211946Sjchandra blk1->gmac_port[0].base_addr = XLR_IO_XGMAC_0_OFFSET; 563211946Sjchandra blk1->gmac_port[0].mii_addr = XLR_IO_XGMAC_0_OFFSET; 564211946Sjchandra blk1->gmac_port[0].tx_bucket_id = blk1->station_txbase; 565211946Sjchandra blk1->gmac_port[0].mdint_id = 1; 566211946Sjchandra 567211946Sjchandra /* ---------------- XGMAC1 ---------------- */ 568211946Sjchandra blk2->type = XLR_XGMAC; 569211946Sjchandra blk2->mode = XLR_XGMII; 570211946Sjchandra blk2->enabled = 0; 571211946Sjchandra blk2->credit_config = &cc_table_xgs_1; 572211946Sjchandra blk2->station_txbase = MSGRNG_STNID_XGS1_TX; 573211946Sjchandra blk2->station_rfr = MSGRNG_STNID_XMAC1RFR; 574213377Sjchandra blk2->station_id = MSGRNG_STNID_XGS1FR; 575211946Sjchandra blk2->baseaddr = XLR_IO_XGMAC_1_OFFSET; 576211946Sjchandra blk2->baseirq = PIC_XGS_1_IRQ; 577211946Sjchandra blk2->baseinst = 5; 578211946Sjchandra 579211946Sjchandra blk2->gmac_port[0].type = XLR_XGMII; 580211946Sjchandra blk2->gmac_port[0].instance = 0; 581211946Sjchandra blk2->gmac_port[0].phy_addr = 0; 582211946Sjchandra blk2->gmac_port[0].base_addr = XLR_IO_XGMAC_1_OFFSET; 583211946Sjchandra blk2->gmac_port[0].mii_addr = XLR_IO_XGMAC_1_OFFSET; 584211946Sjchandra blk2->gmac_port[0].tx_bucket_id = blk2->station_txbase; 585211946Sjchandra blk2->gmac_port[0].mdint_id = 2; 586211946Sjchandra 587213448Sjchandra /* Done with default setup. Now handle chip and board-specific 588213448Sjchandra variations. */ 589213448Sjchandra xlr_chip_specific_overrides(&xlr_board_info); 590211946Sjchandra xlr_board_specific_overrides(&xlr_board_info); 591211946Sjchandra } 592211946Sjchandra return 0; 593198160Srrs} 594