cpuregs.h revision 211453
1130803Smarcel/* $NetBSD: cpuregs.h,v 1.70 2006/05/15 02:26:54 simonb Exp $ */ 2130803Smarcel 3130803Smarcel/* 4130803Smarcel * Copyright (c) 1992, 1993 5130803Smarcel * The Regents of the University of California. All rights reserved. 6130803Smarcel * 7130803Smarcel * This code is derived from software contributed to Berkeley by 8130803Smarcel * Ralph Campbell and Rick Macklem. 9130803Smarcel * 10130803Smarcel * Redistribution and use in source and binary forms, with or without 11130803Smarcel * modification, are permitted provided that the following conditions 12130803Smarcel * are met: 13130803Smarcel * 1. Redistributions of source code must retain the above copyright 14130803Smarcel * notice, this list of conditions and the following disclaimer. 15130803Smarcel * 2. Redistributions in binary form must reproduce the above copyright 16130803Smarcel * notice, this list of conditions and the following disclaimer in the 17130803Smarcel * documentation and/or other materials provided with the distribution. 18130803Smarcel * 3. Neither the name of the University nor the names of its contributors 19130803Smarcel * may be used to endorse or promote products derived from this software 20130803Smarcel * without specific prior written permission. 21130803Smarcel * 22130803Smarcel * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23130803Smarcel * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24130803Smarcel * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25130803Smarcel * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26130803Smarcel * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27130803Smarcel * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28130803Smarcel * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29130803Smarcel * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30130803Smarcel * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31130803Smarcel * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32130803Smarcel * SUCH DAMAGE. 33130803Smarcel * 34130803Smarcel * @(#)machConst.h 8.1 (Berkeley) 6/10/93 35130803Smarcel * 36130803Smarcel * machConst.h -- 37130803Smarcel * 38130803Smarcel * Machine dependent constants. 39130803Smarcel * 40130803Smarcel * Copyright (C) 1989 Digital Equipment Corporation. 41130803Smarcel * Permission to use, copy, modify, and distribute this software and 42130803Smarcel * its documentation for any purpose and without fee is hereby granted, 43130803Smarcel * provided that the above copyright notice appears in all copies. 44130803Smarcel * Digital Equipment Corporation makes no representations about the 45130803Smarcel * suitability of this software for any purpose. It is provided "as is" 46130803Smarcel * without express or implied warranty. 47130803Smarcel * 48130803Smarcel * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 49130803Smarcel * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) 50130803Smarcel * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 51130803Smarcel * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) 52130803Smarcel * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 53130803Smarcel * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) 54130803Smarcel * 55130803Smarcel * $FreeBSD: head/sys/mips/include/cpuregs.h 211453 2010-08-18 12:52:21Z jchandra $ 56130803Smarcel */ 57130803Smarcel 58130803Smarcel#ifndef _MIPS_CPUREGS_H_ 59130803Smarcel#define _MIPS_CPUREGS_H_ 60130803Smarcel 61130803Smarcel#if defined(_KERNEL_OPT) 62130803Smarcel#include "opt_cputype.h" 63130803Smarcel#endif 64130803Smarcel 65130803Smarcel/* 66130803Smarcel * Address space. 67130803Smarcel * 32-bit mips CPUS partition their 32-bit address space into four segments: 68130803Smarcel * 69130803Smarcel * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped 70130803Smarcel * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped 71130803Smarcel * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped 72130803Smarcel * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped 73130803Smarcel * 74130803Smarcel * mips1 physical memory is limited to 512Mbytes, which is 75130803Smarcel * doubly mapped in kseg0 (cached) and kseg1 (uncached.) 76130803Smarcel * Caching of mapped addresses is controlled by bits in the TLB entry. 77130803Smarcel */ 78130803Smarcel 79130803Smarcel#define MIPS_KSEG0_LARGEST_PHYS (0x20000000) 80130803Smarcel#define MIPS_KSEG0_PHYS_MASK (0x1fffffff) 81130803Smarcel#define MIPS_XKPHYS_LARGEST_PHYS (0x10000000000) /* 40 bit PA */ 82130803Smarcel#define MIPS_XKPHYS_PHYS_MASK (0x0ffffffffff) 83130803Smarcel 84130803Smarcel#ifndef LOCORE 85130803Smarcel#define MIPS_KUSEG_START 0x00000000 86130803Smarcel#define MIPS_KSEG0_START ((intptr_t)(int32_t)0x80000000) 87130803Smarcel#define MIPS_KSEG0_END ((intptr_t)(int32_t)0x9fffffff) 88130803Smarcel#define MIPS_KSEG1_START ((intptr_t)(int32_t)0xa0000000) 89130803Smarcel#define MIPS_KSEG1_END ((intptr_t)(int32_t)0xbfffffff) 90130803Smarcel#define MIPS_KSSEG_START ((intptr_t)(int32_t)0xc0000000) 91130803Smarcel#define MIPS_KSSEG_END ((intptr_t)(int32_t)0xdfffffff) 92130803Smarcel#define MIPS_KSEG3_START ((intptr_t)(int32_t)0xe0000000) 93130803Smarcel#define MIPS_KSEG3_END ((intptr_t)(int32_t)0xffffffff) 94130803Smarcel#define MIPS_KSEG2_START MIPS_KSSEG_START 95130803Smarcel#define MIPS_KSEG2_END MIPS_KSSEG_END 96130803Smarcel#endif 97130803Smarcel 98130803Smarcel#define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | MIPS_KSEG0_START) 99130803Smarcel#define MIPS_PHYS_TO_KSEG1(x) ((uintptr_t)(x) | MIPS_KSEG1_START) 100130803Smarcel#define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_KSEG0_PHYS_MASK) 101130803Smarcel#define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_KSEG0_PHYS_MASK) 102130803Smarcel 103130803Smarcel#define MIPS_IS_KSEG0_ADDR(x) \ 104130803Smarcel (((vm_offset_t)(x) >= MIPS_KSEG0_START) && \ 105130803Smarcel ((vm_offset_t)(x) <= MIPS_KSEG0_END)) 106130803Smarcel#define MIPS_IS_KSEG1_ADDR(x) \ 107130803Smarcel (((vm_offset_t)(x) >= MIPS_KSEG1_START) && \ 108130803Smarcel ((vm_offset_t)(x) <= MIPS_KSEG1_END)) 109130803Smarcel#define MIPS_IS_VALID_PTR(x) (MIPS_IS_KSEG0_ADDR(x) || \ 110130803Smarcel MIPS_IS_KSEG1_ADDR(x)) 111130803Smarcel 112130803Smarcel/* 113130803Smarcel * Cache Coherency Attributes: 114130803Smarcel * UC: Uncached. 115130803Smarcel * UA: Uncached accelerated. 116130803Smarcel * C: Cacheable, coherency unspecified. 117130803Smarcel * CNC: Cacheable non-coherent. 118130803Smarcel * CC: Cacheable coherent. 119130803Smarcel * CCE: Cacheable coherent, exclusive read. 120130803Smarcel * CCEW: Cacheable coherent, exclusive write. 121130803Smarcel * CCUOW: Cacheable coherent, update on write. 122130803Smarcel * 123130803Smarcel * Note that some bits vary in meaning across implementations (and that the 124130803Smarcel * listing here is no doubt incomplete) and that the optimal cached mode varies 125130803Smarcel * between implementations. 0x02 is required to be UC and 0x03 is required to 126130803Smarcel * be a least C. 127130803Smarcel * 128130803Smarcel * We define the following logical bits: 129130803Smarcel * UNCACHED: 130130803Smarcel * The optimal uncached mode for the target CPU type. This must 131130803Smarcel * be suitable for use in accessing memory-mapped devices. 132130803Smarcel * CACHED: The optional cached mode for the target CPU type. 133130803Smarcel */ 134130803Smarcel 135130803Smarcel#define MIPS_CCA_UC 0x02 /* Uncached. */ 136130803Smarcel#define MIPS_CCA_C 0x03 /* Cacheable, coherency unspecified. */ 137130803Smarcel 138130803Smarcel#if defined(CPU_R4000) || defined(CPU_R10000) 139130803Smarcel#define MIPS_CCA_CNC 0x03 140130803Smarcel#define MIPS_CCA_CCE 0x04 141130803Smarcel#define MIPS_CCA_CCEW 0x05 142130803Smarcel 143130803Smarcel#ifdef CPU_R4000 144130803Smarcel#define MIPS_CCA_CCUOW 0x06 145130803Smarcel#endif 146130803Smarcel 147130803Smarcel#ifdef CPU_R10000 148130803Smarcel#define MIPS_CCA_UA 0x07 149130803Smarcel#endif 150130803Smarcel 151130803Smarcel#define MIPS_CCA_CACHED MIPS_CCA_CCEW 152130803Smarcel#endif /* defined(CPU_R4000) || defined(CPU_R10000) */ 153130803Smarcel 154130803Smarcel#if defined(CPU_SB1) 155130803Smarcel#define MIPS_CCA_CC 0x05 /* Cacheable Coherent. */ 156130803Smarcel#endif 157130803Smarcel 158130803Smarcel#ifndef MIPS_CCA_UNCACHED 159130803Smarcel#define MIPS_CCA_UNCACHED MIPS_CCA_UC 160130803Smarcel#endif 161130803Smarcel 162130803Smarcel/* 163130803Smarcel * If we don't know which cached mode to use and there is a cache coherent 164130803Smarcel * mode, use it. If there is not a cache coherent mode, use the required 165130803Smarcel * cacheable mode. 166130803Smarcel */ 167130803Smarcel#ifndef MIPS_CCA_CACHED 168130803Smarcel#ifdef MIPS_CCA_CC 169130803Smarcel#define MIPS_CCA_CACHED MIPS_CCA_CC 170130803Smarcel#else 171130803Smarcel#define MIPS_CCA_CACHED MIPS_CCA_C 172130803Smarcel#endif 173130803Smarcel#endif 174130803Smarcel 175130803Smarcel#define MIPS_PHYS_TO_XKPHYS(cca,x) \ 176130803Smarcel ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x)) 177130803Smarcel#define MIPS_PHYS_TO_XKPHYS_CACHED(x) \ 178130803Smarcel ((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_CACHED) << 59) | (x)) 179130803Smarcel#define MIPS_PHYS_TO_XKPHYS_UNCACHED(x) \ 180130803Smarcel ((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_UNCACHED) << 59) | (x)) 181130803Smarcel 182130803Smarcel#define MIPS_XKPHYS_TO_PHYS(x) ((uintptr_t)(x) & MIPS_XKPHYS_PHYS_MASK) 183130803Smarcel 184130803Smarcel#define MIPS_XKPHYS_START 0x8000000000000000 185130803Smarcel#define MIPS_XKPHYS_END 0xbfffffffffffffff 186130803Smarcel#define MIPS_XUSEG_START 0x0000000000000000 187130803Smarcel#define MIPS_XUSEG_END 0x0000010000000000 188130803Smarcel#define MIPS_XKSEG_START 0xc000000000000000 189130803Smarcel#define MIPS_XKSEG_END 0xc00000ff80000000 190130803Smarcel 191130803Smarcel#ifdef __mips_n64 192130803Smarcel#define MIPS_DIRECT_MAPPABLE(pa) 1 193130803Smarcel#define MIPS_PHYS_TO_DIRECT(pa) MIPS_PHYS_TO_XKPHYS_CACHED(pa) 194130803Smarcel#define MIPS_PHYS_TO_DIRECT_UNCACHED(pa) MIPS_PHYS_TO_XKPHYS_UNCACHED(pa) 195130803Smarcel#define MIPS_DIRECT_TO_PHYS(va) MIPS_XKPHYS_TO_PHYS(va) 196130803Smarcel#else 197130803Smarcel#define MIPS_DIRECT_MAPPABLE(pa) ((pa) < MIPS_KSEG0_LARGEST_PHYS) 198130803Smarcel#define MIPS_PHYS_TO_DIRECT(pa) MIPS_PHYS_TO_KSEG0(pa) 199130803Smarcel#define MIPS_PHYS_TO_DIRECT_UNCACHED(pa) MIPS_PHYS_TO_KSEG1(pa) 200130803Smarcel#define MIPS_DIRECT_TO_PHYS(va) MIPS_KSEG0_TO_PHYS(va) 201130803Smarcel#endif 202130803Smarcel 203130803Smarcel/* CPU dependent mtc0 hazard hook */ 204130803Smarcel#ifdef CPU_CNMIPS 205130803Smarcel#define COP0_SYNC nop; nop; nop; nop; nop; 206130803Smarcel#elif defined(CPU_SB1) 207130803Smarcel#define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop 208130803Smarcel#elif defined(CPU_RMI) 209130803Smarcel#define COP0_SYNC 210130803Smarcel#else 211130803Smarcel/* 212130803Smarcel * Pick a reasonable default based on the "typical" spacing described in the 213130803Smarcel * "CP0 Hazards" chapter of MIPS Architecture Book Vol III. 214130803Smarcel */ 215130803Smarcel#define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop 216130803Smarcel#endif 217130803Smarcel#define COP0_HAZARD_FPUENABLE nop; nop; nop; nop; 218130803Smarcel 219130803Smarcel/* 220130803Smarcel * The bits in the cause register. 221130803Smarcel * 222130803Smarcel * Bits common to r3000 and r4000: 223130803Smarcel * 224130803Smarcel * MIPS_CR_BR_DELAY Exception happened in branch delay slot. 225130803Smarcel * MIPS_CR_COP_ERR Coprocessor error. 226130803Smarcel * MIPS_CR_IP Interrupt pending bits defined below. 227130803Smarcel * (same meaning as in CAUSE register). 228130803Smarcel * MIPS_CR_EXC_CODE The exception type (see exception codes below). 229130803Smarcel * 230130803Smarcel * Differences: 231130803Smarcel * r3k has 4 bits of execption type, r4k has 5 bits. 232130803Smarcel */ 233130803Smarcel#define MIPS_CR_BR_DELAY 0x80000000 234130803Smarcel#define MIPS_CR_COP_ERR 0x30000000 235130803Smarcel#define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */ 236130803Smarcel#define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */ 237130803Smarcel#define MIPS_CR_IP 0x0000FF00 238130803Smarcel#define MIPS_CR_EXC_CODE_SHIFT 2 239130803Smarcel 240130803Smarcel/* 241130803Smarcel * The bits in the status register. All bits are active when set to 1. 242130803Smarcel * 243130803Smarcel * R3000 status register fields: 244130803Smarcel * MIPS_SR_COP_USABILITY Control the usability of the four coprocessors. 245130803Smarcel * MIPS_SR_TS TLB shutdown. 246130803Smarcel * 247130803Smarcel * MIPS_SR_INT_IE Master (current) interrupt enable bit. 248130803Smarcel * 249130803Smarcel * Differences: 250130803Smarcel * r3k has cache control is via frobbing SR register bits, whereas the 251130803Smarcel * r4k cache control is via explicit instructions. 252130803Smarcel * r3k has a 3-entry stack of kernel/user bits, whereas the 253130803Smarcel * r4k has kernel/supervisor/user. 254130803Smarcel */ 255130803Smarcel#define MIPS_SR_COP_USABILITY 0xf0000000 256130803Smarcel#define MIPS_SR_COP_0_BIT 0x10000000 257130803Smarcel#define MIPS_SR_COP_1_BIT 0x20000000 258130803Smarcel#define MIPS_SR_COP_2_BIT 0x40000000 259130803Smarcel 260130803Smarcel /* r4k and r3k differences, see below */ 261130803Smarcel 262130803Smarcel#define MIPS_SR_MX 0x01000000 /* MIPS64 */ 263130803Smarcel#define MIPS_SR_PX 0x00800000 /* MIPS64 */ 264130803Smarcel#define MIPS_SR_BEV 0x00400000 /* Use boot exception vector */ 265130803Smarcel#define MIPS_SR_TS 0x00200000 266130803Smarcel#define MIPS_SR_DE 0x00010000 267130803Smarcel 268130803Smarcel#define MIPS_SR_INT_IE 0x00000001 269130803Smarcel/*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */ 270130803Smarcel#define MIPS_SR_INT_MASK 0x0000ff00 271130803Smarcel 272130803Smarcel/* 273130803Smarcel * The R2000/R3000-specific status register bit definitions. 274130803Smarcel * all bits are active when set to 1. 275130803Smarcel * 276130803Smarcel * MIPS_SR_PARITY_ERR Parity error. 277130803Smarcel * MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss. 278130803Smarcel * MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits. 279130803Smarcel * MIPS_SR_SWAP_CACHES Swap I-cache and D-cache. 280130803Smarcel * MIPS_SR_ISOL_CACHES Isolate D-cache from main memory. 281130803Smarcel * Interrupt enable bits defined below. 282130803Smarcel * MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode. 283130803Smarcel * MIPS_SR_INT_ENA_OLD Old interrupt enable bit. 284130803Smarcel * MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode. 285130803Smarcel * MIPS_SR_INT_ENA_PREV Previous interrupt enable bit. 286130803Smarcel * MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode. 287130803Smarcel */ 288130803Smarcel 289130803Smarcel#define MIPS1_PARITY_ERR 0x00100000 290130803Smarcel#define MIPS1_CACHE_MISS 0x00080000 291130803Smarcel#define MIPS1_PARITY_ZERO 0x00040000 292130803Smarcel#define MIPS1_SWAP_CACHES 0x00020000 293130803Smarcel#define MIPS1_ISOL_CACHES 0x00010000 294130803Smarcel 295130803Smarcel#define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/ 296130803Smarcel#define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/ 297130803Smarcel#define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/ 298130803Smarcel#define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/ 299130803Smarcel#define MIPS1_SR_KU_CUR 0x00000002 /* current KU */ 300130803Smarcel 301130803Smarcel/* backwards compatibility */ 302130803Smarcel#define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR 303130803Smarcel#define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS 304130803Smarcel#define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO 305130803Smarcel#define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES 306130803Smarcel#define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES 307130803Smarcel 308130803Smarcel#define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD 309130803Smarcel#define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD 310130803Smarcel#define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV 311130803Smarcel#define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR 312130803Smarcel#define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV 313130803Smarcel 314130803Smarcel/* 315130803Smarcel * R4000 status register bit definitons, 316130803Smarcel * where different from r2000/r3000. 317130803Smarcel */ 318130803Smarcel#define MIPS3_SR_XX 0x80000000 319130803Smarcel#define MIPS3_SR_RP 0x08000000 320130803Smarcel#define MIPS3_SR_FR 0x04000000 321130803Smarcel#define MIPS3_SR_RE 0x02000000 322130803Smarcel 323130803Smarcel#define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */ 324130803Smarcel#define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */ 325130803Smarcel#define MIPS3_SR_SR 0x00100000 326130803Smarcel#define MIPS3_SR_NMI 0x00080000 /* MIPS32/64 */ 327130803Smarcel#define MIPS3_SR_DIAG_CH 0x00040000 328130803Smarcel#define MIPS3_SR_DIAG_CE 0x00020000 329130803Smarcel#define MIPS3_SR_DIAG_PE 0x00010000 330130803Smarcel#define MIPS3_SR_EIE 0x00010000 /* TX79/R5900 */ 331130803Smarcel#define MIPS3_SR_KX 0x00000080 332130803Smarcel#define MIPS3_SR_SX 0x00000040 333130803Smarcel#define MIPS3_SR_UX 0x00000020 334130803Smarcel#define MIPS3_SR_KSU_MASK 0x00000018 335130803Smarcel#define MIPS3_SR_KSU_USER 0x00000010 336130803Smarcel#define MIPS3_SR_KSU_SUPER 0x00000008 337130803Smarcel#define MIPS3_SR_KSU_KERNEL 0x00000000 338130803Smarcel#define MIPS3_SR_ERL 0x00000004 339130803Smarcel#define MIPS3_SR_EXL 0x00000002 340130803Smarcel 341130803Smarcel#ifdef MIPS3_5900 342130803Smarcel#undef MIPS_SR_INT_IE 343130803Smarcel#define MIPS_SR_INT_IE 0x00010001 /* XXX */ 344130803Smarcel#endif 345130803Smarcel 346130803Smarcel/* 347130803Smarcel * These definitions are for MIPS32 processors. 348130803Smarcel */ 349130803Smarcel#define MIPS32_SR_RP 0x08000000 /* reduced power mode */ 350130803Smarcel#define MIPS32_SR_FR 0x04000000 /* 64-bit capable fpu */ 351130803Smarcel#define MIPS32_SR_RE 0x02000000 /* reverse user endian */ 352130803Smarcel#define MIPS32_SR_MX 0x01000000 /* MIPS64 */ 353130803Smarcel#define MIPS32_SR_PX 0x00800000 /* MIPS64 */ 354130803Smarcel#define MIPS32_SR_BEV 0x00400000 /* Use boot exception vector */ 355130803Smarcel#define MIPS32_SR_TS 0x00200000 /* TLB multiple match */ 356130803Smarcel#define MIPS32_SR_SOFT_RESET 0x00100000 /* soft reset occurred */ 357130803Smarcel#define MIPS32_SR_NMI 0x00080000 /* NMI occurred */ 358130803Smarcel#define MIPS32_SR_INT_MASK 0x0000ff00 359130803Smarcel#define MIPS32_SR_KX 0x00000080 /* MIPS64 */ 360130803Smarcel#define MIPS32_SR_SX 0x00000040 /* MIPS64 */ 361130803Smarcel#define MIPS32_SR_UX 0x00000020 /* MIPS64 */ 362130803Smarcel#define MIPS32_SR_KSU_MASK 0x00000018 /* privilege mode */ 363130803Smarcel#define MIPS32_SR_KSU_USER 0x00000010 364130803Smarcel#define MIPS32_SR_KSU_SUPER 0x00000008 365130803Smarcel#define MIPS32_SR_KSU_KERNEL 0x00000000 366130803Smarcel#define MIPS32_SR_ERL 0x00000004 /* error level */ 367130803Smarcel#define MIPS32_SR_EXL 0x00000002 /* exception level */ 368130803Smarcel 369130803Smarcel#define MIPS_SR_SOFT_RESET MIPS3_SR_SR 370130803Smarcel#define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH 371130803Smarcel#define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE 372130803Smarcel#define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE 373130803Smarcel#define MIPS_SR_KX MIPS3_SR_KX 374130803Smarcel#define MIPS_SR_SX MIPS3_SR_SX 375130803Smarcel#define MIPS_SR_UX MIPS3_SR_UX 376130803Smarcel 377130803Smarcel#define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK 378130803Smarcel#define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER 379130803Smarcel#define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER 380130803Smarcel#define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL 381130803Smarcel#define MIPS_SR_ERL MIPS3_SR_ERL 382130803Smarcel#define MIPS_SR_EXL MIPS3_SR_EXL 383130803Smarcel 384130803Smarcel 385130803Smarcel/* 386130803Smarcel * The interrupt masks. 387 * If a bit in the mask is 1 then the interrupt is enabled (or pending). 388 */ 389#define MIPS_INT_MASK 0xff00 390#define MIPS_INT_MASK_5 0x8000 391#define MIPS_INT_MASK_4 0x4000 392#define MIPS_INT_MASK_3 0x2000 393#define MIPS_INT_MASK_2 0x1000 394#define MIPS_INT_MASK_1 0x0800 395#define MIPS_INT_MASK_0 0x0400 396#define MIPS_HARD_INT_MASK 0xfc00 397#define MIPS_SOFT_INT_MASK_1 0x0200 398#define MIPS_SOFT_INT_MASK_0 0x0100 399 400/* 401 * mips3 CPUs have on-chip timer at INT_MASK_5. Each platform can 402 * choose to enable this interrupt. 403 */ 404#if defined(MIPS3_ENABLE_CLOCK_INTR) 405#define MIPS3_INT_MASK MIPS_INT_MASK 406#define MIPS3_HARD_INT_MASK MIPS_HARD_INT_MASK 407#else 408#define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5) 409#define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5) 410#endif 411 412/* 413 * The bits in the context register. 414 */ 415#define MIPS1_CNTXT_PTE_BASE 0xFFE00000 416#define MIPS1_CNTXT_BAD_VPN 0x001FFFFC 417 418#define MIPS3_CNTXT_PTE_BASE 0xFF800000 419#define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0 420 421/* 422 * Location of MIPS32 exception vectors. Most are multiplexed in 423 * the sense that further decoding is necessary (e.g. reading the 424 * CAUSE register or NMI bits in STATUS). 425 * Most interrupts go via the 426 * The INT vector is dedicated for hardware interrupts; it is 427 * only referenced if the IV bit in CAUSE is set to 1. 428 */ 429#define MIPS_VEC_RESET 0xBFC00000 /* Hard, soft, or NMI */ 430#define MIPS_VEC_EJTAG 0xBFC00480 431#define MIPS_VEC_TLB 0x80000000 432#define MIPS_VEC_XTLB 0x80000080 433#define MIPS_VEC_CACHE 0x80000100 434#define MIPS_VEC_GENERIC 0x80000180 /* Most exceptions */ 435#define MIPS_VEC_INTERRUPT 0x80000200 436 437/* 438 * The bits in the MIPS3 config register. 439 * 440 * bit 0..5: R/W, Bit 6..31: R/O 441 */ 442 443/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ 444#define MIPS3_CONFIG_K0_MASK 0x00000007 445 446/* 447 * R/W Update on Store Conditional 448 * 0: Store Conditional uses coherency algorithm specified by TLB 449 * 1: Store Conditional uses cacheable coherent update on write 450 */ 451#define MIPS3_CONFIG_CU 0x00000008 452 453#define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */ 454#define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */ 455#define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \ 456 (((config) & (bit)) ? 32 : 16) 457 458#define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */ 459#define MIPS3_CONFIG_DC_SHIFT 6 460#define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */ 461#define MIPS3_CONFIG_IC_SHIFT 9 462#define MIPS3_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */ 463 464/* Cache size mode indication: available only on Vr41xx CPUs */ 465#define MIPS3_CONFIG_CS 0x00001000 466#define MIPS3_CONFIG_C_4100BASE 0x0400 /* base is 2^10 if CS=1 */ 467#define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \ 468 ((base) << (((config) & (mask)) >> (shift))) 469 470/* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */ 471#define MIPS3_CONFIG_SE 0x00001000 472 473/* Block ordering: 0: sequential, 1: sub-block */ 474#define MIPS3_CONFIG_EB 0x00002000 475 476/* ECC mode - 0: ECC mode, 1: parity mode */ 477#define MIPS3_CONFIG_EM 0x00004000 478 479/* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */ 480#define MIPS3_CONFIG_BE 0x00008000 481 482/* Dirty Shared coherency state - 0: enabled, 1: disabled */ 483#define MIPS3_CONFIG_SM 0x00010000 484 485/* Secondary Cache - 0: present, 1: not present */ 486#define MIPS3_CONFIG_SC 0x00020000 487 488/* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */ 489#define MIPS3_CONFIG_EW_MASK 0x000c0000 490#define MIPS3_CONFIG_EW_SHIFT 18 491 492/* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */ 493#define MIPS3_CONFIG_SW 0x00100000 494 495/* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */ 496#define MIPS3_CONFIG_SS 0x00200000 497 498/* Secondary Cache line size */ 499#define MIPS3_CONFIG_SB_MASK 0x00c00000 500#define MIPS3_CONFIG_SB_SHIFT 22 501#define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \ 502 (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT)) 503 504/* Write back data rate */ 505#define MIPS3_CONFIG_EP_MASK 0x0f000000 506#define MIPS3_CONFIG_EP_SHIFT 24 507 508/* System clock ratio - this value is CPU dependent */ 509#define MIPS3_CONFIG_EC_MASK 0x70000000 510#define MIPS3_CONFIG_EC_SHIFT 28 511 512/* Master-Checker Mode - 1: enabled */ 513#define MIPS3_CONFIG_CM 0x80000000 514 515/* 516 * The bits in the MIPS4 config register. 517 */ 518 519/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */ 520#define MIPS4_CONFIG_K0_MASK MIPS3_CONFIG_K0_MASK 521#define MIPS4_CONFIG_DN_MASK 0x00000018 /* Device number */ 522#define MIPS4_CONFIG_CT 0x00000020 /* CohPrcReqTar */ 523#define MIPS4_CONFIG_PE 0x00000040 /* PreElmReq */ 524#define MIPS4_CONFIG_PM_MASK 0x00000180 /* PreReqMax */ 525#define MIPS4_CONFIG_EC_MASK 0x00001e00 /* SysClkDiv */ 526#define MIPS4_CONFIG_SB 0x00002000 /* SCBlkSize */ 527#define MIPS4_CONFIG_SK 0x00004000 /* SCColEn */ 528#define MIPS4_CONFIG_BE 0x00008000 /* MemEnd */ 529#define MIPS4_CONFIG_SS_MASK 0x00070000 /* SCSize */ 530#define MIPS4_CONFIG_SC_MASK 0x00380000 /* SCClkDiv */ 531#define MIPS4_CONFIG_RESERVED 0x03c00000 /* Reserved wired 0 */ 532#define MIPS4_CONFIG_DC_MASK 0x1c000000 /* Primary D-Cache size */ 533#define MIPS4_CONFIG_IC_MASK 0xe0000000 /* Primary I-Cache size */ 534 535#define MIPS4_CONFIG_DC_SHIFT 26 536#define MIPS4_CONFIG_IC_SHIFT 29 537 538#define MIPS4_CONFIG_CACHE_SIZE(config, mask, base, shift) \ 539 ((base) << (((config) & (mask)) >> (shift))) 540 541#define MIPS4_CONFIG_CACHE_L2_LSIZE(config) \ 542 (((config) & MIPS4_CONFIG_SB) ? 128 : 64) 543 544/* 545 * Location of exception vectors. 546 * 547 * Common vectors: reset and UTLB miss. 548 */ 549#define MIPS_RESET_EXC_VEC ((intptr_t)(int32_t)0xBFC00000) 550#define MIPS_UTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000000) 551 552/* 553 * MIPS-1 general exception vector (everything else) 554 */ 555#define MIPS1_GEN_EXC_VEC ((intptr_t)(int32_t)0x80000080) 556 557/* 558 * MIPS-III exception vectors 559 */ 560#define MIPS3_XTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000080) 561#define MIPS3_CACHE_ERR_EXC_VEC ((intptr_t)(int32_t)0x80000100) 562#define MIPS3_GEN_EXC_VEC ((intptr_t)(int32_t)0x80000180) 563 564/* 565 * TX79 (R5900) exception vectors 566 */ 567#define MIPS_R5900_COUNTER_EXC_VEC 0x80000080 568#define MIPS_R5900_DEBUG_EXC_VEC 0x80000100 569 570/* 571 * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector. 572 */ 573#define MIPS3_INTR_EXC_VEC 0x80000200 574 575/* 576 * Coprocessor 0 registers: 577 * 578 * v--- width for mips I,III,32,64 579 * (3=32bit, 6=64bit, i=impl dep) 580 * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index. 581 * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random. 582 * 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low. 583 * 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended. 584 * 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context. 585 * 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register. 586 * 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number. 587 * 7 MIPS_COP_0_INFO ..33 Info registers 588 * 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address. 589 * 9 MIPS_COP_0_COUNT .333 Count register. 590 * 10 MIPS_COP_0_TLB_HI 3636 TLB entry high. 591 * 11 MIPS_COP_0_COMPARE .333 Compare (against Count). 592 * 12 MIPS_COP_0_STATUS 3333 Status register. 593 * 13 MIPS_COP_0_CAUSE 3333 Exception cause register. 594 * 14 MIPS_COP_0_EXC_PC 3636 Exception PC. 595 * 15 MIPS_COP_0_PRID 3333 Processor revision identifier. 596 * 16 MIPS_COP_0_CONFIG 3333 Configuration register. 597 * 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1. 598 * 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2. 599 * 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3. 600 * 17 MIPS_COP_0_LLADDR .336 Load Linked Address. 601 * 18 MIPS_COP_0_WATCH_LO .336 WatchLo register. 602 * 19 MIPS_COP_0_WATCH_HI .333 WatchHi register. 603 * 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register. 604 * 23 MIPS_COP_0_DEBUG .... Debug JTAG register. 605 * 24 MIPS_COP_0_DEPC .... DEPC JTAG register. 606 * 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register. 607 * 26 MIPS_COP_0_ECC .3ii ECC / Error Control register. 608 * 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register. 609 * 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr). 610 * 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr). 611 * 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data). 612 * 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data). 613 * 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr). 614 * 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr). 615 * 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data). 616 * 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data). 617 * 30 MIPS_COP_0_ERROR_PC .636 Error EPC register. 618 * 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register. 619 */ 620 621/* Deal with inclusion from an assembly file. */ 622#if defined(_LOCORE) || defined(LOCORE) 623#define _(n) $n 624#else 625#define _(n) n 626#endif 627 628 629#define MIPS_COP_0_TLB_INDEX _(0) 630#define MIPS_COP_0_TLB_RANDOM _(1) 631 /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */ 632 633#define MIPS_COP_0_TLB_CONTEXT _(4) 634 /* $5 and $6 new with MIPS-III */ 635#define MIPS_COP_0_BAD_VADDR _(8) 636#define MIPS_COP_0_TLB_HI _(10) 637#define MIPS_COP_0_STATUS _(12) 638#define MIPS_COP_0_CAUSE _(13) 639#define MIPS_COP_0_EXC_PC _(14) 640#define MIPS_COP_0_PRID _(15) 641 642/* MIPS-III */ 643#define MIPS_COP_0_TLB_LO0 _(2) 644#define MIPS_COP_0_TLB_LO1 _(3) 645 646#define MIPS_COP_0_TLB_PG_MASK _(5) 647#define MIPS_COP_0_TLB_WIRED _(6) 648 649#define MIPS_COP_0_COUNT _(9) 650#define MIPS_COP_0_COMPARE _(11) 651 652#define MIPS_COP_0_CONFIG _(16) 653#define MIPS_COP_0_LLADDR _(17) 654#define MIPS_COP_0_WATCH_LO _(18) 655#define MIPS_COP_0_WATCH_HI _(19) 656#define MIPS_COP_0_TLB_XCONTEXT _(20) 657#define MIPS_COP_0_ECC _(26) 658#define MIPS_COP_0_CACHE_ERR _(27) 659#define MIPS_COP_0_TAG_LO _(28) 660#define MIPS_COP_0_TAG_HI _(29) 661#define MIPS_COP_0_ERROR_PC _(30) 662 663/* MIPS32/64 */ 664#define MIPS_COP_0_INFO _(7) 665#define MIPS_COP_0_DEBUG _(23) 666#define MIPS_COP_0_DEPC _(24) 667#define MIPS_COP_0_PERFCNT _(25) 668#define MIPS_COP_0_DATA_LO _(28) 669#define MIPS_COP_0_DATA_HI _(29) 670#define MIPS_COP_0_DESAVE _(31) 671 672/* MIPS32 Config register definitions */ 673#define MIPS_MMU_NONE 0x00 /* No MMU present */ 674#define MIPS_MMU_TLB 0x01 /* Standard TLB */ 675#define MIPS_MMU_BAT 0x02 /* Standard BAT */ 676#define MIPS_MMU_FIXED 0x03 /* Standard fixed mapping */ 677 678#define MIPS_CONFIG0_MT_MASK 0x00000380 /* bits 9..7 MMU Type */ 679#define MIPS_CONFIG0_MT_SHIFT 7 680#define MIPS_CONFIG0_BE 0x00008000 /* data is big-endian */ 681#define MIPS_CONFIG0_VI 0x00000004 /* instruction cache is virtual */ 682 683#define MIPS_CONFIG1_TLBSZ_MASK 0x7E000000 /* bits 30..25 # tlb entries minus one */ 684#define MIPS_CONFIG1_TLBSZ_SHIFT 25 685#define MIPS_MAX_TLB_ENTRIES 64 686 687#define MIPS_CONFIG1_IS_MASK 0x01C00000 /* bits 24..22 icache sets per way */ 688#define MIPS_CONFIG1_IS_SHIFT 22 689#define MIPS_CONFIG1_IL_MASK 0x00380000 /* bits 21..19 icache line size */ 690#define MIPS_CONFIG1_IL_SHIFT 19 691#define MIPS_CONFIG1_IA_MASK 0x00070000 /* bits 18..16 icache associativity */ 692#define MIPS_CONFIG1_IA_SHIFT 16 693#define MIPS_CONFIG1_DS_MASK 0x0000E000 /* bits 15..13 dcache sets per way */ 694#define MIPS_CONFIG1_DS_SHIFT 13 695#define MIPS_CONFIG1_DL_MASK 0x00001C00 /* bits 12..10 dcache line size */ 696#define MIPS_CONFIG1_DL_SHIFT 10 697#define MIPS_CONFIG1_DA_MASK 0x00000380 /* bits 9.. 7 dcache associativity */ 698#define MIPS_CONFIG1_DA_SHIFT 7 699#define MIPS_CONFIG1_LOWBITS 0x0000007F 700#define MIPS_CONFIG1_C2 0x00000040 /* Coprocessor 2 implemented */ 701#define MIPS_CONFIG1_MD 0x00000020 /* MDMX ASE implemented (MIPS64) */ 702#define MIPS_CONFIG1_PC 0x00000010 /* Performance counters implemented */ 703#define MIPS_CONFIG1_WR 0x00000008 /* Watch registers implemented */ 704#define MIPS_CONFIG1_CA 0x00000004 /* MIPS16e ISA implemented */ 705#define MIPS_CONFIG1_EP 0x00000002 /* EJTAG implemented */ 706#define MIPS_CONFIG1_FP 0x00000001 /* FPU implemented */ 707 708/* 709 * Values for the code field in a break instruction. 710 */ 711#define MIPS_BREAK_INSTR 0x0000000d 712#define MIPS_BREAK_VAL_MASK 0x03ff0000 713#define MIPS_BREAK_VAL_SHIFT 16 714#define MIPS_BREAK_KDB_VAL 512 715#define MIPS_BREAK_SSTEP_VAL 513 716#define MIPS_BREAK_BRKPT_VAL 514 717#define MIPS_BREAK_SOVER_VAL 515 718#define MIPS_BREAK_DDB_VAL 516 719#define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \ 720 (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT)) 721#define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \ 722 (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT)) 723#define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \ 724 (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT)) 725#define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \ 726 (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT)) 727#define MIPS_BREAK_DDB (MIPS_BREAK_INSTR | \ 728 (MIPS_BREAK_DDB_VAL << MIPS_BREAK_VAL_SHIFT)) 729 730/* 731 * Mininum and maximum cache sizes. 732 */ 733#define MIPS_MIN_CACHE_SIZE (16 * 1024) 734#define MIPS_MAX_CACHE_SIZE (256 * 1024) 735#define MIPS3_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */ 736 737/* 738 * The floating point version and status registers. 739 */ 740#define MIPS_FPU_ID $0 741#define MIPS_FPU_CSR $31 742 743/* 744 * The floating point coprocessor status register bits. 745 */ 746#define MIPS_FPU_ROUNDING_BITS 0x00000003 747#define MIPS_FPU_ROUND_RN 0x00000000 748#define MIPS_FPU_ROUND_RZ 0x00000001 749#define MIPS_FPU_ROUND_RP 0x00000002 750#define MIPS_FPU_ROUND_RM 0x00000003 751#define MIPS_FPU_STICKY_BITS 0x0000007c 752#define MIPS_FPU_STICKY_INEXACT 0x00000004 753#define MIPS_FPU_STICKY_UNDERFLOW 0x00000008 754#define MIPS_FPU_STICKY_OVERFLOW 0x00000010 755#define MIPS_FPU_STICKY_DIV0 0x00000020 756#define MIPS_FPU_STICKY_INVALID 0x00000040 757#define MIPS_FPU_ENABLE_BITS 0x00000f80 758#define MIPS_FPU_ENABLE_INEXACT 0x00000080 759#define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100 760#define MIPS_FPU_ENABLE_OVERFLOW 0x00000200 761#define MIPS_FPU_ENABLE_DIV0 0x00000400 762#define MIPS_FPU_ENABLE_INVALID 0x00000800 763#define MIPS_FPU_EXCEPTION_BITS 0x0003f000 764#define MIPS_FPU_EXCEPTION_INEXACT 0x00001000 765#define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000 766#define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000 767#define MIPS_FPU_EXCEPTION_DIV0 0x00008000 768#define MIPS_FPU_EXCEPTION_INVALID 0x00010000 769#define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000 770#define MIPS_FPU_COND_BIT 0x00800000 771#define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */ 772#define MIPS1_FPC_MBZ_BITS 0xff7c0000 773#define MIPS3_FPC_MBZ_BITS 0xfe7c0000 774 775 776/* 777 * Constants to determine if have a floating point instruction. 778 */ 779#define MIPS_OPCODE_SHIFT 26 780#define MIPS_OPCODE_C1 0x11 781 782 783/* 784 * The low part of the TLB entry. 785 */ 786#define MIPS1_TLB_PFN 0xfffff000 787#define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800 788#define MIPS1_TLB_DIRTY_BIT 0x00000400 789#define MIPS1_TLB_VALID_BIT 0x00000200 790#define MIPS1_TLB_GLOBAL_BIT 0x00000100 791 792#define MIPS3_TLB_PFN 0x3fffffc0 793#define MIPS3_TLB_ATTR_MASK 0x00000038 794#define MIPS3_TLB_ATTR_SHIFT 3 795#define MIPS3_TLB_DIRTY_BIT 0x00000004 796#define MIPS3_TLB_VALID_BIT 0x00000002 797#define MIPS3_TLB_GLOBAL_BIT 0x00000001 798 799#define MIPS1_TLB_PHYS_PAGE_SHIFT 12 800#define MIPS3_TLB_PHYS_PAGE_SHIFT 6 801#define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN 802#define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN 803#define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT 804#define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT 805 806/* 807 * MIPS3_TLB_ATTR values - coherency algorithm: 808 * 0: cacheable, noncoherent, write-through, no write allocate 809 * 1: cacheable, noncoherent, write-through, write allocate 810 * 2: uncached 811 * 3: cacheable, noncoherent, write-back (noncoherent) 812 * 4: cacheable, coherent, write-back, exclusive (exclusive) 813 * 5: cacheable, coherent, write-back, exclusive on write (sharable) 814 * 6: cacheable, coherent, write-back, update on write (update) 815 * 7: uncached, accelerated (gather STORE operations) 816 */ 817#define MIPS3_TLB_ATTR_WT 0 /* IDT */ 818#define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */ 819#define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */ 820#define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */ 821#define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */ 822#define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */ 823#define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */ 824#define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED 7 /* R10000 */ 825 826 827/* 828 * The high part of the TLB entry. 829 */ 830#define MIPS1_TLB_VPN 0xfffff000 831#define MIPS1_TLB_PID 0x00000fc0 832#define MIPS1_TLB_PID_SHIFT 6 833 834#define MIPS3_TLB_VPN2 0xffffe000 835#define MIPS3_TLB_ASID 0x000000ff 836 837#define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN 838#define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2 839#define MIPS3_TLB_PID MIPS3_TLB_ASID 840#define MIPS_TLB_VIRT_PAGE_SHIFT 12 841 842/* 843 * r3000: shift count to put the index in the right spot. 844 */ 845#define MIPS1_TLB_INDEX_SHIFT 8 846 847/* 848 * The first TLB that write random hits. 849 */ 850#define MIPS1_TLB_FIRST_RAND_ENTRY 8 851#define MIPS3_TLB_WIRED_UPAGES 1 852 853/* 854 * The number of process id entries. 855 */ 856#define MIPS1_TLB_NUM_PIDS 64 857#define MIPS3_TLB_NUM_ASIDS 256 858 859/* 860 * Patch codes to hide CPU design differences between MIPS1 and MIPS3. 861 */ 862 863/* XXX simonb: this is before MIPS3_PLUS is defined (and is ugly!) */ 864 865#if !(defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \ 866 && defined(MIPS1) /* XXX simonb must be neater! */ 867#define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT 868#define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS 869#endif 870 871#if (defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \ 872 && !defined(MIPS1) /* XXX simonb must be neater! */ 873#define MIPS_TLB_PID_SHIFT 0 874#define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS 875#endif 876 877 878#if !defined(MIPS_TLB_PID_SHIFT) 879#define MIPS_TLB_PID_SHIFT \ 880 ((MIPS_HAS_R4K_MMU) ? 0 : MIPS1_TLB_PID_SHIFT) 881 882#define MIPS_TLB_NUM_PIDS \ 883 ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS) 884#endif 885 886/* 887 * CPU processor revision IDs for company ID == 0 (non mips32/64 chips) 888 */ 889#define MIPS_R2000 0x01 /* MIPS R2000 ISA I */ 890#define MIPS_R3000 0x02 /* MIPS R3000 ISA I */ 891#define MIPS_R6000 0x03 /* MIPS R6000 ISA II */ 892#define MIPS_R4000 0x04 /* MIPS R4000/R4400 ISA III */ 893#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivative ISA I */ 894#define MIPS_R6000A 0x06 /* MIPS R6000A ISA II */ 895#define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 ISA I */ 896#define MIPS_R10000 0x09 /* MIPS R10000 ISA IV */ 897#define MIPS_R4200 0x0a /* NEC VR4200 ISA III */ 898#define MIPS_R4300 0x0b /* NEC VR4300 ISA III */ 899#define MIPS_R4100 0x0c /* NEC VR4100 ISA III */ 900#define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */ 901#define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */ 902#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 903#define MIPS_RC32300 0x18 /* IDT RC32334,332,355 ISA 32 */ 904#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 905#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */ 906#define MIPS_R3SONY 0x21 /* Sony R3000 based ISA I */ 907#define MIPS_R4650 0x22 /* QED R4650 ISA III */ 908#define MIPS_TX3900 0x22 /* Toshiba TX39 family ISA I */ 909#define MIPS_R5000 0x23 /* MIPS R5000 ISA IV */ 910#define MIPS_R3NKK 0x23 /* NKK R3000 based ISA I */ 911#define MIPS_RC32364 0x26 /* IDT RC32364 ISA 32 */ 912#define MIPS_RM7000 0x27 /* QED RM7000 ISA IV */ 913#define MIPS_RM5200 0x28 /* QED RM5200s ISA IV */ 914#define MIPS_TX4900 0x2d /* Toshiba TX49 family ISA III */ 915#define MIPS_R5900 0x2e /* Toshiba R5900 (EECore) ISA --- */ 916#define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 ISA III */ 917#define MIPS_TX7900 0x38 /* Toshiba TX79 ISA III+*/ 918#define MIPS_R5400 0x54 /* NEC VR5400 ISA IV */ 919#define MIPS_R5500 0x55 /* NEC VR5500 ISA IV */ 920 921/* 922 * CPU revision IDs for some prehistoric processors. 923 */ 924 925/* For MIPS_R3000 */ 926#define MIPS_REV_R3000 0x20 927#define MIPS_REV_R3000A 0x30 928 929/* For MIPS_TX3900 */ 930#define MIPS_REV_TX3912 0x10 931#define MIPS_REV_TX3922 0x30 932#define MIPS_REV_TX3927 0x40 933 934/* For MIPS_R4000 */ 935#define MIPS_REV_R4000_A 0x00 936#define MIPS_REV_R4000_B 0x22 937#define MIPS_REV_R4000_C 0x30 938#define MIPS_REV_R4400_A 0x40 939#define MIPS_REV_R4400_B 0x50 940#define MIPS_REV_R4400_C 0x60 941 942/* For MIPS_TX4900 */ 943#define MIPS_REV_TX4927 0x22 944 945/* 946 * CPU processor revision IDs for company ID == 1 (MIPS) 947 */ 948#define MIPS_4Kc 0x80 /* MIPS 4Kc ISA 32 */ 949#define MIPS_5Kc 0x81 /* MIPS 5Kc ISA 64 */ 950#define MIPS_20Kc 0x82 /* MIPS 20Kc ISA 64 */ 951#define MIPS_4Kmp 0x83 /* MIPS 4Km/4Kp ISA 32 */ 952#define MIPS_4KEc 0x84 /* MIPS 4KEc ISA 32 */ 953#define MIPS_4KEmp 0x85 /* MIPS 4KEm/4KEp ISA 32 */ 954#define MIPS_4KSc 0x86 /* MIPS 4KSc ISA 32 */ 955#define MIPS_M4K 0x87 /* MIPS M4K ISA 32 Rel 2 */ 956#define MIPS_25Kf 0x88 /* MIPS 25Kf ISA 64 */ 957#define MIPS_5KE 0x89 /* MIPS 5KE ISA 64 Rel 2 */ 958#define MIPS_4KEc_R2 0x90 /* MIPS 4KEc_R2 ISA 32 Rel 2 */ 959#define MIPS_4KEmp_R2 0x91 /* MIPS 4KEm/4KEp_R2 ISA 32 Rel 2 */ 960#define MIPS_4KSd 0x92 /* MIPS 4KSd ISA 32 Rel 2 */ 961#define MIPS_24K 0x93 /* MIPS 24Kc/24Kf ISA 32 Rel 2 */ 962#define MIPS_34K 0x95 /* MIPS 34K ISA 32 R2 MT */ 963#define MIPS_24KE 0x96 /* MIPS 24KEc ISA 32 Rel 2 */ 964#define MIPS_74K 0x97 /* MIPS 74Kc/74Kf ISA 32 Rel 2 */ 965 966/* 967 * AMD (company ID 3) use the processor ID field to donote the CPU core 968 * revision and the company options field do donate the SOC chip type. 969 */ 970 971/* CPU processor revision IDs */ 972#define MIPS_AU_REV1 0x01 /* Alchemy Au1000 (Rev 1) ISA 32 */ 973#define MIPS_AU_REV2 0x02 /* Alchemy Au1000 (Rev 2) ISA 32 */ 974 975/* CPU company options IDs */ 976#define MIPS_AU1000 0x00 977#define MIPS_AU1500 0x01 978#define MIPS_AU1100 0x02 979#define MIPS_AU1550 0x03 980 981/* 982 * CPU processor revision IDs for company ID == 4 (Broadcom) 983 */ 984#define MIPS_SB1 0x01 /* SiByte SB1 ISA 64 */ 985 986/* 987 * CPU processor revision IDs for company ID == 5 (SandCraft) 988 */ 989#define MIPS_SR7100 0x04 /* SandCraft SR7100 ISA 64 */ 990 991/* 992 * FPU processor revision ID 993 */ 994#define MIPS_SOFT 0x00 /* Software emulation ISA I */ 995#define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */ 996#define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */ 997#define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */ 998#define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */ 999#define MIPS_R4010 0x05 /* MIPS R4010 FPC ISA II */ 1000#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */ 1001#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */ 1002 1003#ifdef ENABLE_MIPS_TX3900 1004#include <mips/r3900regs.h> 1005#endif 1006#ifdef MIPS3_5900 1007#include <mips/r5900regs.h> 1008#endif 1009#ifdef MIPS64_SB1 1010#include <mips/sb1regs.h> 1011#endif 1012 1013#endif /* _MIPS_CPUREGS_H_ */ 1014