cpu.h revision 206717
1/* $OpenBSD: cpu.h,v 1.4 1998/09/15 10:50:12 pefo Exp $ */ 2 3/*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * Copyright (C) 1989 Digital Equipment Corporation. 35 * Permission to use, copy, modify, and distribute this software and 36 * its documentation for any purpose and without fee is hereby granted, 37 * provided that the above copyright notice appears in all copies. 38 * Digital Equipment Corporation makes no representations about the 39 * suitability of this software for any purpose. It is provided "as is" 40 * without express or implied warranty. 41 * 42 * from: @(#)cpu.h 8.4 (Berkeley) 1/4/94 43 * JNPR: cpu.h,v 1.9.2.2 2007/09/10 08:23:46 girish 44 * $FreeBSD: head/sys/mips/include/cpu.h 206717 2010-04-17 01:17:31Z jmallett $ 45 */ 46 47#ifndef _MACHINE_CPU_H_ 48#define _MACHINE_CPU_H_ 49 50#include <machine/endian.h> 51 52#define MIPS_KSEG0_LARGEST_PHYS 0x20000000 53#define MIPS_PHYS_MASK (0x1fffffff) 54 55#define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | MIPS_KSEG0_START) 56#define MIPS_PHYS_TO_KSEG1(x) ((uintptr_t)(x) | MIPS_KSEG1_START) 57#define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK) 58#define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK) 59 60#define MIPS_IS_KSEG0_ADDR(x) \ 61 (((vm_offset_t)(x) >= MIPS_KSEG0_START) && \ 62 ((vm_offset_t)(x) <= MIPS_KSEG0_END)) 63#define MIPS_IS_KSEG1_ADDR(x) \ 64 (((vm_offset_t)(x) >= MIPS_KSEG1_START) && \ 65 ((vm_offset_t)(x) <= MIPS_KSEG1_END)) 66#define MIPS_IS_VALID_PTR(x) (MIPS_IS_KSEG0_ADDR(x) || \ 67 MIPS_IS_KSEG1_ADDR(x)) 68 69/* 70 * Status register. 71 */ 72#define SR_COP_USABILITY 0xf0000000 73#define SR_COP_0_BIT 0x10000000 74#define SR_COP_1_BIT 0x20000000 75#define SR_COP_2_BIT 0x40000000 76#define SR_RP 0x08000000 77#define SR_FR_32 0x04000000 78#define SR_RE 0x02000000 79#define SR_PX 0x00800000 80#define SR_BOOT_EXC_VEC 0x00400000 81#define SR_TLB_SHUTDOWN 0x00200000 82#define SR_SOFT_RESET 0x00100000 83#define SR_DIAG_CH 0x00040000 84#define SR_DIAG_CE 0x00020000 85#define SR_DIAG_DE 0x00010000 86#define SR_KX 0x00000080 87#define SR_SX 0x00000040 88#define SR_UX 0x00000020 89#define SR_KSU_MASK 0x00000018 90#define SR_KSU_USER 0x00000010 91#define SR_KSU_SUPER 0x00000008 92#define SR_KSU_KERNEL 0x00000000 93#define SR_ERL 0x00000004 94#define SR_EXL 0x00000002 95#define SR_INT_ENAB 0x00000001 96 97#define SR_INT_MASK 0x0000ff00 98#define SOFT_INT_MASK_0 0x00000100 99#define SOFT_INT_MASK_1 0x00000200 100#define SR_INT_MASK_0 0x00000400 101#define SR_INT_MASK_1 0x00000800 102#define SR_INT_MASK_2 0x00001000 103#define SR_INT_MASK_3 0x00002000 104#define SR_INT_MASK_4 0x00004000 105#define SR_INT_MASK_5 0x00008000 106#define ALL_INT_MASK SR_INT_MASK 107#define SOFT_INT_MASK (SOFT_INT_MASK_0 | SOFT_INT_MASK_1) 108#define HW_INT_MASK (ALL_INT_MASK & ~SOFT_INT_MASK) 109 110#define soft_int_mask(softintr) (1 << ((softintr) + 8)) 111#define hard_int_mask(hardintr) (1 << ((hardintr) + 10)) 112 113/* 114 * The bits in the cause register. 115 * 116 * CR_BR_DELAY Exception happened in branch delay slot. 117 * CR_COP_ERR Coprocessor error. 118 * CR_IP Interrupt pending bits defined below. 119 * CR_EXC_CODE The exception type (see exception codes below). 120 */ 121#define CR_BR_DELAY 0x80000000 122#define CR_COP_ERR 0x30000000 123#define CR_EXC_CODE 0x0000007c 124#define CR_EXC_CODE_SHIFT 2 125#define CR_IPEND 0x0000ff00 126 127/* 128 * Cause Register Format: 129 * 130 * 31 30 29 28 27 26 25 24 23 8 7 6 2 1 0 131 * ---------------------------------------------------------------------- 132 * | BD | 0| CE | 0| W2| W1| IV| IP15 - IP0 | 0| Exc Code | 0| 133 * |______________________________________________________________________ 134 */ 135 136#define CR_INT_SOFT0 0x00000100 137#define CR_INT_SOFT1 0x00000200 138#define CR_INT_0 0x00000400 139#define CR_INT_1 0x00000800 140#define CR_INT_2 0x00001000 141#define CR_INT_3 0x00002000 142#define CR_INT_4 0x00004000 143#define CR_INT_5 0x00008000 144 145#define CR_INT_UART CR_INT_1 146#define CR_INT_IPI CR_INT_2 147#define CR_INT_CLOCK CR_INT_5 148 149/* 150 * The bits in the CONFIG register 151 */ 152#define CFG_K0_UNCACHED 2 153#define CFG_K0_CACHED 3 154#define CFG_K0_MASK 0x7 155 156/* 157 * The bits in the context register. 158 */ 159#define CNTXT_PTE_BASE 0xff800000 160#define CNTXT_BAD_VPN2 0x007ffff0 161 162/* 163 * Location of exception vectors. 164 */ 165#define RESET_EXC_VEC 0xbfc00000 166#define TLB_MISS_EXC_VEC 0x80000000 167#define XTLB_MISS_EXC_VEC 0x80000080 168#define CACHE_ERR_EXC_VEC 0x80000100 169#define GEN_EXC_VEC 0x80000180 170 171/* 172 * Coprocessor 0 registers: 173 */ 174#define COP_0_TLB_INDEX $0 175#define COP_0_TLB_RANDOM $1 176#define COP_0_TLB_LO0 $2 177#define COP_0_TLB_LO1 $3 178#define COP_0_TLB_CONTEXT $4 179#define COP_0_TLB_PG_MASK $5 180#define COP_0_TLB_WIRED $6 181#define COP_0_INFO $7 182#define COP_0_BAD_VADDR $8 183#define COP_0_COUNT $9 184#define COP_0_TLB_HI $10 185#define COP_0_COMPARE $11 186#define COP_0_STATUS_REG $12 187#define COP_0_CAUSE_REG $13 188#define COP_0_EXC_PC $14 189#define COP_0_PRID $15 190#define COP_0_CONFIG $16 191#define COP_0_LLADDR $17 192#define COP_0_WATCH_LO $18 193#define COP_0_WATCH_HI $19 194#define COP_0_TLB_XCONTEXT $20 195#define COP_0_ECC $26 196#define COP_0_CACHE_ERR $27 197#define COP_0_TAG_LO $28 198#define COP_0_TAG_HI $29 199#define COP_0_ERROR_PC $30 200 201/* 202 * Coprocessor 0 Set 1 203 */ 204#define C0P_1_IPLLO $18 205#define C0P_1_IPLHI $19 206#define C0P_1_INTCTL $20 207#define C0P_1_DERRADDR0 $26 208#define C0P_1_DERRADDR1 $27 209 210/* 211 * Values for the code field in a break instruction. 212 */ 213#define BREAK_INSTR 0x0000000d 214#define BREAK_VAL_MASK 0x03ffffc0 215#define BREAK_VAL_SHIFT 16 216#define BREAK_KDB_VAL 512 217#define BREAK_SSTEP_VAL 513 218#define BREAK_BRKPT_VAL 514 219#define BREAK_SOVER_VAL 515 220#define BREAK_DDB_VAL 516 221#define BREAK_KDB (BREAK_INSTR | (BREAK_KDB_VAL << BREAK_VAL_SHIFT)) 222#define BREAK_SSTEP (BREAK_INSTR | (BREAK_SSTEP_VAL << BREAK_VAL_SHIFT)) 223#define BREAK_BRKPT (BREAK_INSTR | (BREAK_BRKPT_VAL << BREAK_VAL_SHIFT)) 224#define BREAK_SOVER (BREAK_INSTR | (BREAK_SOVER_VAL << BREAK_VAL_SHIFT)) 225#define BREAK_DDB (BREAK_INSTR | (BREAK_DDB_VAL << BREAK_VAL_SHIFT)) 226 227/* 228 * Mininum and maximum cache sizes. 229 */ 230#define MIN_CACHE_SIZE (16 * 1024) 231#define MAX_CACHE_SIZE (256 * 1024) 232 233/* 234 * The floating point version and status registers. 235 */ 236#define FPC_ID $0 237#define FPC_CSR $31 238 239/* 240 * The floating point coprocessor status register bits. 241 */ 242#define FPC_ROUNDING_BITS 0x00000003 243#define FPC_ROUND_RN 0x00000000 244#define FPC_ROUND_RZ 0x00000001 245#define FPC_ROUND_RP 0x00000002 246#define FPC_ROUND_RM 0x00000003 247#define FPC_STICKY_BITS 0x0000007c 248#define FPC_STICKY_INEXACT 0x00000004 249#define FPC_STICKY_UNDERFLOW 0x00000008 250#define FPC_STICKY_OVERFLOW 0x00000010 251#define FPC_STICKY_DIV0 0x00000020 252#define FPC_STICKY_INVALID 0x00000040 253#define FPC_ENABLE_BITS 0x00000f80 254#define FPC_ENABLE_INEXACT 0x00000080 255#define FPC_ENABLE_UNDERFLOW 0x00000100 256#define FPC_ENABLE_OVERFLOW 0x00000200 257#define FPC_ENABLE_DIV0 0x00000400 258#define FPC_ENABLE_INVALID 0x00000800 259#define FPC_EXCEPTION_BITS 0x0003f000 260#define FPC_EXCEPTION_INEXACT 0x00001000 261#define FPC_EXCEPTION_UNDERFLOW 0x00002000 262#define FPC_EXCEPTION_OVERFLOW 0x00004000 263#define FPC_EXCEPTION_DIV0 0x00008000 264#define FPC_EXCEPTION_INVALID 0x00010000 265#define FPC_EXCEPTION_UNIMPL 0x00020000 266#define FPC_COND_BIT 0x00800000 267#define FPC_FLUSH_BIT 0x01000000 268#define FPC_MBZ_BITS 0xfe7c0000 269 270/* 271 * Constants to determine if have a floating point instruction. 272 */ 273#define OPCODE_SHIFT 26 274#define OPCODE_C1 0x11 275 276/* 277 * The low part of the TLB entry. 278 */ 279#define VMTLB_PF_NUM 0x3fffffc0 280#define VMTLB_ATTR_MASK 0x00000038 281#define VMTLB_MOD_BIT 0x00000004 282#define VMTLB_VALID_BIT 0x00000002 283#define VMTLB_GLOBAL_BIT 0x00000001 284 285#define VMTLB_PHYS_PAGE_SHIFT 6 286 287/* 288 * The high part of the TLB entry. 289 */ 290#define VMTLB_VIRT_PAGE_NUM 0xffffe000 291#define VMTLB_PID 0x000000ff 292#define VMTLB_PID_R9K 0x00000fff 293#define VMTLB_PID_SHIFT 0 294#define VMTLB_VIRT_PAGE_SHIFT 12 295#define VMTLB_VIRT_PAGE_SHIFT_R9K 13 296 297/* 298 * The first TLB entry that write random hits. 299 * TLB entry 0 maps the kernel stack of the currently running thread 300 * TLB entry 1 maps the pcpu area of processor (only for SMP builds) 301 */ 302#define KSTACK_TLB_ENTRY 0 303#ifdef SMP 304#define PCPU_TLB_ENTRY 1 305#define VMWIRED_ENTRIES 2 306#else 307#define VMWIRED_ENTRIES 1 308#endif /* SMP */ 309 310/* 311 * The number of process id entries. 312 */ 313#define VMNUM_PIDS 256 314 315/* 316 * TLB probe return codes. 317 */ 318#define VMTLB_NOT_FOUND 0 319#define VMTLB_FOUND 1 320#define VMTLB_FOUND_WITH_PATCH 2 321#define VMTLB_PROBE_ERROR 3 322 323/* 324 * Exported definitions unique to mips cpu support. 325 */ 326 327/* 328 * definitions of cpu-dependent requirements 329 * referenced in generic code 330 */ 331#define COPY_SIGCODE /* copy sigcode above user stack in exec */ 332 333#define cpu_swapout(p) panic("cpu_swapout: can't get here"); 334 335#ifndef _LOCORE 336#include <machine/cpufunc.h> 337#include <machine/frame.h> 338/* 339 * Arguments to hardclock and gatherstats encapsulate the previous 340 * machine state in an opaque clockframe. 341 */ 342#define clockframe trapframe /* Use normal trap frame */ 343 344#define CLKF_USERMODE(framep) ((framep)->sr & SR_KSU_USER) 345#define CLKF_PC(framep) ((framep)->pc) 346#define CLKF_INTR(framep) (0) 347#define MIPS_CLKF_INTR() (intr_nesting_level >= 1) 348#define TRAPF_USERMODE(framep) (((framep)->sr & SR_KSU_USER) != 0) 349#define TRAPF_PC(framep) ((framep)->pc) 350#define cpu_getstack(td) ((td)->td_frame->sp) 351 352/* 353 * A machine-independent interface to the CPU's counter. 354 */ 355#define get_cyclecount() mips_rd_count() 356 357/* 358 * CPU identification, from PRID register. 359 */ 360union cpuprid { 361 int cpuprid; 362 struct { 363#if BYTE_ORDER == BIG_ENDIAN 364 u_int pad1:8; /* reserved */ 365 u_int cp_vendor:8; /* company identifier */ 366 u_int cp_imp:8; /* implementation identifier */ 367 u_int cp_majrev:4; /* major revision identifier */ 368 u_int cp_minrev:4; /* minor revision identifier */ 369#else 370 u_int cp_minrev:4; /* minor revision identifier */ 371 u_int cp_majrev:4; /* major revision identifier */ 372 u_int cp_imp:8; /* implementation identifier */ 373 u_int cp_vendor:8; /* company identifier */ 374 u_int pad1:8; /* reserved */ 375#endif 376 } cpu; 377}; 378 379#endif /* !_LOCORE */ 380 381/* 382 * CTL_MACHDEP definitions. 383 */ 384#define CPU_CONSDEV 1 /* dev_t: console terminal device */ 385#define CPU_ADJKERNTZ 2 /* int: timezone offset (seconds) */ 386#define CPU_DISRTCSET 3 /* int: disable resettodr() call */ 387#define CPU_BOOTINFO 4 /* struct: bootinfo */ 388#define CPU_WALLCLOCK 5 /* int: indicates wall CMOS clock */ 389#define CPU_MAXID 6 /* number of valid machdep ids */ 390 391#define CTL_MACHDEP_NAMES { \ 392 { 0, 0 }, \ 393 { "console_device", CTLTYPE_STRUCT }, \ 394 { "adjkerntz", CTLTYPE_INT }, \ 395 { "disable_rtc_set", CTLTYPE_INT }, \ 396 { "bootinfo", CTLTYPE_STRUCT }, \ 397 { "wall_cmos_clock", CTLTYPE_INT }, \ 398} 399 400/* 401 * MIPS CPU types (cp_imp). 402 */ 403#define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */ 404#define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */ 405#define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */ 406#define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */ 407#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */ 408#define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */ 409#define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */ 410#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */ 411#define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */ 412#define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */ 413#define MIPS_R4100 0x0c /* NEC VR41xx CPU MIPS-16 ISA III */ 414#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 415#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 416#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */ 417#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */ 418#define MIPS_R5000 0x23 /* MIPS R5000 CPU ISA IV */ 419#define MIPS_RM7000 0x27 /* QED RM7000 CPU ISA IV */ 420#define MIPS_RM52X0 0x28 /* QED RM52X0 CPU ISA IV */ 421#define MIPS_VR5400 0x54 /* NEC Vr5400 CPU ISA IV+ */ 422#define MIPS_RM9000 0x34 /* E9000 CPU */ 423 424/* 425 * MIPS FPU types 426 */ 427#define MIPS_SOFT 0x00 /* Software emulation ISA I */ 428#define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */ 429#define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */ 430#define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */ 431#define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */ 432#define MIPS_R4010 0x05 /* MIPS R4000/R4400 FPC ISA II */ 433#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */ 434#define MIPS_R10010 0x09 /* MIPS R10000/T5 FPU ISA IV */ 435#define MIPS_R4210 0x0a /* MIPS R4200 FPC (ICE) ISA III */ 436#define MIPS_UNKF1 0x0b /* unnanounced product cpu ISA III */ 437#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 438#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 439#define MIPS_R3SONY 0x21 /* Sony R3000 based FPU ISA I */ 440#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */ 441#define MIPS_R5010 0x23 /* MIPS R5000 based FPU ISA IV */ 442#define MIPS_RM7000 0x27 /* QED RM7000 FPU ISA IV */ 443#define MIPS_RM5230 0x28 /* QED RM52X0 based FPU ISA IV */ 444#define MIPS_RM52XX 0x28 /* QED RM52X0 based FPU ISA IV */ 445#define MIPS_VR5400 0x54 /* NEC Vr5400 FPU ISA IV+ */ 446 447#ifndef _LOCORE 448extern union cpuprid cpu_id; 449 450#define mips_proc_type() ((cpu_id.cpu.cp_vendor << 8) | cpu_id.cpu.cp_imp) 451#define mips_set_proc_type(type) (cpu_id.cpu.cp_vendor = (type) >> 8, \ 452 cpu_id.cpu.cp_imp = ((type) & 0x00ff)) 453#endif /* !_LOCORE */ 454 455#if defined(_KERNEL) && !defined(_LOCORE) 456extern union cpuprid fpu_id; 457 458struct tlb; 459struct user; 460 461u_int32_t mips_cp0_config1_read(void); 462int Mips_ConfigCache(void); 463void Mips_SetWIRED(int); 464void Mips_SetPID(int); 465u_int Mips_GetCOUNT(void); 466void Mips_SetCOMPARE(u_int); 467u_int Mips_GetCOMPARE(void); 468 469void Mips_SyncCache(void); 470void Mips_SyncDCache(vm_offset_t, int); 471void Mips_HitSyncDCache(vm_offset_t, int); 472void Mips_HitSyncSCache(vm_offset_t, int); 473void Mips_IOSyncDCache(vm_offset_t, int, int); 474void Mips_HitInvalidateDCache(vm_offset_t, int); 475void Mips_SyncICache(vm_offset_t, int); 476void Mips_InvalidateICache(vm_offset_t, int); 477 478void Mips_TLBFlush(int); 479void Mips_TLBFlushAddr(vm_offset_t); 480void Mips_TLBWriteIndexed(int, struct tlb *); 481void Mips_TLBUpdate(vm_offset_t, unsigned); 482void Mips_TLBRead(int, struct tlb *); 483void mips_TBIAP(int); 484void wbflush(void); 485 486extern u_int32_t cpu_counter_interval; /* Number of counter ticks/tick */ 487extern u_int32_t cpu_counter_last; /* Last compare value loaded */ 488extern int num_tlbentries; 489extern char btext[]; 490extern char etext[]; 491extern int intr_nesting_level; 492 493#define func_0args_asmmacro(func, in) \ 494 __asm __volatile ( "jalr %0" \ 495 : "=r" (in) /* outputs */ \ 496 : "r" (func) /* inputs */ \ 497 : "$31", "$4"); 498 499#define func_1args_asmmacro(func, arg0) \ 500 __asm __volatile ("move $4, %1;" \ 501 "jalr %0" \ 502 : /* outputs */ \ 503 : "r" (func), "r" (arg0) /* inputs */ \ 504 : "$31", "$4"); 505 506#define func_2args_asmmacro(func, arg0, arg1) \ 507 __asm __volatile ("move $4, %1;" \ 508 "move $5, %2;" \ 509 "jalr %0" \ 510 : /* outputs */ \ 511 : "r" (func), "r" (arg0), "r" (arg1) /* inputs */ \ 512 : "$31", "$4", "$5"); 513 514#define func_3args_asmmacro(func, arg0, arg1, arg2) \ 515 __asm __volatile ( "move $4, %1;" \ 516 "move $5, %2;" \ 517 "move $6, %3;" \ 518 "jalr %0" \ 519 : /* outputs */ \ 520 : "r" (func), "r" (arg0), "r" (arg1), "r" (arg2) /* inputs */ \ 521 : "$31", "$4", "$5", "$6"); 522 523#define MachSetPID Mips_SetPID 524#define MachTLBUpdate Mips_TLBUpdate 525#define mips_TBIS Mips_TLBFlushAddr 526#define MIPS_TBIAP() mips_TBIAP(num_tlbentries) 527#define MachSetWIRED(index) Mips_SetWIRED(index) 528#define MachTLBFlush(count) Mips_TLBFlush(count) 529#define MachTLBGetPID(pid) (pid = Mips_TLBGetPID()) 530#define MachTLBRead(tlbno, tlbp) Mips_TLBRead(tlbno, tlbp) 531#define MachFPTrap(sr, cause, pc) MipsFPTrap(sr, cause, pc) 532 533/* 534 * Enable realtime clock (always enabled). 535 */ 536#define enablertclock() 537 538/* 539 * Are we in an interrupt handler? required by JunOS 540 */ 541#define IN_INT_HANDLER() \ 542 (curthread->td_intr_nesting_level != 0 || \ 543 (curthread->td_pflags & TDP_ITHREAD)) 544 545/* 546 * Low level access routines to CPU registers 547 */ 548 549int Mips_TLBGetPID(void); 550 551void swi_vm(void *); 552void cpu_halt(void); 553void cpu_reset(void); 554 555u_int32_t set_intr_mask(u_int32_t); 556u_int32_t get_intr_mask(void); 557 558#define cpu_spinwait() /* nothing */ 559 560#endif /* _KERNEL */ 561#endif /* !_MACHINE_CPU_H_ */ 562