asm_octeon.S revision 201921 
1
2#include <machine/asm.h>
3#include <machine/cache_r4k.h>
4#include <machine/cpuregs.h>
5#include <machine/param.h>
6#include <machine/pte.h>
7
8#include "assym.s"
9
10
11
12#define CPU_DISABLE_INTERRUPTS(reg, reg2, reg3) \
13        mfc0    reg, MIPS_COP_0_STATUS; \
14        nop; \
15        move    reg3, reg; \
16        li      reg2, ~MIPS_SR_INT_IE; \
17        and     reg, reg2, reg; \
18        mtc0    reg, MIPS_COP_0_STATUS; \
19        COP0_SYNC
20
21
22
23#define CPU_ENABLE_INTERRUPTS(reg, reg3) \
24        mfc0    reg, MIPS_COP_0_STATUS; \
25        nop; \
26        or      reg, reg, reg3; \
27        mtc0    reg, MIPS_COP_0_STATUS; \
28        COP0_SYNC
29
30
31#define PUSHR(reg) \
32        addiu   sp,sp,-16        ; \
33        sd      reg, 8(sp)      ; \
34        nop                     ;
35
36#define POPR(reg) \
37        ld      reg, 8(sp)      ; \
38        addiu   sp,sp,16        ; \
39        nop                     ;
40
41
42
43
44/*
45 * octeon_ciu_get_interrupt_reg_addr
46 *
47 * Given  Int-X, En-X combination, return the CIU Interrupt Enable Register addr
48 * a0 = ciu Int-X:  0/1
49 * a1 = ciu EN-0:   0/1
50 */
51LEAF(octeon_ciu_get_interrupt_reg_addr)
52        .set    noreorder
53        .set    mips3
54
55        beqz    a0, ciu_get_interrupt_reg_addr_Int_0
56        nop
57
58ciu_get_interrupt_reg_addr_Int_1:
59        beqz    a1, ciu_get_interrupt_reg_addr_Int_1_En_0
60        nop
61
62ciu_get_interrupt_reg_addr_Int_1_En1:
63        li      a0, OCTEON_CIU_ADDR_HI
64        dsll32  a0, a0, 0
65        nop
66        ori      a0, OCTEON_CIU_EN1_INT1_LO
67        j       ciu_get_interrupt_reg_addr_ret
68        nop
69
70ciu_get_interrupt_reg_addr_Int_1_En_0:
71        li      a0, OCTEON_CIU_ADDR_HI
72        dsll32  a0, a0, 0
73        nop
74        ori     a0, OCTEON_CIU_EN0_INT1_LO
75        j       ciu_get_interrupt_reg_addr_ret
76        nop
77
78ciu_get_interrupt_reg_addr_Int_0:
79        beqz    a1, ciu_get_interrupt_reg_addr_Int_0_En_0
80        nop
81
82ciu_get_interrupt_reg_addr_Int_0_En_1:
83        li      a0, OCTEON_CIU_ADDR_HI
84        dsll32  a0, a0, 0
85        nop
86        ori     a0, OCTEON_CIU_EN1_INT0_LO
87        j       ciu_get_interrupt_reg_addr_ret
88        nop
89
90ciu_get_interrupt_reg_addr_Int_0_En_0:
91        li      a0, OCTEON_CIU_ADDR_HI
92        dsll32  a0, a0, 0
93        nop
94        ori     a0, OCTEON_CIU_EN0_INT0_LO
95
96
97ciu_get_interrupt_reg_addr_ret:
98        j       ra
99        nop
100
101        .set	mips0
102        .set    reorder
103END(octeon_ciu_get_interrupt_reg_addr)
104
105
106
107/*
108 * octeon_ciu_mask_all_interrupts
109 *
110 * a0 = ciu Interrupt-X:  0/1
111 * a1 = ciu Enable-X:   0/1
112 */
113LEAF(octeon_ciu_mask_all_interrupts)
114	.set    noreorder
115        .set    mips3
116
117        PUSHR(ra)
118        PUSHR(s0)
119
120        move    t0, a0
121        move    t1, a1
122        li      a0, MIPS_SR_INT_IE
123        CPU_DISABLE_INTERRUPTS(a2, a1, s0)
124        move    a0, t0
125        move    t1, a1
126        jal     octeon_ciu_get_interrupt_reg_addr
127        nop
128        ld      a2, 0(a0)       # Dummy read
129        nop
130        move    a2, zero        # Clear all
131        sd      a2, 0(a0)       # Write new Enable bits
132        nop
133        CPU_ENABLE_INTERRUPTS(a2, s0)
134
135        POPR(s0)
136        POPR(ra)
137	j	ra			# Return
138	nop				# (bd slot)
139
140        .set	mips0
141	.set	reorder
142END(octeon_ciu_mask_all_interrupts)
143
144