ar71xx_pci.c revision 194273
1187706Sgonzo/*- 2187706Sgonzo * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org> 3187706Sgonzo * All rights reserved. 4187706Sgonzo * 5187706Sgonzo * Redistribution and use in source and binary forms, with or without 6187706Sgonzo * modification, are permitted provided that the following conditions 7187706Sgonzo * are met: 8187706Sgonzo * 1. Redistributions of source code must retain the above copyright 9187706Sgonzo * notice unmodified, this list of conditions, and the following 10187706Sgonzo * disclaimer. 11187706Sgonzo * 2. Redistributions in binary form must reproduce the above copyright 12187706Sgonzo * notice, this list of conditions and the following disclaimer in the 13187706Sgonzo * documentation and/or other materials provided with the distribution. 14187706Sgonzo * 15187706Sgonzo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16187706Sgonzo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17187706Sgonzo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18187706Sgonzo * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19187706Sgonzo * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20187706Sgonzo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21187706Sgonzo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22187706Sgonzo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23187706Sgonzo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24187706Sgonzo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25187706Sgonzo * SUCH DAMAGE. 26187706Sgonzo */ 27187706Sgonzo 28187706Sgonzo#include <sys/cdefs.h> 29187706Sgonzo__FBSDID("$FreeBSD$"); 30187706Sgonzo 31187706Sgonzo#include <sys/param.h> 32187706Sgonzo#include <sys/systm.h> 33187706Sgonzo 34187706Sgonzo#include <sys/bus.h> 35187706Sgonzo#include <sys/interrupt.h> 36187706Sgonzo#include <sys/malloc.h> 37187706Sgonzo#include <sys/kernel.h> 38187706Sgonzo#include <sys/module.h> 39187706Sgonzo#include <sys/rman.h> 40187706Sgonzo 41187706Sgonzo#include <vm/vm.h> 42187706Sgonzo#include <vm/pmap.h> 43187706Sgonzo#include <vm/vm_extern.h> 44187706Sgonzo 45187706Sgonzo#include <machine/bus.h> 46187706Sgonzo#include <machine/cpu.h> 47187706Sgonzo#include <machine/pmap.h> 48187706Sgonzo 49187706Sgonzo#include <dev/pci/pcivar.h> 50187706Sgonzo#include <dev/pci/pcireg.h> 51187706Sgonzo 52187706Sgonzo#include <dev/pci/pcib_private.h> 53187706Sgonzo#include "pcib_if.h" 54187706Sgonzo 55192161Sgonzo#include <mips/atheros/ar71xxreg.h> 56192161Sgonzo#include <mips/atheros/ar71xx_pci_bus_space.h> 57187706Sgonzo 58187706Sgonzo#undef AR71XX_PCI_DEBUG 59187706Sgonzo#ifdef AR71XX_PCI_DEBUG 60187706Sgonzo#define dprintf printf 61187706Sgonzo#else 62187706Sgonzo#define dprintf(x, arg...) 63187706Sgonzo#endif 64187706Sgonzo 65187706Sgonzostruct ar71xx_pci_softc { 66187706Sgonzo device_t sc_dev; 67187706Sgonzo 68187706Sgonzo int sc_busno; 69187706Sgonzo struct rman sc_mem_rman; 70187706Sgonzo struct rman sc_irq_rman; 71187706Sgonzo 72191872Sgonzo struct intr_event *sc_eventstab[AR71XX_PCI_NIRQS]; 73187706Sgonzo struct resource *sc_irq; 74187706Sgonzo void *sc_ih; 75187706Sgonzo}; 76187706Sgonzo 77191872Sgonzostatic int ar71xx_pci_setup_intr(device_t, device_t, struct resource *, int, 78191872Sgonzo driver_filter_t *, driver_intr_t *, void *, void **); 79191872Sgonzostatic int ar71xx_pci_teardown_intr(device_t, device_t, struct resource *, 80191872Sgonzo void *); 81191872Sgonzostatic int ar71xx_pci_intr(void *); 82191872Sgonzo 83192822Sgonzostatic void 84192822Sgonzoar71xx_pci_mask_irq(void *source) 85191872Sgonzo{ 86191872Sgonzo uint32_t reg; 87192822Sgonzo unsigned int irq = (unsigned int)source; 88191872Sgonzo 89191872Sgonzo reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK); 90194273Sgonzo /* flush */ 91194273Sgonzo reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK); 92191872Sgonzo ATH_WRITE_REG(AR71XX_PCI_INTR_MASK, reg & ~(1 << irq)); 93191872Sgonzo} 94191872Sgonzo 95192822Sgonzostatic void 96192822Sgonzoar71xx_pci_unmask_irq(void *source) 97191872Sgonzo{ 98191872Sgonzo uint32_t reg; 99192822Sgonzo unsigned int irq = (unsigned int)source; 100191872Sgonzo 101191872Sgonzo reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK); 102191872Sgonzo ATH_WRITE_REG(AR71XX_PCI_INTR_MASK, reg | (1 << irq)); 103194273Sgonzo /* flush */ 104194273Sgonzo reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK); 105191872Sgonzo} 106191872Sgonzo 107187706Sgonzo/* 108187706Sgonzo * get bitmask for bytes of interest: 109187706Sgonzo * 0 - we want this byte, 1 - ignore it. e.g: we read 1 byte 110187706Sgonzo * from register 7. Bitmask would be: 0111 111187706Sgonzo */ 112187706Sgonzostatic uint32_t 113187706Sgonzoar71xx_get_bytes_to_read(int reg, int bytes) 114187706Sgonzo{ 115187706Sgonzo uint32_t bytes_to_read = 0; 116187706Sgonzo if ((bytes % 4) == 0) 117187706Sgonzo bytes_to_read = 0; 118187706Sgonzo else if ((bytes % 4) == 1) 119187706Sgonzo bytes_to_read = (~(1 << (reg % 4))) & 0xf; 120187706Sgonzo else if ((bytes % 4) == 2) 121187706Sgonzo bytes_to_read = (~(3 << (reg % 4))) & 0xf; 122187706Sgonzo else 123187706Sgonzo panic("%s: wrong combination", __func__); 124187706Sgonzo 125187706Sgonzo return (bytes_to_read); 126187706Sgonzo} 127187706Sgonzo 128187706Sgonzostatic int 129187706Sgonzoar71xx_pci_check_bus_error(void) 130187706Sgonzo{ 131187706Sgonzo uint32_t error, addr, has_errors = 0; 132187706Sgonzo error = ATH_READ_REG(AR71XX_PCI_ERROR) & 0x3; 133187706Sgonzo dprintf("%s: PCI error = %02x\n", __func__, error); 134187706Sgonzo if (error) { 135187706Sgonzo addr = ATH_READ_REG(AR71XX_PCI_ERROR_ADDR); 136187706Sgonzo 137187706Sgonzo /* Do not report it yet */ 138187706Sgonzo#if 0 139187706Sgonzo printf("PCI bus error %d at addr 0x%08x\n", error, addr); 140187706Sgonzo#endif 141187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_ERROR, error); 142187706Sgonzo has_errors = 1; 143187706Sgonzo } 144187706Sgonzo 145187706Sgonzo error = ATH_READ_REG(AR71XX_PCI_AHB_ERROR) & 0x1; 146187706Sgonzo dprintf("%s: AHB error = %02x\n", __func__, error); 147187706Sgonzo if (error) { 148187706Sgonzo addr = ATH_READ_REG(AR71XX_PCI_AHB_ERROR_ADDR); 149187706Sgonzo /* Do not report it yet */ 150187706Sgonzo#if 0 151187706Sgonzo printf("AHB bus error %d at addr 0x%08x\n", error, addr); 152187706Sgonzo#endif 153187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_AHB_ERROR, error); 154187706Sgonzo has_errors = 1; 155187706Sgonzo } 156187706Sgonzo 157187706Sgonzo return (has_errors); 158187706Sgonzo} 159187706Sgonzo 160187706Sgonzostatic uint32_t 161187706Sgonzoar71xx_pci_make_addr(int bus, int slot, int func, int reg) 162187706Sgonzo{ 163187706Sgonzo if (bus == 0) { 164187706Sgonzo return ((1 << slot) | (func << 8) | (reg & ~3)); 165187706Sgonzo } else { 166187706Sgonzo return ((bus << 16) | (slot << 11) | (func << 8) 167187706Sgonzo | (reg & ~3) | 1); 168187706Sgonzo } 169187706Sgonzo} 170187706Sgonzo 171187706Sgonzostatic int 172187706Sgonzoar71xx_pci_conf_setup(int bus, int slot, int func, int reg, int bytes, 173187706Sgonzo uint32_t cmd) 174187706Sgonzo{ 175187706Sgonzo uint32_t addr = ar71xx_pci_make_addr(bus, slot, func, (reg & ~3)); 176187706Sgonzo cmd |= (ar71xx_get_bytes_to_read(reg, bytes) << 4); 177187706Sgonzo 178187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_CONF_ADDR, addr); 179187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_CONF_CMD, cmd); 180187706Sgonzo 181187706Sgonzo dprintf("%s: tag (%x, %x, %x) %d/%d addr=%08x, cmd=%08x\n", __func__, 182187706Sgonzo bus, slot, func, reg, bytes, addr, cmd); 183187706Sgonzo 184187706Sgonzo return ar71xx_pci_check_bus_error(); 185187706Sgonzo} 186187706Sgonzo 187187706Sgonzostatic uint32_t 188194059Sgonzoar71xx_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func, 189194059Sgonzo u_int reg, int bytes) 190187706Sgonzo{ 191187706Sgonzo uint32_t data; 192187706Sgonzo uint32_t cmd, shift, mask; 193187706Sgonzo 194187706Sgonzo /* register access is 32-bit aligned */ 195187706Sgonzo shift = (reg & 3) * 8; 196187706Sgonzo if (shift) 197187706Sgonzo mask = (1 << shift) - 1; 198187706Sgonzo else 199187706Sgonzo mask = 0xffffffff; 200187706Sgonzo 201187706Sgonzo dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot, 202187706Sgonzo func, reg, bytes); 203187706Sgonzo 204187706Sgonzo if ((bus == 0) && (slot == 0) && (func == 0)) { 205187706Sgonzo cmd = PCI_LCONF_CMD_READ | (reg & ~3); 206187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_LCONF_CMD, cmd); 207187706Sgonzo data = ATH_READ_REG(AR71XX_PCI_LCONF_READ_DATA); 208187706Sgonzo } else { 209187706Sgonzo if (ar71xx_pci_conf_setup(bus, slot, func, reg, bytes, 210187706Sgonzo PCI_CONF_CMD_READ) == 0) 211187706Sgonzo data = ATH_READ_REG(AR71XX_PCI_CONF_READ_DATA); 212187706Sgonzo else 213187706Sgonzo data = -1; 214187706Sgonzo } 215187706Sgonzo 216187706Sgonzo /* get request bytes from 32-bit word */ 217187706Sgonzo data = (data >> shift) & mask; 218187706Sgonzo 219187706Sgonzo dprintf("%s: read 0x%x\n", __func__, data); 220187706Sgonzo 221187706Sgonzo return (data); 222187706Sgonzo} 223187706Sgonzo 224187706Sgonzostatic void 225194059Sgonzoar71xx_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func, 226194059Sgonzo u_int reg, uint32_t data, int bytes) 227187706Sgonzo{ 228187706Sgonzo uint32_t cmd; 229187706Sgonzo 230187706Sgonzo dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot, 231187706Sgonzo func, reg, bytes); 232187706Sgonzo 233187706Sgonzo data = data << (8*(reg % 4)); 234187706Sgonzo 235187706Sgonzo if ((bus == 0) && (slot == 0) && (func == 0)) { 236187706Sgonzo cmd = PCI_LCONF_CMD_WRITE | (reg & ~3); 237187706Sgonzo cmd |= ar71xx_get_bytes_to_read(reg, bytes) << 20; 238187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_LCONF_CMD, cmd); 239187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_LCONF_WRITE_DATA, data); 240187706Sgonzo } else { 241187706Sgonzo if (ar71xx_pci_conf_setup(bus, slot, func, reg, bytes, 242187706Sgonzo PCI_CONF_CMD_WRITE) == 0) 243187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_CONF_WRITE_DATA, data); 244187706Sgonzo } 245187706Sgonzo} 246187706Sgonzo 247187706Sgonzostatic int 248187706Sgonzoar71xx_pci_probe(device_t dev) 249187706Sgonzo{ 250187706Sgonzo 251187706Sgonzo return (0); 252187706Sgonzo} 253187706Sgonzo 254187706Sgonzostatic int 255187706Sgonzoar71xx_pci_attach(device_t dev) 256187706Sgonzo{ 257187706Sgonzo int busno = 0; 258187706Sgonzo int rid = 0; 259187706Sgonzo uint32_t reset; 260187706Sgonzo struct ar71xx_pci_softc *sc = device_get_softc(dev); 261187706Sgonzo 262187706Sgonzo sc->sc_mem_rman.rm_type = RMAN_ARRAY; 263187706Sgonzo sc->sc_mem_rman.rm_descr = "ar71xx PCI memory window"; 264187706Sgonzo if (rman_init(&sc->sc_mem_rman) != 0 || 265187706Sgonzo rman_manage_region(&sc->sc_mem_rman, AR71XX_PCI_MEM_BASE, 266187706Sgonzo AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1) != 0) { 267187706Sgonzo panic("ar71xx_pci_attach: failed to set up I/O rman"); 268187706Sgonzo } 269187706Sgonzo 270187706Sgonzo sc->sc_irq_rman.rm_type = RMAN_ARRAY; 271187706Sgonzo sc->sc_irq_rman.rm_descr = "ar71xx PCI IRQs"; 272187706Sgonzo if (rman_init(&sc->sc_irq_rman) != 0 || 273187706Sgonzo rman_manage_region(&sc->sc_irq_rman, AR71XX_PCI_IRQ_START, 274187706Sgonzo AR71XX_PCI_IRQ_END) != 0) 275187706Sgonzo panic("ar71xx_pci_attach: failed to set up IRQ rman"); 276187706Sgonzo 277187706Sgonzo 278187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_INTR_STATUS, 0); 279187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_INTR_MASK, 0); 280187706Sgonzo 281187706Sgonzo /* Hook up our interrupt handler. */ 282187706Sgonzo if ((sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 283187706Sgonzo RF_SHAREABLE | RF_ACTIVE)) == NULL) { 284187706Sgonzo device_printf(dev, "unable to allocate IRQ resource\n"); 285187706Sgonzo return ENXIO; 286187706Sgonzo } 287187706Sgonzo 288187706Sgonzo if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC, 289191872Sgonzo ar71xx_pci_intr, NULL, sc, &sc->sc_ih))) { 290187706Sgonzo device_printf(dev, 291187706Sgonzo "WARNING: unable to register interrupt handler\n"); 292187706Sgonzo return ENXIO; 293187706Sgonzo } 294187706Sgonzo 295187706Sgonzo /* reset PCI core and PCI bus */ 296187706Sgonzo reset = ATH_READ_REG(AR71XX_RST_RESET); 297187706Sgonzo reset |= (RST_RESET_PCI_CORE | RST_RESET_PCI_BUS); 298187706Sgonzo ATH_WRITE_REG(AR71XX_RST_RESET, reset); 299187706Sgonzo DELAY(1000); 300194273Sgonzo ATH_READ_REG(AR71XX_RST_RESET); 301187706Sgonzo 302187706Sgonzo reset &= ~(RST_RESET_PCI_CORE | RST_RESET_PCI_BUS); 303187706Sgonzo ATH_WRITE_REG(AR71XX_RST_RESET, reset); 304187706Sgonzo DELAY(1000); 305194273Sgonzo ATH_READ_REG(AR71XX_RST_RESET); 306187706Sgonzo 307187706Sgonzo /* Init PCI windows */ 308187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW0, PCI_WINDOW0_ADDR); 309187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW1, PCI_WINDOW1_ADDR); 310187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW2, PCI_WINDOW2_ADDR); 311187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW3, PCI_WINDOW3_ADDR); 312187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW4, PCI_WINDOW4_ADDR); 313187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW5, PCI_WINDOW5_ADDR); 314187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW6, PCI_WINDOW6_ADDR); 315187706Sgonzo ATH_WRITE_REG(AR71XX_PCI_WINDOW7, PCI_WINDOW7_CONF_ADDR); 316187706Sgonzo DELAY(1000); 317187706Sgonzo 318187706Sgonzo ar71xx_pci_check_bus_error(); 319187706Sgonzo 320187706Sgonzo /* Fixup internal PCI bridge */ 321187706Sgonzo ar71xx_pci_write_config(dev, 0, 0, 0, PCIR_COMMAND, 322187706Sgonzo PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN 323187706Sgonzo | PCIM_CMD_SERRESPEN | PCIM_CMD_BACKTOBACK 324187706Sgonzo | PCIM_CMD_PERRESPEN | PCIM_CMD_MWRICEN, 2); 325187706Sgonzo 326187706Sgonzo device_add_child(dev, "pci", busno); 327187706Sgonzo return (bus_generic_attach(dev)); 328187706Sgonzo} 329187706Sgonzo 330187706Sgonzostatic int 331187706Sgonzoar71xx_pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 332187706Sgonzo{ 333187706Sgonzo struct ar71xx_pci_softc *sc = device_get_softc(dev); 334187706Sgonzo 335187706Sgonzo switch (which) { 336187706Sgonzo case PCIB_IVAR_DOMAIN: 337187706Sgonzo *result = 0; 338187706Sgonzo return (0); 339187706Sgonzo case PCIB_IVAR_BUS: 340187706Sgonzo *result = sc->sc_busno; 341187706Sgonzo return (0); 342187706Sgonzo } 343187706Sgonzo 344187706Sgonzo return (ENOENT); 345187706Sgonzo} 346187706Sgonzo 347187706Sgonzostatic int 348187706Sgonzoar71xx_pci_write_ivar(device_t dev, device_t child, int which, uintptr_t result) 349187706Sgonzo{ 350187706Sgonzo struct ar71xx_pci_softc * sc = device_get_softc(dev); 351187706Sgonzo 352187706Sgonzo switch (which) { 353187706Sgonzo case PCIB_IVAR_BUS: 354187706Sgonzo sc->sc_busno = result; 355187706Sgonzo return (0); 356187706Sgonzo } 357187706Sgonzo 358187706Sgonzo return (ENOENT); 359187706Sgonzo} 360187706Sgonzo 361187706Sgonzostatic struct resource * 362187706Sgonzoar71xx_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, 363187706Sgonzo u_long start, u_long end, u_long count, u_int flags) 364187706Sgonzo{ 365187706Sgonzo 366187706Sgonzo struct ar71xx_pci_softc *sc = device_get_softc(bus); 367192161Sgonzo struct resource *rv; 368187706Sgonzo struct rman *rm; 369187706Sgonzo 370187706Sgonzo switch (type) { 371187706Sgonzo case SYS_RES_IRQ: 372187706Sgonzo rm = &sc->sc_irq_rman; 373187706Sgonzo break; 374187706Sgonzo case SYS_RES_MEMORY: 375187706Sgonzo rm = &sc->sc_mem_rman; 376187706Sgonzo break; 377187706Sgonzo default: 378187706Sgonzo return (NULL); 379187706Sgonzo } 380187706Sgonzo 381187706Sgonzo rv = rman_reserve_resource(rm, start, end, count, flags, child); 382187706Sgonzo 383187706Sgonzo if (rv == NULL) 384187706Sgonzo return (NULL); 385187706Sgonzo 386187706Sgonzo rman_set_rid(rv, *rid); 387187706Sgonzo 388187706Sgonzo if (flags & RF_ACTIVE) { 389187706Sgonzo if (bus_activate_resource(child, type, *rid, rv)) { 390187706Sgonzo rman_release_resource(rv); 391187706Sgonzo return (NULL); 392187706Sgonzo } 393187706Sgonzo } 394187706Sgonzo 395192161Sgonzo 396187706Sgonzo return (rv); 397187706Sgonzo} 398187706Sgonzo 399192161Sgonzo 400187706Sgonzostatic int 401192161Sgonzoar71xx_pci_activate_resource(device_t bus, device_t child, int type, int rid, 402192161Sgonzo struct resource *r) 403192161Sgonzo{ 404192161Sgonzo int res = (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), 405192161Sgonzo child, type, rid, r)); 406192161Sgonzo 407192161Sgonzo if (!res) { 408192161Sgonzo switch(type) { 409192161Sgonzo case SYS_RES_MEMORY: 410192161Sgonzo case SYS_RES_IOPORT: 411192161Sgonzo rman_set_bustag(r, ar71xx_bus_space_pcimem); 412192161Sgonzo break; 413192161Sgonzo } 414192161Sgonzo } 415192161Sgonzo 416192161Sgonzo return (res); 417192161Sgonzo} 418192161Sgonzo 419192161Sgonzo 420192161Sgonzo 421192161Sgonzostatic int 422191872Sgonzoar71xx_pci_setup_intr(device_t bus, device_t child, struct resource *ires, 423191872Sgonzo int flags, driver_filter_t *filt, driver_intr_t *handler, 424191872Sgonzo void *arg, void **cookiep) 425191872Sgonzo{ 426191872Sgonzo struct ar71xx_pci_softc *sc = device_get_softc(bus); 427191872Sgonzo struct intr_event *event; 428191872Sgonzo int irq, error; 429191872Sgonzo 430191872Sgonzo irq = rman_get_start(ires); 431191872Sgonzo 432191872Sgonzo if (irq > AR71XX_PCI_IRQ_END) 433191872Sgonzo panic("%s: bad irq %d", __func__, irq); 434191872Sgonzo 435191872Sgonzo event = sc->sc_eventstab[irq]; 436191872Sgonzo if (event == NULL) { 437191872Sgonzo error = intr_event_create(&event, (void *)irq, 0, irq, 438192822Sgonzo ar71xx_pci_mask_irq, ar71xx_pci_unmask_irq, NULL, NULL, 439191872Sgonzo "ar71xx_pci intr%d:", irq); 440191872Sgonzo 441191872Sgonzo sc->sc_eventstab[irq] = event; 442191872Sgonzo } 443191872Sgonzo 444191872Sgonzo intr_event_add_handler(event, device_get_nameunit(child), filt, 445191872Sgonzo handler, arg, intr_priority(flags), flags, cookiep); 446191872Sgonzo 447192822Sgonzo ar71xx_pci_unmask_irq((void*)irq); 448191872Sgonzo 449191872Sgonzo return (0); 450191872Sgonzo} 451191872Sgonzo 452191872Sgonzostatic int 453191872Sgonzoar71xx_pci_teardown_intr(device_t dev, device_t child, struct resource *ires, 454187706Sgonzo void *cookie) 455187706Sgonzo{ 456191872Sgonzo struct ar71xx_pci_softc *sc = device_get_softc(dev); 457191872Sgonzo int irq, result; 458187706Sgonzo 459191872Sgonzo irq = rman_get_start(ires); 460191872Sgonzo if (irq > AR71XX_PCI_IRQ_END) 461191872Sgonzo panic("%s: bad irq %d", __func__, irq); 462191872Sgonzo 463191872Sgonzo if (sc->sc_eventstab[irq] == NULL) 464191872Sgonzo panic("Trying to teardown unoccupied IRQ"); 465191872Sgonzo 466192822Sgonzo ar71xx_pci_mask_irq((void*)irq); 467191872Sgonzo 468191872Sgonzo result = intr_event_remove_handler(cookie); 469191872Sgonzo if (!result) 470191872Sgonzo sc->sc_eventstab[irq] = NULL; 471191872Sgonzo 472191872Sgonzo return (result); 473187706Sgonzo} 474187706Sgonzo 475187706Sgonzostatic int 476191872Sgonzoar71xx_pci_intr(void *arg) 477191872Sgonzo{ 478191872Sgonzo struct ar71xx_pci_softc *sc = arg; 479191872Sgonzo struct intr_event *event; 480194273Sgonzo uint32_t reg, irq, mask; 481191872Sgonzo 482191872Sgonzo reg = ATH_READ_REG(AR71XX_PCI_INTR_STATUS); 483194273Sgonzo mask = ATH_READ_REG(AR71XX_PCI_INTR_MASK); 484194273Sgonzo /* 485194273Sgonzo * Handle only unmasked interrupts 486194273Sgonzo */ 487194273Sgonzo reg &= mask; 488191872Sgonzo for (irq = AR71XX_PCI_IRQ_START; irq <= AR71XX_PCI_IRQ_END; irq++) { 489191872Sgonzo if (reg & (1 << irq)) { 490191872Sgonzo event = sc->sc_eventstab[irq]; 491191872Sgonzo if (!event || TAILQ_EMPTY(&event->ie_handlers)) { 492191872Sgonzo /* Ignore timer interrupts */ 493191872Sgonzo if (irq != 0) 494191872Sgonzo printf("Stray IRQ %d\n", irq); 495191872Sgonzo continue; 496191872Sgonzo } 497191872Sgonzo 498191872Sgonzo /* TODO: frame instead of NULL? */ 499191872Sgonzo intr_event_handle(event, NULL); 500191872Sgonzo } 501191872Sgonzo } 502191872Sgonzo 503191872Sgonzo return (FILTER_HANDLED); 504191872Sgonzo} 505191872Sgonzo 506191872Sgonzostatic int 507187706Sgonzoar71xx_pci_maxslots(device_t dev) 508187706Sgonzo{ 509187706Sgonzo 510187706Sgonzo return (PCI_SLOTMAX); 511187706Sgonzo} 512187706Sgonzo 513187706Sgonzostatic int 514187706Sgonzoar71xx_pci_route_interrupt(device_t pcib, device_t device, int pin) 515187706Sgonzo{ 516187706Sgonzo 517187706Sgonzo return (pin); 518187706Sgonzo} 519187706Sgonzo 520187706Sgonzostatic device_method_t ar71xx_pci_methods[] = { 521187706Sgonzo /* Device interface */ 522187706Sgonzo DEVMETHOD(device_probe, ar71xx_pci_probe), 523187706Sgonzo DEVMETHOD(device_attach, ar71xx_pci_attach), 524187706Sgonzo DEVMETHOD(device_shutdown, bus_generic_shutdown), 525187706Sgonzo DEVMETHOD(device_suspend, bus_generic_suspend), 526187706Sgonzo DEVMETHOD(device_resume, bus_generic_resume), 527187706Sgonzo 528187706Sgonzo /* Bus interface */ 529187706Sgonzo DEVMETHOD(bus_print_child, bus_generic_print_child), 530187706Sgonzo DEVMETHOD(bus_read_ivar, ar71xx_pci_read_ivar), 531187706Sgonzo DEVMETHOD(bus_write_ivar, ar71xx_pci_write_ivar), 532187706Sgonzo DEVMETHOD(bus_alloc_resource, ar71xx_pci_alloc_resource), 533187706Sgonzo DEVMETHOD(bus_release_resource, bus_generic_release_resource), 534192161Sgonzo DEVMETHOD(bus_activate_resource, ar71xx_pci_activate_resource), 535187706Sgonzo DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 536191872Sgonzo DEVMETHOD(bus_setup_intr, ar71xx_pci_setup_intr), 537187706Sgonzo DEVMETHOD(bus_teardown_intr, ar71xx_pci_teardown_intr), 538187706Sgonzo 539187706Sgonzo /* pcib interface */ 540187706Sgonzo DEVMETHOD(pcib_maxslots, ar71xx_pci_maxslots), 541187706Sgonzo DEVMETHOD(pcib_read_config, ar71xx_pci_read_config), 542187706Sgonzo DEVMETHOD(pcib_write_config, ar71xx_pci_write_config), 543187706Sgonzo DEVMETHOD(pcib_route_interrupt, ar71xx_pci_route_interrupt), 544187706Sgonzo 545187706Sgonzo {0, 0} 546187706Sgonzo}; 547187706Sgonzo 548187706Sgonzostatic driver_t ar71xx_pci_driver = { 549187706Sgonzo "pcib", 550187706Sgonzo ar71xx_pci_methods, 551187706Sgonzo sizeof(struct ar71xx_pci_softc), 552187706Sgonzo}; 553187706Sgonzo 554187706Sgonzostatic devclass_t ar71xx_pci_devclass; 555187706Sgonzo 556187706SgonzoDRIVER_MODULE(ar71xx_pci, nexus, ar71xx_pci_driver, ar71xx_pci_devclass, 0, 0); 557