166633Sdfr.file "__divsi3.s" 266633Sdfr 366633Sdfr// $FreeBSD$ 4139815Simp 5139815Simp//- 666633Sdfr// Copyright (c) 2000, Intel Corporation 766633Sdfr// All rights reserved. 866633Sdfr// 966633Sdfr// Contributed 2/15/2000 by Marius Cornea, John Harrison, Cristina Iordache, 1066633Sdfr// Ted Kubaska, Bob Norin, and Shane Story of the Computational Software Lab, 1166633Sdfr// Intel Corporation. 1266633Sdfr// 1366633Sdfr// WARRANTY DISCLAIMER 1466633Sdfr// 1566633Sdfr// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1666633Sdfr// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1766633Sdfr// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1866633Sdfr// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS 1966633Sdfr// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 2066633Sdfr// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 2166633Sdfr// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 2266633Sdfr// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 2366633Sdfr// OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING 2466633Sdfr// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 2566633Sdfr// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2666633Sdfr// 2766633Sdfr// Intel Corporation is the author of this code, and requests that all 2866633Sdfr// problem reports or change requests be submitted to it directly at 2966633Sdfr// http://developer.intel.com/opensource. 3066633Sdfr// 3166633Sdfr 3266633Sdfr.section .text 3366633Sdfr 3466633Sdfr// 32-bit signed integer divide 3566633Sdfr 3666633Sdfr.proc __divsi3# 3766633Sdfr.align 32 3866633Sdfr.global __divsi3# 3966633Sdfr.align 32 4066633Sdfr 4166633Sdfr__divsi3: 4266633Sdfr 4366633Sdfr{ .mii 4466633Sdfr alloc r31=ar.pfs,2,0,0,0 4566633Sdfr nop.i 0 4666633Sdfr nop.i 0;; 4766633Sdfr} { .mii 4866633Sdfr nop.m 0 4966633Sdfr 5066633Sdfr // 32-BIT SIGNED INTEGER DIVIDE BEGINS HERE 5166633Sdfr 5266633Sdfr // general register used: 5366633Sdfr // r32 - 32-bit signed integer dividend 5466633Sdfr // r33 - 32-bit signed integer divisor 5566633Sdfr // r8 - 32-bit signed integer result 5666633Sdfr // r2 - scratch register 5766633Sdfr // floating-point registers used: f6, f7, f8, f9 5866633Sdfr // predicate registers used: p6 5966633Sdfr 6066633Sdfr sxt4 r32=r32 6166633Sdfr sxt4 r33=r33;; 6266633Sdfr} { .mmb 6366633Sdfr setf.sig f6=r32 6466633Sdfr setf.sig f7=r33 6566633Sdfr nop.b 0;; 6666633Sdfr} { .mfi 6766633Sdfr nop.m 0 6866633Sdfr fcvt.xf f6=f6 6966633Sdfr nop.i 0 7066633Sdfr} { .mfi 7166633Sdfr nop.m 0 7266633Sdfr fcvt.xf f7=f7 7366633Sdfr mov r2 = 0x0ffdd;; 7466633Sdfr} { .mfi 7566633Sdfr setf.exp f9 = r2 7666633Sdfr // (1) y0 7766633Sdfr frcpa.s1 f8,p6=f6,f7 7866633Sdfr nop.i 0;; 7966633Sdfr} { .mfi 8066633Sdfr nop.m 0 8166633Sdfr // (2) q0 = a * y0 8266633Sdfr (p6) fma.s1 f6=f6,f8,f0 8366633Sdfr nop.i 0 8466633Sdfr} { .mfi 8566633Sdfr nop.m 0 8666633Sdfr // (3) e0 = 1 - b * y0 8766633Sdfr (p6) fnma.s1 f7=f7,f8,f1 8866633Sdfr nop.i 0;; 8966633Sdfr} { .mfi 9066633Sdfr nop.m 0 9166633Sdfr // (4) q1 = q0 + e0 * q0 9266633Sdfr (p6) fma.s1 f6=f7,f6,f6 9366633Sdfr nop.i 0 9466633Sdfr} { .mfi 9566633Sdfr nop.m 0 9666633Sdfr // (5) e1 = e0 * e0 + 2^-34 9766633Sdfr (p6) fma.s1 f7=f7,f7,f9 9866633Sdfr nop.i 0;; 9966633Sdfr} { .mfi 10066633Sdfr nop.m 0 10166633Sdfr // (6) q2 = q1 + e1 * q1 10266633Sdfr (p6) fma.s1 f8=f7,f6,f6 10366633Sdfr nop.i 0;; 10466633Sdfr} { .mfi 10566633Sdfr nop.m 0 10666633Sdfr // (7) q = trunc(q2) 10766633Sdfr fcvt.fx.trunc.s1 f8=f8 10866633Sdfr nop.i 0;; 10966633Sdfr} { .mmi 11066633Sdfr // quotient will be in the least significant 32 bits of r8 (if b != 0) 11166633Sdfr getf.sig r8=f8 11266633Sdfr nop.m 0 11366633Sdfr nop.i 0;; 11466633Sdfr} 11566633Sdfr 11666633Sdfr // 32-BIT SIGNED INTEGER DIVIDE ENDS HERE 11766633Sdfr 11866633Sdfr{ .mmb 11966633Sdfr nop.m 0 12066633Sdfr nop.m 0 12166633Sdfr br.ret.sptk b0;; 12266633Sdfr} 12366633Sdfr 12466633Sdfr.endp __divsi3 125